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arm: dts: Add nodes for flexcan devices present on LS1021A-Rev2 SoC 

This patch adds the device nodes for flexcan controller(s) present on
LS1021A-Rev2 SoC.

Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Signed-off-by: Sakar Arora <Sakar.Arora@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Reviewed-by: Poonam Aggrwal <poonam.aggrwal@nxp.com>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
This commit is contained in:
Pankaj Bansal 2017-11-24 18:52:13 +05:30 committed by Marc Kleine-Budde
parent d50f4630c2
commit fa2edcfb5f
3 changed files with 68 additions and 0 deletions
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16
arch/arm/boot/dts/ls1021a-qds.dts
View File

@ -331,3 +331,19 @@ &uart0 {
&uart1 { &uart1 {
status = "okay"; status = "okay";
}; };
&can0 {
status = "okay";
};
&can1 {
status = "okay";
};
&can2 {
status = "disabled";
};
&can3 {
status = "disabled";
};

16
arch/arm/boot/dts/ls1021a-twr.dts
View File

@ -243,3 +243,19 @@ &uart0 {
&uart1 { &uart1 {
status = "okay"; status = "okay";
}; };
&can0 {
status = "okay";
};
&can1 {
status = "okay";
};
&can2 {
status = "disabled";
};
&can3 {
status = "disabled";
};

36
arch/arm/boot/dts/ls1021a.dtsi
View File

@ -730,5 +730,41 @@ pcie@3500000 {
<0000 0 0 3 &gic GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 3 &gic GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; <0000 0 0 4 &gic GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
}; };
can0: can@2a70000 {
compatible = "fsl,ls1021ar2-flexcan";
reg = <0x0 0x2a70000 0x0 0x1000>;
interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 1>, <&clockgen 4 1>;
clock-names = "ipg", "per";
big-endian;
};
can1: can@2a80000 {
compatible = "fsl,ls1021ar2-flexcan";
reg = <0x0 0x2a80000 0x0 0x1000>;
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 1>, <&clockgen 4 1>;
clock-names = "ipg", "per";
big-endian;
};
can2: can@2a90000 {
compatible = "fsl,ls1021ar2-flexcan";
reg = <0x0 0x2a90000 0x0 0x1000>;
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 1>, <&clockgen 4 1>;
clock-names = "ipg", "per";
big-endian;
};
can3: can@2aa0000 {
compatible = "fsl,ls1021ar2-flexcan";
reg = <0x0 0x2aa0000 0x0 0x1000>;
interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen 4 1>, <&clockgen 4 1>;
clock-names = "ipg", "per";
big-endian;
};
}; };
}; };