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drm/tegra: Add driver documentation
Adds some driver documentation for Tegra. It provides a short overview of the hardware and software architectures. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Thierry Reding
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@ -12,6 +12,7 @@ Linux GPU Driver Developer's Guide
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drm-uapi
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i915
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meson
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tegra
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tinydrm
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vc4
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vga-switcheroo
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@ -0,0 +1,178 @@
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===============================================
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drm/tegra NVIDIA Tegra GPU and display driver
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===============================================
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NVIDIA Tegra SoCs support a set of display, graphics and video functions via
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the host1x controller. host1x supplies command streams, gathered from a push
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buffer provided directly by the CPU, to its clients via channels. Software,
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or blocks amongst themselves, can use syncpoints for synchronization.
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Up until, but not including, Tegra124 (aka Tegra K1) the drm/tegra driver
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supports the built-in GPU, comprised of the gr2d and gr3d engines. Starting
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with Tegra124 the GPU is based on the NVIDIA desktop GPU architecture and
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supported by the drm/nouveau driver.
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The drm/tegra driver supports NVIDIA Tegra SoC generations since Tegra20. It
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has three parts:
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- A host1x driver that provides infrastructure and access to the host1x
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services.
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- A KMS driver that supports the display controllers as well as a number of
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outputs, such as RGB, HDMI, DSI, and DisplayPort.
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- A set of custom userspace IOCTLs that can be used to submit jobs to the
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GPU and video engines via host1x.
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Driver Infrastructure
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=====================
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The various host1x clients need to be bound together into a logical device in
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order to expose their functionality to users. The infrastructure that supports
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this is implemented in the host1x driver. When a driver is registered with the
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infrastructure it provides a list of compatible strings specifying the devices
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that it needs. The infrastructure creates a logical device and scan the device
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tree for matching device nodes, adding the required clients to a list. Drivers
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for individual clients register with the infrastructure as well and are added
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to the logical host1x device.
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Once all clients are available, the infrastructure will initialize the logical
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device using a driver-provided function which will set up the bits specific to
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the subsystem and in turn initialize each of its clients.
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Similarly, when one of the clients is unregistered, the infrastructure will
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destroy the logical device by calling back into the driver, which ensures that
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the subsystem specific bits are torn down and the clients destroyed in turn.
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Host1x Infrastructure Reference
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-------------------------------
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.. kernel-doc:: include/linux/host1x.h
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.. kernel-doc:: drivers/gpu/host1x/bus.c
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:export:
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Host1x Syncpoint Reference
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--------------------------
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.. kernel-doc:: drivers/gpu/host1x/syncpt.c
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:export:
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KMS driver
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==========
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The display hardware has remained mostly backwards compatible over the various
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Tegra SoC generations, up until Tegra186 which introduces several changes that
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make it difficult to support with a parameterized driver.
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Display Controllers
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-------------------
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Tegra SoCs have two display controllers, each of which can be associated with
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zero or more outputs. Outputs can also share a single display controller, but
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only if they run with compatible display timings. Two display controllers can
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also share a single framebuffer, allowing cloned configurations even if modes
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on two outputs don't match. A display controller is modelled as a CRTC in KMS
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terms.
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On Tegra186, the number of display controllers has been increased to three. A
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display controller can no longer drive all of the outputs. While two of these
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controllers can drive both DSI outputs and both SOR outputs, the third cannot
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drive any DSI.
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Windows
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~~~~~~~
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A display controller controls a set of windows that can be used to composite
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multiple buffers onto the screen. While it is possible to assign arbitrary Z
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ordering to individual windows (by programming the corresponding blending
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registers), this is currently not supported by the driver. Instead, it will
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assume a fixed Z ordering of the windows (window A is the root window, that
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is, the lowest, while windows B and C are overlaid on top of window A). The
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overlay windows support multiple pixel formats and can automatically convert
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from YUV to RGB at scanout time. This makes them useful for displaying video
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content. In KMS, each window is modelled as a plane. Each display controller
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has a hardware cursor that is exposed as a cursor plane.
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Outputs
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-------
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The type and number of supported outputs varies between Tegra SoC generations.
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All generations support at least HDMI. While earlier generations supported the
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very simple RGB interfaces (one per display controller), recent generations no
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longer do and instead provide standard interfaces such as DSI and eDP/DP.
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Outputs are modelled as a composite encoder/connector pair.
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RGB/LVDS
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~~~~~~~~
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This interface is no longer available since Tegra124. It has been replaced by
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the more standard DSI and eDP interfaces.
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HDMI
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~~~~
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HDMI is supported on all Tegra SoCs. Starting with Tegra210, HDMI is provided
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by the versatile SOR output, which supports eDP, DP and HDMI. The SOR is able
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to support HDMI 2.0, though support for this is currently not merged.
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DSI
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~~~
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Although Tegra has supported DSI since Tegra30, the controller has changed in
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several ways in Tegra114. Since none of the publicly available development
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boards prior to Dalmore (Tegra114) have made use of DSI, only Tegra114 and
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later are supported by the drm/tegra driver.
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eDP/DP
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~~~~~~
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eDP was first introduced in Tegra124 where it was used to drive the display
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panel for notebook form factors. Tegra210 added support for full DisplayPort
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support, though this is currently not implemented in the drm/tegra driver.
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Userspace Interface
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===================
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The userspace interface provided by drm/tegra allows applications to create
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GEM buffers, access and control syncpoints as well as submit command streams
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to host1x.
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GEM Buffers
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-----------
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The ``DRM_IOCTL_TEGRA_GEM_CREATE`` IOCTL is used to create a GEM buffer object
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with Tegra-specific flags. This is useful for buffers that should be tiled, or
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that are to be scanned out upside down (useful for 3D content).
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After a GEM buffer object has been created, its memory can be mapped by an
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application using the mmap offset returned by the ``DRM_IOCTL_TEGRA_GEM_MMAP``
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IOCTL.
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Syncpoints
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----------
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The current value of a syncpoint can be obtained by executing the
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``DRM_IOCTL_TEGRA_SYNCPT_READ`` IOCTL. Incrementing the syncpoint is achieved
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using the ``DRM_IOCTL_TEGRA_SYNCPT_INCR`` IOCTL.
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Userspace can also request blocking on a syncpoint. To do so, it needs to
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execute the ``DRM_IOCTL_TEGRA_SYNCPT_WAIT`` IOCTL, specifying the value of
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the syncpoint to wait for. The kernel will release the application when the
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syncpoint reaches that value or after a specified timeout.
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Command Stream Submission
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-------------------------
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Before an application can submit command streams to host1x it needs to open a
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channel to an engine using the ``DRM_IOCTL_TEGRA_OPEN_CHANNEL`` IOCTL. Client
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IDs are used to identify the target of the channel. When a channel is no
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longer needed, it can be closed using the ``DRM_IOCTL_TEGRA_CLOSE_CHANNEL``
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IOCTL. To retrieve the syncpoint associated with a channel, an application
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can use the ``DRM_IOCTL_TEGRA_GET_SYNCPT``.
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After opening a channel, submitting command streams is easy. The application
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writes commands into the memory backing a GEM buffer object and passes these
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to the ``DRM_IOCTL_TEGRA_SUBMIT`` IOCTL along with various other parameters,
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such as the syncpoints or relocations used in the job submission.
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