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Samsung DeviceTree updates and improvements for v4.6: 

1. Add SROM controller device nodes.
 2. Add Ethernet chip as child of SROM controller on SMDK5410.
 3. Allow simultaneous usage exynos-rng and s5p-sss drivers on Exynos5.
 4. Cleanup CPU configuration on Exynos542x/5800.
 5. Add necessary nodes for cpufreq-dt driver on Exynos542x/5800 (OPPs,
    regulator supplies) which allows frequency and voltage scalling
    of this SoC.
 6. Minor cleanups.
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Merge tag 'samsung-dt-4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/dt

Samsung DeviceTree updates and improvements for v4.6:
1. Add SROM controller device nodes.
2. Add Ethernet chip as child of SROM controller on SMDK5410.
3. Allow simultaneous usage exynos-rng and s5p-sss drivers on Exynos5.
4. Cleanup CPU configuration on Exynos542x/5800.
5. Add necessary nodes for cpufreq-dt driver on Exynos542x/5800 (OPPs,
   regulator supplies) which allows frequency and voltage scalling
   of this SoC.
6. Minor cleanups.

* tag 'samsung-dt-4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  ARM: dts: Replace legacy *,wakeup property with wakeup-source for exynos boards
  ARM: dts: Add GSCL block parent clock management to pm domain on exynos542x
  ARM: dts: Extend existing CPU OPP for exynos5800
  ARM: dts: Add CPU OPP properties for exynos542x/5800
  ARM: dts: Add cluster regulator supply properties for exynos542x/5800
  ARM: dts: Make CPU configuration more readable on exynos542x/5800
  ARM: dts: Replace legacy *,wakeup property with wakeup-source on s5pv210
  ARM: dts: Allow simultaneous usage exynos-rng and s5p-sss drivers on exynos5
  ARM: dts: Add Ethernet chip to exynos5410-smdk5410
  ARM: dts: Add SROM to exynos5410
  ARM: dts: Add SROM device node for exynos5
  ARM: dts: Add SROM device node for exynos4
  ARM: dts: Add pinctrl support to exynos5410

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2016-02-24 14:30:50 -08:00
parent fc2834a465 36a0282a41
commit fab4db0d35
32 changed files with 990 additions and 164 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
arch/arm/boot/dts/exynos3250-monk.dts
View File

@ -43,7 +43,7 @@ power_key {
linux,code = <KEY_POWER>;
label = "power key";
debounce-interval = <10>;
gpio-key,wakeup;
wakeup-source;
};
};
@ -67,7 +67,7 @@ max77836: subpmic@25 {
interrupt-parent = <&gpx1>;
interrupts = <5 0>;
reg = <0x25>;
wakeup;
wakeup-source;
muic: max77836-muic {
compatible = "maxim,max77836-muic";
@ -185,7 +185,7 @@ s2mps14_pmic@66 {
interrupt-parent = <&gpx0>;
interrupts = <7 0>;
reg = <0x66>;
wakeup;
wakeup-source;
s2mps14_osc: clocks {
compatible = "samsung,s2mps14-clk";

6
arch/arm/boot/dts/exynos3250-rinato.dts
View File

@ -43,7 +43,7 @@ power_key {
linux,code = <KEY_POWER>;
label = "power key";
debounce-interval = <10>;
gpio-key,wakeup;
wakeup-source;
};
};
@ -58,7 +58,7 @@ max77836: subpmic@25 {
interrupt-parent = <&gpx1>;
interrupts = <5 0>;
reg = <0x25>;
wakeup;
wakeup-source;
muic: max77836-muic {
compatible = "maxim,max77836-muic";
@ -246,7 +246,7 @@ s2mps14_pmic@66 {
interrupt-parent = <&gpx0>;
interrupts = <7 0>;
reg = <0x66>;
wakeup;
wakeup-source;
s2mps14_osc: clocks {
compatible = "samsung,s2mps14-clk";

5
arch/arm/boot/dts/exynos4.dtsi
View File

@ -76,6 +76,11 @@ chipid@10000000 {
reg = <0x10000000 0x100>;
};
sromc@12570000 {
compatible = "samsung,exynos-srom";
reg = <0x12570000 0x14>;
};
mipi_phy: video-phy@10020710 {
compatible = "samsung,s5pv210-mipi-video-phy";
#phy-cells = <1>;

10
arch/arm/boot/dts/exynos4210-origen.dts
View File

@ -60,35 +60,35 @@ up {
label = "Up";
gpios = <&gpx2 0 GPIO_ACTIVE_LOW>;
linux,code = <KEY_UP>;
gpio-key,wakeup;
wakeup-source;
};
down {
label = "Down";
gpios = <&gpx2 1 GPIO_ACTIVE_LOW>;
linux,code = <KEY_DOWN>;
gpio-key,wakeup;
wakeup-source;
};
back {
label = "Back";
gpios = <&gpx1 7 GPIO_ACTIVE_LOW>;
linux,code = <KEY_BACK>;
gpio-key,wakeup;
wakeup-source;
};
home {
label = "Home";
gpios = <&gpx1 6 GPIO_ACTIVE_LOW>;
linux,code = <KEY_HOME>;
gpio-key,wakeup;
wakeup-source;
};
menu {
label = "Menu";
gpios = <&gpx1 5 GPIO_ACTIVE_LOW>;
linux,code = <KEY_MENU>;
gpio-key,wakeup;
wakeup-source;
};
};

2
arch/arm/boot/dts/exynos4210-smdkv310.dts
View File

@ -66,7 +66,7 @@ &keypad {
samsung,keypad-num-rows = <2>;
samsung,keypad-num-columns = <8>;
linux,keypad-no-autorepeat;
linux,keypad-wakeup;
wakeup-source;
pinctrl-names = "default";
pinctrl-0 = <&keypad_rows &keypad_cols>;
status = "okay";

2
arch/arm/boot/dts/exynos4210-trats.dts
View File

@ -112,7 +112,7 @@ power-key {
linux,code = <116>;
label = "power";
debounce-interval = <10>;
gpio-key,wakeup;
wakeup-source;
};
ok-key {

4
arch/arm/boot/dts/exynos4210-universal_c210.dts
View File

@ -92,7 +92,7 @@ config-key {
linux,code = <171>;
label = "config";
debounce-interval = <1>;
gpio-key,wakeup;
wakeup-source;
};
camera-key {
@ -107,7 +107,7 @@ power-key {
linux,code = <116>;
label = "power";
debounce-interval = <1>;
gpio-key,wakeup;
wakeup-source;
};
ok-key {

2
arch/arm/boot/dts/exynos4412-odroid-common.dtsi
View File

@ -35,7 +35,7 @@ power_key {
linux,code = <KEY_POWER>;
label = "power key";
debounce-interval = <10>;
gpio-key,wakeup;
wakeup-source;
};
};

2
arch/arm/boot/dts/exynos4412-odroidx.dts
View File

@ -48,7 +48,7 @@ home_key {
linux,code = <KEY_HOME>;
label = "home key";
debounce-interval = <10>;
gpio-key,wakeup;
wakeup-source;
};
};

2
arch/arm/boot/dts/exynos4412-origen.dts
View File

@ -423,7 +423,7 @@ &keypad {
samsung,keypad-num-rows = <3>;
samsung,keypad-num-columns = <2>;
linux,keypad-no-autorepeat;
linux,keypad-wakeup;
wakeup-source;
pinctrl-0 = <&keypad_rows &keypad_cols>;
pinctrl-names = "default";
status = "okay";

2
arch/arm/boot/dts/exynos4412-smdk4412.dts
View File

@ -45,7 +45,7 @@ &keypad {
samsung,keypad-num-rows = <3>;
samsung,keypad-num-columns = <8>;
linux,keypad-no-autorepeat;
linux,keypad-wakeup;
wakeup-source;
pinctrl-0 = <&keypad_rows &keypad_cols>;
pinctrl-names = "default";
status = "okay";

4
arch/arm/boot/dts/exynos4412-trats2.dts
View File

@ -119,7 +119,7 @@ key-power {
linux,code = <116>;
label = "power";
debounce-interval = <10>;
gpio-key,wakeup;
wakeup-source;
};
key-ok {
@ -127,7 +127,7 @@ key-ok {
linux,code = <139>;
label = "ok";
debounce-inteval = <10>;
gpio-key,wakeup;
wakeup-source;
};
};

5
arch/arm/boot/dts/exynos5.dtsi
View File

@ -30,6 +30,11 @@ chipid@10000000 {
reg = <0x10000000 0x100>;
};
sromc@12250000 {
compatible = "samsung,exynos-srom";
reg = <0x12250000 0x14>;
};
combiner: interrupt-controller@10440000 {
compatible = "samsung,exynos4210-combiner";
#interrupt-cells = <2>;

12
arch/arm/boot/dts/exynos5250-arndale.dts
View File

@ -34,42 +34,42 @@ menu {
label = "SW-TACT2";
gpios = <&gpx1 4 GPIO_ACTIVE_LOW>;
linux,code = <KEY_MENU>;
gpio-key,wakeup;
wakeup-source;
};
home {
label = "SW-TACT3";
gpios = <&gpx1 5 GPIO_ACTIVE_LOW>;
linux,code = <KEY_HOME>;
gpio-key,wakeup;
wakeup-source;
};
up {
label = "SW-TACT4";
gpios = <&gpx1 6 GPIO_ACTIVE_LOW>;
linux,code = <KEY_UP>;
gpio-key,wakeup;
wakeup-source;
};
down {
label = "SW-TACT5";
gpios = <&gpx1 7 GPIO_ACTIVE_LOW>;
linux,code = <KEY_DOWN>;
gpio-key,wakeup;
wakeup-source;
};
back {
label = "SW-TACT6";
gpios = <&gpx2 0 GPIO_ACTIVE_LOW>;
linux,code = <KEY_BACK>;
gpio-key,wakeup;
wakeup-source;
};
wakeup {
label = "SW-TACT7";
gpios = <&gpx2 1 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WAKEUP>;
gpio-key,wakeup;
wakeup-source;
};
};

4
arch/arm/boot/dts/exynos5250-snow-common.dtsi
View File

@ -37,7 +37,7 @@ power {
label = "Power";
gpios = <&gpx1 3 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
gpio-key,wakeup;
wakeup-source;
};
lid-switch {
@ -46,7 +46,7 @@ lid-switch {
linux,input-type = <5>; /* EV_SW */
linux,code = <0>; /* SW_LID */
debounce-interval = <1>;
gpio-key,wakeup;
wakeup-source;
};
};

4
arch/arm/boot/dts/exynos5250-spring.dts
View File

@ -37,7 +37,7 @@ power {
label = "Power";
gpios = <&gpx1 3 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
gpio-key,wakeup;
wakeup-source;
};
lid-switch {
@ -46,7 +46,7 @@ lid-switch {
linux,input-type = <5>; /* EV_SW */
linux,code = <0>; /* SW_LID */
debounce-interval = <1>;
gpio-key,wakeup;
wakeup-source;
};
};

2
arch/arm/boot/dts/exynos5250.dtsi
View File

@ -807,7 +807,7 @@ adc: adc@12D10000 {
sss@10830000 {
compatible = "samsung,exynos4210-secss";
reg = <0x10830000 0x10000>;
reg = <0x10830000 0x300>;
interrupts = <0 112 0>;
clocks = <&clock CLK_SSS>;
clock-names = "secss";

406
arch/arm/boot/dts/exynos5410-pinctrl.dtsi Normal file
View File

@ -0,0 +1,406 @@
/*
* Exynos5410 SoC pin-mux and pin-config device tree source
*
* Copyright (c) 2013 Hardkernel Co., Ltd.
* http://www.hardkernel.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
&pinctrl_0 {
gpa0: gpa0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpa1: gpa1 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpa2: gpa2 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpb0: gpb0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpb1: gpb1 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpb2: gpb2 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpb3: gpb3 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpc0: gpc0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpc3: gpc3 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpc1: gpc1 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpc2: gpc2 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpm5: gpm5 {
gpio-controller;
#gpio-cells = <2>;
};
gpd1: gpd1 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpe0: gpe0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpe1: gpe1 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpf0: gpf0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpf1: gpf1 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpg0: gpg0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpg1: gpg1 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpg2: gpg2 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gph0: gph0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gph1: gph1 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpm7: gpm7 {
gpio-controller;
#gpio-cells = <2>;
};
gpy0: gpy0 {
gpio-controller;
#gpio-cells = <2>;
};
gpy1: gpy1 {
gpio-controller;
#gpio-cells = <2>;
};
gpy2: gpy2 {
gpio-controller;
#gpio-cells = <2>;
};
gpy3: gpy3 {
gpio-controller;
#gpio-cells = <2>;
};
gpy4: gpy4 {
gpio-controller;
#gpio-cells = <2>;
};
gpy5: gpy5 {
gpio-controller;
#gpio-cells = <2>;
};
gpy6: gpy6 {
gpio-controller;
#gpio-cells = <2>;
};
gpy7: gpy7 {
gpio-controller;
#gpio-cells = <2>;
};
gpx0: gpx0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
interrupt-parent = <&combiner>;
#interrupt-cells = <2>;
interrupts = <23 0>,
<24 0>,
<25 0>,
<25 1>,
<26 0>,
<26 1>,
<27 0>,
<27 1>;
};
gpx1: gpx1 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
interrupt-parent = <&combiner>;
#interrupt-cells = <2>;
interrupts = <28 0>,
<28 1>,
<29 0>,
<29 1>,
<30 0>,
<30 1>,
<31 0>,
<31 1>;
};
gpx2: gpx2 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpx3: gpx3 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
&pinctrl_1 {
gpj0: gpj0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpj1: gpj1 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpj2: gpj2 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpj3: gpj3 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpj4: gpj4 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpk0: gpk0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpk1: gpk1 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpk2: gpk2 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpk3: gpk3 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
&pinctrl_2 {
gpv0: gpv0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpv1: gpv1 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpv2: gpv2 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpv3: gpv3 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpv4: gpv4 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
&pinctrl_3 {
gpz: gpz {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};

41
arch/arm/boot/dts/exynos5410-smdk5410.dts
View File

@ -11,6 +11,7 @@
/dts-v1/;
#include "exynos5410.dtsi"
#include <dt-bindings/interrupt-controller/irq.h>
/ {
model = "Samsung SMDK5410 board based on EXYNOS5410";
compatible = "samsung,smdk5410", "samsung,exynos5410", "samsung,exynos5";
@ -61,6 +62,46 @@ &mmc_2 {
disable-wp;
};
&pinctrl_0 {
srom_ctl: srom-ctl {
samsung,pins = "gpy0-3", "gpy0-4", "gpy0-5",
"gpy1-0", "gpy1-1", "gpy1-2", "gpy1-3";
samsung,pin-function = <2>;
samsung,pin-drv = <0>;
};
srom_ebi: srom-ebi {
samsung,pins = "gpy3-0", "gpy3-1", "gpy3-2", "gpy3-3",
"gpy3-4", "gpy3-5", "gpy3-6", "gpy3-7",
"gpy5-0", "gpy5-1", "gpy5-2", "gpy5-3",
"gpy5-4", "gpy5-5", "gpy5-6", "gpy5-7",
"gpy6-0", "gpy6-1", "gpy6-2", "gpy6-3",
"gpy6-4", "gpy6-5", "gpy6-6", "gpy6-7";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
};
&sromc {
pinctrl-names = "default";
pinctrl-0 = <&srom_ctl>, <&srom_ebi>;
ethernet@3,0 {
compatible = "smsc,lan9115";
reg = <3 0 0x10000>;
phy-mode = "mii";
interrupt-parent = <&gpx0>;
interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
reg-io-width = <2>;
smsc,irq-push-pull;
smsc,force-internal-phy;
samsung,srom-page-mode = <1>;
samsung,srom-timing = <9 12 1 9 1 1>;
};
};
&uart0 {
status = "okay";
};

47
arch/arm/boot/dts/exynos5410.dtsi
View File

@ -21,6 +21,10 @@ / {
interrupt-parent = <&gic>;
aliases {
pinctrl0 = &pinctrl_0;
pinctrl1 = &pinctrl_1;
pinctrl2 = &pinctrl_2;
pinctrl3 = &pinctrl_3;
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
@ -97,6 +101,17 @@ chipid@10000000 {
reg = <0x10000000 0x100>;
};
sromc: sromc@12250000 {
compatible = "samsung,exynos-srom";
reg = <0x12250000 0x14>;
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0x04000000 0x20000
1 0 0x05000000 0x20000
2 0 0x06000000 0x20000
3 0 0x07000000 0x20000>;
};
pmu_system_controller: system-controller@10040000 {
compatible = "samsung,exynos5410-pmu", "syscon";
reg = <0x10040000 0x5000>;
@ -205,6 +220,36 @@ mmc_2: mmc@12220000 {
status = "disabled";
};
pinctrl_0: pinctrl@13400000 {
compatible = "samsung,exynos5410-pinctrl";
reg = <0x13400000 0x1000>;
interrupts = <0 45 0>;
wakeup-interrupt-controller {
compatible = "samsung,exynos4210-wakeup-eint";
interrupt-parent = <&gic>;
interrupts = <0 32 0>;
};
};
pinctrl_1: pinctrl@14000000 {
compatible = "samsung,exynos5410-pinctrl";
reg = <0x14000000 0x1000>;
interrupts = <0 46 0>;
};
pinctrl_2: pinctrl@10d10000 {
compatible = "samsung,exynos5410-pinctrl";
reg = <0x10d10000 0x1000>;
interrupts = <0 50 0>;
};
pinctrl_3: pinctrl@03860000 {
compatible = "samsung,exynos5410-pinctrl";
reg = <0x03860000 0x1000>;
interrupts = <0 47 0>;
};
uart0: serial@12C00000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C00000 0x100>;
@ -233,3 +278,5 @@ uart2: serial@12C20000 {
};
};
};
#include "exynos5410-pinctrl.dtsi"

11
arch/arm/boot/dts/exynos5420-arndale-octa.dts
View File

@ -11,6 +11,7 @@
/dts-v1/;
#include "exynos5420.dtsi"
#include "exynos5420-cpus.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/input/input.h>
@ -47,11 +48,19 @@ wakeup {
label = "SW-TACT1";
gpios = <&gpx2 7 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WAKEUP>;
gpio-key,wakeup;
wakeup-source;
};
};
};
&cpu0 {
cpu-supply = <&buck2_reg>;
};
&cpu4 {
cpu-supply = <&buck6_reg>;
};
&usbdrd_dwc3_1 {
dr_mode = "host";
};

102
arch/arm/boot/dts/exynos5420-cpus.dtsi Normal file
View File

@ -0,0 +1,102 @@
/*
* SAMSUNG EXYNOS5420 SoC cpu device tree source
*
* Copyright (c) 2015 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* This file provides desired ordering for Exynos5420 and Exynos5800
* boards: CPU[0123] being the A15.
*
* The Exynos5420, 5422 and 5800 actually share the same CPU configuration
* but particular boards choose different booting order.
*
* Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
* booting cluster (big or LITTLE) is chosen by IROM code by reading
* the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
* from the LITTLE: Cortex-A7.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x0>;
clocks = <&clock CLK_ARM_CLK>;
clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>;
operating-points-v2 = <&cluster_a15_opp_table>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x1>;
clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>;
operating-points-v2 = <&cluster_a15_opp_table>;
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x2>;
clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>;
operating-points-v2 = <&cluster_a15_opp_table>;
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x3>;
clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>;
operating-points-v2 = <&cluster_a15_opp_table>;
};
cpu4: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x100>;
clocks = <&clock CLK_KFC_CLK>;
clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>;
operating-points-v2 = <&cluster_a7_opp_table>;
};
cpu5: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x101>;
clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>;
operating-points-v2 = <&cluster_a7_opp_table>;
};
cpu6: cpu@102 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x102>;
clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>;
operating-points-v2 = <&cluster_a7_opp_table>;
};
cpu7: cpu@103 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x103>;
clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>;
operating-points-v2 = <&cluster_a7_opp_table>;
};
};
};

13
arch/arm/boot/dts/exynos5420-peach-pit.dts
View File

@ -15,6 +15,7 @@
#include <dt-bindings/clock/maxim,max77802.h>
#include <dt-bindings/regulator/maxim,max77802.h>
#include "exynos5420.dtsi"
#include "exynos5420-cpus.dtsi"
/ {
model = "Google Peach Pit Rev 6+";
@ -64,7 +65,7 @@ power {
label = "Power";
gpios = <&gpx1 2 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
gpio-key,wakeup;
wakeup-source;
};
lid-switch {
@ -73,7 +74,7 @@ lid-switch {
linux,input-type = <5>; /* EV_SW */
linux,code = <0>; /* SW_LID */
debounce-interval = <1>;
gpio-key,wakeup;
wakeup-source;
};
};
@ -143,6 +144,14 @@ &adc {
vdd-supply = <&ldo9_reg>;
};
&cpu0 {
cpu-supply = <&buck2_reg>;
};
&cpu4 {
cpu-supply = <&buck6_reg>;
};
&dp {
status = "okay";
pinctrl-names = "default";

9
arch/arm/boot/dts/exynos5420-smdk5420.dts
View File

@ -11,6 +11,7 @@
/dts-v1/;
#include "exynos5420.dtsi"
#include "exynos5420-cpus.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
@ -89,6 +90,14 @@ usb301_vbus_reg: regulator-usb301 {
};
&cpu0 {
cpu-supply = <&buck2_reg>;
};
&cpu4 {
cpu-supply = <&buck6_reg>;
};
&dp {
pinctrl-names = "default";
pinctrl-0 = <&dp_hpd>;

172
arch/arm/boot/dts/exynos5420.dtsi
View File

@ -50,75 +50,121 @@ aliases {
usbdrdphy1 = &usbdrd_phy1;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x0>;
clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>;
cluster_a15_opp_table: opp_table0 {
compatible = "operating-points-v2";
opp-shared;
opp@1800000000 {
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <1250000>;
clock-latency-ns = <140000>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x1>;
clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>;
opp@1700000000 {
opp-hz = /bits/ 64 <1700000000>;
opp-microvolt = <1212500>;
clock-latency-ns = <140000>;
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x2>;
clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>;
opp@1600000000 {
opp-hz = /bits/ 64 <1600000000>;
opp-microvolt = <1175000>;
clock-latency-ns = <140000>;
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x3>;
clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>;
opp@1500000000 {
opp-hz = /bits/ 64 <1500000000>;
opp-microvolt = <1137500>;
clock-latency-ns = <140000>;
};
cpu4: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x100>;
clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>;
opp@1400000000 {
opp-hz = /bits/ 64 <1400000000>;
opp-microvolt = <1112500>;
clock-latency-ns = <140000>;
};
cpu5: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x101>;
clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>;
opp@1300000000 {
opp-hz = /bits/ 64 <1300000000>;
opp-microvolt = <1062500>;
clock-latency-ns = <140000>;
};
cpu6: cpu@102 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x102>;
clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>;
opp@1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <1037500>;
clock-latency-ns = <140000>;
};
cpu7: cpu@103 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x103>;
clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>;
opp@1100000000 {
opp-hz = /bits/ 64 <1100000000>;
opp-microvolt = <1012500>;
clock-latency-ns = <140000>;
};
opp@1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = < 987500>;
clock-latency-ns = <140000>;
};
opp@900000000 {
opp-hz = /bits/ 64 <900000000>;
opp-microvolt = < 962500>;
clock-latency-ns = <140000>;
};
opp@800000000 {
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = < 937500>;
clock-latency-ns = <140000>;
};
opp@700000000 {
opp-hz = /bits/ 64 <700000000>;
opp-microvolt = < 912500>;
clock-latency-ns = <140000>;
};
};
cluster_a7_opp_table: opp_table1 {
compatible = "operating-points-v2";
opp-shared;
opp@1300000000 {
opp-hz = /bits/ 64 <1300000000>;
opp-microvolt = <1275000>;
clock-latency-ns = <140000>;
};
opp@1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <1212500>;
clock-latency-ns = <140000>;
};
opp@1100000000 {
opp-hz = /bits/ 64 <1100000000>;
opp-microvolt = <1162500>;
clock-latency-ns = <140000>;
};
opp@1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <1112500>;
clock-latency-ns = <140000>;
};
opp@900000000 {
opp-hz = /bits/ 64 <900000000>;
opp-microvolt = <1062500>;
clock-latency-ns = <140000>;
};
opp@800000000 {
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = <1025000>;
clock-latency-ns = <140000>;
};
opp@700000000 {
opp-hz = /bits/ 64 <700000000>;
opp-microvolt = <975000>;
clock-latency-ns = <140000>;
};
opp@600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <937500>;
clock-latency-ns = <140000>;
};
};
/*
* The 'cpus' node is not present here but instead it is provided
* by exynos5420-cpus.dtsi or exynos5422-cpus.dtsi.
*/
cci: cci@10d20000 {
compatible = "arm,cci-400";
#address-cells = <1>;
@ -252,8 +298,10 @@ gsc_pd: power-domain@10044000 {
compatible = "samsung,exynos4210-pd";
reg = <0x10044000 0x20>;
#power-domain-cells = <0>;
clocks = <&clock CLK_GSCL0>, <&clock CLK_GSCL1>;
clock-names = "asb0", "asb1";
clocks = <&clock CLK_FIN_PLL>,
<&clock CLK_MOUT_USER_ACLK300_GSCL>,
<&clock CLK_GSCL0>, <&clock CLK_GSCL1>;
clock-names = "oscclk", "clk0", "asb0", "asb1";
};
isp_pd: power-domain@10044020 {
@ -859,7 +907,7 @@ watchdog: watchdog@101D0000 {
sss: sss@10830000 {
compatible = "samsung,exynos4210-secss";
reg = <0x10830000 0x10000>;
reg = <0x10830000 0x300>;
interrupts = <0 112 0>;
clocks = <&clock CLK_SSS>;
clock-names = "secss";

140
arch/arm/boot/dts/exynos5422-cpus.dtsi
View File

@ -4,78 +4,98 @@
* Copyright (c) 2015 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* The only difference between EXYNOS5422 and EXYNOS5800 is cpu ordering. The
* EXYNOS5422 is booting from Cortex-A7 core while the EXYNOS5800 is booting
* from Cortex-A15 core.
* This file provides desired ordering for Exynos5422: CPU[0123] being the A7.
*
* EXYNOS5422 based board files can include this file to provide cpu ordering
* which could boot a cortex-a7 from cpu0.
* The Exynos5420, 5422 and 5800 actually share the same CPU configuration
* but particular boards choose different booting order.
*
* Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
* booting cluster (big or LITTLE) is chosen by IROM code by reading
* the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
* from the LITTLE: Cortex-A7.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
&cpu0 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x100>;
clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>;
};
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
&cpu1 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x101>;
clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>;
};
cpu0: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x100>;
clocks = <&clock CLK_KFC_CLK>;
clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>;
operating-points-v2 = <&cluster_a7_opp_table>;
};
&cpu2 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x102>;
clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>;
};
cpu1: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x101>;
clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>;
operating-points-v2 = <&cluster_a7_opp_table>;
};
&cpu3 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x103>;
clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>;
};
cpu2: cpu@102 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x102>;
clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>;
operating-points-v2 = <&cluster_a7_opp_table>;
};
&cpu4 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x0>;
clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>;
};
cpu3: cpu@103 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x103>;
clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>;
operating-points-v2 = <&cluster_a7_opp_table>;
};
&cpu5 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x1>;
clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>;
};
cpu4: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a15";
clocks = <&clock CLK_ARM_CLK>;
reg = <0x0>;
clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>;
operating-points-v2 = <&cluster_a15_opp_table>;
};
&cpu6 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x2>;
clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>;
};
cpu5: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x1>;
clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>;
operating-points-v2 = <&cluster_a15_opp_table>;
};
&cpu7 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x3>;
clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>;
cpu6: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x2>;
clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>;
operating-points-v2 = <&cluster_a15_opp_table>;
};
cpu7: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x3>;
clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>;
operating-points-v2 = <&cluster_a15_opp_table>;
};
};
};

8
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
View File

@ -67,6 +67,14 @@ &clock_audss {
<19200000>;
};
&cpu0 {
cpu-supply = <&buck6_reg>;
};
&cpu4 {
cpu-supply = <&buck2_reg>;
};
&hdmi {
status = "okay";
hpd-gpio = <&gpx3 7 GPIO_ACTIVE_HIGH>;

13
arch/arm/boot/dts/exynos5800-peach-pi.dts
View File

@ -15,6 +15,7 @@
#include <dt-bindings/clock/maxim,max77802.h>
#include <dt-bindings/regulator/maxim,max77802.h>
#include "exynos5800.dtsi"
#include "exynos5420-cpus.dtsi"
/ {
model = "Google Peach Pi Rev 10+";
@ -63,7 +64,7 @@ power {
label = "Power";
gpios = <&gpx1 2 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
gpio-key,wakeup;
wakeup-source;
};
lid-switch {
@ -72,7 +73,7 @@ lid-switch {
linux,input-type = <5>; /* EV_SW */
linux,code = <0>; /* SW_LID */
debounce-interval = <1>;
gpio-key,wakeup;
wakeup-source;
};
};
@ -143,6 +144,14 @@ &adc {
vdd-supply = <&ldo9_reg>;
};
&cpu0 {
cpu-supply = <&buck2_reg>;
};
&cpu4 {
cpu-supply = <&buck6_reg>;
};
&dp {
status = "okay";
pinctrl-names = "default";

108
arch/arm/boot/dts/exynos5800.dtsi
View File

@ -23,6 +23,114 @@ &clock {
compatible = "samsung,exynos5800-clock";
};
&cluster_a15_opp_table {
opp@1700000000 {
opp-microvolt = <1250000>;
};
opp@1600000000 {
opp-microvolt = <1250000>;
};
opp@1500000000 {
opp-microvolt = <1100000>;
};
opp@1400000000 {
opp-microvolt = <1100000>;
};
opp@1300000000 {
opp-microvolt = <1100000>;
};
opp@1200000000 {
opp-microvolt = <1000000>;
};
opp@1100000000 {
opp-microvolt = <1000000>;
};
opp@1000000000 {
opp-microvolt = <1000000>;
};
opp@900000000 {
opp-microvolt = <1000000>;
};
opp@800000000 {
opp-microvolt = <900000>;
};
opp@700000000 {
opp-microvolt = <900000>;
};
opp@600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <900000>;
clock-latency-ns = <140000>;
};
opp@500000000 {
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <900000>;
clock-latency-ns = <140000>;
};
opp@400000000 {
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <900000>;
clock-latency-ns = <140000>;
};
opp@300000000 {
opp-hz = /bits/ 64 <300000000>;
opp-microvolt = <900000>;
clock-latency-ns = <140000>;
};
opp@200000000 {
opp-hz = /bits/ 64 <200000000>;
opp-microvolt = <900000>;
clock-latency-ns = <140000>;
};
};
&cluster_a7_opp_table {
opp@1300000000 {
opp-microvolt = <1250000>;
};
opp@1200000000 {
opp-microvolt = <1250000>;
};
opp@1100000000 {
opp-microvolt = <1250000>;
};
opp@1000000000 {
opp-microvolt = <1100000>;
};
opp@900000000 {
opp-microvolt = <1100000>;
};
opp@800000000 {
opp-microvolt = <1100000>;
};
opp@700000000 {
opp-microvolt = <1000000>;
};
opp@600000000 {
opp-microvolt = <1000000>;
};
opp@500000000 {
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <1000000>;
clock-latency-ns = <140000>;
};
opp@400000000 {
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <1000000>;
clock-latency-ns = <140000>;
};
opp@300000000 {
opp-hz = /bits/ 64 <300000000>;
opp-microvolt = <900000>;
clock-latency-ns = <140000>;
};
opp@200000000 {
opp-hz = /bits/ 64 <200000000>;
opp-microvolt = <900000>;
clock-latency-ns = <140000>;
};
};
&mfc {
compatible = "samsung,mfc-v8";
};

4
arch/arm/boot/dts/s5pv210-aquila.dts
View File

@ -257,7 +257,7 @@ power-key {
linux,code = <KEY_POWER>;
label = "power";
debounce-interval = <1>;
gpio-key,wakeup;
wakeup-source;
};
};
};
@ -268,7 +268,7 @@ &xusbxti {
&keypad {
linux,input-no-autorepeat;
linux,input-wakeup;
wakeup-source;
samsung,keypad-num-rows = <3>;
samsung,keypad-num-columns = <3>;
pinctrl-names = "default";

4
arch/arm/boot/dts/s5pv210-goni.dts
View File

@ -239,7 +239,7 @@ power-key {
linux,code = <KEY_POWER>;
label = "power";
debounce-interval = <1>;
gpio-key,wakeup;
wakeup-source;
};
};
};
@ -250,7 +250,7 @@ &xusbxti {
&keypad {
linux,input-no-autorepeat;
linux,input-wakeup;
wakeup-source;
samsung,keypad-num-rows = <3>;
samsung,keypad-num-columns = <3>;
pinctrl-names = "default";

2
arch/arm/boot/dts/s5pv210-smdkv210.dts
View File

@ -59,7 +59,7 @@ &xusbxti {
&keypad {
linux,input-no-autorepeat;
linux,input-wakeup;
wakeup-source;
samsung,keypad-num-rows = <8>;
samsung,keypad-num-columns = <8>;
pinctrl-names = "default";