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ARM: dts: socfpga: add the clk-phase property for sd/mmc clock 

The CIU clock for the SD/MMC should be the sdmmc_clk and not the
sdmmc_free_clk. Also, add the correct phase shift the sdmmc_clk.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
This commit is contained in:
Dinh Nguyen 2016-01-05 14:59:38 -06:00 committed by Dinh Nguyen
parent d07e187cf0
commit faf68cdfdf
1 changed files with 2 additions and 1 deletions
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3
arch/arm/boot/dts/socfpga_arria10.dtsi
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@ -362,6 +362,7 @@ sdmmc_clk: sdmmc_clk {
compatible = "altr,socfpga-a10-gate-clk"; compatible = "altr,socfpga-a10-gate-clk";
clocks = <&sdmmc_free_clk>; clocks = <&sdmmc_free_clk>;
clk-gate = <0xC8 5>; clk-gate = <0xC8 5>;
clk-phase = <0 135>;
}; };
qspi_clk: qspi_clk { qspi_clk: qspi_clk {
@ -589,7 +590,7 @@ mmc: dwmmc0@ff808000 {
reg = <0xff808000 0x1000>; reg = <0xff808000 0x1000>;
interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
fifo-depth = <0x400>; fifo-depth = <0x400>;
clocks = <&l4_mp_clk>, <&sdmmc_free_clk>; clocks = <&l4_mp_clk>, <&sdmmc_clk>;
clock-names = "biu", "ciu"; clock-names = "biu", "ciu";
status = "disabled"; status = "disabled";
}; };