mirror of https://gitee.com/openkylin/linux.git
drm/amdgpu/gfx8: add state setup for CZ/ST GFX power gating
This sets up the CP jump table and GDS buffer and sets the PG state registers. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher
parent
9406d216fe
commit
fb16007bf0
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@ -1150,6 +1150,71 @@ static void gfx_v8_0_get_csb_buffer(struct amdgpu_device *adev,
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buffer[count++] = cpu_to_le32(0);
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}
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static void cz_init_cp_jump_table(struct amdgpu_device *adev)
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{
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const __le32 *fw_data;
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volatile u32 *dst_ptr;
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int me, i, max_me = 4;
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u32 bo_offset = 0;
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u32 table_offset, table_size;
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if (adev->asic_type == CHIP_CARRIZO)
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max_me = 5;
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/* write the cp table buffer */
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dst_ptr = adev->gfx.rlc.cp_table_ptr;
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for (me = 0; me < max_me; me++) {
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if (me == 0) {
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const struct gfx_firmware_header_v1_0 *hdr =
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(const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
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fw_data = (const __le32 *)
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(adev->gfx.ce_fw->data +
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le32_to_cpu(hdr->header.ucode_array_offset_bytes));
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table_offset = le32_to_cpu(hdr->jt_offset);
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table_size = le32_to_cpu(hdr->jt_size);
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} else if (me == 1) {
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const struct gfx_firmware_header_v1_0 *hdr =
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(const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
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fw_data = (const __le32 *)
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(adev->gfx.pfp_fw->data +
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le32_to_cpu(hdr->header.ucode_array_offset_bytes));
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table_offset = le32_to_cpu(hdr->jt_offset);
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table_size = le32_to_cpu(hdr->jt_size);
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} else if (me == 2) {
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const struct gfx_firmware_header_v1_0 *hdr =
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(const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
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fw_data = (const __le32 *)
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(adev->gfx.me_fw->data +
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le32_to_cpu(hdr->header.ucode_array_offset_bytes));
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table_offset = le32_to_cpu(hdr->jt_offset);
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table_size = le32_to_cpu(hdr->jt_size);
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} else if (me == 3) {
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const struct gfx_firmware_header_v1_0 *hdr =
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(const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
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fw_data = (const __le32 *)
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(adev->gfx.mec_fw->data +
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le32_to_cpu(hdr->header.ucode_array_offset_bytes));
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table_offset = le32_to_cpu(hdr->jt_offset);
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table_size = le32_to_cpu(hdr->jt_size);
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} else if (me == 4) {
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const struct gfx_firmware_header_v1_0 *hdr =
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(const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
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fw_data = (const __le32 *)
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(adev->gfx.mec2_fw->data +
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le32_to_cpu(hdr->header.ucode_array_offset_bytes));
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table_offset = le32_to_cpu(hdr->jt_offset);
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table_size = le32_to_cpu(hdr->jt_size);
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}
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for (i = 0; i < table_size; i ++) {
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dst_ptr[bo_offset + i] =
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cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
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}
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bo_offset += table_size;
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}
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}
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static void gfx_v8_0_rlc_fini(struct amdgpu_device *adev)
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{
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int r;
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@ -1165,6 +1230,18 @@ static void gfx_v8_0_rlc_fini(struct amdgpu_device *adev)
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amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj);
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adev->gfx.rlc.clear_state_obj = NULL;
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}
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/* jump table block */
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if (adev->gfx.rlc.cp_table_obj) {
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r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false);
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if (unlikely(r != 0))
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dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r);
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amdgpu_bo_unpin(adev->gfx.rlc.cp_table_obj);
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amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
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amdgpu_bo_unref(&adev->gfx.rlc.cp_table_obj);
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adev->gfx.rlc.cp_table_obj = NULL;
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}
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}
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static int gfx_v8_0_rlc_init(struct amdgpu_device *adev)
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@ -1221,6 +1298,46 @@ static int gfx_v8_0_rlc_init(struct amdgpu_device *adev)
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amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
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}
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if ((adev->asic_type == CHIP_CARRIZO) ||
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(adev->asic_type == CHIP_STONEY)) {
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adev->gfx.rlc.cp_table_size = (96 * 5 * 4) + (64 * 1024); /* JT + GDS */
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if (adev->gfx.rlc.cp_table_obj == NULL) {
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r = amdgpu_bo_create(adev, adev->gfx.rlc.cp_table_size, PAGE_SIZE, true,
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AMDGPU_GEM_DOMAIN_VRAM,
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AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
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NULL, NULL,
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&adev->gfx.rlc.cp_table_obj);
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if (r) {
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dev_warn(adev->dev, "(%d) create RLC cp table bo failed\n", r);
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return r;
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}
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}
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r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false);
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if (unlikely(r != 0)) {
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dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r);
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return r;
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}
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r = amdgpu_bo_pin(adev->gfx.rlc.cp_table_obj, AMDGPU_GEM_DOMAIN_VRAM,
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&adev->gfx.rlc.cp_table_gpu_addr);
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if (r) {
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amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
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dev_warn(adev->dev, "(%d) pin RLC cp_table bo failed\n", r);
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return r;
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}
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r = amdgpu_bo_kmap(adev->gfx.rlc.cp_table_obj, (void **)&adev->gfx.rlc.cp_table_ptr);
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if (r) {
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dev_warn(adev->dev, "(%d) map RLC cp table bo failed\n", r);
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return r;
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}
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cz_init_cp_jump_table(adev);
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amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj);
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amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
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}
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return 0;
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}
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@ -3683,13 +3800,13 @@ static void gfx_v8_0_enable_save_restore_machine(struct amdgpu_device *adev)
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WREG32(mmRLC_SRM_CNTL, data);
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}
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static void polaris11_init_power_gating(struct amdgpu_device *adev)
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static void gfx_v8_0_init_power_gating(struct amdgpu_device *adev)
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{
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uint32_t data;
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if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
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AMD_PG_SUPPORT_GFX_SMG |
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AMD_PG_SUPPORT_GFX_DMG)) {
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AMD_PG_SUPPORT_GFX_SMG |
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AMD_PG_SUPPORT_GFX_DMG)) {
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data = RREG32(mmCP_RB_WPTR_POLL_CNTL);
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data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK;
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data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
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@ -3726,8 +3843,14 @@ static void gfx_v8_0_init_pg(struct amdgpu_device *adev)
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gfx_v8_0_init_save_restore_list(adev);
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gfx_v8_0_enable_save_restore_machine(adev);
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if (adev->asic_type == CHIP_POLARIS11)
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polaris11_init_power_gating(adev);
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if ((adev->asic_type == CHIP_CARRIZO) ||
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(adev->asic_type == CHIP_STONEY)) {
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WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8);
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gfx_v8_0_init_power_gating(adev);
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WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask);
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} else if (adev->asic_type == CHIP_POLARIS11) {
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gfx_v8_0_init_power_gating(adev);
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}
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}
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}
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