mirror of https://gitee.com/openkylin/linux.git
OMAP1: clock: some cleanup
Convert most of the magic numbers in mach-omap1/clock_data.c to use macros. Clean up a few comments to conform with Documentation/CodingStyle. Mark the current clkops_uart as being OMAP16xx-only, and add some comments to indicate that it does not belong there, for future cleanup. This patch should not cause any functional changes. Signed-off-by: Paul Walmsley <paul@pwsan.com>
This commit is contained in:
Paul Walmsley
parent
936305a96c
commit
fb2fc9204f
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@ -11,7 +11,6 @@
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/list.h>
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#include <linux/errno.h>
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@ -34,9 +33,9 @@
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__u32 arm_idlect1_mask;
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struct clk *api_ck_p, *ck_dpll1_p, *ck_ref_p;
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/*-------------------------------------------------------------------------
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/*
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* Omap1 specific clock functions
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*-------------------------------------------------------------------------*/
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*/
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unsigned long omap1_uart_recalc(struct clk *clk)
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{
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@ -523,7 +522,8 @@ const struct clkops clkops_dspck = {
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.disable = omap1_clk_disable_dsp_domain,
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};
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static int omap1_clk_enable_uart_functional(struct clk *clk)
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/* XXX SYSC register handling does not belong in the clock framework */
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static int omap1_clk_enable_uart_functional_16xx(struct clk *clk)
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{
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int ret;
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struct uart_clk *uclk;
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@ -539,7 +539,8 @@ static int omap1_clk_enable_uart_functional(struct clk *clk)
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return ret;
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}
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static void omap1_clk_disable_uart_functional(struct clk *clk)
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/* XXX SYSC register handling does not belong in the clock framework */
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static void omap1_clk_disable_uart_functional_16xx(struct clk *clk)
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{
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struct uart_clk *uclk;
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@ -550,9 +551,10 @@ static void omap1_clk_disable_uart_functional(struct clk *clk)
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omap1_clk_disable_generic(clk);
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}
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const struct clkops clkops_uart = {
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.enable = omap1_clk_enable_uart_functional,
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.disable = omap1_clk_disable_uart_functional,
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/* XXX SYSC register handling does not belong in the clock framework */
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const struct clkops clkops_uart_16xx = {
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.enable = omap1_clk_enable_uart_functional_16xx,
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.disable = omap1_clk_disable_uart_functional_16xx,
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};
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long omap1_clk_round_rate(struct clk *clk, unsigned long rate)
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@ -572,9 +574,9 @@ int omap1_clk_set_rate(struct clk *clk, unsigned long rate)
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return ret;
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}
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/*-------------------------------------------------------------------------
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/*
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* Omap1 clock reset and init functions
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*-------------------------------------------------------------------------*/
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*/
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#ifdef CONFIG_OMAP_RESET_CLOCKS
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@ -107,7 +107,7 @@ extern struct clk *api_ck_p, *ck_dpll1_p, *ck_ref_p;
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extern const struct clkops clkops_dspck;
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extern const struct clkops clkops_dummy;
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extern const struct clkops clkops_uart;
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extern const struct clkops clkops_uart_16xx;
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extern const struct clkops clkops_generic;
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#endif
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@ -8,6 +8,10 @@
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* To do:
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* - Clocks that are only available on some chips should be marked with the
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* chips that they are present on.
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*/
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#include <linux/kernel.h>
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@ -23,9 +27,49 @@
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#include "clock.h"
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/*------------------------------------------------------------------------
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/* Some ARM_IDLECT1 bit shifts - used in struct arm_idlect1_clk */
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#define IDL_CLKOUT_ARM_SHIFT 12
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#define IDLTIM_ARM_SHIFT 9
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#define IDLAPI_ARM_SHIFT 8
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#define IDLIF_ARM_SHIFT 6
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#define IDLLB_ARM_SHIFT 4 /* undocumented? */
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#define OMAP1510_IDLLCD_ARM_SHIFT 3 /* undocumented? */
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#define IDLPER_ARM_SHIFT 2
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#define IDLXORP_ARM_SHIFT 1
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#define IDLWDT_ARM_SHIFT 0
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/* Some MOD_CONF_CTRL_0 bit shifts - used in struct clk.enable_bit */
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#define CONF_MOD_UART3_CLK_MODE_R 31
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#define CONF_MOD_UART2_CLK_MODE_R 30
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#define CONF_MOD_UART1_CLK_MODE_R 29
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#define CONF_MOD_MMC_SD_CLK_REQ_R 23
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#define CONF_MOD_MCBSP3_AUXON 20
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/* Some MOD_CONF_CTRL_1 bit shifts - used in struct clk.enable_bit */
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#define CONF_MOD_SOSSI_CLK_EN_R 16
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/* Some OTG_SYSCON_2-specific bit fields */
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#define OTG_SYSCON_2_UHOST_EN_SHIFT 8
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/* Some SOFT_REQ_REG bit fields - used in struct clk.enable_bit */
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#define SOFT_MMC2_DPLL_REQ_SHIFT 13
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#define SOFT_MMC_DPLL_REQ_SHIFT 12
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#define SOFT_UART3_DPLL_REQ_SHIFT 11
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#define SOFT_UART2_DPLL_REQ_SHIFT 10
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#define SOFT_UART1_DPLL_REQ_SHIFT 9
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#define SOFT_USB_OTG_DPLL_REQ_SHIFT 8
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#define SOFT_CAM_DPLL_REQ_SHIFT 7
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#define SOFT_COM_MCKO_REQ_SHIFT 6
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#define SOFT_PERIPH_REQ_SHIFT 5 /* sys_ck gate for UART2 ? */
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#define USB_REQ_EN_SHIFT 4
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#define SOFT_USB_REQ_SHIFT 3 /* sys_ck gate for USB host? */
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#define SOFT_SDW_REQ_SHIFT 2 /* sys_ck gate for Bluetooth? */
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#define SOFT_COM_REQ_SHIFT 1 /* sys_ck gate for com proc? */
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#define SOFT_DPLL_REQ_SHIFT 0
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/*
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* Omap1 clocks
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*-------------------------------------------------------------------------*/
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*/
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static struct clk ck_ref = {
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.name = "ck_ref",
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@ -54,7 +98,7 @@ static struct arm_idlect1_clk ck_dpll1out = {
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.enable_bit = EN_CKOUT_ARM,
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.recalc = &followparent_recalc,
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},
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.idlect_shift = 12,
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.idlect_shift = IDL_CLKOUT_ARM_SHIFT,
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};
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static struct clk sossi_ck = {
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@ -63,7 +107,7 @@ static struct clk sossi_ck = {
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.parent = &ck_dpll1out.clk,
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.flags = CLOCK_NO_IDLE_PARENT | ENABLE_REG_32BIT,
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.enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1),
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.enable_bit = 16,
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.enable_bit = CONF_MOD_SOSSI_CLK_EN_R,
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.recalc = &omap1_sossi_recalc,
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.set_rate = &omap1_set_sossi_rate,
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};
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@ -91,7 +135,7 @@ static struct arm_idlect1_clk armper_ck = {
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.round_rate = omap1_clk_round_rate_ckctl_arm,
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.set_rate = omap1_clk_set_rate_ckctl_arm,
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},
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.idlect_shift = 2,
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.idlect_shift = IDLPER_ARM_SHIFT,
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};
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/*
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@ -118,7 +162,7 @@ static struct arm_idlect1_clk armxor_ck = {
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.enable_bit = EN_XORPCK,
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.recalc = &followparent_recalc,
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},
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.idlect_shift = 1,
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.idlect_shift = IDLXORP_ARM_SHIFT,
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};
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static struct arm_idlect1_clk armtim_ck = {
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@ -131,7 +175,7 @@ static struct arm_idlect1_clk armtim_ck = {
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.enable_bit = EN_TIMCK,
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.recalc = &followparent_recalc,
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},
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.idlect_shift = 9,
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.idlect_shift = IDLTIM_ARM_SHIFT,
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};
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static struct arm_idlect1_clk armwdt_ck = {
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@ -145,7 +189,7 @@ static struct arm_idlect1_clk armwdt_ck = {
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.fixed_div = 14,
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.recalc = &omap_fixed_divisor_recalc,
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},
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.idlect_shift = 0,
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.idlect_shift = IDLWDT_ARM_SHIFT,
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};
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static struct clk arminth_ck16xx = {
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@ -212,7 +256,6 @@ static struct clk dsptim_ck = {
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.recalc = &followparent_recalc,
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};
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/* Tie ARM_IDLECT1:IDLIF_ARM to this logical clock structure */
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static struct arm_idlect1_clk tc_ck = {
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.clk = {
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.name = "tc_ck",
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@ -224,7 +267,7 @@ static struct arm_idlect1_clk tc_ck = {
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.round_rate = omap1_clk_round_rate_ckctl_arm,
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.set_rate = omap1_clk_set_rate_ckctl_arm,
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},
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.idlect_shift = 6,
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.idlect_shift = IDLIF_ARM_SHIFT,
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};
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static struct clk arminth_ck1510 = {
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@ -304,7 +347,7 @@ static struct arm_idlect1_clk api_ck = {
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.enable_bit = EN_APICK,
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.recalc = &followparent_recalc,
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},
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.idlect_shift = 8,
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.idlect_shift = IDLAPI_ARM_SHIFT,
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};
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static struct arm_idlect1_clk lb_ck = {
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@ -317,7 +360,7 @@ static struct arm_idlect1_clk lb_ck = {
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.enable_bit = EN_LBCK,
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.recalc = &followparent_recalc,
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},
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.idlect_shift = 4,
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.idlect_shift = IDLLB_ARM_SHIFT,
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};
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static struct clk rhea1_ck = {
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@ -359,9 +402,15 @@ static struct arm_idlect1_clk lcd_ck_1510 = {
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.round_rate = omap1_clk_round_rate_ckctl_arm,
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.set_rate = omap1_clk_set_rate_ckctl_arm,
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},
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.idlect_shift = 3,
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.idlect_shift = OMAP1510_IDLLCD_ARM_SHIFT,
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};
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/*
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* XXX The enable_bit here is misused - it simply switches between 12MHz
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* and 48MHz. Reimplement with clksel.
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*
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* XXX does this need SYSC register handling?
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*/
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static struct clk uart1_1510 = {
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.name = "uart1_ck",
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.ops = &clkops_null,
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@ -370,25 +419,37 @@ static struct clk uart1_1510 = {
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.rate = 12000000,
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.flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
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.enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
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.enable_bit = 29, /* Chooses between 12MHz and 48MHz */
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.enable_bit = CONF_MOD_UART1_CLK_MODE_R,
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.set_rate = &omap1_set_uart_rate,
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.recalc = &omap1_uart_recalc,
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};
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/*
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* XXX The enable_bit here is misused - it simply switches between 12MHz
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* and 48MHz. Reimplement with clksel.
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*
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* XXX SYSC register handling does not belong in the clock framework
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*/
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static struct uart_clk uart1_16xx = {
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.clk = {
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.name = "uart1_ck",
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.ops = &clkops_uart,
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.ops = &clkops_uart_16xx,
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/* Direct from ULPD, no real parent */
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.parent = &armper_ck.clk,
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.rate = 48000000,
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.flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
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.enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
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.enable_bit = 29,
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.enable_bit = CONF_MOD_UART1_CLK_MODE_R,
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},
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.sysc_addr = 0xfffb0054,
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};
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/*
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* XXX The enable_bit here is misused - it simply switches between 12MHz
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* and 48MHz. Reimplement with clksel.
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*
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* XXX does this need SYSC register handling?
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*/
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static struct clk uart2_ck = {
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.name = "uart2_ck",
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.ops = &clkops_null,
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@ -397,11 +458,17 @@ static struct clk uart2_ck = {
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.rate = 12000000,
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.flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
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.enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
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.enable_bit = 30, /* Chooses between 12MHz and 48MHz */
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.enable_bit = CONF_MOD_UART2_CLK_MODE_R,
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.set_rate = &omap1_set_uart_rate,
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.recalc = &omap1_uart_recalc,
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};
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/*
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* XXX The enable_bit here is misused - it simply switches between 12MHz
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* and 48MHz. Reimplement with clksel.
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*
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* XXX does this need SYSC register handling?
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*/
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static struct clk uart3_1510 = {
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.name = "uart3_ck",
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.ops = &clkops_null,
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@ -410,21 +477,27 @@ static struct clk uart3_1510 = {
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.rate = 12000000,
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.flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
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.enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
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.enable_bit = 31, /* Chooses between 12MHz and 48MHz */
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.enable_bit = CONF_MOD_UART3_CLK_MODE_R,
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.set_rate = &omap1_set_uart_rate,
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.recalc = &omap1_uart_recalc,
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};
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/*
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* XXX The enable_bit here is misused - it simply switches between 12MHz
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* and 48MHz. Reimplement with clksel.
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*
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* XXX SYSC register handling does not belong in the clock framework
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*/
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static struct uart_clk uart3_16xx = {
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.clk = {
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.name = "uart3_ck",
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.ops = &clkops_uart,
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.ops = &clkops_uart_16xx,
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/* Direct from ULPD, no real parent */
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.parent = &armper_ck.clk,
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.rate = 48000000,
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.flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
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.enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
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.enable_bit = 31,
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.enable_bit = CONF_MOD_UART3_CLK_MODE_R,
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},
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.sysc_addr = 0xfffb9854,
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};
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@ -457,7 +530,7 @@ static struct clk usb_hhc_ck16xx = {
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/* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
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.flags = ENABLE_REG_32BIT,
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.enable_reg = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */
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.enable_bit = 8 /* UHOST_EN */,
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.enable_bit = OTG_SYSCON_2_UHOST_EN_SHIFT
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};
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static struct clk usb_dc_ck = {
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@ -466,7 +539,7 @@ static struct clk usb_dc_ck = {
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/* Direct from ULPD, no parent */
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.rate = 48000000,
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.enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
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.enable_bit = 4,
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.enable_bit = USB_REQ_EN_SHIFT,
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};
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static struct clk usb_dc_ck7xx = {
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@ -475,7 +548,7 @@ static struct clk usb_dc_ck7xx = {
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/* Direct from ULPD, no parent */
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.rate = 48000000,
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.enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
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.enable_bit = 8,
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.enable_bit = SOFT_USB_OTG_DPLL_REQ_SHIFT,
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};
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static struct clk mclk_1510 = {
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@ -484,7 +557,7 @@ static struct clk mclk_1510 = {
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/* Direct from ULPD, no parent. May be enabled by ext hardware. */
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.rate = 12000000,
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.enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
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.enable_bit = 6,
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.enable_bit = SOFT_COM_MCKO_REQ_SHIFT,
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};
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static struct clk mclk_16xx = {
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@ -524,9 +597,13 @@ static struct clk mmc1_ck = {
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.rate = 48000000,
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.flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
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.enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
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.enable_bit = 23,
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.enable_bit = CONF_MOD_MMC_SD_CLK_REQ_R,
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};
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/*
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* XXX MOD_CONF_CTRL_0 bit 20 is defined in the 1510 TRM as
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* CONF_MOD_MCBSP3_AUXON ??
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*/
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static struct clk mmc2_ck = {
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.name = "mmc2_ck",
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.ops = &clkops_generic,
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@ -546,7 +623,7 @@ static struct clk mmc3_ck = {
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.rate = 48000000,
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.flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
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.enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
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.enable_bit = 12,
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.enable_bit = SOFT_MMC_DPLL_REQ_SHIFT,
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};
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static struct clk virtual_ck_mpu = {
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