mirror of https://gitee.com/openkylin/linux.git
Merge ath-next from git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/ath.git
ath.git patches for 4.13. Major changes: ath10k * add initial SDIO support (still work in progress)
This commit is contained in:
commit
fb53905cf2
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@ -22,6 +22,13 @@ config ATH10K_AHB
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---help---
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---help---
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This module adds support for AHB bus
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This module adds support for AHB bus
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config ATH10K_SDIO
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tristate "Atheros ath10k SDIO support (EXPERIMENTAL)"
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depends on ATH10K && MMC
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---help---
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This module adds experimental support for SDIO/MMC bus. Currently
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work in progress and will not fully work.
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config ATH10K_DEBUG
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config ATH10K_DEBUG
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bool "Atheros ath10k debugging"
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bool "Atheros ath10k debugging"
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depends on ATH10K
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depends on ATH10K
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@ -27,5 +27,8 @@ ath10k_pci-y += pci.o \
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ath10k_pci-$(CONFIG_ATH10K_AHB) += ahb.o
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ath10k_pci-$(CONFIG_ATH10K_AHB) += ahb.o
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obj-$(CONFIG_ATH10K_SDIO) += ath10k_sdio.o
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ath10k_sdio-y += sdio.o
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# for tracing framework to find trace.h
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# for tracing framework to find trace.h
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CFLAGS_trace.o := -I$(src)
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CFLAGS_trace.o := -I$(src)
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@ -97,6 +97,77 @@ int ath10k_bmi_get_target_info(struct ath10k *ar,
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return 0;
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return 0;
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}
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}
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#define TARGET_VERSION_SENTINAL 0xffffffffu
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int ath10k_bmi_get_target_info_sdio(struct ath10k *ar,
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struct bmi_target_info *target_info)
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{
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struct bmi_cmd cmd;
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union bmi_resp resp;
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u32 cmdlen = sizeof(cmd.id) + sizeof(cmd.get_target_info);
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u32 resplen, ver_len;
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__le32 tmp;
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int ret;
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ath10k_dbg(ar, ATH10K_DBG_BMI, "bmi get target info SDIO\n");
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if (ar->bmi.done_sent) {
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ath10k_warn(ar, "BMI Get Target Info Command disallowed\n");
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return -EBUSY;
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}
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cmd.id = __cpu_to_le32(BMI_GET_TARGET_INFO);
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/* Step 1: Read 4 bytes of the target info and check if it is
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* the special sentinal version word or the first word in the
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* version response.
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*/
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resplen = sizeof(u32);
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ret = ath10k_hif_exchange_bmi_msg(ar, &cmd, cmdlen, &tmp, &resplen);
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if (ret) {
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ath10k_warn(ar, "unable to read from device\n");
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return ret;
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}
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/* Some SDIO boards have a special sentinal byte before the real
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* version response.
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*/
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if (__le32_to_cpu(tmp) == TARGET_VERSION_SENTINAL) {
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/* Step 1b: Read the version length */
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resplen = sizeof(u32);
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ret = ath10k_hif_exchange_bmi_msg(ar, NULL, 0, &tmp,
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&resplen);
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if (ret) {
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ath10k_warn(ar, "unable to read from device\n");
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return ret;
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}
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}
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ver_len = __le32_to_cpu(tmp);
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/* Step 2: Check the target info length */
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if (ver_len != sizeof(resp.get_target_info)) {
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ath10k_warn(ar, "Unexpected target info len: %u. Expected: %zu\n",
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ver_len, sizeof(resp.get_target_info));
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return -EINVAL;
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}
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/* Step 3: Read the rest of the version response */
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resplen = sizeof(resp.get_target_info) - sizeof(u32);
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ret = ath10k_hif_exchange_bmi_msg(ar, NULL, 0,
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&resp.get_target_info.version,
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&resplen);
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if (ret) {
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ath10k_warn(ar, "unable to read from device\n");
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return ret;
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}
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target_info->version = __le32_to_cpu(resp.get_target_info.version);
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target_info->type = __le32_to_cpu(resp.get_target_info.type);
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return 0;
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}
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int ath10k_bmi_read_memory(struct ath10k *ar,
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int ath10k_bmi_read_memory(struct ath10k *ar,
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u32 address, void *buffer, u32 length)
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u32 address, void *buffer, u32 length)
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{
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{
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@ -198,6 +198,8 @@ void ath10k_bmi_start(struct ath10k *ar);
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int ath10k_bmi_done(struct ath10k *ar);
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int ath10k_bmi_done(struct ath10k *ar);
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int ath10k_bmi_get_target_info(struct ath10k *ar,
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int ath10k_bmi_get_target_info(struct ath10k *ar,
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struct bmi_target_info *target_info);
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struct bmi_target_info *target_info);
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int ath10k_bmi_get_target_info_sdio(struct ath10k *ar,
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struct bmi_target_info *target_info);
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int ath10k_bmi_read_memory(struct ath10k *ar, u32 address,
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int ath10k_bmi_read_memory(struct ath10k *ar, u32 address,
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void *buffer, u32 length);
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void *buffer, u32 length);
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int ath10k_bmi_write_memory(struct ath10k *ar, u32 address,
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int ath10k_bmi_write_memory(struct ath10k *ar, u32 address,
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@ -389,6 +389,21 @@ static void ath10k_send_suspend_complete(struct ath10k *ar)
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complete(&ar->target_suspend);
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complete(&ar->target_suspend);
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}
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}
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static void ath10k_init_sdio(struct ath10k *ar)
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{
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u32 param = 0;
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ath10k_bmi_write32(ar, hi_mbox_io_block_sz, 256);
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ath10k_bmi_write32(ar, hi_mbox_isr_yield_limit, 99);
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ath10k_bmi_read32(ar, hi_acs_flags, ¶m);
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param |= (HI_ACS_FLAGS_SDIO_SWAP_MAILBOX_SET |
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HI_ACS_FLAGS_SDIO_REDUCE_TX_COMPL_SET |
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HI_ACS_FLAGS_ALT_DATA_CREDIT_SIZE);
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ath10k_bmi_write32(ar, hi_acs_flags, param);
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}
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static int ath10k_init_configure_target(struct ath10k *ar)
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static int ath10k_init_configure_target(struct ath10k *ar)
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{
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{
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u32 param_host;
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u32 param_host;
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@ -1395,7 +1410,18 @@ int ath10k_core_fetch_firmware_api_n(struct ath10k *ar, const char *name,
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static void ath10k_core_get_fw_name(struct ath10k *ar, char *fw_name,
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static void ath10k_core_get_fw_name(struct ath10k *ar, char *fw_name,
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size_t fw_name_len, int fw_api)
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size_t fw_name_len, int fw_api)
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{
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{
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scnprintf(fw_name, fw_name_len, "%s-%d.bin", ATH10K_FW_FILE_BASE, fw_api);
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switch (ar->hif.bus) {
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case ATH10K_BUS_SDIO:
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scnprintf(fw_name, fw_name_len, "%s-%s-%d.bin",
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ATH10K_FW_FILE_BASE, ath10k_bus_str(ar->hif.bus),
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fw_api);
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break;
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case ATH10K_BUS_PCI:
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case ATH10K_BUS_AHB:
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scnprintf(fw_name, fw_name_len, "%s-%d.bin",
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ATH10K_FW_FILE_BASE, fw_api);
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break;
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}
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}
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}
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static int ath10k_core_fetch_firmware_files(struct ath10k *ar)
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static int ath10k_core_fetch_firmware_files(struct ath10k *ar)
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@ -1953,6 +1979,9 @@ int ath10k_core_start(struct ath10k *ar, enum ath10k_firmware_mode mode,
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if (status)
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if (status)
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goto err;
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goto err;
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if (ar->hif.bus == ATH10K_BUS_SDIO)
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ath10k_init_sdio(ar);
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ar->htc.htc_ops.target_send_suspend_complete =
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ar->htc.htc_ops.target_send_suspend_complete =
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ath10k_send_suspend_complete;
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ath10k_send_suspend_complete;
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@ -2200,7 +2229,10 @@ static int ath10k_core_probe_fw(struct ath10k *ar)
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}
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}
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memset(&target_info, 0, sizeof(target_info));
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memset(&target_info, 0, sizeof(target_info));
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ret = ath10k_bmi_get_target_info(ar, &target_info);
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if (ar->hif.bus == ATH10K_BUS_SDIO)
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ret = ath10k_bmi_get_target_info_sdio(ar, &target_info);
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else
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ret = ath10k_bmi_get_target_info(ar, &target_info);
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if (ret) {
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if (ret) {
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ath10k_err(ar, "could not get target info (%d)\n", ret);
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ath10k_err(ar, "could not get target info (%d)\n", ret);
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goto err_power_down;
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goto err_power_down;
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@ -91,6 +91,7 @@ struct ath10k;
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enum ath10k_bus {
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enum ath10k_bus {
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ATH10K_BUS_PCI,
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ATH10K_BUS_PCI,
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ATH10K_BUS_AHB,
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ATH10K_BUS_AHB,
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ATH10K_BUS_SDIO,
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};
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};
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static inline const char *ath10k_bus_str(enum ath10k_bus bus)
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static inline const char *ath10k_bus_str(enum ath10k_bus bus)
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@ -100,6 +101,8 @@ static inline const char *ath10k_bus_str(enum ath10k_bus bus)
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return "pci";
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return "pci";
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case ATH10K_BUS_AHB:
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case ATH10K_BUS_AHB:
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return "ahb";
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return "ahb";
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case ATH10K_BUS_SDIO:
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return "sdio";
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}
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}
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|
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return "unknown";
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return "unknown";
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|
|
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@ -625,17 +625,21 @@ static ssize_t ath10k_write_simulate_fw_crash(struct file *file,
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size_t count, loff_t *ppos)
|
size_t count, loff_t *ppos)
|
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{
|
{
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struct ath10k *ar = file->private_data;
|
struct ath10k *ar = file->private_data;
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char buf[32];
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char buf[32] = {0};
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|
ssize_t rc;
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int ret;
|
int ret;
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|
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simple_write_to_buffer(buf, sizeof(buf) - 1, ppos, user_buf, count);
|
/* filter partial writes and invalid commands */
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if (*ppos != 0 || count >= sizeof(buf) || count == 0)
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|
return -EINVAL;
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||||||
|
|
||||||
/* make sure that buf is null terminated */
|
rc = simple_write_to_buffer(buf, sizeof(buf) - 1, ppos, user_buf, count);
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buf[sizeof(buf) - 1] = 0;
|
if (rc < 0)
|
||||||
|
return rc;
|
||||||
|
|
||||||
/* drop the possible '\n' from the end */
|
/* drop the possible '\n' from the end */
|
||||||
if (buf[count - 1] == '\n')
|
if (buf[*ppos - 1] == '\n')
|
||||||
buf[count - 1] = 0;
|
buf[*ppos - 1] = '\0';
|
||||||
|
|
||||||
mutex_lock(&ar->conf_mutex);
|
mutex_lock(&ar->conf_mutex);
|
||||||
|
|
||||||
|
|
|
@ -38,6 +38,8 @@ enum ath10k_debug_mask {
|
||||||
ATH10K_DBG_WMI_PRINT = 0x00002000,
|
ATH10K_DBG_WMI_PRINT = 0x00002000,
|
||||||
ATH10K_DBG_PCI_PS = 0x00004000,
|
ATH10K_DBG_PCI_PS = 0x00004000,
|
||||||
ATH10K_DBG_AHB = 0x00008000,
|
ATH10K_DBG_AHB = 0x00008000,
|
||||||
|
ATH10K_DBG_SDIO = 0x00010000,
|
||||||
|
ATH10K_DBG_SDIO_DUMP = 0x00020000,
|
||||||
ATH10K_DBG_ANY = 0xffffffff,
|
ATH10K_DBG_ANY = 0xffffffff,
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
|
@ -57,8 +57,8 @@ static inline void ath10k_htc_restore_tx_skb(struct ath10k_htc *htc,
|
||||||
skb_pull(skb, sizeof(struct ath10k_htc_hdr));
|
skb_pull(skb, sizeof(struct ath10k_htc_hdr));
|
||||||
}
|
}
|
||||||
|
|
||||||
static void ath10k_htc_notify_tx_completion(struct ath10k_htc_ep *ep,
|
void ath10k_htc_notify_tx_completion(struct ath10k_htc_ep *ep,
|
||||||
struct sk_buff *skb)
|
struct sk_buff *skb)
|
||||||
{
|
{
|
||||||
struct ath10k *ar = ep->htc->ar;
|
struct ath10k *ar = ep->htc->ar;
|
||||||
|
|
||||||
|
@ -75,6 +75,7 @@ static void ath10k_htc_notify_tx_completion(struct ath10k_htc_ep *ep,
|
||||||
|
|
||||||
ep->ep_ops.ep_tx_complete(ep->htc->ar, skb);
|
ep->ep_ops.ep_tx_complete(ep->htc->ar, skb);
|
||||||
}
|
}
|
||||||
|
EXPORT_SYMBOL(ath10k_htc_notify_tx_completion);
|
||||||
|
|
||||||
static void ath10k_htc_prepare_tx_skb(struct ath10k_htc_ep *ep,
|
static void ath10k_htc_prepare_tx_skb(struct ath10k_htc_ep *ep,
|
||||||
struct sk_buff *skb)
|
struct sk_buff *skb)
|
||||||
|
@ -230,12 +231,79 @@ ath10k_htc_process_credit_report(struct ath10k_htc *htc,
|
||||||
spin_unlock_bh(&htc->tx_lock);
|
spin_unlock_bh(&htc->tx_lock);
|
||||||
}
|
}
|
||||||
|
|
||||||
static int ath10k_htc_process_trailer(struct ath10k_htc *htc,
|
static int
|
||||||
u8 *buffer,
|
ath10k_htc_process_lookahead(struct ath10k_htc *htc,
|
||||||
int length,
|
const struct ath10k_htc_lookahead_report *report,
|
||||||
enum ath10k_htc_ep_id src_eid)
|
int len,
|
||||||
|
enum ath10k_htc_ep_id eid,
|
||||||
|
void *next_lookaheads,
|
||||||
|
int *next_lookaheads_len)
|
||||||
{
|
{
|
||||||
struct ath10k *ar = htc->ar;
|
struct ath10k *ar = htc->ar;
|
||||||
|
|
||||||
|
/* Invalid lookahead flags are actually transmitted by
|
||||||
|
* the target in the HTC control message.
|
||||||
|
* Since this will happen at every boot we silently ignore
|
||||||
|
* the lookahead in this case
|
||||||
|
*/
|
||||||
|
if (report->pre_valid != ((~report->post_valid) & 0xFF))
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
if (next_lookaheads && next_lookaheads_len) {
|
||||||
|
ath10k_dbg(ar, ATH10K_DBG_HTC,
|
||||||
|
"htc rx lookahead found pre_valid 0x%x post_valid 0x%x\n",
|
||||||
|
report->pre_valid, report->post_valid);
|
||||||
|
|
||||||
|
/* look ahead bytes are valid, copy them over */
|
||||||
|
memcpy((u8 *)next_lookaheads, report->lookahead, 4);
|
||||||
|
|
||||||
|
*next_lookaheads_len = 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int
|
||||||
|
ath10k_htc_process_lookahead_bundle(struct ath10k_htc *htc,
|
||||||
|
const struct ath10k_htc_lookahead_bundle *report,
|
||||||
|
int len,
|
||||||
|
enum ath10k_htc_ep_id eid,
|
||||||
|
void *next_lookaheads,
|
||||||
|
int *next_lookaheads_len)
|
||||||
|
{
|
||||||
|
struct ath10k *ar = htc->ar;
|
||||||
|
int bundle_cnt = len / sizeof(*report);
|
||||||
|
|
||||||
|
if (!bundle_cnt || (bundle_cnt > HTC_HOST_MAX_MSG_PER_BUNDLE)) {
|
||||||
|
ath10k_warn(ar, "Invalid lookahead bundle count: %d\n",
|
||||||
|
bundle_cnt);
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (next_lookaheads && next_lookaheads_len) {
|
||||||
|
int i;
|
||||||
|
|
||||||
|
for (i = 0; i < bundle_cnt; i++) {
|
||||||
|
memcpy(((u8 *)next_lookaheads) + 4 * i,
|
||||||
|
report->lookahead, 4);
|
||||||
|
report++;
|
||||||
|
}
|
||||||
|
|
||||||
|
*next_lookaheads_len = bundle_cnt;
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
int ath10k_htc_process_trailer(struct ath10k_htc *htc,
|
||||||
|
u8 *buffer,
|
||||||
|
int length,
|
||||||
|
enum ath10k_htc_ep_id src_eid,
|
||||||
|
void *next_lookaheads,
|
||||||
|
int *next_lookaheads_len)
|
||||||
|
{
|
||||||
|
struct ath10k_htc_lookahead_bundle *bundle;
|
||||||
|
struct ath10k *ar = htc->ar;
|
||||||
int status = 0;
|
int status = 0;
|
||||||
struct ath10k_htc_record *record;
|
struct ath10k_htc_record *record;
|
||||||
u8 *orig_buffer;
|
u8 *orig_buffer;
|
||||||
|
@ -274,6 +342,29 @@ static int ath10k_htc_process_trailer(struct ath10k_htc *htc,
|
||||||
record->hdr.len,
|
record->hdr.len,
|
||||||
src_eid);
|
src_eid);
|
||||||
break;
|
break;
|
||||||
|
case ATH10K_HTC_RECORD_LOOKAHEAD:
|
||||||
|
len = sizeof(struct ath10k_htc_lookahead_report);
|
||||||
|
if (record->hdr.len < len) {
|
||||||
|
ath10k_warn(ar, "Lookahead report too long\n");
|
||||||
|
status = -EINVAL;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
status = ath10k_htc_process_lookahead(htc,
|
||||||
|
record->lookahead_report,
|
||||||
|
record->hdr.len,
|
||||||
|
src_eid,
|
||||||
|
next_lookaheads,
|
||||||
|
next_lookaheads_len);
|
||||||
|
break;
|
||||||
|
case ATH10K_HTC_RECORD_LOOKAHEAD_BUNDLE:
|
||||||
|
bundle = record->lookahead_bundle;
|
||||||
|
status = ath10k_htc_process_lookahead_bundle(htc,
|
||||||
|
bundle,
|
||||||
|
record->hdr.len,
|
||||||
|
src_eid,
|
||||||
|
next_lookaheads,
|
||||||
|
next_lookaheads_len);
|
||||||
|
break;
|
||||||
default:
|
default:
|
||||||
ath10k_warn(ar, "Unhandled record: id:%d length:%d\n",
|
ath10k_warn(ar, "Unhandled record: id:%d length:%d\n",
|
||||||
record->hdr.id, record->hdr.len);
|
record->hdr.id, record->hdr.len);
|
||||||
|
@ -294,6 +385,7 @@ static int ath10k_htc_process_trailer(struct ath10k_htc *htc,
|
||||||
|
|
||||||
return status;
|
return status;
|
||||||
}
|
}
|
||||||
|
EXPORT_SYMBOL(ath10k_htc_process_trailer);
|
||||||
|
|
||||||
void ath10k_htc_rx_completion_handler(struct ath10k *ar, struct sk_buff *skb)
|
void ath10k_htc_rx_completion_handler(struct ath10k *ar, struct sk_buff *skb)
|
||||||
{
|
{
|
||||||
|
@ -360,7 +452,8 @@ void ath10k_htc_rx_completion_handler(struct ath10k *ar, struct sk_buff *skb)
|
||||||
trailer += payload_len;
|
trailer += payload_len;
|
||||||
trailer -= trailer_len;
|
trailer -= trailer_len;
|
||||||
status = ath10k_htc_process_trailer(htc, trailer,
|
status = ath10k_htc_process_trailer(htc, trailer,
|
||||||
trailer_len, hdr->eid);
|
trailer_len, hdr->eid,
|
||||||
|
NULL, NULL);
|
||||||
if (status)
|
if (status)
|
||||||
goto out;
|
goto out;
|
||||||
|
|
||||||
|
@ -371,42 +464,6 @@ void ath10k_htc_rx_completion_handler(struct ath10k *ar, struct sk_buff *skb)
|
||||||
/* zero length packet with trailer data, just drop these */
|
/* zero length packet with trailer data, just drop these */
|
||||||
goto out;
|
goto out;
|
||||||
|
|
||||||
if (eid == ATH10K_HTC_EP_0) {
|
|
||||||
struct ath10k_htc_msg *msg = (struct ath10k_htc_msg *)skb->data;
|
|
||||||
|
|
||||||
switch (__le16_to_cpu(msg->hdr.message_id)) {
|
|
||||||
case ATH10K_HTC_MSG_READY_ID:
|
|
||||||
case ATH10K_HTC_MSG_CONNECT_SERVICE_RESP_ID:
|
|
||||||
/* handle HTC control message */
|
|
||||||
if (completion_done(&htc->ctl_resp)) {
|
|
||||||
/*
|
|
||||||
* this is a fatal error, target should not be
|
|
||||||
* sending unsolicited messages on the ep 0
|
|
||||||
*/
|
|
||||||
ath10k_warn(ar, "HTC rx ctrl still processing\n");
|
|
||||||
complete(&htc->ctl_resp);
|
|
||||||
goto out;
|
|
||||||
}
|
|
||||||
|
|
||||||
htc->control_resp_len =
|
|
||||||
min_t(int, skb->len,
|
|
||||||
ATH10K_HTC_MAX_CTRL_MSG_LEN);
|
|
||||||
|
|
||||||
memcpy(htc->control_resp_buffer, skb->data,
|
|
||||||
htc->control_resp_len);
|
|
||||||
|
|
||||||
complete(&htc->ctl_resp);
|
|
||||||
break;
|
|
||||||
case ATH10K_HTC_MSG_SEND_SUSPEND_COMPLETE:
|
|
||||||
htc->htc_ops.target_send_suspend_complete(ar);
|
|
||||||
break;
|
|
||||||
default:
|
|
||||||
ath10k_warn(ar, "ignoring unsolicited htc ep0 event\n");
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
goto out;
|
|
||||||
}
|
|
||||||
|
|
||||||
ath10k_dbg(ar, ATH10K_DBG_HTC, "htc rx completion ep %d skb %pK\n",
|
ath10k_dbg(ar, ATH10K_DBG_HTC, "htc rx completion ep %d skb %pK\n",
|
||||||
eid, skb);
|
eid, skb);
|
||||||
ep->ep_ops.ep_rx_complete(ar, skb);
|
ep->ep_ops.ep_rx_complete(ar, skb);
|
||||||
|
@ -421,10 +478,40 @@ EXPORT_SYMBOL(ath10k_htc_rx_completion_handler);
|
||||||
static void ath10k_htc_control_rx_complete(struct ath10k *ar,
|
static void ath10k_htc_control_rx_complete(struct ath10k *ar,
|
||||||
struct sk_buff *skb)
|
struct sk_buff *skb)
|
||||||
{
|
{
|
||||||
/* This is unexpected. FW is not supposed to send regular rx on this
|
struct ath10k_htc *htc = &ar->htc;
|
||||||
* endpoint.
|
struct ath10k_htc_msg *msg = (struct ath10k_htc_msg *)skb->data;
|
||||||
*/
|
|
||||||
ath10k_warn(ar, "unexpected htc rx\n");
|
switch (__le16_to_cpu(msg->hdr.message_id)) {
|
||||||
|
case ATH10K_HTC_MSG_READY_ID:
|
||||||
|
case ATH10K_HTC_MSG_CONNECT_SERVICE_RESP_ID:
|
||||||
|
/* handle HTC control message */
|
||||||
|
if (completion_done(&htc->ctl_resp)) {
|
||||||
|
/* this is a fatal error, target should not be
|
||||||
|
* sending unsolicited messages on the ep 0
|
||||||
|
*/
|
||||||
|
ath10k_warn(ar, "HTC rx ctrl still processing\n");
|
||||||
|
complete(&htc->ctl_resp);
|
||||||
|
goto out;
|
||||||
|
}
|
||||||
|
|
||||||
|
htc->control_resp_len =
|
||||||
|
min_t(int, skb->len,
|
||||||
|
ATH10K_HTC_MAX_CTRL_MSG_LEN);
|
||||||
|
|
||||||
|
memcpy(htc->control_resp_buffer, skb->data,
|
||||||
|
htc->control_resp_len);
|
||||||
|
|
||||||
|
complete(&htc->ctl_resp);
|
||||||
|
break;
|
||||||
|
case ATH10K_HTC_MSG_SEND_SUSPEND_COMPLETE:
|
||||||
|
htc->htc_ops.target_send_suspend_complete(ar);
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
ath10k_warn(ar, "ignoring unsolicited htc ep0 event\n");
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
out:
|
||||||
kfree_skb(skb);
|
kfree_skb(skb);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -497,12 +584,8 @@ int ath10k_htc_wait_target(struct ath10k_htc *htc)
|
||||||
struct ath10k *ar = htc->ar;
|
struct ath10k *ar = htc->ar;
|
||||||
int i, status = 0;
|
int i, status = 0;
|
||||||
unsigned long time_left;
|
unsigned long time_left;
|
||||||
struct ath10k_htc_svc_conn_req conn_req;
|
|
||||||
struct ath10k_htc_svc_conn_resp conn_resp;
|
|
||||||
struct ath10k_htc_msg *msg;
|
struct ath10k_htc_msg *msg;
|
||||||
u16 message_id;
|
u16 message_id;
|
||||||
u16 credit_count;
|
|
||||||
u16 credit_size;
|
|
||||||
|
|
||||||
time_left = wait_for_completion_timeout(&htc->ctl_resp,
|
time_left = wait_for_completion_timeout(&htc->ctl_resp,
|
||||||
ATH10K_HTC_WAIT_TIMEOUT_HZ);
|
ATH10K_HTC_WAIT_TIMEOUT_HZ);
|
||||||
|
@ -539,16 +622,14 @@ int ath10k_htc_wait_target(struct ath10k_htc *htc)
|
||||||
|
|
||||||
msg = (struct ath10k_htc_msg *)htc->control_resp_buffer;
|
msg = (struct ath10k_htc_msg *)htc->control_resp_buffer;
|
||||||
message_id = __le16_to_cpu(msg->hdr.message_id);
|
message_id = __le16_to_cpu(msg->hdr.message_id);
|
||||||
credit_count = __le16_to_cpu(msg->ready.credit_count);
|
|
||||||
credit_size = __le16_to_cpu(msg->ready.credit_size);
|
|
||||||
|
|
||||||
if (message_id != ATH10K_HTC_MSG_READY_ID) {
|
if (message_id != ATH10K_HTC_MSG_READY_ID) {
|
||||||
ath10k_err(ar, "Invalid HTC ready msg: 0x%x\n", message_id);
|
ath10k_err(ar, "Invalid HTC ready msg: 0x%x\n", message_id);
|
||||||
return -ECOMM;
|
return -ECOMM;
|
||||||
}
|
}
|
||||||
|
|
||||||
htc->total_transmit_credits = credit_count;
|
htc->total_transmit_credits = __le16_to_cpu(msg->ready.credit_count);
|
||||||
htc->target_credit_size = credit_size;
|
htc->target_credit_size = __le16_to_cpu(msg->ready.credit_size);
|
||||||
|
|
||||||
ath10k_dbg(ar, ATH10K_DBG_HTC,
|
ath10k_dbg(ar, ATH10K_DBG_HTC,
|
||||||
"Target ready! transmit resources: %d size:%d\n",
|
"Target ready! transmit resources: %d size:%d\n",
|
||||||
|
@ -561,20 +642,17 @@ int ath10k_htc_wait_target(struct ath10k_htc *htc)
|
||||||
return -ECOMM;
|
return -ECOMM;
|
||||||
}
|
}
|
||||||
|
|
||||||
/* setup our pseudo HTC control endpoint connection */
|
/* The only way to determine if the ready message is an extended
|
||||||
memset(&conn_req, 0, sizeof(conn_req));
|
* message is from the size.
|
||||||
memset(&conn_resp, 0, sizeof(conn_resp));
|
*/
|
||||||
conn_req.ep_ops.ep_tx_complete = ath10k_htc_control_tx_complete;
|
if (htc->control_resp_len >=
|
||||||
conn_req.ep_ops.ep_rx_complete = ath10k_htc_control_rx_complete;
|
sizeof(msg->hdr) + sizeof(msg->ready_ext)) {
|
||||||
conn_req.max_send_queue_depth = ATH10K_NUM_CONTROL_TX_BUFFERS;
|
htc->max_msgs_per_htc_bundle =
|
||||||
conn_req.service_id = ATH10K_HTC_SVC_ID_RSVD_CTRL;
|
min_t(u8, msg->ready_ext.max_msgs_per_htc_bundle,
|
||||||
|
HTC_HOST_MAX_MSG_PER_BUNDLE);
|
||||||
/* connect fake service */
|
ath10k_dbg(ar, ATH10K_DBG_HTC,
|
||||||
status = ath10k_htc_connect_service(htc, &conn_req, &conn_resp);
|
"Extended ready message. RX bundle size: %d\n",
|
||||||
if (status) {
|
htc->max_msgs_per_htc_bundle);
|
||||||
ath10k_err(ar, "could not connect to htc service (%d)\n",
|
|
||||||
status);
|
|
||||||
return status;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
|
@ -772,6 +850,13 @@ int ath10k_htc_start(struct ath10k_htc *htc)
|
||||||
msg->hdr.message_id =
|
msg->hdr.message_id =
|
||||||
__cpu_to_le16(ATH10K_HTC_MSG_SETUP_COMPLETE_EX_ID);
|
__cpu_to_le16(ATH10K_HTC_MSG_SETUP_COMPLETE_EX_ID);
|
||||||
|
|
||||||
|
if (ar->hif.bus == ATH10K_BUS_SDIO) {
|
||||||
|
/* Extra setup params used by SDIO */
|
||||||
|
msg->setup_complete_ext.flags =
|
||||||
|
__cpu_to_le32(ATH10K_HTC_SETUP_COMPLETE_FLAGS_RX_BNDL_EN);
|
||||||
|
msg->setup_complete_ext.max_msgs_per_bundled_recv =
|
||||||
|
htc->max_msgs_per_htc_bundle;
|
||||||
|
}
|
||||||
ath10k_dbg(ar, ATH10K_DBG_HTC, "HTC is using TX credit flow control\n");
|
ath10k_dbg(ar, ATH10K_DBG_HTC, "HTC is using TX credit flow control\n");
|
||||||
|
|
||||||
status = ath10k_htc_send(htc, ATH10K_HTC_EP_0, skb);
|
status = ath10k_htc_send(htc, ATH10K_HTC_EP_0, skb);
|
||||||
|
@ -786,8 +871,10 @@ int ath10k_htc_start(struct ath10k_htc *htc)
|
||||||
/* registered target arrival callback from the HIF layer */
|
/* registered target arrival callback from the HIF layer */
|
||||||
int ath10k_htc_init(struct ath10k *ar)
|
int ath10k_htc_init(struct ath10k *ar)
|
||||||
{
|
{
|
||||||
struct ath10k_htc_ep *ep = NULL;
|
int status;
|
||||||
struct ath10k_htc *htc = &ar->htc;
|
struct ath10k_htc *htc = &ar->htc;
|
||||||
|
struct ath10k_htc_svc_conn_req conn_req;
|
||||||
|
struct ath10k_htc_svc_conn_resp conn_resp;
|
||||||
|
|
||||||
spin_lock_init(&htc->tx_lock);
|
spin_lock_init(&htc->tx_lock);
|
||||||
|
|
||||||
|
@ -795,10 +882,21 @@ int ath10k_htc_init(struct ath10k *ar)
|
||||||
|
|
||||||
htc->ar = ar;
|
htc->ar = ar;
|
||||||
|
|
||||||
/* Get HIF default pipe for HTC message exchange */
|
/* setup our pseudo HTC control endpoint connection */
|
||||||
ep = &htc->endpoint[ATH10K_HTC_EP_0];
|
memset(&conn_req, 0, sizeof(conn_req));
|
||||||
|
memset(&conn_resp, 0, sizeof(conn_resp));
|
||||||
|
conn_req.ep_ops.ep_tx_complete = ath10k_htc_control_tx_complete;
|
||||||
|
conn_req.ep_ops.ep_rx_complete = ath10k_htc_control_rx_complete;
|
||||||
|
conn_req.max_send_queue_depth = ATH10K_NUM_CONTROL_TX_BUFFERS;
|
||||||
|
conn_req.service_id = ATH10K_HTC_SVC_ID_RSVD_CTRL;
|
||||||
|
|
||||||
ath10k_hif_get_default_pipe(ar, &ep->ul_pipe_id, &ep->dl_pipe_id);
|
/* connect fake service */
|
||||||
|
status = ath10k_htc_connect_service(htc, &conn_req, &conn_resp);
|
||||||
|
if (status) {
|
||||||
|
ath10k_err(ar, "could not connect to htc service (%d)\n",
|
||||||
|
status);
|
||||||
|
return status;
|
||||||
|
}
|
||||||
|
|
||||||
init_completion(&htc->ctl_resp);
|
init_completion(&htc->ctl_resp);
|
||||||
|
|
||||||
|
|
|
@ -50,6 +50,8 @@ struct ath10k;
|
||||||
* 4-byte aligned.
|
* 4-byte aligned.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
#define HTC_HOST_MAX_MSG_PER_BUNDLE 8
|
||||||
|
|
||||||
enum ath10k_htc_tx_flags {
|
enum ath10k_htc_tx_flags {
|
||||||
ATH10K_HTC_FLAG_NEED_CREDIT_UPDATE = 0x01,
|
ATH10K_HTC_FLAG_NEED_CREDIT_UPDATE = 0x01,
|
||||||
ATH10K_HTC_FLAG_SEND_BUNDLE = 0x02
|
ATH10K_HTC_FLAG_SEND_BUNDLE = 0x02
|
||||||
|
@ -110,6 +112,10 @@ enum ath10k_htc_conn_svc_status {
|
||||||
ATH10K_HTC_CONN_SVC_STATUS_NO_MORE_EP = 4
|
ATH10K_HTC_CONN_SVC_STATUS_NO_MORE_EP = 4
|
||||||
};
|
};
|
||||||
|
|
||||||
|
enum ath10k_htc_setup_complete_flags {
|
||||||
|
ATH10K_HTC_SETUP_COMPLETE_FLAGS_RX_BNDL_EN = 1
|
||||||
|
};
|
||||||
|
|
||||||
struct ath10k_ath10k_htc_msg_hdr {
|
struct ath10k_ath10k_htc_msg_hdr {
|
||||||
__le16 message_id; /* @enum htc_message_id */
|
__le16 message_id; /* @enum htc_message_id */
|
||||||
} __packed;
|
} __packed;
|
||||||
|
@ -174,8 +180,10 @@ struct ath10k_htc_msg {
|
||||||
} __packed __aligned(4);
|
} __packed __aligned(4);
|
||||||
|
|
||||||
enum ath10k_ath10k_htc_record_id {
|
enum ath10k_ath10k_htc_record_id {
|
||||||
ATH10K_HTC_RECORD_NULL = 0,
|
ATH10K_HTC_RECORD_NULL = 0,
|
||||||
ATH10K_HTC_RECORD_CREDITS = 1
|
ATH10K_HTC_RECORD_CREDITS = 1,
|
||||||
|
ATH10K_HTC_RECORD_LOOKAHEAD = 2,
|
||||||
|
ATH10K_HTC_RECORD_LOOKAHEAD_BUNDLE = 3,
|
||||||
};
|
};
|
||||||
|
|
||||||
struct ath10k_ath10k_htc_record_hdr {
|
struct ath10k_ath10k_htc_record_hdr {
|
||||||
|
@ -192,10 +200,28 @@ struct ath10k_htc_credit_report {
|
||||||
u8 pad1;
|
u8 pad1;
|
||||||
} __packed;
|
} __packed;
|
||||||
|
|
||||||
|
struct ath10k_htc_lookahead_report {
|
||||||
|
u8 pre_valid;
|
||||||
|
u8 pad0;
|
||||||
|
u8 pad1;
|
||||||
|
u8 pad2;
|
||||||
|
u8 lookahead[4];
|
||||||
|
u8 post_valid;
|
||||||
|
u8 pad3;
|
||||||
|
u8 pad4;
|
||||||
|
u8 pad5;
|
||||||
|
} __packed;
|
||||||
|
|
||||||
|
struct ath10k_htc_lookahead_bundle {
|
||||||
|
u8 lookahead[4];
|
||||||
|
} __packed;
|
||||||
|
|
||||||
struct ath10k_htc_record {
|
struct ath10k_htc_record {
|
||||||
struct ath10k_ath10k_htc_record_hdr hdr;
|
struct ath10k_ath10k_htc_record_hdr hdr;
|
||||||
union {
|
union {
|
||||||
struct ath10k_htc_credit_report credit_report[0];
|
struct ath10k_htc_credit_report credit_report[0];
|
||||||
|
struct ath10k_htc_lookahead_report lookahead_report[0];
|
||||||
|
struct ath10k_htc_lookahead_bundle lookahead_bundle[0];
|
||||||
u8 pauload[0];
|
u8 pauload[0];
|
||||||
};
|
};
|
||||||
} __packed __aligned(4);
|
} __packed __aligned(4);
|
||||||
|
@ -338,6 +364,7 @@ struct ath10k_htc {
|
||||||
|
|
||||||
int total_transmit_credits;
|
int total_transmit_credits;
|
||||||
int target_credit_size;
|
int target_credit_size;
|
||||||
|
u8 max_msgs_per_htc_bundle;
|
||||||
};
|
};
|
||||||
|
|
||||||
int ath10k_htc_init(struct ath10k *ar);
|
int ath10k_htc_init(struct ath10k *ar);
|
||||||
|
@ -351,5 +378,13 @@ int ath10k_htc_send(struct ath10k_htc *htc, enum ath10k_htc_ep_id eid,
|
||||||
struct sk_buff *ath10k_htc_alloc_skb(struct ath10k *ar, int size);
|
struct sk_buff *ath10k_htc_alloc_skb(struct ath10k *ar, int size);
|
||||||
void ath10k_htc_tx_completion_handler(struct ath10k *ar, struct sk_buff *skb);
|
void ath10k_htc_tx_completion_handler(struct ath10k *ar, struct sk_buff *skb);
|
||||||
void ath10k_htc_rx_completion_handler(struct ath10k *ar, struct sk_buff *skb);
|
void ath10k_htc_rx_completion_handler(struct ath10k *ar, struct sk_buff *skb);
|
||||||
|
void ath10k_htc_notify_tx_completion(struct ath10k_htc_ep *ep,
|
||||||
|
struct sk_buff *skb);
|
||||||
|
int ath10k_htc_process_trailer(struct ath10k_htc *htc,
|
||||||
|
u8 *buffer,
|
||||||
|
int length,
|
||||||
|
enum ath10k_htc_ep_id src_eid,
|
||||||
|
void *next_lookaheads,
|
||||||
|
int *next_lookaheads_len);
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
@ -863,6 +863,59 @@ ath10k_rx_desc_get_l3_pad_bytes(struct ath10k_hw_params *hw,
|
||||||
#define QCA9887_EEPROM_ADDR_LO_MASK 0x00ff0000
|
#define QCA9887_EEPROM_ADDR_LO_MASK 0x00ff0000
|
||||||
#define QCA9887_EEPROM_ADDR_LO_LSB 16
|
#define QCA9887_EEPROM_ADDR_LO_LSB 16
|
||||||
|
|
||||||
|
#define MBOX_RESET_CONTROL_ADDRESS 0x00000000
|
||||||
|
#define MBOX_HOST_INT_STATUS_ADDRESS 0x00000800
|
||||||
|
#define MBOX_HOST_INT_STATUS_ERROR_LSB 7
|
||||||
|
#define MBOX_HOST_INT_STATUS_ERROR_MASK 0x00000080
|
||||||
|
#define MBOX_HOST_INT_STATUS_CPU_LSB 6
|
||||||
|
#define MBOX_HOST_INT_STATUS_CPU_MASK 0x00000040
|
||||||
|
#define MBOX_HOST_INT_STATUS_COUNTER_LSB 4
|
||||||
|
#define MBOX_HOST_INT_STATUS_COUNTER_MASK 0x00000010
|
||||||
|
#define MBOX_CPU_INT_STATUS_ADDRESS 0x00000801
|
||||||
|
#define MBOX_ERROR_INT_STATUS_ADDRESS 0x00000802
|
||||||
|
#define MBOX_ERROR_INT_STATUS_WAKEUP_LSB 2
|
||||||
|
#define MBOX_ERROR_INT_STATUS_WAKEUP_MASK 0x00000004
|
||||||
|
#define MBOX_ERROR_INT_STATUS_RX_UNDERFLOW_LSB 1
|
||||||
|
#define MBOX_ERROR_INT_STATUS_RX_UNDERFLOW_MASK 0x00000002
|
||||||
|
#define MBOX_ERROR_INT_STATUS_TX_OVERFLOW_LSB 0
|
||||||
|
#define MBOX_ERROR_INT_STATUS_TX_OVERFLOW_MASK 0x00000001
|
||||||
|
#define MBOX_COUNTER_INT_STATUS_ADDRESS 0x00000803
|
||||||
|
#define MBOX_COUNTER_INT_STATUS_COUNTER_LSB 0
|
||||||
|
#define MBOX_COUNTER_INT_STATUS_COUNTER_MASK 0x000000ff
|
||||||
|
#define MBOX_RX_LOOKAHEAD_VALID_ADDRESS 0x00000805
|
||||||
|
#define MBOX_INT_STATUS_ENABLE_ADDRESS 0x00000828
|
||||||
|
#define MBOX_INT_STATUS_ENABLE_ERROR_LSB 7
|
||||||
|
#define MBOX_INT_STATUS_ENABLE_ERROR_MASK 0x00000080
|
||||||
|
#define MBOX_INT_STATUS_ENABLE_CPU_LSB 6
|
||||||
|
#define MBOX_INT_STATUS_ENABLE_CPU_MASK 0x00000040
|
||||||
|
#define MBOX_INT_STATUS_ENABLE_INT_LSB 5
|
||||||
|
#define MBOX_INT_STATUS_ENABLE_INT_MASK 0x00000020
|
||||||
|
#define MBOX_INT_STATUS_ENABLE_COUNTER_LSB 4
|
||||||
|
#define MBOX_INT_STATUS_ENABLE_COUNTER_MASK 0x00000010
|
||||||
|
#define MBOX_INT_STATUS_ENABLE_MBOX_DATA_LSB 0
|
||||||
|
#define MBOX_INT_STATUS_ENABLE_MBOX_DATA_MASK 0x0000000f
|
||||||
|
#define MBOX_CPU_INT_STATUS_ENABLE_ADDRESS 0x00000819
|
||||||
|
#define MBOX_CPU_INT_STATUS_ENABLE_BIT_LSB 0
|
||||||
|
#define MBOX_CPU_INT_STATUS_ENABLE_BIT_MASK 0x000000ff
|
||||||
|
#define MBOX_ERROR_STATUS_ENABLE_ADDRESS 0x0000081a
|
||||||
|
#define MBOX_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB 1
|
||||||
|
#define MBOX_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK 0x00000002
|
||||||
|
#define MBOX_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB 0
|
||||||
|
#define MBOX_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK 0x00000001
|
||||||
|
#define MBOX_COUNTER_INT_STATUS_ENABLE_ADDRESS 0x0000081b
|
||||||
|
#define MBOX_COUNTER_INT_STATUS_ENABLE_BIT_LSB 0
|
||||||
|
#define MBOX_COUNTER_INT_STATUS_ENABLE_BIT_MASK 0x000000ff
|
||||||
|
#define MBOX_COUNT_ADDRESS 0x00000820
|
||||||
|
#define MBOX_COUNT_DEC_ADDRESS 0x00000840
|
||||||
|
#define MBOX_WINDOW_DATA_ADDRESS 0x00000874
|
||||||
|
#define MBOX_WINDOW_WRITE_ADDR_ADDRESS 0x00000878
|
||||||
|
#define MBOX_WINDOW_READ_ADDR_ADDRESS 0x0000087c
|
||||||
|
#define MBOX_CPU_DBG_SEL_ADDRESS 0x00000883
|
||||||
|
#define MBOX_CPU_DBG_ADDRESS 0x00000884
|
||||||
|
#define MBOX_RTC_BASE_ADDRESS 0x00000000
|
||||||
|
#define MBOX_GPIO_BASE_ADDRESS 0x00005000
|
||||||
|
#define MBOX_MBOX_BASE_ADDRESS 0x00008000
|
||||||
|
|
||||||
#define RTC_STATE_V_GET(x) (((x) & RTC_STATE_V_MASK) >> RTC_STATE_V_LSB)
|
#define RTC_STATE_V_GET(x) (((x) & RTC_STATE_V_MASK) >> RTC_STATE_V_LSB)
|
||||||
|
|
||||||
/* Register definitions for first generation ath10k cards. These cards include
|
/* Register definitions for first generation ath10k cards. These cards include
|
||||||
|
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,229 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2004-2011 Atheros Communications Inc.
|
||||||
|
* Copyright (c) 2011-2012 Qualcomm Atheros, Inc.
|
||||||
|
* Copyright (c) 2016-2017 Erik Stromdahl <erik.stromdahl@gmail.com>
|
||||||
|
*
|
||||||
|
* Permission to use, copy, modify, and/or distribute this software for any
|
||||||
|
* purpose with or without fee is hereby granted, provided that the above
|
||||||
|
* copyright notice and this permission notice appear in all copies.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||||
|
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||||
|
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||||
|
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||||
|
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||||
|
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||||
|
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _SDIO_H_
|
||||||
|
#define _SDIO_H_
|
||||||
|
|
||||||
|
#define ATH10K_HIF_MBOX_BLOCK_SIZE 256
|
||||||
|
|
||||||
|
#define QCA_MANUFACTURER_ID_BASE GENMASK(11, 8)
|
||||||
|
#define QCA_MANUFACTURER_ID_AR6005_BASE 0x5
|
||||||
|
#define QCA_MANUFACTURER_ID_QCA9377_BASE 0x7
|
||||||
|
#define QCA_SDIO_ID_AR6005_BASE 0x500
|
||||||
|
#define QCA_SDIO_ID_QCA9377_BASE 0x700
|
||||||
|
#define QCA_MANUFACTURER_ID_REV_MASK 0x00FF
|
||||||
|
#define QCA_MANUFACTURER_CODE 0x271 /* Qualcomm/Atheros */
|
||||||
|
|
||||||
|
#define ATH10K_SDIO_MAX_BUFFER_SIZE 4096 /*Unsure of this constant*/
|
||||||
|
|
||||||
|
/* Mailbox address in SDIO address space */
|
||||||
|
#define ATH10K_HIF_MBOX_BASE_ADDR 0x1000
|
||||||
|
#define ATH10K_HIF_MBOX_WIDTH 0x800
|
||||||
|
|
||||||
|
#define ATH10K_HIF_MBOX_TOT_WIDTH \
|
||||||
|
(ATH10K_HIF_MBOX_NUM_MAX * ATH10K_HIF_MBOX_WIDTH)
|
||||||
|
|
||||||
|
#define ATH10K_HIF_MBOX0_EXT_BASE_ADDR 0x5000
|
||||||
|
#define ATH10K_HIF_MBOX0_EXT_WIDTH (36 * 1024)
|
||||||
|
#define ATH10K_HIF_MBOX0_EXT_WIDTH_ROME_2_0 (56 * 1024)
|
||||||
|
#define ATH10K_HIF_MBOX1_EXT_WIDTH (36 * 1024)
|
||||||
|
#define ATH10K_HIF_MBOX_DUMMY_SPACE_SIZE (2 * 1024)
|
||||||
|
|
||||||
|
#define ATH10K_HTC_MBOX_MAX_PAYLOAD_LENGTH \
|
||||||
|
(ATH10K_SDIO_MAX_BUFFER_SIZE - sizeof(struct ath10k_htc_hdr))
|
||||||
|
|
||||||
|
#define ATH10K_HIF_MBOX_NUM_MAX 4
|
||||||
|
#define ATH10K_SDIO_BUS_REQUEST_MAX_NUM 64
|
||||||
|
|
||||||
|
#define ATH10K_SDIO_HIF_COMMUNICATION_TIMEOUT_HZ (100 * HZ)
|
||||||
|
|
||||||
|
/* HTC runs over mailbox 0 */
|
||||||
|
#define ATH10K_HTC_MAILBOX 0
|
||||||
|
#define ATH10K_HTC_MAILBOX_MASK BIT(ATH10K_HTC_MAILBOX)
|
||||||
|
|
||||||
|
/* GMBOX addresses */
|
||||||
|
#define ATH10K_HIF_GMBOX_BASE_ADDR 0x7000
|
||||||
|
#define ATH10K_HIF_GMBOX_WIDTH 0x4000
|
||||||
|
|
||||||
|
/* Modified versions of the sdio.h macros.
|
||||||
|
* The macros in sdio.h can't be used easily with the FIELD_{PREP|GET}
|
||||||
|
* macros in bitfield.h, so we define our own macros here.
|
||||||
|
*/
|
||||||
|
#define ATH10K_SDIO_DRIVE_DTSX_MASK \
|
||||||
|
(SDIO_DRIVE_DTSx_MASK << SDIO_DRIVE_DTSx_SHIFT)
|
||||||
|
|
||||||
|
#define ATH10K_SDIO_DRIVE_DTSX_TYPE_B 0
|
||||||
|
#define ATH10K_SDIO_DRIVE_DTSX_TYPE_A 1
|
||||||
|
#define ATH10K_SDIO_DRIVE_DTSX_TYPE_C 2
|
||||||
|
#define ATH10K_SDIO_DRIVE_DTSX_TYPE_D 3
|
||||||
|
|
||||||
|
/* SDIO CCCR register definitions */
|
||||||
|
#define CCCR_SDIO_IRQ_MODE_REG 0xF0
|
||||||
|
#define CCCR_SDIO_IRQ_MODE_REG_SDIO3 0x16
|
||||||
|
|
||||||
|
#define CCCR_SDIO_DRIVER_STRENGTH_ENABLE_ADDR 0xF2
|
||||||
|
|
||||||
|
#define CCCR_SDIO_DRIVER_STRENGTH_ENABLE_A 0x02
|
||||||
|
#define CCCR_SDIO_DRIVER_STRENGTH_ENABLE_C 0x04
|
||||||
|
#define CCCR_SDIO_DRIVER_STRENGTH_ENABLE_D 0x08
|
||||||
|
|
||||||
|
#define CCCR_SDIO_ASYNC_INT_DELAY_ADDRESS 0xF0
|
||||||
|
#define CCCR_SDIO_ASYNC_INT_DELAY_MASK 0xC0
|
||||||
|
|
||||||
|
/* mode to enable special 4-bit interrupt assertion without clock */
|
||||||
|
#define SDIO_IRQ_MODE_ASYNC_4BIT_IRQ BIT(0)
|
||||||
|
#define SDIO_IRQ_MODE_ASYNC_4BIT_IRQ_SDIO3 BIT(1)
|
||||||
|
|
||||||
|
#define ATH10K_SDIO_TARGET_DEBUG_INTR_MASK 0x01
|
||||||
|
|
||||||
|
/* The theoretical maximum number of RX messages that can be fetched
|
||||||
|
* from the mbox interrupt handler in one loop is derived in the following
|
||||||
|
* way:
|
||||||
|
*
|
||||||
|
* Let's assume that each packet in a bundle of the maximum bundle size
|
||||||
|
* (HTC_HOST_MAX_MSG_PER_BUNDLE) has the HTC header bundle count set
|
||||||
|
* to the maximum value (HTC_HOST_MAX_MSG_PER_BUNDLE).
|
||||||
|
*
|
||||||
|
* in this case the driver must allocate
|
||||||
|
* (HTC_HOST_MAX_MSG_PER_BUNDLE * HTC_HOST_MAX_MSG_PER_BUNDLE) skb's.
|
||||||
|
*/
|
||||||
|
#define ATH10K_SDIO_MAX_RX_MSGS \
|
||||||
|
(HTC_HOST_MAX_MSG_PER_BUNDLE * HTC_HOST_MAX_MSG_PER_BUNDLE)
|
||||||
|
|
||||||
|
#define ATH10K_FIFO_TIMEOUT_AND_CHIP_CONTROL 0x00000868u
|
||||||
|
#define ATH10K_FIFO_TIMEOUT_AND_CHIP_CONTROL_DISABLE_SLEEP_OFF 0xFFFEFFFF
|
||||||
|
#define ATH10K_FIFO_TIMEOUT_AND_CHIP_CONTROL_DISABLE_SLEEP_ON 0x10000
|
||||||
|
|
||||||
|
struct ath10k_sdio_bus_request {
|
||||||
|
struct list_head list;
|
||||||
|
|
||||||
|
/* sdio address */
|
||||||
|
u32 address;
|
||||||
|
|
||||||
|
struct sk_buff *skb;
|
||||||
|
enum ath10k_htc_ep_id eid;
|
||||||
|
int status;
|
||||||
|
/* Specifies if the current request is an HTC message.
|
||||||
|
* If not, the eid is not applicable an the TX completion handler
|
||||||
|
* associated with the endpoint will not be invoked.
|
||||||
|
*/
|
||||||
|
bool htc_msg;
|
||||||
|
/* Completion that (if set) will be invoked for non HTC requests
|
||||||
|
* (htc_msg == false) when the request has been processed.
|
||||||
|
*/
|
||||||
|
struct completion *comp;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct ath10k_sdio_rx_data {
|
||||||
|
struct sk_buff *skb;
|
||||||
|
size_t alloc_len;
|
||||||
|
size_t act_len;
|
||||||
|
enum ath10k_htc_ep_id eid;
|
||||||
|
bool part_of_bundle;
|
||||||
|
bool last_in_bundle;
|
||||||
|
bool trailer_only;
|
||||||
|
int status;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct ath10k_sdio_irq_proc_regs {
|
||||||
|
u8 host_int_status;
|
||||||
|
u8 cpu_int_status;
|
||||||
|
u8 error_int_status;
|
||||||
|
u8 counter_int_status;
|
||||||
|
u8 mbox_frame;
|
||||||
|
u8 rx_lookahead_valid;
|
||||||
|
u8 host_int_status2;
|
||||||
|
u8 gmbox_rx_avail;
|
||||||
|
__le32 rx_lookahead[2];
|
||||||
|
__le32 rx_gmbox_lookahead_alias[2];
|
||||||
|
};
|
||||||
|
|
||||||
|
struct ath10k_sdio_irq_enable_regs {
|
||||||
|
u8 int_status_en;
|
||||||
|
u8 cpu_int_status_en;
|
||||||
|
u8 err_int_status_en;
|
||||||
|
u8 cntr_int_status_en;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct ath10k_sdio_irq_data {
|
||||||
|
/* protects irq_proc_reg and irq_en_reg below.
|
||||||
|
* We use a mutex here and not a spinlock since we will have the
|
||||||
|
* mutex locked while calling the sdio_memcpy_ functions.
|
||||||
|
* These function require non atomic context, and hence, spinlocks
|
||||||
|
* can be held while calling these functions.
|
||||||
|
*/
|
||||||
|
struct mutex mtx;
|
||||||
|
struct ath10k_sdio_irq_proc_regs *irq_proc_reg;
|
||||||
|
struct ath10k_sdio_irq_enable_regs *irq_en_reg;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct ath10k_mbox_ext_info {
|
||||||
|
u32 htc_ext_addr;
|
||||||
|
u32 htc_ext_sz;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct ath10k_mbox_info {
|
||||||
|
u32 htc_addr;
|
||||||
|
struct ath10k_mbox_ext_info ext_info[2];
|
||||||
|
u32 block_size;
|
||||||
|
u32 block_mask;
|
||||||
|
u32 gmbox_addr;
|
||||||
|
u32 gmbox_sz;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct ath10k_sdio {
|
||||||
|
struct sdio_func *func;
|
||||||
|
|
||||||
|
struct ath10k_mbox_info mbox_info;
|
||||||
|
bool swap_mbox;
|
||||||
|
u32 mbox_addr[ATH10K_HTC_EP_COUNT];
|
||||||
|
u32 mbox_size[ATH10K_HTC_EP_COUNT];
|
||||||
|
|
||||||
|
/* available bus requests */
|
||||||
|
struct ath10k_sdio_bus_request bus_req[ATH10K_SDIO_BUS_REQUEST_MAX_NUM];
|
||||||
|
/* free list of bus requests */
|
||||||
|
struct list_head bus_req_freeq;
|
||||||
|
/* protects access to bus_req_freeq */
|
||||||
|
spinlock_t lock;
|
||||||
|
|
||||||
|
struct ath10k_sdio_rx_data rx_pkts[ATH10K_SDIO_MAX_RX_MSGS];
|
||||||
|
size_t n_rx_pkts;
|
||||||
|
|
||||||
|
struct ath10k *ar;
|
||||||
|
struct ath10k_sdio_irq_data irq_data;
|
||||||
|
|
||||||
|
/* temporary buffer for BMI requests */
|
||||||
|
u8 *bmi_buf;
|
||||||
|
|
||||||
|
wait_queue_head_t irq_wq;
|
||||||
|
|
||||||
|
bool is_disabled;
|
||||||
|
|
||||||
|
struct workqueue_struct *workqueue;
|
||||||
|
struct work_struct wr_async_work;
|
||||||
|
struct list_head wr_asyncq;
|
||||||
|
/* protects access to wr_asyncq */
|
||||||
|
spinlock_t wr_async_lock;
|
||||||
|
};
|
||||||
|
|
||||||
|
static inline struct ath10k_sdio *ath10k_sdio_priv(struct ath10k *ar)
|
||||||
|
{
|
||||||
|
return (struct ath10k_sdio *)ar->drv_priv;
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif
|
|
@ -205,6 +205,24 @@ struct host_interest {
|
||||||
*/
|
*/
|
||||||
/* Bit 1 - unused */
|
/* Bit 1 - unused */
|
||||||
u32 hi_fw_swap; /* 0x104 */
|
u32 hi_fw_swap; /* 0x104 */
|
||||||
|
|
||||||
|
/* global arenas pointer address, used by host driver debug */
|
||||||
|
u32 hi_dynamic_mem_arenas_addr; /* 0x108 */
|
||||||
|
|
||||||
|
/* allocated bytes of DRAM use by allocated */
|
||||||
|
u32 hi_dynamic_mem_allocated; /* 0x10C */
|
||||||
|
|
||||||
|
/* remaining bytes of DRAM */
|
||||||
|
u32 hi_dynamic_mem_remaining; /* 0x110 */
|
||||||
|
|
||||||
|
/* memory track count, configured by host */
|
||||||
|
u32 hi_dynamic_mem_track_max; /* 0x114 */
|
||||||
|
|
||||||
|
/* minidump buffer */
|
||||||
|
u32 hi_minidump; /* 0x118 */
|
||||||
|
|
||||||
|
/* bdata's sig and key addr */
|
||||||
|
u32 hi_bd_sig_key; /* 0x11c */
|
||||||
} __packed;
|
} __packed;
|
||||||
|
|
||||||
#define HI_ITEM(item) offsetof(struct host_interest, item)
|
#define HI_ITEM(item) offsetof(struct host_interest, item)
|
||||||
|
@ -319,6 +337,12 @@ struct host_interest {
|
||||||
#define HI_ACS_FLAGS_USE_WWAN (1 << 1)
|
#define HI_ACS_FLAGS_USE_WWAN (1 << 1)
|
||||||
/* Use test VAP */
|
/* Use test VAP */
|
||||||
#define HI_ACS_FLAGS_TEST_VAP (1 << 2)
|
#define HI_ACS_FLAGS_TEST_VAP (1 << 2)
|
||||||
|
/* SDIO/mailbox ACS flag definitions */
|
||||||
|
#define HI_ACS_FLAGS_SDIO_SWAP_MAILBOX_SET (1 << 0)
|
||||||
|
#define HI_ACS_FLAGS_SDIO_REDUCE_TX_COMPL_SET (1 << 1)
|
||||||
|
#define HI_ACS_FLAGS_ALT_DATA_CREDIT_SIZE (1 << 2)
|
||||||
|
#define HI_ACS_FLAGS_SDIO_SWAP_MAILBOX_FW_ACK (1 << 16)
|
||||||
|
#define HI_ACS_FLAGS_SDIO_REDUCE_TX_COMPL_FW_ACK (1 << 17)
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* CONSOLE FLAGS
|
* CONSOLE FLAGS
|
||||||
|
|
|
@ -137,6 +137,13 @@ static int ath10k_tm_cmd_get_version(struct ath10k *ar, struct nlattr *tb[])
|
||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
ret = nla_put_u32(skb, ATH10K_TM_ATTR_WMI_OP_VERSION,
|
||||||
|
ar->normal_mode_fw.fw_file.wmi_op_version);
|
||||||
|
if (ret) {
|
||||||
|
kfree_skb(skb);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
return cfg80211_testmode_reply(skb);
|
return cfg80211_testmode_reply(skb);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -33,6 +33,7 @@ enum ath10k_tm_attr {
|
||||||
ATH10K_TM_ATTR_WMI_CMDID = 3,
|
ATH10K_TM_ATTR_WMI_CMDID = 3,
|
||||||
ATH10K_TM_ATTR_VERSION_MAJOR = 4,
|
ATH10K_TM_ATTR_VERSION_MAJOR = 4,
|
||||||
ATH10K_TM_ATTR_VERSION_MINOR = 5,
|
ATH10K_TM_ATTR_VERSION_MINOR = 5,
|
||||||
|
ATH10K_TM_ATTR_WMI_OP_VERSION = 6,
|
||||||
|
|
||||||
/* keep last */
|
/* keep last */
|
||||||
__ATH10K_TM_ATTR_AFTER_LAST,
|
__ATH10K_TM_ATTR_AFTER_LAST,
|
||||||
|
|
|
@ -938,7 +938,10 @@ static int open_file_eeprom(struct inode *inode, struct file *file)
|
||||||
}
|
}
|
||||||
|
|
||||||
for (i = 0; i < eesize; ++i) {
|
for (i = 0; i < eesize; ++i) {
|
||||||
AR5K_EEPROM_READ(i, val);
|
if (!ath5k_hw_nvram_read(ah, i, &val)) {
|
||||||
|
ret = -EIO;
|
||||||
|
goto freebuf;
|
||||||
|
}
|
||||||
buf[i] = val;
|
buf[i] = val;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -399,15 +399,10 @@ int ath6kl_data_tx(struct sk_buff *skb, struct net_device *dev)
|
||||||
csum_dest = skb->csum_offset + csum_start;
|
csum_dest = skb->csum_offset + csum_start;
|
||||||
}
|
}
|
||||||
|
|
||||||
if (skb_headroom(skb) < dev->needed_headroom) {
|
if (skb_cow_head(skb, dev->needed_headroom)) {
|
||||||
struct sk_buff *tmp_skb = skb;
|
dev->stats.tx_dropped++;
|
||||||
|
kfree_skb(skb);
|
||||||
skb = skb_realloc_headroom(skb, dev->needed_headroom);
|
return 0;
|
||||||
kfree_skb(tmp_skb);
|
|
||||||
if (skb == NULL) {
|
|
||||||
dev->stats.tx_dropped++;
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
if (ath6kl_wmi_dix_2_dot3(ar->wmi, skb)) {
|
if (ath6kl_wmi_dix_2_dot3(ar->wmi, skb)) {
|
||||||
|
|
|
@ -369,7 +369,7 @@ void ath9k_cmn_update_txpow(struct ath_hw *ah, u16 cur_txpow,
|
||||||
{
|
{
|
||||||
struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
|
struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
|
||||||
|
|
||||||
if (reg->power_limit != new_txpow)
|
if (ah->curchan && reg->power_limit != new_txpow)
|
||||||
ath9k_hw_set_txpowerlimit(ah, new_txpow, false);
|
ath9k_hw_set_txpowerlimit(ah, new_txpow, false);
|
||||||
|
|
||||||
/* read back in case value is clamped */
|
/* read back in case value is clamped */
|
||||||
|
|
|
@ -143,7 +143,7 @@ bool ath9k_hw_nvram_read(struct ath_hw *ah, u32 off, u16 *data)
|
||||||
|
|
||||||
if (ah->eeprom_blob)
|
if (ah->eeprom_blob)
|
||||||
ret = ath9k_hw_nvram_read_firmware(ah->eeprom_blob, off, data);
|
ret = ath9k_hw_nvram_read_firmware(ah->eeprom_blob, off, data);
|
||||||
else if (pdata && !pdata->use_eeprom && pdata->eeprom_data)
|
else if (pdata && !pdata->use_eeprom)
|
||||||
ret = ath9k_hw_nvram_read_pdata(pdata, off, data);
|
ret = ath9k_hw_nvram_read_pdata(pdata, off, data);
|
||||||
else
|
else
|
||||||
ret = common->bus_ops->eeprom_read(common, off, data);
|
ret = common->bus_ops->eeprom_read(common, off, data);
|
||||||
|
|
|
@ -153,7 +153,7 @@ static int ath9k_tx99_init(struct ath_softc *sc)
|
||||||
sc->tx99_power,
|
sc->tx99_power,
|
||||||
sc->tx99_power / 2);
|
sc->tx99_power / 2);
|
||||||
|
|
||||||
/* We leave the harware awake as it will be chugging on */
|
/* We leave the hardware awake as it will be chugging on */
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
|
@ -795,15 +795,11 @@ static ssize_t wil_write_file_txmgmt(struct file *file, const char __user *buf,
|
||||||
struct wireless_dev *wdev = wil_to_wdev(wil);
|
struct wireless_dev *wdev = wil_to_wdev(wil);
|
||||||
struct cfg80211_mgmt_tx_params params;
|
struct cfg80211_mgmt_tx_params params;
|
||||||
int rc;
|
int rc;
|
||||||
void *frame = kmalloc(len, GFP_KERNEL);
|
void *frame;
|
||||||
|
|
||||||
if (!frame)
|
frame = memdup_user(buf, len);
|
||||||
return -ENOMEM;
|
if (IS_ERR(frame))
|
||||||
|
return PTR_ERR(frame);
|
||||||
if (copy_from_user(frame, buf, len)) {
|
|
||||||
kfree(frame);
|
|
||||||
return -EIO;
|
|
||||||
}
|
|
||||||
|
|
||||||
params.buf = frame;
|
params.buf = frame;
|
||||||
params.len = len;
|
params.len = len;
|
||||||
|
|
Loading…
Reference in New Issue