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drm/rockchip: Separate RK3288 from RK3368 win01 registers 

This commit splits the registers for RK3288 from those
for RK3328, RK3368 and RK3399. It seems RK3288 does not
support plane x-y-mirroring, and so in order to support this
for the other SoCs, we need to have separate set of registers
for win0 and win1.

Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://patchwork.freedesktop.org/patch/msgid/20190109185639.5093-3-ezequiel@collabora.com
This commit is contained in:
Ezequiel Garcia 2019-01-09 15:56:38 -03:00 committed by Heiko Stuebner
parent 2996fb75d6
commit fbb1c73826
1 changed files with 25 additions and 6 deletions
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31
drivers/gpu/drm/rockchip/rockchip_vop_reg.c
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@ -550,6 +550,25 @@ static const struct vop_intr rk3368_vop_intr = {
.clear = VOP_REG_MASK_SYNC(RK3368_INTR_CLEAR, 0x3fff, 0), .clear = VOP_REG_MASK_SYNC(RK3368_INTR_CLEAR, 0x3fff, 0),
}; };
static const struct vop_win_phy rk3368_win01_data = {
.scl = &rk3288_win_full_scl,
.data_formats = formats_win_full,
.nformats = ARRAY_SIZE(formats_win_full),
.enable = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 0),
.format = VOP_REG(RK3368_WIN0_CTRL0, 0x7, 1),
.rb_swap = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 12),
.act_info = VOP_REG(RK3368_WIN0_ACT_INFO, 0x1fff1fff, 0),
.dsp_info = VOP_REG(RK3368_WIN0_DSP_INFO, 0x0fff0fff, 0),
.dsp_st = VOP_REG(RK3368_WIN0_DSP_ST, 0x1fff1fff, 0),
.yrgb_mst = VOP_REG(RK3368_WIN0_YRGB_MST, 0xffffffff, 0),
.uv_mst = VOP_REG(RK3368_WIN0_CBR_MST, 0xffffffff, 0),
.yrgb_vir = VOP_REG(RK3368_WIN0_VIR, 0x3fff, 0),
.uv_vir = VOP_REG(RK3368_WIN0_VIR, 0x3fff, 16),
.src_alpha_ctl = VOP_REG(RK3368_WIN0_SRC_ALPHA_CTRL, 0xff, 0),
.dst_alpha_ctl = VOP_REG(RK3368_WIN0_DST_ALPHA_CTRL, 0xff, 0),
.channel = VOP_REG(RK3368_WIN0_CTRL2, 0xff, 0),
};
static const struct vop_win_phy rk3368_win23_data = { static const struct vop_win_phy rk3368_win23_data = {
.data_formats = formats_win_lite, .data_formats = formats_win_lite,
.nformats = ARRAY_SIZE(formats_win_lite), .nformats = ARRAY_SIZE(formats_win_lite),
@ -566,9 +585,9 @@ static const struct vop_win_phy rk3368_win23_data = {
}; };
static const struct vop_win_data rk3368_vop_win_data[] = { static const struct vop_win_data rk3368_vop_win_data[] = {
{ .base = 0x00, .phy = &rk3288_win01_data, { .base = 0x00, .phy = &rk3368_win01_data,
.type = DRM_PLANE_TYPE_PRIMARY }, .type = DRM_PLANE_TYPE_PRIMARY },
{ .base = 0x40, .phy = &rk3288_win01_data, { .base = 0x40, .phy = &rk3368_win01_data,
.type = DRM_PLANE_TYPE_OVERLAY }, .type = DRM_PLANE_TYPE_OVERLAY },
{ .base = 0x00, .phy = &rk3368_win23_data, { .base = 0x00, .phy = &rk3368_win23_data,
.type = DRM_PLANE_TYPE_OVERLAY }, .type = DRM_PLANE_TYPE_OVERLAY },
@ -679,7 +698,7 @@ static const struct vop_data rk3399_vop_big = {
}; };
static const struct vop_win_data rk3399_vop_lit_win_data[] = { static const struct vop_win_data rk3399_vop_lit_win_data[] = {
{ .base = 0x00, .phy = &rk3288_win01_data, { .base = 0x00, .phy = &rk3368_win01_data,
.type = DRM_PLANE_TYPE_PRIMARY }, .type = DRM_PLANE_TYPE_PRIMARY },
{ .base = 0x00, .phy = &rk3368_win23_data, { .base = 0x00, .phy = &rk3368_win23_data,
.type = DRM_PLANE_TYPE_CURSOR}, .type = DRM_PLANE_TYPE_CURSOR},
@ -766,11 +785,11 @@ static const struct vop_intr rk3328_vop_intr = {
}; };
static const struct vop_win_data rk3328_vop_win_data[] = { static const struct vop_win_data rk3328_vop_win_data[] = {
{ .base = 0xd0, .phy = &rk3288_win01_data, { .base = 0xd0, .phy = &rk3368_win01_data,
.type = DRM_PLANE_TYPE_PRIMARY }, .type = DRM_PLANE_TYPE_PRIMARY },
{ .base = 0x1d0, .phy = &rk3288_win01_data, { .base = 0x1d0, .phy = &rk3368_win01_data,
.type = DRM_PLANE_TYPE_OVERLAY }, .type = DRM_PLANE_TYPE_OVERLAY },
{ .base = 0x2d0, .phy = &rk3288_win01_data, { .base = 0x2d0, .phy = &rk3368_win01_data,
.type = DRM_PLANE_TYPE_CURSOR }, .type = DRM_PLANE_TYPE_CURSOR },
}; };