mirror of https://gitee.com/openkylin/linux.git
net: ipa: add IPA v4.5 configuration data
Add support for the SDX55 SoC, which includes IPA version 4.5. Starting with IPA v4.5, a few of the memory regions have a different number of "canary" values; update comments in the where the region identifers are defined to accurately reflect that. I'll note three differences in SDX55 versus the other two existing platforms (SDM845 and SC7180): - SDX55 uses a 32-bit Linux kernel - SDX55 has four interconnects rather than three - SDX55 uses IPA v4.5, which uses inline checksum offload Signed-off-by: Alex Elder <elder@linaro.org> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Alex Elder
David S. Miller
parent
c88c34fcf8
commit
fbb763e7e7
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@ -9,4 +9,5 @@ ipa-y := ipa_main.o ipa_clock.o ipa_reg.o ipa_mem.o \
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ipa_endpoint.o ipa_cmd.o ipa_modem.o \
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ipa_resource.o ipa_qmi.o ipa_qmi_msg.o
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ipa-y += ipa_data-v3.5.1.o ipa_data-v4.2.o
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ipa-y += ipa_data-v3.5.1.o ipa_data-v4.2.o \
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ipa_data-v4.5.o
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@ -0,0 +1,437 @@
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// SPDX-License-Identifier: GPL-2.0
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/* Copyright (C) 2021 Linaro Ltd. */
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#include <linux/log2.h>
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#include "gsi.h"
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#include "ipa_data.h"
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#include "ipa_endpoint.h"
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#include "ipa_mem.h"
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/** enum ipa_resource_type - IPA resource types for an SoC having IPA v4.5 */
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enum ipa_resource_type {
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/* Source resource types; first must have value 0 */
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IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS = 0,
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IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS,
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IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF,
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IPA_RESOURCE_TYPE_SRC_HPS_DMARS,
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IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES,
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/* Destination resource types; first must have value 0 */
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IPA_RESOURCE_TYPE_DST_DATA_SECTORS = 0,
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IPA_RESOURCE_TYPE_DST_DPS_DMARS,
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};
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/* Resource groups used for an SoC having IPA v4.5 */
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enum ipa_rsrc_group_id {
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/* Source resource group identifiers */
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IPA_RSRC_GROUP_SRC_UNUSED_0 = 0,
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IPA_RSRC_GROUP_SRC_UL_DL,
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IPA_RSRC_GROUP_SRC_UNUSED_2,
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IPA_RSRC_GROUP_SRC_UNUSED_3,
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IPA_RSRC_GROUP_SRC_UC_RX_Q,
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IPA_RSRC_GROUP_SRC_COUNT, /* Last in set; not a source group */
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/* Destination resource group identifiers */
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IPA_RSRC_GROUP_DST_UNUSED_0 = 0,
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IPA_RSRC_GROUP_DST_UL_DL_DPL,
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IPA_RSRC_GROUP_DST_UNUSED_2,
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IPA_RSRC_GROUP_DST_UNUSED_3,
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IPA_RSRC_GROUP_DST_UC,
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IPA_RSRC_GROUP_DST_COUNT, /* Last; not a destination group */
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};
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/* QSB configuration data for an SoC having IPA v4.5 */
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static const struct ipa_qsb_data ipa_qsb_data[] = {
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[IPA_QSB_MASTER_DDR] = {
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.max_writes = 8,
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.max_reads = 0, /* no limit (hardware max) */
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.max_reads_beats = 120,
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},
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[IPA_QSB_MASTER_PCIE] = {
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.max_writes = 8,
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.max_reads = 12,
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/* no outstanding read byte (beat) limit */
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},
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};
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/* Endpoint configuration data for an SoC having IPA v4.5 */
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static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = {
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[IPA_ENDPOINT_AP_COMMAND_TX] = {
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.ee_id = GSI_EE_AP,
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.channel_id = 9,
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.endpoint_id = 7,
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.toward_ipa = true,
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.channel = {
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.tre_count = 256,
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.event_count = 256,
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.tlv_count = 20,
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},
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.endpoint = {
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.config = {
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.resource_group = IPA_RSRC_GROUP_SRC_UL_DL,
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.dma_mode = true,
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.dma_endpoint = IPA_ENDPOINT_AP_LAN_RX,
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.tx = {
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.seq_type = IPA_SEQ_DMA,
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},
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},
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},
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},
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[IPA_ENDPOINT_AP_LAN_RX] = {
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.ee_id = GSI_EE_AP,
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.channel_id = 10,
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.endpoint_id = 16,
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.toward_ipa = false,
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.channel = {
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.tre_count = 256,
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.event_count = 256,
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.tlv_count = 9,
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},
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.endpoint = {
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.config = {
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.resource_group = IPA_RSRC_GROUP_DST_UL_DL_DPL,
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.aggregation = true,
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.status_enable = true,
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.rx = {
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.pad_align = ilog2(sizeof(u32)),
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},
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},
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},
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},
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[IPA_ENDPOINT_AP_MODEM_TX] = {
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.ee_id = GSI_EE_AP,
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.channel_id = 7,
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.endpoint_id = 2,
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.toward_ipa = true,
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.channel = {
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.tre_count = 512,
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.event_count = 512,
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.tlv_count = 16,
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},
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.endpoint = {
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.filter_support = true,
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.config = {
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.resource_group = IPA_RSRC_GROUP_SRC_UL_DL,
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.qmap = true,
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.status_enable = true,
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.tx = {
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.seq_type = IPA_SEQ_2_PASS_SKIP_LAST_UC,
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.status_endpoint =
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IPA_ENDPOINT_MODEM_AP_RX,
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},
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},
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},
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},
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[IPA_ENDPOINT_AP_MODEM_RX] = {
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.ee_id = GSI_EE_AP,
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.channel_id = 1,
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.endpoint_id = 14,
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.toward_ipa = false,
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.channel = {
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.tre_count = 256,
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.event_count = 256,
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.tlv_count = 9,
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},
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.endpoint = {
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.config = {
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.resource_group = IPA_RSRC_GROUP_DST_UL_DL_DPL,
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.qmap = true,
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.aggregation = true,
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.rx = {
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.aggr_close_eof = true,
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},
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},
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},
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},
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[IPA_ENDPOINT_MODEM_AP_TX] = {
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.ee_id = GSI_EE_MODEM,
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.channel_id = 0,
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.endpoint_id = 5,
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.toward_ipa = true,
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.endpoint = {
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.filter_support = true,
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},
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},
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[IPA_ENDPOINT_MODEM_AP_RX] = {
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.ee_id = GSI_EE_MODEM,
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.channel_id = 7,
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.endpoint_id = 21,
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.toward_ipa = false,
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},
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[IPA_ENDPOINT_MODEM_DL_NLO_TX] = {
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.ee_id = GSI_EE_MODEM,
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.channel_id = 2,
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.endpoint_id = 8,
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.toward_ipa = true,
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.endpoint = {
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.filter_support = true,
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},
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},
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};
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/* Source resource configuration data for an SoC having IPA v4.5 */
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static const struct ipa_resource ipa_resource_src[] = {
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[IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS] = {
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.limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
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.min = 1, .max = 11,
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},
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.limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
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.min = 1, .max = 63,
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},
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},
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[IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS] = {
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.limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
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.min = 14, .max = 14,
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},
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.limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
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.min = 3, .max = 3,
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},
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},
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[IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF] = {
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.limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
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.min = 18, .max = 18,
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},
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.limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
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.min = 8, .max = 8,
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},
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},
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[IPA_RESOURCE_TYPE_SRC_HPS_DMARS] = {
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.limits[IPA_RSRC_GROUP_SRC_UNUSED_0] = {
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.min = 0, .max = 63,
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},
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.limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
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.min = 0, .max = 63,
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},
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.limits[IPA_RSRC_GROUP_SRC_UNUSED_2] = {
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.min = 0, .max = 63,
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},
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.limits[IPA_RSRC_GROUP_SRC_UNUSED_3] = {
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.min = 0, .max = 63,
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},
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.limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
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.min = 0, .max = 63,
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},
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},
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[IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES] = {
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.limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
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.min = 24, .max = 24,
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},
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.limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
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.min = 8, .max = 8,
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},
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},
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};
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/* Destination resource configuration data for an SoC having IPA v4.5 */
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static const struct ipa_resource ipa_resource_dst[] = {
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[IPA_RESOURCE_TYPE_DST_DATA_SECTORS] = {
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.limits[IPA_RSRC_GROUP_DST_UL_DL_DPL] = {
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.min = 16, .max = 16,
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},
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.limits[IPA_RSRC_GROUP_DST_UNUSED_2] = {
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.min = 2, .max = 2,
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},
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.limits[IPA_RSRC_GROUP_DST_UNUSED_3] = {
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.min = 2, .max = 2,
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},
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},
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[IPA_RESOURCE_TYPE_DST_DPS_DMARS] = {
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.limits[IPA_RSRC_GROUP_DST_UL_DL_DPL] = {
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.min = 2, .max = 63,
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},
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.limits[IPA_RSRC_GROUP_DST_UNUSED_2] = {
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.min = 1, .max = 2,
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},
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.limits[IPA_RSRC_GROUP_DST_UNUSED_3] = {
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.min = 1, .max = 2,
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},
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.limits[IPA_RSRC_GROUP_DST_UC] = {
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.min = 0, .max = 2,
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},
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},
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};
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/* Resource configuration data for an SoC having IPA v4.5 */
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static const struct ipa_resource_data ipa_resource_data = {
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.rsrc_group_src_count = IPA_RSRC_GROUP_SRC_COUNT,
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.rsrc_group_dst_count = IPA_RSRC_GROUP_DST_COUNT,
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.resource_src_count = ARRAY_SIZE(ipa_resource_src),
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.resource_src = ipa_resource_src,
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.resource_dst_count = ARRAY_SIZE(ipa_resource_dst),
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.resource_dst = ipa_resource_dst,
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};
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/* IPA-resident memory region data for an SoC having IPA v4.5 */
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static const struct ipa_mem ipa_mem_local_data[] = {
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[IPA_MEM_UC_SHARED] = {
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.offset = 0x0000,
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.size = 0x0080,
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.canary_count = 0,
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},
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[IPA_MEM_UC_INFO] = {
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.offset = 0x0080,
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.size = 0x0200,
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.canary_count = 0,
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},
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[IPA_MEM_V4_FILTER_HASHED] = {
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.offset = 0x0288,
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.size = 0x0078,
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.canary_count = 2,
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},
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[IPA_MEM_V4_FILTER] = {
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.offset = 0x0308,
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.size = 0x0078,
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.canary_count = 2,
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},
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[IPA_MEM_V6_FILTER_HASHED] = {
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.offset = 0x0388,
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.size = 0x0078,
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.canary_count = 2,
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},
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[IPA_MEM_V6_FILTER] = {
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.offset = 0x0408,
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.size = 0x0078,
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.canary_count = 2,
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},
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[IPA_MEM_V4_ROUTE_HASHED] = {
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.offset = 0x0488,
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.size = 0x0078,
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.canary_count = 2,
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},
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[IPA_MEM_V4_ROUTE] = {
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.offset = 0x0508,
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.size = 0x0078,
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.canary_count = 2,
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},
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[IPA_MEM_V6_ROUTE_HASHED] = {
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.offset = 0x0588,
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.size = 0x0078,
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.canary_count = 2,
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},
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[IPA_MEM_V6_ROUTE] = {
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.offset = 0x0608,
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.size = 0x0078,
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.canary_count = 2,
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},
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[IPA_MEM_MODEM_HEADER] = {
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.offset = 0x0688,
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.size = 0x0240,
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.canary_count = 2,
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},
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[IPA_MEM_AP_HEADER] = {
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.offset = 0x08c8,
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.size = 0x0200,
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.canary_count = 0,
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},
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[IPA_MEM_MODEM_PROC_CTX] = {
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.offset = 0x0ad0,
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.size = 0x0b20,
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.canary_count = 2,
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},
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[IPA_MEM_AP_PROC_CTX] = {
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.offset = 0x15f0,
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.size = 0x0200,
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.canary_count = 0,
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},
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[IPA_MEM_NAT_TABLE] = {
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.offset = 0x1800,
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.size = 0x0d00,
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.canary_count = 4,
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},
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[IPA_MEM_STATS_QUOTA_MODEM] = {
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.offset = 0x2510,
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.size = 0x0030,
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.canary_count = 4,
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},
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[IPA_MEM_STATS_QUOTA_AP] = {
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.offset = 0x2540,
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.size = 0x0048,
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.canary_count = 0,
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},
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[IPA_MEM_STATS_TETHERING] = {
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.offset = 0x2588,
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.size = 0x0238,
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.canary_count = 0,
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},
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[IPA_MEM_STATS_FILTER_ROUTE] = {
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.offset = 0x27c0,
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.size = 0x0800,
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.canary_count = 0,
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},
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[IPA_MEM_STATS_DROP] = {
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.offset = 0x2fc0,
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.size = 0x0020,
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.canary_count = 0,
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},
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[IPA_MEM_MODEM] = {
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.offset = 0x2fe8,
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.size = 0x0800,
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.canary_count = 2,
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},
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[IPA_MEM_UC_EVENT_RING] = {
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.offset = 0x3800,
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.size = 0x1000,
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.canary_count = 1,
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},
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[IPA_MEM_PDN_CONFIG] = {
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.offset = 0x4800,
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.size = 0x0050,
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.canary_count = 0,
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},
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};
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/* Memory configuration data for an SoC having IPA v4.5 */
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static const struct ipa_mem_data ipa_mem_data = {
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.local_count = ARRAY_SIZE(ipa_mem_local_data),
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.local = ipa_mem_local_data,
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.imem_addr = 0x14688000,
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.imem_size = 0x00003000,
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.smem_id = 497,
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.smem_size = 0x00009000,
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};
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/* Interconnect rates are in 1000 byte/second units */
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static const struct ipa_interconnect_data ipa_interconnect_data[] = {
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{
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.name = "memory-a",
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.peak_bandwidth = 600000, /* 600 MBps */
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.average_bandwidth = 150000, /* 150 MBps */
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},
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{
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.name = "memory-b",
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.peak_bandwidth = 1804000, /* 1.804 GBps */
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.average_bandwidth = 150000, /* 150 MBps */
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},
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/* Average rate is unused for the next two interconnects */
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{
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.name = "imem",
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.peak_bandwidth = 450000, /* 450 MBps */
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.average_bandwidth = 75000, /* 75 MBps (unused?) */
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},
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{
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.name = "config",
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.peak_bandwidth = 171400, /* 171.4 MBps */
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.average_bandwidth = 0, /* unused */
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},
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};
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/* Clock and interconnect configuration data for an SoC having IPA v4.5 */
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static const struct ipa_clock_data ipa_clock_data = {
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.core_clock_rate = 150 * 1000 * 1000, /* Hz (150? 60?) */
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.interconnect_count = ARRAY_SIZE(ipa_interconnect_data),
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.interconnect_data = ipa_interconnect_data,
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};
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/* Configuration data for an SoC having IPA v4.5 */
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const struct ipa_data ipa_data_v4_5 = {
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.version = IPA_VERSION_4_5,
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.qsb_count = ARRAY_SIZE(ipa_qsb_data),
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.qsb_data = ipa_qsb_data,
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.endpoint_count = ARRAY_SIZE(ipa_gsi_endpoint_data),
|
||||
.endpoint_data = ipa_gsi_endpoint_data,
|
||||
.resource_data = &ipa_resource_data,
|
||||
.mem_data = &ipa_mem_data,
|
||||
.clock_data = &ipa_clock_data,
|
||||
};
|
||||
|
|
@ -302,5 +302,6 @@ struct ipa_data {
|
|||
|
||||
extern const struct ipa_data ipa_data_v3_5_1;
|
||||
extern const struct ipa_data ipa_data_v4_2;
|
||||
extern const struct ipa_data ipa_data_v4_5;
|
||||
|
||||
#endif /* _IPA_DATA_H_ */
|
||||
|
|
|
|||
|
|
@ -573,6 +573,10 @@ static const struct of_device_id ipa_match[] = {
|
|||
.compatible = "qcom,sc7180-ipa",
|
||||
.data = &ipa_data_v4_2,
|
||||
},
|
||||
{
|
||||
.compatible = "qcom,sdx55-ipa",
|
||||
.data = &ipa_data_v4_5,
|
||||
},
|
||||
{ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, ipa_match);
|
||||
|
|
|
|||
|
|
@ -58,8 +58,8 @@ enum ipa_mem_id {
|
|||
IPA_MEM_MODEM_PROC_CTX, /* 2 canaries */
|
||||
IPA_MEM_AP_PROC_CTX, /* 0 canaries */
|
||||
IPA_MEM_NAT_TABLE, /* 4 canaries (IPA v4.5 and above) */
|
||||
IPA_MEM_PDN_CONFIG, /* 2 canaries (IPA v4.0 and above) */
|
||||
IPA_MEM_STATS_QUOTA_MODEM, /* 2 canaries (IPA v4.0 and above) */
|
||||
IPA_MEM_PDN_CONFIG, /* 0/2 canaries (IPA v4.0 and above) */
|
||||
IPA_MEM_STATS_QUOTA_MODEM, /* 2/4 canaries (IPA v4.0 and above) */
|
||||
IPA_MEM_STATS_QUOTA_AP, /* 0 canaries (IPA v4.0 and above) */
|
||||
IPA_MEM_STATS_TETHERING, /* 0 canaries (IPA v4.0 and above) */
|
||||
IPA_MEM_STATS_V4_FILTER, /* 0 canaries (IPA v4.0-v4.2) */
|
||||
|
|
@ -68,7 +68,7 @@ enum ipa_mem_id {
|
|||
IPA_MEM_STATS_V6_ROUTE, /* 0 canaries (IPA v4.0-v4.2) */
|
||||
IPA_MEM_STATS_FILTER_ROUTE, /* 0 canaries (IPA v4.5 and above) */
|
||||
IPA_MEM_STATS_DROP, /* 0 canaries (IPA v4.0 and above) */
|
||||
IPA_MEM_MODEM, /* 0 canaries */
|
||||
IPA_MEM_MODEM, /* 0/2 canaries */
|
||||
IPA_MEM_UC_EVENT_RING, /* 1 canary */
|
||||
IPA_MEM_COUNT, /* Number of regions (not an index) */
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in New Issue