From 8869dff1bdb3337594e50e66e594a027b1ac7fb5 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Fri, 29 May 2020 15:14:49 +1000 Subject: [PATCH 001/145] drm/nouveau/disp/gm200-: remove 'head' parameter from nvkm_ior_func.hdmi.scdc() It's no longer required. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigm200.c | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h | 4 ++-- drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c | 3 +-- 3 files changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigm200.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigm200.c index bf6d41fb0c9f..bb32befa6ad4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigm200.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigm200.c @@ -24,7 +24,7 @@ #include "hdmi.h" void -gm200_hdmi_scdc(struct nvkm_ior *ior, int head, u8 scdc) +gm200_hdmi_scdc(struct nvkm_ior *ior, u8 scdc) { struct nvkm_device *device = ior->disp->engine.subdev.device; const u32 soff = nv50_ior_base(ior); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h b/drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h index 1a200a9ba4e4..09f3038eff26 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h @@ -66,7 +66,7 @@ struct nvkm_ior_func { void (*ctrl)(struct nvkm_ior *, int head, bool enable, u8 max_ac_packet, u8 rekey, u8 *avi, u8 avi_size, u8 *vendor, u8 vendor_size); - void (*scdc)(struct nvkm_ior *, int head, u8 scdc); + void (*scdc)(struct nvkm_ior *, u8 scdc); } hdmi; struct { @@ -156,7 +156,7 @@ void gf119_hdmi_ctrl(struct nvkm_ior *, int, bool, u8, u8, u8 *, u8 , u8 *, u8); void gk104_hdmi_ctrl(struct nvkm_ior *, int, bool, u8, u8, u8 *, u8 , u8 *, u8); void gv100_hdmi_ctrl(struct nvkm_ior *, int, bool, u8, u8, u8 *, u8 , u8 *, u8); -void gm200_hdmi_scdc(struct nvkm_ior *, int, u8); +void gm200_hdmi_scdc(struct nvkm_ior *, u8); void gt215_hda_hpd(struct nvkm_ior *, int, bool); void gt215_hda_eld(struct nvkm_ior *, int, u8 *, u8); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c index fb5de44e4b8d..ecde98dd2454 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c @@ -205,8 +205,7 @@ nv50_disp_root_mthd_(struct nvkm_object *object, u32 mthd, void *data, u32 size) vendor, vendor_size); if (outp->ior->func->hdmi.scdc) - outp->ior->func->hdmi.scdc( - outp->ior, hidx, args->v0.scdc); + outp->ior->func->hdmi.scdc(outp->ior, args->v0.scdc); return 0; } From f612b0f66cbe300230bd3465a08205e71072467d Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sat, 30 May 2020 09:34:08 +1000 Subject: [PATCH 002/145] drm/nouveau/gr/gf100-: make some functions static Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c | 6 +++--- drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c index f2f5636efac4..9ac0f9449b5e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c @@ -741,7 +741,7 @@ gf100_gr_fecs_ctrl_ctxsw(struct gf100_gr *gr, u32 mthd) return -ETIMEDOUT; } -int +static int gf100_gr_fecs_start_ctxsw(struct nvkm_gr *base) { struct gf100_gr *gr = gf100_gr(base); @@ -756,7 +756,7 @@ gf100_gr_fecs_start_ctxsw(struct nvkm_gr *base) return ret; } -int +static int gf100_gr_fecs_stop_ctxsw(struct nvkm_gr *base) { struct gf100_gr *gr = gf100_gr(base); @@ -2032,7 +2032,7 @@ gf100_gr_fini(struct nvkm_gr *base, bool suspend) return 0; } -void * +static void * gf100_gr_dtor(struct nvkm_gr *base) { struct gf100_gr *gr = gf100_gr(base); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c index e56880f3e3bd..6d4d72851610 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c @@ -33,7 +33,7 @@ struct gk20a_fw_av u32 data; }; -int +static int gk20a_gr_av_to_init(struct gf100_gr *gr, const char *path, const char *name, int ver, struct gf100_gr_pack **ppack) { @@ -83,7 +83,7 @@ struct gk20a_fw_aiv u32 data; }; -int +static int gk20a_gr_aiv_to_init(struct gf100_gr *gr, const char *path, const char *name, int ver, struct gf100_gr_pack **ppack) { @@ -126,7 +126,7 @@ gk20a_gr_aiv_to_init(struct gf100_gr *gr, const char *path, const char *name, return ret; } -int +static int gk20a_gr_av_to_method(struct gf100_gr *gr, const char *path, const char *name, int ver, struct gf100_gr_pack **ppack) { From 8b962dc4ece7177ad7f5357f4694df1ed5558e44 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sat, 30 May 2020 09:35:55 +1000 Subject: [PATCH 003/145] drm/nouveau/nvfw/acr: make lsb_header_tail_dump static Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c b/drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c index 0d063b8317f7..bef790ad8f2f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c +++ b/drivers/gpu/drm/nouveau/nvkm/nvfw/acr.c @@ -45,9 +45,8 @@ wpr_header_v1_dump(struct nvkm_subdev *subdev, const struct wpr_header_v1 *hdr) nvkm_debug(subdev, "\tstatus : %d\n", hdr->status); } -void -lsb_header_tail_dump(struct nvkm_subdev *subdev, - struct lsb_header_tail *hdr) +static void +lsb_header_tail_dump(struct nvkm_subdev *subdev, struct lsb_header_tail *hdr) { nvkm_debug(subdev, "lsbHeader\n"); nvkm_debug(subdev, "\tucodeOff : 0x%x\n", hdr->ucode_off); From 94cad89ae4505672ae65457d12f77c44ca87655b Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sat, 30 May 2020 09:53:57 +1000 Subject: [PATCH 004/145] drm/nouveau/mc/gp10b: make gp10b_mc_init static Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/subdev/mc/gp10b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gp10b.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gp10b.c index ff8629de97d6..45c62f5ef782 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gp10b.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gp10b.c @@ -23,7 +23,7 @@ #include "priv.h" -void +static void gp10b_mc_init(struct nvkm_mc *mc) { struct nvkm_device *device = mc->subdev.device; From 3b54befd49dc526284312e6d481b08246943197f Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sat, 30 May 2020 09:54:26 +1000 Subject: [PATCH 005/145] drm/nouveau/mmu: make a couple of functions static Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/mmu/tu102.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c index ee11ccaf0563..de91e9a26172 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c @@ -61,7 +61,7 @@ nvkm_mmu_ptp_put(struct nvkm_mmu *mmu, bool force, struct nvkm_mmu_pt *pt) kfree(pt); } -struct nvkm_mmu_pt * +static struct nvkm_mmu_pt * nvkm_mmu_ptp_get(struct nvkm_mmu *mmu, u32 size, bool zero) { struct nvkm_mmu_pt *pt; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/tu102.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/tu102.c index b21e82eb0916..94081f35f967 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/tu102.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/tu102.c @@ -27,7 +27,7 @@ #include -const u8 * +static const u8 * tu102_mmu_kind(struct nvkm_mmu *mmu, int *count, u8 *invalid) { static const u8 From 9c64a8dbcb4671df868d7214442c62269e8b671c Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sat, 30 May 2020 09:55:19 +1000 Subject: [PATCH 006/145] drm/nouveau/therm/gt215: make gt215_therm_init static Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/subdev/therm/gt215.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gt215.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gt215.c index 4caf401d001a..c08097f2aff5 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gt215.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gt215.c @@ -36,7 +36,7 @@ gt215_therm_fan_sense(struct nvkm_therm *therm) return -ENODEV; } -void +static void gt215_therm_init(struct nvkm_therm *therm) { struct nvkm_device *device = therm->subdev.device; From 804f570502289f9ccb31660da8d041fa14af6c65 Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Tue, 9 Jun 2020 07:52:03 -0500 Subject: [PATCH 007/145] drm/nouveau/tmr: fix nvkm_usec/nvkm_msec definitions nvkm_timer_wait_init() takes a u64 as a duration parameter, but the expression "(m) * 1000" will be promoted only to a 32-bit integer, if 'm' is also an integer. Changing the 1000 to 1000ULL ensures that the expression will be 64 bits. This change currently has no effect as there are no callers of nvkm_msec() that exceed 2000ms. Signed-off-by: Timur Tabi Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/include/nvkm/subdev/timer.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/timer.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/timer.h index a8c21c6c800b..d06dcbe1faa6 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/timer.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/timer.h @@ -63,8 +63,8 @@ s64 nvkm_timer_wait_test(struct nvkm_timer_wait *); dev_WARN(_wait.tmr->subdev.device->dev, "timeout\n"); \ _taken; \ }) -#define nvkm_usec(d,u,cond...) nvkm_nsec((d), (u) * 1000, ##cond) -#define nvkm_msec(d,m,cond...) nvkm_usec((d), (m) * 1000, ##cond) +#define nvkm_usec(d, u, cond...) nvkm_nsec((d), (u) * 1000ULL, ##cond) +#define nvkm_msec(d, m, cond...) nvkm_usec((d), (m) * 1000ULL, ##cond) #define nvkm_wait_nsec(d,n,addr,mask,data) \ nvkm_nsec(d, n, \ From b448a266cc4a2a960a65108a4a36d36c17cd74b2 Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Tue, 9 Jun 2020 07:52:04 -0500 Subject: [PATCH 008/145] drm/nouveau/nvfw: firmware structures should begin with nvfw_ Rename all structures that are used directly by firmware to have a nvfw_ prefix. This makes it easier to identify structures that have a fixed, specific layout. A future patch will define several more such structures, so it's important to be consistent now. Signed-off-by: Timur Tabi Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/include/nvfw/pmu.h | 6 +++--- drivers/gpu/drm/nouveau/include/nvfw/sec2.h | 6 +++--- drivers/gpu/drm/nouveau/include/nvkm/core/falcon.h | 10 +++++----- drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c | 2 +- drivers/gpu/drm/nouveau/nvkm/falcon/cmdq.c | 6 +++--- drivers/gpu/drm/nouveau/nvkm/falcon/msgq.c | 8 ++++---- drivers/gpu/drm/nouveau/nvkm/falcon/qmgr.h | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm20b.c | 4 ++-- drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp10b.c | 2 +- 9 files changed, 23 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/nouveau/include/nvfw/pmu.h b/drivers/gpu/drm/nouveau/include/nvfw/pmu.h index 452ed7d03827..64a51e7c4543 100644 --- a/drivers/gpu/drm/nouveau/include/nvfw/pmu.h +++ b/drivers/gpu/drm/nouveau/include/nvfw/pmu.h @@ -25,7 +25,7 @@ struct nv_pmu_args { #define NV_PMU_UNIT_ACR 0x0a struct nv_pmu_init_msg { - struct nv_falcon_msg hdr; + struct nvfw_falcon_msg hdr; #define NV_PMU_INIT_MSG_INIT 0x00 u8 msg_type; @@ -44,7 +44,7 @@ struct nv_pmu_init_msg { }; struct nv_pmu_acr_cmd { - struct nv_falcon_cmd hdr; + struct nvfw_falcon_cmd hdr; #define NV_PMU_ACR_CMD_INIT_WPR_REGION 0x00 #define NV_PMU_ACR_CMD_BOOTSTRAP_FALCON 0x01 #define NV_PMU_ACR_CMD_BOOTSTRAP_MULTIPLE_FALCONS 0x03 @@ -52,7 +52,7 @@ struct nv_pmu_acr_cmd { }; struct nv_pmu_acr_msg { - struct nv_falcon_cmd hdr; + struct nvfw_falcon_cmd hdr; u8 msg_type; }; diff --git a/drivers/gpu/drm/nouveau/include/nvfw/sec2.h b/drivers/gpu/drm/nouveau/include/nvfw/sec2.h index 03496558b775..9a37ad4179cb 100644 --- a/drivers/gpu/drm/nouveau/include/nvfw/sec2.h +++ b/drivers/gpu/drm/nouveau/include/nvfw/sec2.h @@ -13,7 +13,7 @@ struct nv_sec2_args { #define NV_SEC2_UNIT_ACR 0x08 struct nv_sec2_init_msg { - struct nv_falcon_msg hdr; + struct nvfw_falcon_msg hdr; #define NV_SEC2_INIT_MSG_INIT 0x00 u8 msg_type; @@ -34,13 +34,13 @@ struct nv_sec2_init_msg { }; struct nv_sec2_acr_cmd { - struct nv_falcon_cmd hdr; + struct nvfw_falcon_cmd hdr; #define NV_SEC2_ACR_CMD_BOOTSTRAP_FALCON 0x00 u8 cmd_type; }; struct nv_sec2_acr_msg { - struct nv_falcon_cmd hdr; + struct nvfw_falcon_cmd hdr; u8 msg_type; }; diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/falcon.h b/drivers/gpu/drm/nouveau/include/nvkm/core/falcon.h index daa8e4bfb6bf..3981cb106aae 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/falcon.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/falcon.h @@ -31,21 +31,21 @@ int gp102_sec2_flcn_enable(struct nvkm_falcon *); #define FLCN_ERR(f,fmt,a...) FLCN_PRINTK(error, (f), fmt, ##a) /** - * struct nv_falcon_msg - header for all messages + * struct nvfw_falcon_msg - header for all messages * * @unit_id: id of firmware process that sent the message * @size: total size of message * @ctrl_flags: control flags * @seq_id: used to match a message from its corresponding command */ -struct nv_falcon_msg { +struct nvfw_falcon_msg { u8 unit_id; u8 size; u8 ctrl_flags; u8 seq_id; }; -#define nv_falcon_cmd nv_falcon_msg +#define nvfw_falcon_cmd nvfw_falcon_msg #define NV_FALCON_CMD_UNIT_ID_REWIND 0x00 struct nvkm_falcon_qmgr; @@ -53,7 +53,7 @@ int nvkm_falcon_qmgr_new(struct nvkm_falcon *, struct nvkm_falcon_qmgr **); void nvkm_falcon_qmgr_del(struct nvkm_falcon_qmgr **); typedef int -(*nvkm_falcon_qmgr_callback)(void *priv, struct nv_falcon_msg *); +(*nvkm_falcon_qmgr_callback)(void *priv, struct nvfw_falcon_msg *); struct nvkm_falcon_cmdq; int nvkm_falcon_cmdq_new(struct nvkm_falcon_qmgr *, const char *name, @@ -62,7 +62,7 @@ void nvkm_falcon_cmdq_del(struct nvkm_falcon_cmdq **); void nvkm_falcon_cmdq_init(struct nvkm_falcon_cmdq *, u32 index, u32 offset, u32 size); void nvkm_falcon_cmdq_fini(struct nvkm_falcon_cmdq *); -int nvkm_falcon_cmdq_send(struct nvkm_falcon_cmdq *, struct nv_falcon_cmd *, +int nvkm_falcon_cmdq_send(struct nvkm_falcon_cmdq *, struct nvfw_falcon_cmd *, nvkm_falcon_qmgr_callback, void *priv, unsigned long timeout_jiffies); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c b/drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c index 368f2a0042ff..a2a9a8418777 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c @@ -29,7 +29,7 @@ #include static int -gp102_sec2_acr_bootstrap_falcon_callback(void *priv, struct nv_falcon_msg *hdr) +gp102_sec2_acr_bootstrap_falcon_callback(void *priv, struct nvfw_falcon_msg *hdr) { struct nv_sec2_acr_bootstrap_falcon_msg *msg = container_of(hdr, typeof(*msg), msg.hdr); diff --git a/drivers/gpu/drm/nouveau/nvkm/falcon/cmdq.c b/drivers/gpu/drm/nouveau/nvkm/falcon/cmdq.c index 40e3f3fc83ef..44cf6a8862e1 100644 --- a/drivers/gpu/drm/nouveau/nvkm/falcon/cmdq.c +++ b/drivers/gpu/drm/nouveau/nvkm/falcon/cmdq.c @@ -58,7 +58,7 @@ nvkm_falcon_cmdq_push(struct nvkm_falcon_cmdq *cmdq, void *data, u32 size) static void nvkm_falcon_cmdq_rewind(struct nvkm_falcon_cmdq *cmdq) { - struct nv_falcon_cmd cmd; + struct nvfw_falcon_cmd cmd; cmd.unit_id = NV_FALCON_CMD_UNIT_ID_REWIND; cmd.size = sizeof(cmd); @@ -97,7 +97,7 @@ nvkm_falcon_cmdq_close(struct nvkm_falcon_cmdq *cmdq) } static int -nvkm_falcon_cmdq_write(struct nvkm_falcon_cmdq *cmdq, struct nv_falcon_cmd *cmd) +nvkm_falcon_cmdq_write(struct nvkm_falcon_cmdq *cmdq, struct nvfw_falcon_cmd *cmd) { static unsigned timeout = 2000; unsigned long end_jiffies = jiffies + msecs_to_jiffies(timeout); @@ -121,7 +121,7 @@ nvkm_falcon_cmdq_write(struct nvkm_falcon_cmdq *cmdq, struct nv_falcon_cmd *cmd) #define CMD_FLAGS_INTR BIT(1) int -nvkm_falcon_cmdq_send(struct nvkm_falcon_cmdq *cmdq, struct nv_falcon_cmd *cmd, +nvkm_falcon_cmdq_send(struct nvkm_falcon_cmdq *cmdq, struct nvfw_falcon_cmd *cmd, nvkm_falcon_qmgr_callback cb, void *priv, unsigned long timeout) { diff --git a/drivers/gpu/drm/nouveau/nvkm/falcon/msgq.c b/drivers/gpu/drm/nouveau/nvkm/falcon/msgq.c index cbfe09a561a1..e74371dffc76 100644 --- a/drivers/gpu/drm/nouveau/nvkm/falcon/msgq.c +++ b/drivers/gpu/drm/nouveau/nvkm/falcon/msgq.c @@ -74,7 +74,7 @@ nvkm_falcon_msgq_pop(struct nvkm_falcon_msgq *msgq, void *data, u32 size) } static int -nvkm_falcon_msgq_read(struct nvkm_falcon_msgq *msgq, struct nv_falcon_msg *hdr) +nvkm_falcon_msgq_read(struct nvkm_falcon_msgq *msgq, struct nvfw_falcon_msg *hdr) { int ret = 0; @@ -112,7 +112,7 @@ nvkm_falcon_msgq_read(struct nvkm_falcon_msgq *msgq, struct nv_falcon_msg *hdr) } static int -nvkm_falcon_msgq_exec(struct nvkm_falcon_msgq *msgq, struct nv_falcon_msg *hdr) +nvkm_falcon_msgq_exec(struct nvkm_falcon_msgq *msgq, struct nvfw_falcon_msg *hdr) { struct nvkm_falcon_qmgr_seq *seq; @@ -144,7 +144,7 @@ nvkm_falcon_msgq_recv(struct nvkm_falcon_msgq *msgq) * stack space to work with. */ u8 msg_buffer[MSG_BUF_SIZE]; - struct nv_falcon_msg *hdr = (void *)msg_buffer; + struct nvfw_falcon_msg *hdr = (void *)msg_buffer; while (nvkm_falcon_msgq_read(msgq, hdr) > 0) nvkm_falcon_msgq_exec(msgq, hdr); @@ -155,7 +155,7 @@ nvkm_falcon_msgq_recv_initmsg(struct nvkm_falcon_msgq *msgq, void *data, u32 size) { struct nvkm_falcon *falcon = msgq->qmgr->falcon; - struct nv_falcon_msg *hdr = data; + struct nvfw_falcon_msg *hdr = data; int ret; msgq->head_reg = falcon->func->msgq.head; diff --git a/drivers/gpu/drm/nouveau/nvkm/falcon/qmgr.h b/drivers/gpu/drm/nouveau/nvkm/falcon/qmgr.h index a45cd705e4f7..976cb7b7aa99 100644 --- a/drivers/gpu/drm/nouveau/nvkm/falcon/qmgr.h +++ b/drivers/gpu/drm/nouveau/nvkm/falcon/qmgr.h @@ -3,7 +3,7 @@ #define __NVKM_FALCON_QMGR_H__ #include -#define HDR_SIZE sizeof(struct nv_falcon_msg) +#define HDR_SIZE sizeof(struct nvfw_falcon_msg) #define QUEUE_ALIGNMENT 4 /* max size of the messages we can receive */ #define MSG_BUF_SIZE 128 diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm20b.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm20b.c index 82571032a07d..3a0cca3d3c3b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm20b.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm20b.c @@ -28,7 +28,7 @@ #include static int -gm20b_pmu_acr_bootstrap_falcon_cb(void *priv, struct nv_falcon_msg *hdr) +gm20b_pmu_acr_bootstrap_falcon_cb(void *priv, struct nvfw_falcon_msg *hdr) { struct nv_pmu_acr_bootstrap_falcon_msg *msg = container_of(hdr, typeof(*msg), msg.hdr); @@ -130,7 +130,7 @@ gm20b_pmu_acr = { }; static int -gm20b_pmu_acr_init_wpr_callback(void *priv, struct nv_falcon_msg *hdr) +gm20b_pmu_acr_init_wpr_callback(void *priv, struct nvfw_falcon_msg *hdr) { struct nv_pmu_acr_init_wpr_region_msg *msg = container_of(hdr, typeof(*msg), msg.hdr); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp10b.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp10b.c index 5b81c7320479..fdfb1470587a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp10b.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp10b.c @@ -28,7 +28,7 @@ static int gp10b_pmu_acr_bootstrap_multiple_falcons_cb(void *priv, - struct nv_falcon_msg *hdr) + struct nvfw_falcon_msg *hdr) { struct nv_pmu_acr_bootstrap_multiple_falcons_msg *msg = container_of(hdr, typeof(*msg), msg.hdr); From b9f327f1afc7c061233adf585736857d20c6ac06 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Wed, 10 Jun 2020 14:46:01 +1000 Subject: [PATCH 009/145] drm/nouveau/mmu/gp100-: enable mmu invalidate depth optimisation This causes us to invalidate MMU only at the level we made modifications - ie: if we've only modified PTEs, there's no need to have MMU dump the PDs it's fetched into L2. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c | 1 - drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmtu102.c | 4 ++-- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c index d86287565542..97520e9721c9 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c @@ -466,7 +466,6 @@ void gp100_vmm_flush(struct nvkm_vmm *vmm, int depth) { u32 type = (5 /* CACHE_LEVEL_UP_TO_PDE3 */ - depth) << 24; - type = 0; /*XXX: need to confirm stuff works with depth enabled... */ if (atomic_read(&vmm->engref[NVKM_SUBDEV_BAR])) type |= 0x00000004; /* HUB_ONLY */ type |= 0x00000001; /* PAGE_ALL */ diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmtu102.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmtu102.c index be91cffc3b52..b1294d0076c0 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmtu102.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmtu102.c @@ -28,9 +28,9 @@ tu102_vmm_flush(struct nvkm_vmm *vmm, int depth) { struct nvkm_subdev *subdev = &vmm->mmu->subdev; struct nvkm_device *device = subdev->device; - u32 type = depth << 24; /*XXX: not confirmed */ + u32 type = (5 /* CACHE_LEVEL_UP_TO_PDE3 */ - depth) << 24; - type = 0x00000001; /* PAGE_ALL */ + type |= 0x00000001; /* PAGE_ALL */ if (atomic_read(&vmm->engref[NVKM_SUBDEV_BAR])) type |= 0x00000004; /* HUB_ONLY */ From 8140f92c277ffe75083117f90a6417c043aef97d Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Tue, 16 Jun 2020 11:14:41 +1000 Subject: [PATCH 010/145] drm/nouveau/core: drop error message when no compatible FW found This is less than useful with some subdevs having _nofw variants in their FWIF lists - it's cleaner to handle them all in the same way. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/include/nvkm/core/firmware.h | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/firmware.h b/drivers/gpu/drm/nouveau/include/nvkm/core/firmware.h index d14b7fb07368..85bcb80f6873 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/firmware.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/firmware.h @@ -45,11 +45,8 @@ int nvkm_firmware_load_name(const struct nvkm_subdev *subdev, const char *path, } \ } \ \ - if (_ret) { \ - nvkm_error(_s, "failed to load firmware\n"); \ + if (_ret) \ _fwif = ERR_PTR(_ret); \ - } \ - \ _fwif; \ }) #endif From 8fdc45e4b61501bbd201006f97902d5e6ecac7ee Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Tue, 16 Jun 2020 11:38:47 +1000 Subject: [PATCH 011/145] drm/nouveau/acr: refuse to load LSFW if HSFW is missing Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/subdev/acr/lsfw.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/acr/lsfw.c b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/lsfw.c index 07d1830126ab..9b1cf6711ae9 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/acr/lsfw.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/lsfw.c @@ -60,7 +60,7 @@ nvkm_acr_lsfw_add(const struct nvkm_acr_lsf_func *func, struct nvkm_acr *acr, { struct nvkm_acr_lsfw *lsfw; - if (!acr) + if (!acr || list_empty(&acr->hsfw)) return ERR_PTR(-ENOSYS); lsfw = nvkm_acr_lsfw_get(acr, id); From 90e9cf749a61deabd1cb167759ff93ee9f0ab01f Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Tue, 16 Jun 2020 10:47:07 +1000 Subject: [PATCH 012/145] drm/nouveau/acr: allow module to load when HSFW(s) are missing Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/subdev/acr/gm200.c | 16 ++++++++++++++-- drivers/gpu/drm/nouveau/nvkm/subdev/acr/gm20b.c | 3 ++- drivers/gpu/drm/nouveau/nvkm/subdev/acr/gp102.c | 3 ++- drivers/gpu/drm/nouveau/nvkm/subdev/acr/gp108.c | 3 ++- drivers/gpu/drm/nouveau/nvkm/subdev/acr/gp10b.c | 3 ++- drivers/gpu/drm/nouveau/nvkm/subdev/acr/priv.h | 2 ++ drivers/gpu/drm/nouveau/nvkm/subdev/acr/tu102.c | 1 + 7 files changed, 25 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/acr/gm200.c b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/gm200.c index 9a6394085cf0..74ffcf1e8de8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/acr/gm200.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/gm200.c @@ -32,6 +32,17 @@ #include #include +const struct nvkm_acr_func +gm200_acr = { +}; + +int +gm200_acr_nofw(struct nvkm_acr *acr, int ver, const struct nvkm_acr_fwif *fwif) +{ + nvkm_warn(&acr->subdev, "firmware unavailable\n"); + return 0; +} + int gm200_acr_init(struct nvkm_acr *acr) { @@ -425,7 +436,7 @@ gm200_acr_load_fwif[] = { }; static const struct nvkm_acr_func -gm200_acr = { +gm200_acr_0 = { .load = gm200_acr_load_fwif, .unload = gm200_acr_unload_fwif, .wpr_parse = gm200_acr_wpr_parse, @@ -459,7 +470,8 @@ gm200_acr_load(struct nvkm_acr *acr, int ver, const struct nvkm_acr_fwif *fwif) static const struct nvkm_acr_fwif gm200_acr_fwif[] = { - { 0, gm200_acr_load, &gm200_acr }, + { 0, gm200_acr_load, &gm200_acr_0 }, + { -1, gm200_acr_nofw, &gm200_acr }, {} }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/acr/gm20b.c b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/gm20b.c index 034a6ede70c7..b1ecc58152cc 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/acr/gm20b.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/gm20b.c @@ -123,7 +123,8 @@ gm20b_acr_load(struct nvkm_acr *acr, int ver, const struct nvkm_acr_fwif *fwif) static const struct nvkm_acr_fwif gm20b_acr_fwif[] = { - { 0, gm20b_acr_load, &gm20b_acr }, + { 0, gm20b_acr_load, &gm20b_acr }, + { -1, gm200_acr_nofw, &gm200_acr }, {} }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/acr/gp102.c b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/gp102.c index 49e11c46d525..80eb9d8dbc80 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/acr/gp102.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/gp102.c @@ -270,7 +270,8 @@ gp102_acr_load(struct nvkm_acr *acr, int ver, const struct nvkm_acr_fwif *fwif) static const struct nvkm_acr_fwif gp102_acr_fwif[] = { - { 0, gp102_acr_load, &gp102_acr }, + { 0, gp102_acr_load, &gp102_acr }, + { -1, gm200_acr_nofw, &gm200_acr }, {} }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/acr/gp108.c b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/gp108.c index f10dc9112678..67a7c141004b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/acr/gp108.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/gp108.c @@ -100,7 +100,8 @@ gp108_acr = { static const struct nvkm_acr_fwif gp108_acr_fwif[] = { - { 0, gp102_acr_load, &gp108_acr }, + { 0, gp102_acr_load, &gp108_acr }, + { -1, gm200_acr_nofw, &gm200_acr }, {} }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/acr/gp10b.c b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/gp10b.c index 39de64292a41..8249f0d2d81d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/acr/gp10b.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/gp10b.c @@ -46,7 +46,8 @@ gp10b_acr = { static const struct nvkm_acr_fwif gp10b_acr_fwif[] = { - { 0, gm20b_acr_load, &gp10b_acr }, + { 0, gm20b_acr_load, &gp10b_acr }, + { -1, gm200_acr_nofw, &gm200_acr }, {} }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/acr/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/priv.h index d8ba72806d39..9c10879051c8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/acr/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/priv.h @@ -10,6 +10,7 @@ struct nvkm_acr_fwif { const struct nvkm_acr_func *func; }; +int gm200_acr_nofw(struct nvkm_acr *, int, const struct nvkm_acr_fwif *); int gm20b_acr_load(struct nvkm_acr *, int, const struct nvkm_acr_fwif *); int gp102_acr_load(struct nvkm_acr *, int, const struct nvkm_acr_fwif *); @@ -29,6 +30,7 @@ struct nvkm_acr_func { void (*fini)(struct nvkm_acr *); }; +extern const struct nvkm_acr_func gm200_acr; int gm200_acr_wpr_parse(struct nvkm_acr *); u32 gm200_acr_wpr_layout(struct nvkm_acr *); int gm200_acr_wpr_build(struct nvkm_acr *, struct nvkm_acr_lsf *); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/acr/tu102.c b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/tu102.c index d28d8f36ae24..c4981bce9a2b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/acr/tu102.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/tu102.c @@ -219,6 +219,7 @@ tu102_acr_load(struct nvkm_acr *acr, int version, static const struct nvkm_acr_fwif tu102_acr_fwif[] = { { 0, tu102_acr_load, &tu102_acr }, + { -1, gm200_acr_nofw, &gm200_acr }, {} }; From 587debc9a79b84fd61674f2c42f5a1b2c89ebd5f Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Tue, 16 Jun 2020 14:19:35 +1000 Subject: [PATCH 013/145] drm/nouveau/acr: store a mask of LS falcons the HSFW can bootstrap This will prevent reloading of HS FW where it's pointless, and bypass hitting some timeouts. Not a situation one should generally hit, but can occur with a messed up firmware installation. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/subdev/acr/base.c | 15 +++++++++++---- drivers/gpu/drm/nouveau/nvkm/subdev/acr/gm200.c | 2 ++ drivers/gpu/drm/nouveau/nvkm/subdev/acr/priv.h | 1 + 3 files changed, 14 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/acr/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/base.c index e4866a02e457..51a669e7bf6a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/acr/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/base.c @@ -141,12 +141,19 @@ nvkm_acr_bootstrap_falcons(struct nvkm_device *device, unsigned long mask) struct nvkm_acr *acr = device->acr; unsigned long id; + /* If there's no LS FW managing bootstrapping of other LS falcons, + * we depend on the HS firmware being able to do it instead. + */ if (!acrflcn) { - int ret = nvkm_acr_reload(acr); - if (ret) - return ret; + /* Which isn't possible everywhere... */ + if ((mask & acr->func->bootstrap_falcons) == mask) { + int ret = nvkm_acr_reload(acr); + if (ret) + return ret; - return acr->done ? 0 : -EINVAL; + return acr->done ? 0 : -EINVAL; + } + return -ENOSYS; } if (acrflcn->func->bootstrap_multiple_falcons) { diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/acr/gm200.c b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/gm200.c index 74ffcf1e8de8..cd41b2e6cc87 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/acr/gm200.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/gm200.c @@ -446,6 +446,8 @@ gm200_acr_0 = { .wpr_patch = gm200_acr_wpr_patch, .wpr_check = gm200_acr_wpr_check, .init = gm200_acr_init, + .bootstrap_falcons = BIT_ULL(NVKM_ACR_LSF_FECS) | + BIT_ULL(NVKM_ACR_LSF_GPCCS), }; static int diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/acr/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/priv.h index 9c10879051c8..d71af17a169a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/acr/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/priv.h @@ -28,6 +28,7 @@ struct nvkm_acr_func { void (*wpr_check)(struct nvkm_acr *, u64 *start, u64 *limit); int (*init)(struct nvkm_acr *); void (*fini)(struct nvkm_acr *); + u64 bootstrap_falcons; }; extern const struct nvkm_acr_func gm200_acr; From de088372da017df35f6545516815ee012ec92ff6 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Tue, 16 Jun 2020 14:57:31 +1000 Subject: [PATCH 014/145] drm/nouveau/acr: store a mask of LS falcons the controlling LSFW can bootstrap This will prevent some pain with broken firmware trees, as under some circumstances the HSFW can fail and leave the GPU in a state we don't know how to recover from. Signed-off-by: Ben Skeggs --- .../gpu/drm/nouveau/include/nvkm/subdev/acr.h | 3 ++ .../gpu/drm/nouveau/nvkm/engine/sec2/gp102.c | 6 ++++ .../gpu/drm/nouveau/nvkm/subdev/acr/base.c | 29 +++++++++++++++---- .../gpu/drm/nouveau/nvkm/subdev/pmu/gm20b.c | 3 ++ .../gpu/drm/nouveau/nvkm/subdev/pmu/gp10b.c | 3 ++ 5 files changed, 38 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/acr.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/acr.h index 5d9c3a966de6..836d8b932822 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/acr.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/acr.h @@ -39,6 +39,8 @@ struct nvkm_acr { struct list_head hsfw, hsf; struct list_head lsfw, lsf; + u64 managed_falcons; + struct nvkm_memory *wpr; u64 wpr_start; u64 wpr_end; @@ -107,6 +109,7 @@ struct nvkm_acr_lsf_func { void (*bld_write)(struct nvkm_acr *, u32 bld, struct nvkm_acr_lsfw *); void (*bld_patch)(struct nvkm_acr *, u32 bld, s64 adjust); int (*boot)(struct nvkm_falcon *); + u64 bootstrap_falcons; int (*bootstrap_falcon)(struct nvkm_falcon *, enum nvkm_acr_lsf_id); int (*bootstrap_multiple_falcons)(struct nvkm_falcon *, u32 mask); }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c b/drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c index a2a9a8418777..36b31bf7bc62 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c @@ -115,6 +115,9 @@ gp102_sec2_acr_0 = { .bld_write = gp102_sec2_acr_bld_write, .bld_patch = gp102_sec2_acr_bld_patch, .boot = gp102_sec2_acr_boot, + .bootstrap_falcons = BIT_ULL(NVKM_ACR_LSF_FECS) | + BIT_ULL(NVKM_ACR_LSF_GPCCS) | + BIT_ULL(NVKM_ACR_LSF_SEC2), .bootstrap_falcon = gp102_sec2_acr_bootstrap_falcon, }; @@ -294,6 +297,9 @@ gp102_sec2_acr_1 = { .bld_write = gp102_sec2_acr_bld_write_1, .bld_patch = gp102_sec2_acr_bld_patch_1, .boot = gp102_sec2_acr_boot, + .bootstrap_falcons = BIT_ULL(NVKM_ACR_LSF_FECS) | + BIT_ULL(NVKM_ACR_LSF_GPCCS) | + BIT_ULL(NVKM_ACR_LSF_SEC2), .bootstrap_falcon = gp102_sec2_acr_bootstrap_falcon, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/acr/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/base.c index 51a669e7bf6a..c962df9910dd 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/acr/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/base.c @@ -156,6 +156,9 @@ nvkm_acr_bootstrap_falcons(struct nvkm_device *device, unsigned long mask) return -ENOSYS; } + if ((mask & acrflcn->func->bootstrap_falcons) != mask) + return -ENOSYS; + if (acrflcn->func->bootstrap_multiple_falcons) { return acrflcn->func-> bootstrap_multiple_falcons(acrflcn->falcon, mask); @@ -174,13 +177,10 @@ bool nvkm_acr_managed_falcon(struct nvkm_device *device, enum nvkm_acr_lsf_id id) { struct nvkm_acr *acr = device->acr; - struct nvkm_acr_lsf *lsf; if (acr) { - list_for_each_entry(lsf, &acr->lsf, head) { - if (lsf->id == id) - return true; - } + if (acr->managed_falcons & BIT_ULL(id)) + return true; } return false; @@ -220,6 +220,7 @@ nvkm_acr_oneinit(struct nvkm_subdev *subdev) struct nvkm_acr_lsfw *lsfw, *lsft; struct nvkm_acr_lsf *lsf; u32 wpr_size = 0; + u64 falcons; int ret, i; if (list_empty(&acr->hsfw)) { @@ -255,12 +256,28 @@ nvkm_acr_oneinit(struct nvkm_subdev *subdev) lsf->falcon = lsfw->falcon; lsf->id = lsfw->id; list_add_tail(&lsf->head, &acr->lsf); + acr->managed_falcons |= BIT_ULL(lsf->id); } /* Ensure the falcon that'll provide ACR functions is booted first. */ lsf = nvkm_acr_falcon(device); - if (lsf) + if (lsf) { + falcons = lsf->func->bootstrap_falcons; list_move(&lsf->head, &acr->lsf); + } else { + falcons = acr->func->bootstrap_falcons; + } + + /* Cull falcons that can't be bootstrapped, or the HSFW can fail to + * boot and leave the GPU in a weird state. + */ + list_for_each_entry_safe(lsfw, lsft, &acr->lsfw, head) { + if (!(falcons & BIT_ULL(lsfw->id))) { + nvkm_warn(subdev, "%s falcon cannot be bootstrapped\n", + nvkm_acr_lsf_id(lsfw->id)); + nvkm_acr_lsfw_del(lsfw); + } + } if (!acr->wpr_fw || acr->wpr_comp) wpr_size = acr->func->wpr_layout(acr); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm20b.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm20b.c index 3a0cca3d3c3b..cf91fd322c98 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm20b.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm20b.c @@ -126,6 +126,9 @@ gm20b_pmu_acr = { .bld_write = gm20b_pmu_acr_bld_write, .bld_patch = gm20b_pmu_acr_bld_patch, .boot = gm20b_pmu_acr_boot, + .bootstrap_falcons = BIT_ULL(NVKM_ACR_LSF_PMU) | + BIT_ULL(NVKM_ACR_LSF_FECS) | + BIT_ULL(NVKM_ACR_LSF_GPCCS), .bootstrap_falcon = gm20b_pmu_acr_bootstrap_falcon, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp10b.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp10b.c index fdfb1470587a..9a4aca2ad831 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp10b.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp10b.c @@ -69,6 +69,9 @@ gp10b_pmu_acr = { .bld_write = gm20b_pmu_acr_bld_write, .bld_patch = gm20b_pmu_acr_bld_patch, .boot = gm20b_pmu_acr_boot, + .bootstrap_falcons = BIT_ULL(NVKM_ACR_LSF_PMU) | + BIT_ULL(NVKM_ACR_LSF_FECS) | + BIT_ULL(NVKM_ACR_LSF_GPCCS), .bootstrap_falcon = gm20b_pmu_acr_bootstrap_falcon, .bootstrap_multiple_falcons = gp10b_pmu_acr_bootstrap_multiple_falcons, }; From 46fc98bfb8bcfb3ba2e5af51ecbbdb394ed67501 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Tue, 16 Jun 2020 15:15:58 +1000 Subject: [PATCH 015/145] drm/nouveau/pmu/gm20x: don't pretend we support loading with our custom FW It technically loads, and runs, but is ultimately pointless outside of a very narrow window (fanless systems where one wants to attempt using the, broken for a lot of gm20x, memory reclocking code). It's also potentially dangerous to override the VBIOS-provided "Pre-OS" PMU, which would be responsible for fan control otherwise. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/device/base.c | 8 ++++---- drivers/gpu/drm/nouveau/nvkm/subdev/pmu/Kbuild | 2 +- .../drm/nouveau/nvkm/subdev/pmu/{gp100.c => gm200.c} | 10 +++++----- 4 files changed, 11 insertions(+), 11 deletions(-) rename drivers/gpu/drm/nouveau/nvkm/subdev/pmu/{gp100.c => gm200.c} (87%) diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h index da553089d2d8..5ff6d1f8985a 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h @@ -47,8 +47,8 @@ int gk110_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **); int gk208_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **); int gk20a_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **); int gm107_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **); +int gm200_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **); int gm20b_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **); -int gp100_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **); int gp102_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **); int gp10b_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c index 5b90c2a1bf3d..9f4ac2672cf2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c @@ -2046,7 +2046,7 @@ nv120_chipset = { .mmu = gm200_mmu_new, .mxm = nv50_mxm_new, .pci = gk104_pci_new, - .pmu = gm107_pmu_new, + .pmu = gm200_pmu_new, .therm = gm200_therm_new, .timer = gk20a_timer_new, .top = gk104_top_new, @@ -2084,7 +2084,7 @@ nv124_chipset = { .mmu = gm200_mmu_new, .mxm = nv50_mxm_new, .pci = gk104_pci_new, - .pmu = gm107_pmu_new, + .pmu = gm200_pmu_new, .therm = gm200_therm_new, .timer = gk20a_timer_new, .top = gk104_top_new, @@ -2122,7 +2122,7 @@ nv126_chipset = { .mmu = gm200_mmu_new, .mxm = nv50_mxm_new, .pci = gk104_pci_new, - .pmu = gm107_pmu_new, + .pmu = gm200_pmu_new, .therm = gm200_therm_new, .timer = gk20a_timer_new, .top = gk104_top_new, @@ -2184,7 +2184,7 @@ nv130_chipset = { .mmu = gp100_mmu_new, .therm = gp100_therm_new, .pci = gp100_pci_new, - .pmu = gp100_pmu_new, + .pmu = gm200_pmu_new, .timer = gk20a_timer_new, .top = gk104_top_new, .ce[0] = gp100_ce_new, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/Kbuild index a76c2a7bd696..eafc9321a08a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/Kbuild @@ -9,7 +9,7 @@ nvkm-y += nvkm/subdev/pmu/gk110.o nvkm-y += nvkm/subdev/pmu/gk208.o nvkm-y += nvkm/subdev/pmu/gk20a.o nvkm-y += nvkm/subdev/pmu/gm107.o +nvkm-y += nvkm/subdev/pmu/gm200.o nvkm-y += nvkm/subdev/pmu/gm20b.o -nvkm-y += nvkm/subdev/pmu/gp100.o nvkm-y += nvkm/subdev/pmu/gp102.o nvkm-y += nvkm/subdev/pmu/gp10b.o diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm200.c similarity index 87% rename from drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp100.c rename to drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm200.c index 09e05db21ff5..97b3acdf9157 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm200.c @@ -24,20 +24,20 @@ #include "priv.h" static const struct nvkm_pmu_func -gp100_pmu = { +gm200_pmu = { .flcn = >215_pmu_flcn, .enabled = gf100_pmu_enabled, .reset = gf100_pmu_reset, }; static const struct nvkm_pmu_fwif -gp100_pmu_fwif[] = { - { -1, gf100_pmu_nofw, &gp100_pmu }, +gm200_pmu_fwif[] = { + { -1, gf100_pmu_nofw, &gm200_pmu }, {} }; int -gp100_pmu_new(struct nvkm_device *device, int index, struct nvkm_pmu **ppmu) +gm200_pmu_new(struct nvkm_device *device, int index, struct nvkm_pmu **ppmu) { - return nvkm_pmu_new_(gp100_pmu_fwif, device, index, ppmu); + return nvkm_pmu_new_(gm200_pmu_fwif, device, index, ppmu); } From 38fd546beb48afdefdcec2ce2c0e5beda71400a3 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Tue, 16 Jun 2020 15:26:20 +1000 Subject: [PATCH 016/145] drm/nouveau/pmu/gm200-: explicitly handle nofw Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm200.c | 10 +++++++++- drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm20b.c | 3 ++- drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp102.c | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp10b.c | 3 ++- drivers/gpu/drm/nouveau/nvkm/subdev/pmu/priv.h | 1 + 5 files changed, 15 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm200.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm200.c index 97b3acdf9157..383376addb41 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm200.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm200.c @@ -30,9 +30,17 @@ gm200_pmu = { .reset = gf100_pmu_reset, }; + +int +gm200_pmu_nofw(struct nvkm_pmu *pmu, int ver, const struct nvkm_pmu_fwif *fwif) +{ + nvkm_warn(&pmu->subdev, "firmware unavailable\n"); + return 0; +} + static const struct nvkm_pmu_fwif gm200_pmu_fwif[] = { - { -1, gf100_pmu_nofw, &gm200_pmu }, + { -1, gm200_pmu_nofw, &gm200_pmu }, {} }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm20b.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm20b.c index cf91fd322c98..8f6ed5373ea1 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm20b.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm20b.c @@ -234,7 +234,8 @@ gm20b_pmu_load(struct nvkm_pmu *pmu, int ver, const struct nvkm_pmu_fwif *fwif) static const struct nvkm_pmu_fwif gm20b_pmu_fwif[] = { - { 0, gm20b_pmu_load, &gm20b_pmu, &gm20b_pmu_acr }, + { 0, gm20b_pmu_load, &gm20b_pmu, &gm20b_pmu_acr }, + { -1, gm200_pmu_nofw, &gm20b_pmu }, {} }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp102.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp102.c index 262b8a3dd507..3d8ce14dba7b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp102.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp102.c @@ -46,7 +46,7 @@ gp102_pmu = { static const struct nvkm_pmu_fwif gp102_pmu_fwif[] = { - { -1, gf100_pmu_nofw, &gp102_pmu }, + { -1, gm200_pmu_nofw, &gp102_pmu }, {} }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp10b.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp10b.c index 9a4aca2ad831..9c237c426599 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp10b.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp10b.c @@ -93,7 +93,8 @@ MODULE_FIRMWARE("nvidia/gp10b/pmu/sig.bin"); static const struct nvkm_pmu_fwif gp10b_pmu_fwif[] = { - { 0, gm20b_pmu_load, &gp10b_pmu, &gp10b_pmu_acr }, + { 0, gm20b_pmu_load, &gp10b_pmu, &gp10b_pmu_acr }, + { -1, gm200_pmu_nofw, &gp10b_pmu }, {} }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/priv.h index f470859244de..276b6d778e53 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/priv.h @@ -59,6 +59,7 @@ struct nvkm_pmu_fwif { }; int gf100_pmu_nofw(struct nvkm_pmu *, int, const struct nvkm_pmu_fwif *); +int gm200_pmu_nofw(struct nvkm_pmu *, int, const struct nvkm_pmu_fwif *); int gm20b_pmu_load(struct nvkm_pmu *, int, const struct nvkm_pmu_fwif *); int nvkm_pmu_ctor(const struct nvkm_pmu_fwif *, struct nvkm_device *, From b9c246ad3b54c50c787409c37a5ccc2e940ac7a9 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Tue, 16 Jun 2020 11:30:04 +1000 Subject: [PATCH 017/145] drm/nouveau/gr/gm200-: explicitly handle nofw Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h | 1 + drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c | 10 +++++++++- drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c | 3 ++- drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c | 3 ++- drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c | 3 ++- drivers/gpu/drm/nouveau/nvkm/engine/gr/gp104.c | 3 ++- drivers/gpu/drm/nouveau/nvkm/engine/gr/gp107.c | 3 ++- drivers/gpu/drm/nouveau/nvkm/engine/gr/gp108.c | 3 ++- drivers/gpu/drm/nouveau/nvkm/engine/gr/gp10b.c | 3 ++- drivers/gpu/drm/nouveau/nvkm/engine/gr/gv100.c | 3 ++- drivers/gpu/drm/nouveau/nvkm/engine/gr/tu102.c | 3 ++- 12 files changed, 29 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c index 9ac0f9449b5e..749f73fc45a8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c @@ -2103,7 +2103,7 @@ gf100_gr_new_(const struct gf100_gr_fwif *fwif, fwif = nvkm_firmware_load(&gr->base.engine.subdev, fwif, "Gr", gr); if (IS_ERR(fwif)) - return -ENODEV; + return PTR_ERR(fwif); gr->func = fwif->func; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h index 88bcb57c2e07..dfd5dd74f0d5 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h @@ -404,6 +404,7 @@ int gf100_gr_nofw(struct gf100_gr *, int, const struct gf100_gr_fwif *); int gk20a_gr_load_sw(struct gf100_gr *, const char *path, int ver); +int gm200_gr_nofw(struct gf100_gr *, int, const struct gf100_gr_fwif *); int gm200_gr_load(struct gf100_gr *, int, const struct gf100_gr_fwif *); extern const struct nvkm_acr_lsf_func gm200_gr_gpccs_acr; extern const struct nvkm_acr_lsf_func gm200_gr_fecs_acr; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c index 3d67cfb08395..815137047518 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c @@ -32,6 +32,13 @@ #include +int +gm200_gr_nofw(struct gf100_gr *gr, int ver, const struct gf100_gr_fwif *fwif) +{ + nvkm_warn(&gr->base.engine.subdev, "firmware unavailable\n"); + return -ENODEV; +} + /******************************************************************************* * PGRAPH engine/subdev functions ******************************************************************************/ @@ -275,7 +282,8 @@ MODULE_FIRMWARE("nvidia/gm206/gr/sw_method_init.bin"); static const struct gf100_gr_fwif gm200_gr_fwif[] = { - { 0, gm200_gr_load, &gm200_gr, &gm200_gr_fecs_acr, &gm200_gr_gpccs_acr }, + { 0, gm200_gr_load, &gm200_gr, &gm200_gr_fecs_acr, &gm200_gr_gpccs_acr }, + { -1, gm200_gr_nofw }, {} }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c index 09d8c5d5b000..1aab691fa71c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c @@ -175,7 +175,8 @@ MODULE_FIRMWARE("nvidia/gm20b/gr/sw_method_init.bin"); static const struct gf100_gr_fwif gm20b_gr_fwif[] = { - { 0, gm20b_gr_load, &gm20b_gr, &gm20b_gr_fecs_acr }, + { 0, gm20b_gr_load, &gm20b_gr, &gm20b_gr_fecs_acr }, + { -1, gm200_gr_nofw }, {} }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c index 33c8634ae567..ddba7ce937c7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c @@ -150,7 +150,8 @@ MODULE_FIRMWARE("nvidia/gp100/gr/sw_method_init.bin"); static const struct gf100_gr_fwif gp100_gr_fwif[] = { - { 0, gm200_gr_load, &gp100_gr, &gm200_gr_fecs_acr, &gm200_gr_gpccs_acr }, + { 0, gm200_gr_load, &gp100_gr, &gm200_gr_fecs_acr, &gm200_gr_gpccs_acr }, + { -1, gm200_gr_nofw }, {} }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c index 7baf67f743f4..c083f3757ff7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c @@ -146,7 +146,8 @@ MODULE_FIRMWARE("nvidia/gp102/gr/sw_method_init.bin"); static const struct gf100_gr_fwif gp102_gr_fwif[] = { - { 0, gm200_gr_load, &gp102_gr, &gm200_gr_fecs_acr, &gm200_gr_gpccs_acr }, + { 0, gm200_gr_load, &gp102_gr, &gm200_gr_fecs_acr, &gm200_gr_gpccs_acr }, + { -1, gm200_gr_nofw }, {} }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp104.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp104.c index d9b8ef875f8d..f6a31e9a8cc8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp104.c @@ -87,7 +87,8 @@ MODULE_FIRMWARE("nvidia/gp106/gr/sw_method_init.bin"); static const struct gf100_gr_fwif gp104_gr_fwif[] = { - { 0, gm200_gr_load, &gp104_gr, &gm200_gr_fecs_acr, &gm200_gr_gpccs_acr }, + { 0, gm200_gr_load, &gp104_gr, &gm200_gr_fecs_acr, &gm200_gr_gpccs_acr }, + { -1, gm200_gr_nofw }, {} }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp107.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp107.c index 2b1ad5522184..2c80c6a75b56 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp107.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp107.c @@ -76,7 +76,8 @@ MODULE_FIRMWARE("nvidia/gp107/gr/sw_method_init.bin"); static const struct gf100_gr_fwif gp107_gr_fwif[] = { - { 0, gm200_gr_load, &gp107_gr, &gm200_gr_fecs_acr, &gm200_gr_gpccs_acr }, + { 0, gm200_gr_load, &gp107_gr, &gm200_gr_fecs_acr, &gm200_gr_gpccs_acr }, + { -1, gm200_gr_nofw }, {} }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp108.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp108.c index 113e4c1ba9e8..2be8f416dd6f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp108.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp108.c @@ -86,7 +86,8 @@ MODULE_FIRMWARE("nvidia/gp108/gr/sw_method_init.bin"); static const struct gf100_gr_fwif gp108_gr_fwif[] = { - { 0, gm200_gr_load, &gp107_gr, &gp108_gr_fecs_acr, &gp108_gr_gpccs_acr }, + { 0, gm200_gr_load, &gp107_gr, &gp108_gr_fecs_acr, &gp108_gr_gpccs_acr }, + { -1, gm200_gr_nofw }, {} }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp10b.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp10b.c index eaf913eb5aa3..6edc4bc7ed44 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp10b.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gp10b.c @@ -88,7 +88,8 @@ MODULE_FIRMWARE("nvidia/gp10b/gr/sw_method_init.bin"); static const struct gf100_gr_fwif gp10b_gr_fwif[] = { - { 0, gm200_gr_load, &gp10b_gr, &gm20b_gr_fecs_acr, &gp10b_gr_gpccs_acr }, + { 0, gm200_gr_load, &gp10b_gr, &gm20b_gr_fecs_acr, &gp10b_gr_gpccs_acr }, + { -1, gm200_gr_nofw }, {} }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gv100.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gv100.c index 70639d88b8e6..2189a8f4e644 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gv100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gv100.c @@ -135,7 +135,8 @@ MODULE_FIRMWARE("nvidia/gv100/gr/sw_method_init.bin"); static const struct gf100_gr_fwif gv100_gr_fwif[] = { - { 0, gm200_gr_load, &gv100_gr, &gp108_gr_fecs_acr, &gp108_gr_gpccs_acr }, + { 0, gm200_gr_load, &gv100_gr, &gp108_gr_fecs_acr, &gp108_gr_gpccs_acr }, + { -1, gm200_gr_nofw }, {} }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/tu102.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/tu102.c index a9efa4d78be9..6039f9948aa2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/tu102.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/tu102.c @@ -192,7 +192,8 @@ MODULE_FIRMWARE("nvidia/tu116/gr/sw_method_init.bin"); static const struct gf100_gr_fwif tu102_gr_fwif[] = { - { 0, gm200_gr_load, &tu102_gr, &gp108_gr_fecs_acr, &gp108_gr_gpccs_acr }, + { 0, gm200_gr_load, &tu102_gr, &gp108_gr_fecs_acr, &gp108_gr_gpccs_acr }, + { -1, gm200_gr_nofw }, {} }; From eddb04732992982169cd40068cd231e63b30065b Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Tue, 16 Jun 2020 10:41:49 +1000 Subject: [PATCH 018/145] drm/nouveau/sec2/gp102: allow module to load when LSFW is missing Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c | 13 +++++++++++-- drivers/gpu/drm/nouveau/nvkm/engine/sec2/priv.h | 1 + drivers/gpu/drm/nouveau/nvkm/engine/sec2/tu102.c | 9 +-------- 3 files changed, 13 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c b/drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c index 36b31bf7bc62..bccf7acb7f98 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c @@ -28,6 +28,14 @@ #include #include +int +gp102_sec2_nofw(struct nvkm_sec2 *sec2, int ver, + const struct nvkm_sec2_fwif *fwif) +{ + nvkm_warn(&sec2->engine.subdev, "firmware unavailable\n"); + return 0; +} + static int gp102_sec2_acr_bootstrap_falcon_callback(void *priv, struct nvfw_falcon_msg *hdr) { @@ -328,8 +336,9 @@ MODULE_FIRMWARE("nvidia/gp107/sec2/sig-1.bin"); static const struct nvkm_sec2_fwif gp102_sec2_fwif[] = { - { 1, gp102_sec2_load, &gp102_sec2, &gp102_sec2_acr_1 }, - { 0, gp102_sec2_load, &gp102_sec2, &gp102_sec2_acr_0 }, + { 1, gp102_sec2_load, &gp102_sec2, &gp102_sec2_acr_1 }, + { 0, gp102_sec2_load, &gp102_sec2, &gp102_sec2_acr_0 }, + { -1, gp102_sec2_nofw, &gp102_sec2 }, {} }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sec2/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/sec2/priv.h index bb88117e018a..8cbc0b7d0a27 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/sec2/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sec2/priv.h @@ -20,6 +20,7 @@ struct nvkm_sec2_fwif { const struct nvkm_acr_lsf_func *acr; }; +int gp102_sec2_nofw(struct nvkm_sec2 *, int, const struct nvkm_sec2_fwif *); int gp102_sec2_load(struct nvkm_sec2 *, int, const struct nvkm_sec2_fwif *); extern const struct nvkm_sec2_func gp102_sec2; extern const struct nvkm_acr_lsf_func gp102_sec2_acr_1; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sec2/tu102.c b/drivers/gpu/drm/nouveau/nvkm/engine/sec2/tu102.c index a8295653ceab..a231c1c6c0a5 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/sec2/tu102.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sec2/tu102.c @@ -49,13 +49,6 @@ tu102_sec2 = { .initmsg = gp102_sec2_initmsg, }; -static int -tu102_sec2_nofw(struct nvkm_sec2 *sec2, int ver, - const struct nvkm_sec2_fwif *fwif) -{ - return 0; -} - MODULE_FIRMWARE("nvidia/tu102/sec2/desc.bin"); MODULE_FIRMWARE("nvidia/tu102/sec2/image.bin"); MODULE_FIRMWARE("nvidia/tu102/sec2/sig.bin"); @@ -75,7 +68,7 @@ MODULE_FIRMWARE("nvidia/tu117/sec2/sig.bin"); static const struct nvkm_sec2_fwif tu102_sec2_fwif[] = { { 0, gp102_sec2_load, &tu102_sec2, &gp102_sec2_acr_1 }, - { -1, tu102_sec2_nofw, &tu102_sec2 } + { -1, gp102_sec2_nofw, &tu102_sec2 } }; int From bfad51c7633325b5d4b32444efe04329d53297b2 Mon Sep 17 00:00:00 2001 From: Aditya Pakki Date: Sat, 13 Jun 2020 20:33:42 -0500 Subject: [PATCH 019/145] drm/nouveau/drm/noveau: fix reference count leak in nouveau_fbcon_open nouveau_fbcon_open() calls calls pm_runtime_get_sync() that increments the reference count. In case of failure, decrement the ref count before returning the error. Signed-off-by: Aditya Pakki Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nouveau_fbcon.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/nouveau/nouveau_fbcon.c b/drivers/gpu/drm/nouveau/nouveau_fbcon.c index f9f5a13fdb80..4a93641c33e1 100644 --- a/drivers/gpu/drm/nouveau/nouveau_fbcon.c +++ b/drivers/gpu/drm/nouveau/nouveau_fbcon.c @@ -189,8 +189,10 @@ nouveau_fbcon_open(struct fb_info *info, int user) struct nouveau_fbdev *fbcon = info->par; struct nouveau_drm *drm = nouveau_drm(fbcon->helper.dev); int ret = pm_runtime_get_sync(drm->dev->dev); - if (ret < 0 && ret != -EACCES) + if (ret < 0 && ret != -EACCES) { + pm_runtime_put(drm->dev->dev); return ret; + } return 0; } From 659fb5f154c3434c90a34586f3b7aa1c39cf6062 Mon Sep 17 00:00:00 2001 From: Aditya Pakki Date: Sat, 13 Jun 2020 20:41:56 -0500 Subject: [PATCH 020/145] drm/nouveau: fix multiple instances of reference count leaks On calling pm_runtime_get_sync() the reference count of the device is incremented. In case of failure, decrement the ref count before returning the error. Signed-off-by: Aditya Pakki Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nouveau_drm.c | 8 ++++++-- drivers/gpu/drm/nouveau/nouveau_gem.c | 4 +++- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c index ac93d12201dc..880d962c1b19 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drm.c +++ b/drivers/gpu/drm/nouveau/nouveau_drm.c @@ -1026,8 +1026,10 @@ nouveau_drm_open(struct drm_device *dev, struct drm_file *fpriv) /* need to bring up power immediately if opening device */ ret = pm_runtime_get_sync(dev->dev); - if (ret < 0 && ret != -EACCES) + if (ret < 0 && ret != -EACCES) { + pm_runtime_put_autosuspend(dev->dev); return ret; + } get_task_comm(tmpname, current); snprintf(name, sizeof(name), "%s[%d]", tmpname, pid_nr(fpriv->pid)); @@ -1109,8 +1111,10 @@ nouveau_drm_ioctl(struct file *file, unsigned int cmd, unsigned long arg) long ret; ret = pm_runtime_get_sync(dev->dev); - if (ret < 0 && ret != -EACCES) + if (ret < 0 && ret != -EACCES) { + pm_runtime_put_autosuspend(dev->dev); return ret; + } switch (_IOC_NR(cmd) - DRM_COMMAND_BASE) { case DRM_NOUVEAU_NVIF: diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.c b/drivers/gpu/drm/nouveau/nouveau_gem.c index 63b832585390..133ab6fb7798 100644 --- a/drivers/gpu/drm/nouveau/nouveau_gem.c +++ b/drivers/gpu/drm/nouveau/nouveau_gem.c @@ -45,8 +45,10 @@ nouveau_gem_object_del(struct drm_gem_object *gem) int ret; ret = pm_runtime_get_sync(dev); - if (WARN_ON(ret < 0 && ret != -EACCES)) + if (WARN_ON(ret < 0 && ret != -EACCES)) { + pm_runtime_put_autosuspend(dev); return; + } if (gem->import_attach) drm_prime_gem_destroy(gem, nvbo->bo.sg); From a2cdf39536b0d21fb06113f5e16692513d7bcb9c Mon Sep 17 00:00:00 2001 From: Aditya Pakki Date: Sat, 13 Jun 2020 20:29:18 -0500 Subject: [PATCH 021/145] drm/nouveau: fix reference count leak in nv50_disp_atomic_commit nv50_disp_atomic_commit() calls calls pm_runtime_get_sync and in turn increments the reference count. In case of failure, decrement the ref count before returning the error. Signed-off-by: Aditya Pakki Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/dispnv50/disp.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c b/drivers/gpu/drm/nouveau/dispnv50/disp.c index 4c2894d8e15b..f4921460dbef 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/disp.c +++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c @@ -2171,8 +2171,10 @@ nv50_disp_atomic_commit(struct drm_device *dev, int ret, i; ret = pm_runtime_get_sync(dev->dev); - if (ret < 0 && ret != -EACCES) + if (ret < 0 && ret != -EACCES) { + pm_runtime_put_autosuspend(dev->dev); return ret; + } ret = drm_atomic_helper_setup_commit(state, nonblock); if (ret) From 990a1162986e8eff7ca18cc5a0e03b4304392ae2 Mon Sep 17 00:00:00 2001 From: Aditya Pakki Date: Sat, 13 Jun 2020 20:22:23 -0500 Subject: [PATCH 022/145] drm/nouveau: Fix reference count leak in nouveau_connector_detect nouveau_connector_detect() calls pm_runtime_get_sync and in turn increments the reference count. In case of failure, decrement the ref count before returning the error. Signed-off-by: Aditya Pakki Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nouveau_connector.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c b/drivers/gpu/drm/nouveau/nouveau_connector.c index ab2c2b2cab10..1fa5d5614261 100644 --- a/drivers/gpu/drm/nouveau/nouveau_connector.c +++ b/drivers/gpu/drm/nouveau/nouveau_connector.c @@ -571,8 +571,10 @@ nouveau_connector_detect(struct drm_connector *connector, bool force) pm_runtime_get_noresume(dev->dev); } else { ret = pm_runtime_get_sync(dev->dev); - if (ret < 0 && ret != -EACCES) + if (ret < 0 && ret != -EACCES) { + pm_runtime_put_autosuspend(dev->dev); return conn_status; + } } nv_encoder = nouveau_connector_ddc_detect(connector); From 8f29432417b11039ef960ab18987c7d61b2b5396 Mon Sep 17 00:00:00 2001 From: Aditya Pakki Date: Sat, 13 Jun 2020 20:48:37 -0500 Subject: [PATCH 023/145] drm/nouveau: fix reference count leak in nouveau_debugfs_strap_peek nouveau_debugfs_strap_peek() calls pm_runtime_get_sync() that increments the reference count. In case of failure, decrement the ref count before returning the error. Signed-off-by: Aditya Pakki Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nouveau_debugfs.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/nouveau/nouveau_debugfs.c b/drivers/gpu/drm/nouveau/nouveau_debugfs.c index 63b5c8cf9ae4..8f63cda3db17 100644 --- a/drivers/gpu/drm/nouveau/nouveau_debugfs.c +++ b/drivers/gpu/drm/nouveau/nouveau_debugfs.c @@ -54,8 +54,10 @@ nouveau_debugfs_strap_peek(struct seq_file *m, void *data) int ret; ret = pm_runtime_get_sync(drm->dev->dev); - if (ret < 0 && ret != -EACCES) + if (ret < 0 && ret != -EACCES) { + pm_runtime_put_autosuspend(drm->dev->dev); return ret; + } seq_printf(m, "0x%08x\n", nvif_rd32(&drm->client.device.object, 0x101000)); From e5c7864f6297c2f6256369bff2f2ef9f1d5edd5e Mon Sep 17 00:00:00 2001 From: Ralph Campbell Date: Mon, 22 Jun 2020 16:38:54 -0700 Subject: [PATCH 024/145] drm/nouveau/mmu: make nvkm_vmm_ctor() static The function nvkm_vmm_ctor() is not called outside of the file defining it, so make it static. Signed-off-by: Ralph Campbell Reviewed-by: John Hubbard Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h | 3 --- 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c index 199f94e15c5f..67b00dcef4b8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c @@ -1030,7 +1030,7 @@ nvkm_vmm_ctor_managed(struct nvkm_vmm *vmm, u64 addr, u64 size) return 0; } -int +static int nvkm_vmm_ctor(const struct nvkm_vmm_func *func, struct nvkm_mmu *mmu, u32 pd_header, bool managed, u64 addr, u64 size, struct lock_class_key *key, const char *name, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h index d3f8f916d0db..a2b179568970 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h @@ -163,9 +163,6 @@ int nvkm_vmm_new_(const struct nvkm_vmm_func *, struct nvkm_mmu *, u32 pd_header, bool managed, u64 addr, u64 size, struct lock_class_key *, const char *name, struct nvkm_vmm **); -int nvkm_vmm_ctor(const struct nvkm_vmm_func *, struct nvkm_mmu *, - u32 pd_header, bool managed, u64 addr, u64 size, - struct lock_class_key *, const char *name, struct nvkm_vmm *); struct nvkm_vma *nvkm_vmm_node_search(struct nvkm_vmm *, u64 addr); struct nvkm_vma *nvkm_vmm_node_split(struct nvkm_vmm *, struct nvkm_vma *, u64 addr, u64 size); From 7763d24f3ba0e5e30daf047cfa6e6bcfd9d7de75 Mon Sep 17 00:00:00 2001 From: Ralph Campbell Date: Tue, 30 Jun 2020 12:57:35 -0700 Subject: [PATCH 025/145] drm/nouveau/vmm/gp100-: fix mapping 2MB sysmem pages The nvif_object_ioctl() method NVIF_VMM_V0_PFNMAP wasn't correctly setting the hardware specific GPU page table entries for 2MB sized pages. Fix this by adding functions to set and clear PD0 GPU page table entries. Signed-off-by: Ralph Campbell Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c | 5 +- .../drm/nouveau/nvkm/subdev/mmu/vmmgp100.c | 82 +++++++++++++++++++ 2 files changed, 84 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c index 67b00dcef4b8..710f3f8dc7c9 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c @@ -1204,7 +1204,6 @@ nvkm_vmm_pfn_unmap(struct nvkm_vmm *vmm, u64 addr, u64 size) /*TODO: * - Avoid PT readback (for dma_unmap etc), this might end up being dealt * with inside HMM, which would be a lot nicer for us to deal with. - * - Multiple page sizes (particularly for huge page support). * - Support for systems without a 4KiB page size. */ int @@ -1220,8 +1219,8 @@ nvkm_vmm_pfn_map(struct nvkm_vmm *vmm, u8 shift, u64 addr, u64 size, u64 *pfn) /* Only support mapping where the page size of the incoming page * array matches a page size available for direct mapping. */ - while (page->shift && page->shift != shift && - page->desc->func->pfn == NULL) + while (page->shift && (page->shift != shift || + page->desc->func->pfn == NULL)) page++; if (!page->shift || !IS_ALIGNED(addr, 1ULL << shift) || diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c index 97520e9721c9..9539e6cda4d9 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c @@ -258,12 +258,94 @@ gp100_vmm_pd0_unmap(struct nvkm_vmm *vmm, VMM_FO128(pt, vmm, pdei * 0x10, 0ULL, 0ULL, pdes); } +static void +gp100_vmm_pd0_pfn_unmap(struct nvkm_vmm *vmm, + struct nvkm_mmu_pt *pt, u32 ptei, u32 ptes) +{ + struct device *dev = vmm->mmu->subdev.device->dev; + dma_addr_t addr; + + nvkm_kmap(pt->memory); + while (ptes--) { + u32 datalo = nvkm_ro32(pt->memory, pt->base + ptei * 16 + 0); + u32 datahi = nvkm_ro32(pt->memory, pt->base + ptei * 16 + 4); + u64 data = (u64)datahi << 32 | datalo; + + if ((data & (3ULL << 1)) != 0) { + addr = (data >> 8) << 12; + dma_unmap_page(dev, addr, 1UL << 21, DMA_BIDIRECTIONAL); + } + ptei++; + } + nvkm_done(pt->memory); +} + +static bool +gp100_vmm_pd0_pfn_clear(struct nvkm_vmm *vmm, + struct nvkm_mmu_pt *pt, u32 ptei, u32 ptes) +{ + bool dma = false; + + nvkm_kmap(pt->memory); + while (ptes--) { + u32 datalo = nvkm_ro32(pt->memory, pt->base + ptei * 16 + 0); + u32 datahi = nvkm_ro32(pt->memory, pt->base + ptei * 16 + 4); + u64 data = (u64)datahi << 32 | datalo; + + if ((data & BIT_ULL(0)) && (data & (3ULL << 1)) != 0) { + VMM_WO064(pt, vmm, ptei * 16, data & ~BIT_ULL(0)); + dma = true; + } + ptei++; + } + nvkm_done(pt->memory); + return dma; +} + +static void +gp100_vmm_pd0_pfn(struct nvkm_vmm *vmm, struct nvkm_mmu_pt *pt, + u32 ptei, u32 ptes, struct nvkm_vmm_map *map) +{ + struct device *dev = vmm->mmu->subdev.device->dev; + dma_addr_t addr; + + nvkm_kmap(pt->memory); + while (ptes--) { + u64 data = 0; + + if (!(*map->pfn & NVKM_VMM_PFN_W)) + data |= BIT_ULL(6); /* RO. */ + + if (!(*map->pfn & NVKM_VMM_PFN_VRAM)) { + addr = *map->pfn >> NVKM_VMM_PFN_ADDR_SHIFT; + addr = dma_map_page(dev, pfn_to_page(addr), 0, + 1UL << 21, DMA_BIDIRECTIONAL); + if (!WARN_ON(dma_mapping_error(dev, addr))) { + data |= addr >> 4; + data |= 2ULL << 1; /* SYSTEM_COHERENT_MEMORY. */ + data |= BIT_ULL(3); /* VOL. */ + data |= BIT_ULL(0); /* VALID. */ + } + } else { + data |= (*map->pfn & NVKM_VMM_PFN_ADDR) >> 4; + data |= BIT_ULL(0); /* VALID. */ + } + + VMM_WO064(pt, vmm, ptei++ * 16, data); + map->pfn++; + } + nvkm_done(pt->memory); +} + static const struct nvkm_vmm_desc_func gp100_vmm_desc_pd0 = { .unmap = gp100_vmm_pd0_unmap, .sparse = gp100_vmm_pd0_sparse, .pde = gp100_vmm_pd0_pde, .mem = gp100_vmm_pd0_mem, + .pfn = gp100_vmm_pd0_pfn, + .pfn_clear = gp100_vmm_pd0_pfn_clear, + .pfn_unmap = gp100_vmm_pd0_pfn_unmap, }; static void From f6e7393edefada6abf7d0b6cd3f81f09d2f22fbf Mon Sep 17 00:00:00 2001 From: "Gustavo A. R. Silva" Date: Tue, 7 Jul 2020 12:36:28 -0500 Subject: [PATCH 026/145] drm/nouveau: Use fallthrough pseudo-keyword Replace the existing /* fall through */ comments and its variants with the new pseudo-keyword macro fallthrough[1]. Also, remove unnecessary fall-through markings when it is the case. [1] https://www.kernel.org/doc/html/latest/process/deprecated.html?highlight=fallthrough#implicit-switch-case-fall-through Signed-off-by: Gustavo A. R. Silva Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/dispnv50/disp.c | 2 +- drivers/gpu/drm/nouveau/nouveau_bo.c | 2 +- drivers/gpu/drm/nouveau/nouveau_connector.c | 4 +-- .../gpu/drm/nouveau/nvkm/engine/disp/hdmi.c | 34 +++++++++---------- .../drm/nouveau/nvkm/engine/dma/usernv04.c | 2 +- .../gpu/drm/nouveau/nvkm/engine/fifo/nv04.c | 4 +-- .../gpu/drm/nouveau/nvkm/engine/fifo/nv40.c | 2 +- .../gpu/drm/nouveau/nvkm/subdev/bios/dcb.c | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/bios/dp.c | 2 +- .../gpu/drm/nouveau/nvkm/subdev/bios/perf.c | 2 +- .../gpu/drm/nouveau/nvkm/subdev/bios/pll.c | 2 +- .../gpu/drm/nouveau/nvkm/subdev/bios/timing.c | 10 +++--- .../gpu/drm/nouveau/nvkm/subdev/clk/base.c | 2 +- .../gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c | 2 +- .../drm/nouveau/nvkm/subdev/devinit/nv04.c | 12 +++---- .../gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c | 4 +-- .../gpu/drm/nouveau/nvkm/subdev/mxm/nv50.c | 2 +- 17 files changed, 45 insertions(+), 45 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c b/drivers/gpu/drm/nouveau/dispnv50/disp.c index f4921460dbef..dbd23597e5d0 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/disp.c +++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c @@ -933,7 +933,7 @@ nv50_dp_bpc_to_depth(unsigned int bpc) switch (bpc) { case 6: return 0x2; case 8: return 0x5; - case 10: /* fall-through */ + case 10: default: return 0x6; } } diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c index 4ccf937df0d0..ad521778c0dd 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c @@ -1461,7 +1461,7 @@ nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *reg) if (drm->client.mem->oclass < NVIF_CLASS_MEM_NV50 || !mem->kind) /* untiled */ break; - /* fall through - tiled memory */ + fallthrough; /* tiled memory */ case TTM_PL_VRAM: reg->bus.offset = reg->start << PAGE_SHIFT; reg->bus.base = device->func->resource_addr(device, 1); diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c b/drivers/gpu/drm/nouveau/nouveau_connector.c index 1fa5d5614261..471fd5ca5352 100644 --- a/drivers/gpu/drm/nouveau/nouveau_connector.c +++ b/drivers/gpu/drm/nouveau/nouveau_connector.c @@ -330,7 +330,7 @@ nouveau_conn_attach_properties(struct drm_connector *connector) case DRM_MODE_CONNECTOR_VGA: if (disp->disp.object.oclass < NV50_DISP) break; /* Can only scale on DFPs. */ - /* Fall-through. */ + fallthrough; default: drm_object_attach_property(&connector->base, dev->mode_config. scaling_mode_property, @@ -445,7 +445,7 @@ nouveau_connector_ddc_detect(struct drm_connector *connector) case DCB_OUTPUT_LVDS: switcheroo_ddc = !!(vga_switcheroo_handler_flags() & VGA_SWITCHEROO_CAN_SWITCH_DDC); - /* fall-through */ + fallthrough; default: if (!nv_encoder->i2c) break; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmi.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmi.c index 7147dc6d9018..1ccfc8314812 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmi.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmi.c @@ -23,55 +23,55 @@ void pack_hdmi_infoframe(struct packed_hdmi_infoframe *packed_frame, */ case 17: subpack1_high = (raw_frame[16] << 16); - /* fall through */ + fallthrough; case 16: subpack1_high |= (raw_frame[15] << 8); - /* fall through */ + fallthrough; case 15: subpack1_high |= raw_frame[14]; - /* fall through */ + fallthrough; case 14: subpack1_low = (raw_frame[13] << 24); - /* fall through */ + fallthrough; case 13: subpack1_low |= (raw_frame[12] << 16); - /* fall through */ + fallthrough; case 12: subpack1_low |= (raw_frame[11] << 8); - /* fall through */ + fallthrough; case 11: subpack1_low |= raw_frame[10]; - /* fall through */ + fallthrough; case 10: subpack0_high = (raw_frame[9] << 16); - /* fall through */ + fallthrough; case 9: subpack0_high |= (raw_frame[8] << 8); - /* fall through */ + fallthrough; case 8: subpack0_high |= raw_frame[7]; - /* fall through */ + fallthrough; case 7: subpack0_low = (raw_frame[6] << 24); - /* fall through */ + fallthrough; case 6: subpack0_low |= (raw_frame[5] << 16); - /* fall through */ + fallthrough; case 5: subpack0_low |= (raw_frame[4] << 8); - /* fall through */ + fallthrough; case 4: subpack0_low |= raw_frame[3]; - /* fall through */ + fallthrough; case 3: header = (raw_frame[2] << 16); - /* fall through */ + fallthrough; case 2: header |= (raw_frame[1] << 8); - /* fall through */ + fallthrough; case 1: header |= raw_frame[0]; - /* fall through */ + fallthrough; case 0: break; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c index 7f1adab21a5f..5159d5df20a2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c @@ -122,7 +122,7 @@ nv04_dmaobj_new(struct nvkm_dma *dma, const struct nvkm_oclass *oclass, break; case NV_MEM_ACCESS_WO: dmaobj->flags0 |= 0x00008000; - /* fall through */ + fallthrough; case NV_MEM_ACCESS_RW: dmaobj->flags2 |= 0x00000002; break; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c index 93493b335d76..c1d1b1aa5bc6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c @@ -117,10 +117,10 @@ nv04_fifo_swmthd(struct nvkm_device *device, u32 chid, u32 addr, u32 data) switch (mthd) { case 0x0000 ... 0x0000: /* subchannel's engine -> software */ nvkm_wr32(device, 0x003280, (engine &= ~mask)); - /* fall through */ + fallthrough; case 0x0180 ... 0x01fc: /* handle -> instance */ data = nvkm_rd32(device, 0x003258) & 0x0000ffff; - /* fall through */ + fallthrough; case 0x0100 ... 0x017c: case 0x0200 ... 0x1ffc: /* pass method down to sw */ if (!(engine & mask) && sw) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c index 47c16821c37f..2d61fd832ddb 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c @@ -81,7 +81,7 @@ nv40_fifo_init(struct nvkm_fifo *base) case 0x49: case 0x4b: nvkm_wr32(device, 0x002230, 0x00000001); - /* fall through */ + fallthrough; case 0x40: case 0x41: case 0x42: diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/dcb.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/dcb.c index a8d5d67feeaf..8698f260b988 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/dcb.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/dcb.c @@ -172,8 +172,8 @@ dcb_outp_parse(struct nvkm_bios *bios, u8 idx, u8 *ver, u8 *len, outp->dpconf.link_nr = 1; break; } + fallthrough; - /* fall-through... */ case DCB_OUTPUT_TMDS: case DCB_OUTPUT_LVDS: outp->link = (conf & 0x00000030) >> 4; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/dp.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/dp.c index b099d1209be8..c694501ae206 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/dp.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/dp.c @@ -100,7 +100,7 @@ nvbios_dpout_parse(struct nvkm_bios *bios, u8 idx, switch (*ver) { case 0x20: info->mask |= 0x00c0; /* match any link */ - /* fall-through */ + fallthrough; case 0x21: case 0x30: info->flags = nvbios_rd08(bios, data + 0x05); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/perf.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/perf.c index 7112992e0e38..f039388f0676 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/perf.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/perf.c @@ -135,7 +135,7 @@ nvbios_perfEp(struct nvkm_bios *bios, int idx, break; case 0x30: info->script = nvbios_rd16(bios, perf + 0x02); - /* fall through */ + fallthrough; case 0x35: info->fanspeed = nvbios_rd08(bios, perf + 0x06); info->voltage = nvbios_rd08(bios, perf + 0x07); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/pll.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/pll.c index bda6cc9a7aaf..350f10a3de37 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/pll.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/pll.c @@ -134,7 +134,7 @@ pll_map(struct nvkm_bios *bios) device->chipset == 0xaa || device->chipset == 0xac) return g84_pll_mapping; - /* fall through */ + fallthrough; default: return NULL; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c index 20ff5173cf8f..2da45e29f68b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c @@ -115,21 +115,21 @@ nvbios_timingEp(struct nvkm_bios *bios, int idx, switch (min_t(u8, *hdr, 25)) { case 25: p->timing_10_24 = nvbios_rd08(bios, data + 0x18); - /* fall through */ + fallthrough; case 24: case 23: case 22: p->timing_10_21 = nvbios_rd08(bios, data + 0x15); - /* fall through */ + fallthrough; case 21: p->timing_10_20 = nvbios_rd08(bios, data + 0x14); - /* fall through */ + fallthrough; case 20: p->timing_10_CWL = nvbios_rd08(bios, data + 0x13); - /* fall through */ + fallthrough; case 19: p->timing_10_18 = nvbios_rd08(bios, data + 0x12); - /* fall through */ + fallthrough; case 18: case 17: p->timing_10_16 = nvbios_rd08(bios, data + 0x10); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c index 40e564524b7a..dc184e857f85 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c @@ -90,7 +90,7 @@ nvkm_cstate_valid(struct nvkm_clk *clk, struct nvkm_cstate *cstate, case NVKM_CLK_BOOST_NONE: if (clk->base_khz && freq > clk->base_khz) return false; - /* fall through */ + fallthrough; case NVKM_CLK_BOOST_BIOS: if (clk->boost_khz && freq > clk->boost_khz) return false; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c index 4f000237796f..efa50274df97 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c @@ -363,7 +363,7 @@ mcp77_clk_prog(struct nvkm_clk *base) switch (clk->vsrc) { case nv_clk_src_cclk: mast |= 0x00400000; - /* fall through */ + fallthrough; default: nvkm_wr32(device, 0x4600, clk->vdiv); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c index c3dae05348eb..317ce9fb8225 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c @@ -119,11 +119,11 @@ powerctrl_1_shift(int chip_version, int reg) switch (reg) { case 0x680520: - shift += 4; /* fall through */ + shift += 4; fallthrough; case 0x680508: - shift += 4; /* fall through */ + shift += 4; fallthrough; case 0x680504: - shift += 4; /* fall through */ + shift += 4; fallthrough; case 0x680500: shift += 4; } @@ -245,11 +245,11 @@ setPLL_double_highregs(struct nvkm_devinit *init, u32 reg1, switch (reg1) { case 0x680504: - shift_c040 += 2; /* fall through */ + shift_c040 += 2; fallthrough; case 0x680500: - shift_c040 += 2; /* fall through */ + shift_c040 += 2; fallthrough; case 0x680520: - shift_c040 += 2; /* fall through */ + shift_c040 += 2; fallthrough; case 0x680508: shift_c040 += 2; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c index 5f4c287d7943..97b3a28ca5c0 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c @@ -131,13 +131,13 @@ nv40_ram_prog(struct nvkm_ram *base) nvkm_mask(device, 0x00402c, 0xc0771100, ram->ctrl); nvkm_wr32(device, 0x004048, ram->coef); nvkm_wr32(device, 0x004030, ram->coef); - /* fall through */ + fallthrough; case 0x43: case 0x49: case 0x4b: nvkm_mask(device, 0x004038, 0xc0771100, ram->ctrl); nvkm_wr32(device, 0x00403c, ram->coef); - /* fall through */ + fallthrough; default: nvkm_mask(device, 0x004020, 0xc0771100, ram->ctrl); nvkm_wr32(device, 0x004024, ram->coef); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/nv50.c index 2a6150ab5611..70e2c414bb7b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/nv50.c @@ -159,7 +159,7 @@ mxm_dcb_sanitise_entry(struct nvkm_bios *bios, void *data, int idx, u16 pdcb) break; case 0x0e: /* eDP, falls through to DPint */ ctx.outp[1] |= 0x00010000; - /* fall through */ + fallthrough; case 0x07: /* DP internal, wtf is this?? HP8670w */ ctx.outp[1] |= 0x00000004; /* use_power_scripts? */ type = DCB_CONNECTOR_eDP; From 188e905ce4fe53fa984fe57357679168f5d7a091 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Fri, 24 Jul 2020 10:13:21 +1000 Subject: [PATCH 027/145] drm/nouveau/kms/tu102: set NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_UPSCALING_ALLOWED to TRUE Fixes issues when switching between scaling modes. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/dispnv50/headc57d.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/headc57d.c b/drivers/gpu/drm/nouveau/dispnv50/headc57d.c index c7d04dd935fd..28d4431bba1b 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/headc57d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/headc57d.c @@ -191,7 +191,7 @@ headc57d_mode(struct nv50_head *head, struct nv50_head_atom *asyh) evo_data(push, m->clock * 1000); /*XXX: HEAD_USAGE_BOUNDS, doesn't belong here. */ evo_mthd(push, 0x2030 + (head->base.index * 0x400), 1); - evo_data(push, 0x00001014); + evo_data(push, 0x00001114); evo_kick(push, core); } } From 6db25fb13abaec0c2f1fa876824bf3c2a9a3e1d4 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 30 Mar 2020 13:45:33 +1000 Subject: [PATCH 028/145] drm/nouveau/nvif: rename client ctor/dtor Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/include/nvif/client.h | 4 ++-- drivers/gpu/drm/nouveau/nouveau_drm.c | 4 ++-- drivers/gpu/drm/nouveau/nvif/client.c | 6 +++--- drivers/gpu/drm/nouveau/nvif/driver.c | 2 +- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/nouveau/include/nvif/client.h b/drivers/gpu/drm/nouveau/include/nvif/client.h index e63c6c965b54..347d2c020bd1 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/client.h +++ b/drivers/gpu/drm/nouveau/include/nvif/client.h @@ -12,9 +12,9 @@ struct nvif_client { bool super; }; -int nvif_client_init(struct nvif_client *parent, const char *name, u64 device, +int nvif_client_ctor(struct nvif_client *parent, const char *name, u64 device, struct nvif_client *); -void nvif_client_fini(struct nvif_client *); +void nvif_client_dtor(struct nvif_client *); int nvif_client_ioctl(struct nvif_client *, void *, u32); int nvif_client_suspend(struct nvif_client *); int nvif_client_resume(struct nvif_client *); diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c index 880d962c1b19..0bf05d9139fe 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drm.c +++ b/drivers/gpu/drm/nouveau/nouveau_drm.c @@ -181,7 +181,7 @@ nouveau_cli_fini(struct nouveau_cli *cli) nvif_mmu_fini(&cli->mmu); nvif_device_fini(&cli->device); mutex_lock(&cli->drm->master.lock); - nvif_client_fini(&cli->base); + nvif_client_dtor(&cli->base); mutex_unlock(&cli->drm->master.lock); } @@ -229,7 +229,7 @@ nouveau_cli_init(struct nouveau_drm *drm, const char *sname, cli->name, device, &cli->base); } else { mutex_lock(&drm->master.lock); - ret = nvif_client_init(&drm->master.base, cli->name, device, + ret = nvif_client_ctor(&drm->master.base, cli->name, device, &cli->base); mutex_unlock(&drm->master.lock); } diff --git a/drivers/gpu/drm/nouveau/nvif/client.c b/drivers/gpu/drm/nouveau/nvif/client.c index 12db54965c20..a36902c1c287 100644 --- a/drivers/gpu/drm/nouveau/nvif/client.c +++ b/drivers/gpu/drm/nouveau/nvif/client.c @@ -48,7 +48,7 @@ nvif_client_resume(struct nvif_client *client) } void -nvif_client_fini(struct nvif_client *client) +nvif_client_dtor(struct nvif_client *client) { nvif_object_fini(&client->object); if (client->driver) { @@ -59,7 +59,7 @@ nvif_client_fini(struct nvif_client *client) } int -nvif_client_init(struct nvif_client *parent, const char *name, u64 device, +nvif_client_ctor(struct nvif_client *parent, const char *name, u64 device, struct nvif_client *client) { struct nvif_client_v0 args = { .device = device }; @@ -88,6 +88,6 @@ nvif_client_init(struct nvif_client *parent, const char *name, u64 device, } if (ret) - nvif_client_fini(client); + nvif_client_dtor(client); return ret; } diff --git a/drivers/gpu/drm/nouveau/nvif/driver.c b/drivers/gpu/drm/nouveau/nvif/driver.c index 701330956e33..5e00dd07afed 100644 --- a/drivers/gpu/drm/nouveau/nvif/driver.c +++ b/drivers/gpu/drm/nouveau/nvif/driver.c @@ -53,6 +53,6 @@ nvif_driver_init(const char *drv, const char *cfg, const char *dbg, } if (ret == 0) - ret = nvif_client_init(client, name, device, client); + ret = nvif_client_ctor(client, name, device, client); return ret; } From 9ac596a4e875e28bb1fa4b2e00549fadfaf4784e Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 30 Mar 2020 09:51:33 +1000 Subject: [PATCH 029/145] drm/nouveau/nvif: give every object a human-readable identifier Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/corec37d.c | 4 +-- drivers/gpu/drm/nouveau/dispnv50/crc.c | 4 +-- drivers/gpu/drm/nouveau/dispnv50/curs507a.c | 4 +-- drivers/gpu/drm/nouveau/dispnv50/disp.c | 17 ++++----- drivers/gpu/drm/nouveau/dispnv50/oimm507b.c | 4 +-- drivers/gpu/drm/nouveau/dispnv50/wndw.c | 6 ++-- drivers/gpu/drm/nouveau/include/nvif/object.h | 8 ++--- drivers/gpu/drm/nouveau/nouveau_abi16.c | 8 ++--- drivers/gpu/drm/nouveau/nouveau_bo.c | 4 +-- drivers/gpu/drm/nouveau/nouveau_chan.c | 36 ++++++++++--------- drivers/gpu/drm/nouveau/nouveau_debugfs.c | 4 +-- drivers/gpu/drm/nouveau/nouveau_drm.c | 16 ++++----- drivers/gpu/drm/nouveau/nouveau_fbcon.c | 14 ++++---- drivers/gpu/drm/nouveau/nouveau_svm.c | 6 ++-- drivers/gpu/drm/nouveau/nv04_fbcon.c | 20 +++++------ drivers/gpu/drm/nouveau/nv10_fence.c | 2 +- drivers/gpu/drm/nouveau/nv17_fence.c | 3 +- drivers/gpu/drm/nouveau/nv50_fbcon.c | 4 +-- drivers/gpu/drm/nouveau/nv50_fence.c | 3 +- drivers/gpu/drm/nouveau/nvc0_fbcon.c | 4 +-- drivers/gpu/drm/nouveau/nvif/client.c | 7 ++-- drivers/gpu/drm/nouveau/nvif/device.c | 6 ++-- drivers/gpu/drm/nouveau/nvif/disp.c | 6 ++-- drivers/gpu/drm/nouveau/nvif/mem.c | 4 +-- drivers/gpu/drm/nouveau/nvif/mmu.c | 6 ++-- drivers/gpu/drm/nouveau/nvif/object.c | 11 +++--- drivers/gpu/drm/nouveau/nvif/user.c | 5 +-- drivers/gpu/drm/nouveau/nvif/vmm.c | 4 +-- 28 files changed, 115 insertions(+), 105 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/corec37d.c b/drivers/gpu/drm/nouveau/dispnv50/corec37d.c index ec83189a1d48..a4a307e13b9f 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/corec37d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/corec37d.c @@ -92,8 +92,8 @@ int corec37d_caps_init(struct nouveau_drm *drm, struct nv50_disp *disp) { int ret; - ret = nvif_object_init(&disp->disp->object, 0, GV100_DISP_CAPS, - NULL, 0, &disp->caps); + ret = nvif_object_ctor(&disp->disp->object, "dispCaps", 0, + GV100_DISP_CAPS, NULL, 0, &disp->caps); if (ret) { NV_ERROR(drm, "Failed to init notifier caps region: %d\n", diff --git a/drivers/gpu/drm/nouveau/dispnv50/crc.c b/drivers/gpu/drm/nouveau/dispnv50/crc.c index f17fb6d56757..5fac476fe130 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/crc.c +++ b/drivers/gpu/drm/nouveau/dispnv50/crc.c @@ -514,7 +514,7 @@ nv50_crc_ctx_init(struct nv50_head *head, struct nvif_mmu *mmu, if (ret) return ret; - ret = nvif_object_init(&core->chan.base.user, + ret = nvif_object_ctor(&core->chan.base.user, "kmsCrcNtfyCtxDma", NV50_DISP_HANDLE_CRC_CTX(head, idx), NV_DMA_IN_MEMORY, &(struct nv_dma_v0) { @@ -538,7 +538,7 @@ nv50_crc_ctx_init(struct nv50_head *head, struct nvif_mmu *mmu, static inline void nv50_crc_ctx_fini(struct nv50_crc_notifier_ctx *ctx) { - nvif_object_fini(&ctx->ntfy); + nvif_object_dtor(&ctx->ntfy); nvif_mem_fini(&ctx->mem); } diff --git a/drivers/gpu/drm/nouveau/dispnv50/curs507a.c b/drivers/gpu/drm/nouveau/dispnv50/curs507a.c index 658a200ab616..2468e91b36db 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/curs507a.c +++ b/drivers/gpu/drm/nouveau/dispnv50/curs507a.c @@ -138,8 +138,8 @@ curs507a_new_(const struct nv50_wimm_func *func, struct nouveau_drm *drm, if (*pwndw = wndw, ret) return ret; - ret = nvif_object_init(&disp->disp->object, 0, oclass, &args, - sizeof(args), &wndw->wimm.base.user); + ret = nvif_object_ctor(&disp->disp->object, "kmsCurs", 0, oclass, + &args, sizeof(args), &wndw->wimm.base.user); if (ret) { NV_ERROR(drm, "curs%04x allocation failed: %d\n", oclass, ret); return ret; diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c b/drivers/gpu/drm/nouveau/dispnv50/disp.c index dbd23597e5d0..5bc40b5e6325 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/disp.c +++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c @@ -79,8 +79,9 @@ nv50_chan_create(struct nvif_device *device, struct nvif_object *disp, while (oclass[0]) { for (i = 0; i < n; i++) { if (sclass[i].oclass == oclass[0]) { - ret = nvif_object_init(disp, 0, oclass[0], - data, size, &chan->user); + ret = nvif_object_ctor(disp, "kmsChan", 0, + oclass[0], data, size, + &chan->user); if (ret == 0) nvif_object_map(&chan->user, NULL, 0); nvif_object_sclass_put(&sclass); @@ -97,7 +98,7 @@ nv50_chan_create(struct nvif_device *device, struct nvif_object *disp, static void nv50_chan_destroy(struct nv50_chan *chan) { - nvif_object_fini(&chan->user); + nvif_object_dtor(&chan->user); } /****************************************************************************** @@ -107,8 +108,8 @@ nv50_chan_destroy(struct nv50_chan *chan) void nv50_dmac_destroy(struct nv50_dmac *dmac) { - nvif_object_fini(&dmac->vram); - nvif_object_fini(&dmac->sync); + nvif_object_dtor(&dmac->vram); + nvif_object_dtor(&dmac->sync); nv50_chan_destroy(&dmac->base); @@ -155,7 +156,7 @@ nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp, if (!syncbuf) return 0; - ret = nvif_object_init(&dmac->base.user, NV50_DISP_HANDLE_SYNCBUF, + ret = nvif_object_ctor(&dmac->base.user, "kmsSyncCtxDma", NV50_DISP_HANDLE_SYNCBUF, NV_DMA_IN_MEMORY, &(struct nv_dma_v0) { .target = NV_DMA_V0_TARGET_VRAM, @@ -167,7 +168,7 @@ nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp, if (ret) return ret; - ret = nvif_object_init(&dmac->base.user, NV50_DISP_HANDLE_VRAM, + ret = nvif_object_ctor(&dmac->base.user, "kmsVramCtxDma", NV50_DISP_HANDLE_VRAM, NV_DMA_IN_MEMORY, &(struct nv_dma_v0) { .target = NV_DMA_V0_TARGET_VRAM, @@ -2465,7 +2466,7 @@ nv50_display_destroy(struct drm_device *dev) nv50_audio_component_fini(nouveau_drm(dev)); nvif_object_unmap(&disp->caps); - nvif_object_fini(&disp->caps); + nvif_object_dtor(&disp->caps); nv50_core_del(&disp->core); nouveau_bo_unmap(disp->sync); diff --git a/drivers/gpu/drm/nouveau/dispnv50/oimm507b.c b/drivers/gpu/drm/nouveau/dispnv50/oimm507b.c index 2ee404b3e19f..a6c3a9b95bdb 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/oimm507b.c +++ b/drivers/gpu/drm/nouveau/dispnv50/oimm507b.c @@ -33,8 +33,8 @@ oimm507b_init_(const struct nv50_wimm_func *func, struct nouveau_drm *drm, struct nv50_disp *disp = nv50_disp(drm->dev); int ret; - ret = nvif_object_init(&disp->disp->object, 0, oclass, &args, - sizeof(args), &wndw->wimm.base.user); + ret = nvif_object_ctor(&disp->disp->object, "kmsOvim", 0, oclass, + &args, sizeof(args), &wndw->wimm.base.user); if (ret) { NV_ERROR(drm, "oimm%04x allocation failed: %d\n", oclass, ret); return ret; diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndw.c b/drivers/gpu/drm/nouveau/dispnv50/wndw.c index 293ccfdba17e..be67ef0785d8 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndw.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndw.c @@ -35,7 +35,7 @@ static void nv50_wndw_ctxdma_del(struct nv50_wndw_ctxdma *ctxdma) { - nvif_object_fini(&ctxdma->object); + nvif_object_dtor(&ctxdma->object); list_del(&ctxdma->head); kfree(ctxdma); } @@ -94,8 +94,8 @@ nv50_wndw_ctxdma_new(struct nv50_wndw *wndw, struct drm_framebuffer *fb) argc += sizeof(args.gf119); } - ret = nvif_object_init(wndw->ctxdma.parent, handle, NV_DMA_IN_MEMORY, - &args, argc, &ctxdma->object); + ret = nvif_object_ctor(wndw->ctxdma.parent, "kmsFbCtxDma", handle, + NV_DMA_IN_MEMORY, &args, argc, &ctxdma->object); if (ret) { nv50_wndw_ctxdma_del(ctxdma); return ERR_PTR(ret); diff --git a/drivers/gpu/drm/nouveau/include/nvif/object.h b/drivers/gpu/drm/nouveau/include/nvif/object.h index 604fabc0e689..f3e20d02b2bc 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/object.h +++ b/drivers/gpu/drm/nouveau/include/nvif/object.h @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: MIT */ #ifndef __NVIF_OBJECT_H__ #define __NVIF_OBJECT_H__ - #include struct nvif_sclass { @@ -12,6 +11,7 @@ struct nvif_sclass { struct nvif_object { struct nvif_client *client; + const char *name; u32 handle; s32 oclass; void *priv; /*XXX: hack */ @@ -21,9 +21,9 @@ struct nvif_object { } map; }; -int nvif_object_init(struct nvif_object *, u32 handle, s32 oclass, void *, u32, - struct nvif_object *); -void nvif_object_fini(struct nvif_object *); +int nvif_object_ctor(struct nvif_object *, const char *name, u32 handle, + s32 oclass, void *, u32, struct nvif_object *); +void nvif_object_dtor(struct nvif_object *); int nvif_object_ioctl(struct nvif_object *, void *, u32, void **); int nvif_object_sclass_get(struct nvif_object *, struct nvif_sclass **); void nvif_object_sclass_put(struct nvif_sclass **); diff --git a/drivers/gpu/drm/nouveau/nouveau_abi16.c b/drivers/gpu/drm/nouveau/nouveau_abi16.c index 5b2406950e53..ace302dc3369 100644 --- a/drivers/gpu/drm/nouveau/nouveau_abi16.c +++ b/drivers/gpu/drm/nouveau/nouveau_abi16.c @@ -114,7 +114,7 @@ static void nouveau_abi16_ntfy_fini(struct nouveau_abi16_chan *chan, struct nouveau_abi16_ntfy *ntfy) { - nvif_object_fini(&ntfy->object); + nvif_object_dtor(&ntfy->object); nvkm_mm_free(&chan->heap, &ntfy->node); list_del(&ntfy->head); kfree(ntfy); @@ -502,8 +502,8 @@ nouveau_abi16_ioctl_grobj_alloc(ABI16_IOCTL_ARGS) list_add(&ntfy->head, &chan->notifiers); client->route = NVDRM_OBJECT_ABI16; - ret = nvif_object_init(&chan->chan->user, init->handle, oclass, - NULL, 0, &ntfy->object); + ret = nvif_object_ctor(&chan->chan->user, "abi16EngObj", init->handle, + oclass, NULL, 0, &ntfy->object); client->route = NVDRM_OBJECT_NVIF; if (ret) @@ -569,7 +569,7 @@ nouveau_abi16_ioctl_notifierobj_alloc(ABI16_IOCTL_ARGS) client->route = NVDRM_OBJECT_ABI16; client->super = true; - ret = nvif_object_init(&chan->chan->user, info->handle, + ret = nvif_object_ctor(&chan->chan->user, "abi16Ntfy", info->handle, NV_DMA_IN_MEMORY, &args, sizeof(args), &ntfy->object); client->super = false; diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c index ad521778c0dd..dea090c176ef 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c @@ -1197,14 +1197,14 @@ nouveau_bo_move_init(struct nouveau_drm *drm) if (chan == NULL) continue; - ret = nvif_object_init(&chan->user, + ret = nvif_object_ctor(&chan->user, "ttmBoMove", mthd->oclass | (mthd->engine << 16), mthd->oclass, NULL, 0, &drm->ttm.copy); if (ret == 0) { ret = mthd->init(chan, drm->ttm.copy.handle); if (ret) { - nvif_object_fini(&drm->ttm.copy); + nvif_object_dtor(&drm->ttm.copy); continue; } diff --git a/drivers/gpu/drm/nouveau/nouveau_chan.c b/drivers/gpu/drm/nouveau/nouveau_chan.c index 3d71dfcb2fde..59dbea9eab36 100644 --- a/drivers/gpu/drm/nouveau/nouveau_chan.c +++ b/drivers/gpu/drm/nouveau/nouveau_chan.c @@ -102,12 +102,12 @@ nouveau_channel_del(struct nouveau_channel **pchan) if (cli) nouveau_svmm_part(chan->vmm->svmm, chan->inst); - nvif_object_fini(&chan->nvsw); - nvif_object_fini(&chan->gart); - nvif_object_fini(&chan->vram); + nvif_object_dtor(&chan->nvsw); + nvif_object_dtor(&chan->gart); + nvif_object_dtor(&chan->vram); nvif_notify_fini(&chan->kill); - nvif_object_fini(&chan->user); - nvif_object_fini(&chan->push.ctxdma); + nvif_object_dtor(&chan->user); + nvif_object_dtor(&chan->push.ctxdma); nouveau_vma_del(&chan->push.vma); nouveau_bo_unmap(chan->push.buffer); if (chan->push.buffer && chan->push.buffer->pin_refcnt) @@ -214,8 +214,9 @@ nouveau_channel_prep(struct nouveau_drm *drm, struct nvif_device *device, } } - ret = nvif_object_init(&device->object, 0, NV_DMA_FROM_MEMORY, - &args, sizeof(args), &chan->push.ctxdma); + ret = nvif_object_ctor(&device->object, "abi16PushCtxDma", 0, + NV_DMA_FROM_MEMORY, &args, sizeof(args), + &chan->push.ctxdma); if (ret) { nouveau_channel_del(pchan); return ret; @@ -290,8 +291,8 @@ nouveau_channel_ind(struct nouveau_drm *drm, struct nvif_device *device, size = sizeof(args.nv50); } - ret = nvif_object_init(&device->object, 0, *oclass++, - &args, size, &chan->user); + ret = nvif_object_ctor(&device->object, "abi16ChanUser", 0, + *oclass++, &args, size, &chan->user); if (ret == 0) { if (chan->user.oclass >= VOLTA_CHANNEL_GPFIFO_A) { chan->chid = args.volta.chid; @@ -341,8 +342,9 @@ nouveau_channel_dma(struct nouveau_drm *drm, struct nvif_device *device, args.offset = chan->push.addr; do { - ret = nvif_object_init(&device->object, 0, *oclass++, - &args, sizeof(args), &chan->user); + ret = nvif_object_ctor(&device->object, "abi16ChanUser", 0, + *oclass++, &args, sizeof(args), + &chan->user); if (ret == 0) { chan->chid = args.chid; return ret; @@ -390,8 +392,9 @@ nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart) args.limit = device->info.ram_user - 1; } - ret = nvif_object_init(&chan->user, vram, NV_DMA_IN_MEMORY, - &args, sizeof(args), &chan->vram); + ret = nvif_object_ctor(&chan->user, "abi16ChanVramCtxDma", vram, + NV_DMA_IN_MEMORY, &args, sizeof(args), + &chan->vram); if (ret) return ret; @@ -414,8 +417,9 @@ nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart) args.limit = chan->vmm->vmm.limit - 1; } - ret = nvif_object_init(&chan->user, gart, NV_DMA_IN_MEMORY, - &args, sizeof(args), &chan->gart); + ret = nvif_object_ctor(&chan->user, "abi16ChanGartCtxDma", gart, + NV_DMA_IN_MEMORY, &args, sizeof(args), + &chan->gart); if (ret) return ret; } @@ -453,7 +457,7 @@ nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart) /* allocate software object class (used for fences on <= nv05) */ if (device->info.family < NV_DEVICE_INFO_V0_CELSIUS) { - ret = nvif_object_init(&chan->user, 0x006e, + ret = nvif_object_ctor(&chan->user, "abi16NvswFence", 0x006e, NVIF_CLASS_SW_NV04, NULL, 0, &chan->nvsw); if (ret) diff --git a/drivers/gpu/drm/nouveau/nouveau_debugfs.c b/drivers/gpu/drm/nouveau/nouveau_debugfs.c index 8f63cda3db17..c2bc05eb2e54 100644 --- a/drivers/gpu/drm/nouveau/nouveau_debugfs.c +++ b/drivers/gpu/drm/nouveau/nouveau_debugfs.c @@ -260,7 +260,7 @@ nouveau_debugfs_init(struct nouveau_drm *drm) if (!drm->debugfs) return -ENOMEM; - ret = nvif_object_init(&drm->client.device.object, 0, + ret = nvif_object_ctor(&drm->client.device.object, "debugfsCtrl", 0, NVIF_CLASS_CONTROL, NULL, 0, &drm->debugfs->ctrl); if (ret) @@ -273,7 +273,7 @@ void nouveau_debugfs_fini(struct nouveau_drm *drm) { if (drm->debugfs && drm->debugfs->ctrl.priv) - nvif_object_fini(&drm->debugfs->ctrl); + nvif_object_dtor(&drm->debugfs->ctrl); kfree(drm->debugfs); drm->debugfs = NULL; diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c index 0bf05d9139fe..97604bda4a60 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drm.c +++ b/drivers/gpu/drm/nouveau/nouveau_drm.c @@ -290,7 +290,7 @@ static void nouveau_accel_ce_fini(struct nouveau_drm *drm) { nouveau_channel_idle(drm->cechan); - nvif_object_fini(&drm->ttm.copy); + nvif_object_dtor(&drm->ttm.copy); nouveau_channel_del(&drm->cechan); } @@ -328,9 +328,9 @@ static void nouveau_accel_gr_fini(struct nouveau_drm *drm) { nouveau_channel_idle(drm->channel); - nvif_object_fini(&drm->ntfy); + nvif_object_dtor(&drm->ntfy); nvkm_gpuobj_del(&drm->notify); - nvif_object_fini(&drm->nvsw); + nvif_object_dtor(&drm->nvsw); nouveau_channel_del(&drm->channel); } @@ -363,9 +363,9 @@ nouveau_accel_gr_init(struct nouveau_drm *drm) * on TNT/TNT2 HW that lacks any kind of support in host. */ if (device->info.family < NV_DEVICE_INFO_V0_TESLA) { - ret = nvif_object_init(&drm->channel->user, NVDRM_NVSW, - nouveau_abi16_swclass(drm), NULL, 0, - &drm->nvsw); + ret = nvif_object_ctor(&drm->channel->user, "drmNvsw", + NVDRM_NVSW, nouveau_abi16_swclass(drm), + NULL, 0, &drm->nvsw); if (ret == 0) { ret = RING_SPACE(drm->channel, 2); if (ret == 0) { @@ -394,8 +394,8 @@ nouveau_accel_gr_init(struct nouveau_drm *drm) return; } - ret = nvif_object_init(&drm->channel->user, NvNotify0, - NV_DMA_IN_MEMORY, + ret = nvif_object_ctor(&drm->channel->user, "drmM2mfNtfy", + NvNotify0, NV_DMA_IN_MEMORY, &(struct nv_dma_v0) { .target = NV_DMA_V0_TARGET_VRAM, .access = NV_DMA_V0_ACCESS_RDWR, diff --git a/drivers/gpu/drm/nouveau/nouveau_fbcon.c b/drivers/gpu/drm/nouveau/nouveau_fbcon.c index 4a93641c33e1..9eb6085c8625 100644 --- a/drivers/gpu/drm/nouveau/nouveau_fbcon.c +++ b/drivers/gpu/drm/nouveau/nouveau_fbcon.c @@ -256,13 +256,13 @@ nouveau_fbcon_accel_fini(struct drm_device *dev) fbcon->helper.fbdev->flags |= FBINFO_HWACCEL_DISABLED; console_unlock(); nouveau_channel_idle(drm->channel); - nvif_object_fini(&fbcon->twod); - nvif_object_fini(&fbcon->blit); - nvif_object_fini(&fbcon->gdi); - nvif_object_fini(&fbcon->patt); - nvif_object_fini(&fbcon->rop); - nvif_object_fini(&fbcon->clip); - nvif_object_fini(&fbcon->surf2d); + nvif_object_dtor(&fbcon->twod); + nvif_object_dtor(&fbcon->blit); + nvif_object_dtor(&fbcon->gdi); + nvif_object_dtor(&fbcon->patt); + nvif_object_dtor(&fbcon->rop); + nvif_object_dtor(&fbcon->clip); + nvif_object_dtor(&fbcon->surf2d); } } diff --git a/drivers/gpu/drm/nouveau/nouveau_svm.c b/drivers/gpu/drm/nouveau/nouveau_svm.c index 6586d9d39874..c1e773964eca 100644 --- a/drivers/gpu/drm/nouveau/nouveau_svm.c +++ b/drivers/gpu/drm/nouveau/nouveau_svm.c @@ -905,7 +905,7 @@ nouveau_svm_fault_buffer_dtor(struct nouveau_svm *svm, int id) nouveau_svm_fault_buffer_fini(svm, id); nvif_notify_fini(&buffer->notify); - nvif_object_fini(&buffer->object); + nvif_object_dtor(&buffer->object); } static int @@ -919,8 +919,8 @@ nouveau_svm_fault_buffer_ctor(struct nouveau_svm *svm, s32 oclass, int id) buffer->id = id; - ret = nvif_object_init(device, 0, oclass, &args, sizeof(args), - &buffer->object); + ret = nvif_object_ctor(device, "svmFaultBuffer", 0, oclass, &args, + sizeof(args), &buffer->object); if (ret < 0) { SVM_ERR(svm, "Fault buffer allocation failed: %d", ret); return ret; diff --git a/drivers/gpu/drm/nouveau/nv04_fbcon.c b/drivers/gpu/drm/nouveau/nv04_fbcon.c index 01731dbeb3d8..936e11f526b6 100644 --- a/drivers/gpu/drm/nouveau/nv04_fbcon.c +++ b/drivers/gpu/drm/nouveau/nv04_fbcon.c @@ -168,33 +168,33 @@ nv04_fbcon_accel_init(struct fb_info *info) return -EINVAL; } - ret = nvif_object_init(&chan->user, 0x0062, + ret = nvif_object_ctor(&chan->user, "fbconCtxSurf2d", 0x0062, device->info.family >= NV_DEVICE_INFO_V0_CELSIUS ? 0x0062 : 0x0042, NULL, 0, &nfbdev->surf2d); if (ret) return ret; - ret = nvif_object_init(&chan->user, 0x0019, 0x0019, NULL, 0, - &nfbdev->clip); + ret = nvif_object_ctor(&chan->user, "fbconCtxClip", 0x0019, 0x0019, + NULL, 0, &nfbdev->clip); if (ret) return ret; - ret = nvif_object_init(&chan->user, 0x0043, 0x0043, NULL, 0, - &nfbdev->rop); + ret = nvif_object_ctor(&chan->user, "fbconCtxRop", 0x0043, 0x0043, + NULL, 0, &nfbdev->rop); if (ret) return ret; - ret = nvif_object_init(&chan->user, 0x0044, 0x0044, NULL, 0, - &nfbdev->patt); + ret = nvif_object_ctor(&chan->user, "fbconCtxPatt", 0x0044, 0x0044, + NULL, 0, &nfbdev->patt); if (ret) return ret; - ret = nvif_object_init(&chan->user, 0x004a, 0x004a, NULL, 0, - &nfbdev->gdi); + ret = nvif_object_ctor(&chan->user, "fbconGdiRectText", 0x004a, 0x004a, + NULL, 0, &nfbdev->gdi); if (ret) return ret; - ret = nvif_object_init(&chan->user, 0x005f, + ret = nvif_object_ctor(&chan->user, "fbconImageBlit", 0x005f, device->info.chipset >= 0x11 ? 0x009f : 0x005f, NULL, 0, &nfbdev->blit); if (ret) diff --git a/drivers/gpu/drm/nouveau/nv10_fence.c b/drivers/gpu/drm/nouveau/nv10_fence.c index 4476b712dc84..32d07f02b24c 100644 --- a/drivers/gpu/drm/nouveau/nv10_fence.c +++ b/drivers/gpu/drm/nouveau/nv10_fence.c @@ -58,7 +58,7 @@ nv10_fence_context_del(struct nouveau_channel *chan) { struct nv10_fence_chan *fctx = chan->fence; nouveau_fence_context_del(&fctx->base); - nvif_object_fini(&fctx->sema); + nvif_object_dtor(&fctx->sema); chan->fence = NULL; nouveau_fence_context_free(&fctx->base); } diff --git a/drivers/gpu/drm/nouveau/nv17_fence.c b/drivers/gpu/drm/nouveau/nv17_fence.c index 5d613d43b84d..c27d225699a5 100644 --- a/drivers/gpu/drm/nouveau/nv17_fence.c +++ b/drivers/gpu/drm/nouveau/nv17_fence.c @@ -90,7 +90,8 @@ nv17_fence_context_new(struct nouveau_channel *chan) fctx->base.read = nv10_fence_read; fctx->base.sync = nv17_fence_sync; - ret = nvif_object_init(&chan->user, NvSema, NV_DMA_FROM_MEMORY, + ret = nvif_object_ctor(&chan->user, "fenceCtxDma", NvSema, + NV_DMA_FROM_MEMORY, &(struct nv_dma_v0) { .target = NV_DMA_V0_TARGET_VRAM, .access = NV_DMA_V0_ACCESS_RDWR, diff --git a/drivers/gpu/drm/nouveau/nv50_fbcon.c b/drivers/gpu/drm/nouveau/nv50_fbcon.c index 47428f79ede8..31d8dca54f9f 100644 --- a/drivers/gpu/drm/nouveau/nv50_fbcon.c +++ b/drivers/gpu/drm/nouveau/nv50_fbcon.c @@ -181,8 +181,8 @@ nv50_fbcon_accel_init(struct fb_info *info) return -EINVAL; } - ret = nvif_object_init(&chan->user, 0x502d, 0x502d, NULL, 0, - &nfbdev->twod); + ret = nvif_object_ctor(&chan->user, "fbconTwoD", 0x502d, 0x502d, + NULL, 0, &nfbdev->twod); if (ret) return ret; diff --git a/drivers/gpu/drm/nouveau/nv50_fence.c b/drivers/gpu/drm/nouveau/nv50_fence.c index a00ecc3de053..ebb740686b44 100644 --- a/drivers/gpu/drm/nouveau/nv50_fence.c +++ b/drivers/gpu/drm/nouveau/nv50_fence.c @@ -51,7 +51,8 @@ nv50_fence_context_new(struct nouveau_channel *chan) fctx->base.read = nv10_fence_read; fctx->base.sync = nv17_fence_sync; - ret = nvif_object_init(&chan->user, NvSema, NV_DMA_IN_MEMORY, + ret = nvif_object_ctor(&chan->user, "fenceCtxDma", NvSema, + NV_DMA_IN_MEMORY, &(struct nv_dma_v0) { .target = NV_DMA_V0_TARGET_VRAM, .access = NV_DMA_V0_ACCESS_RDWR, diff --git a/drivers/gpu/drm/nouveau/nvc0_fbcon.c b/drivers/gpu/drm/nouveau/nvc0_fbcon.c index cb56163ed608..d6ce6323bf41 100644 --- a/drivers/gpu/drm/nouveau/nvc0_fbcon.c +++ b/drivers/gpu/drm/nouveau/nvc0_fbcon.c @@ -154,8 +154,8 @@ nvc0_fbcon_accel_init(struct fb_info *info) struct nouveau_channel *chan = drm->channel; int ret, format; - ret = nvif_object_init(&chan->user, 0x902d, 0x902d, NULL, 0, - &nfbdev->twod); + ret = nvif_object_ctor(&chan->user, "fbconTwoD", 0x902d, 0x902d, + NULL, 0, &nfbdev->twod); if (ret) return ret; diff --git a/drivers/gpu/drm/nouveau/nvif/client.c b/drivers/gpu/drm/nouveau/nvif/client.c index a36902c1c287..12644f811b3e 100644 --- a/drivers/gpu/drm/nouveau/nvif/client.c +++ b/drivers/gpu/drm/nouveau/nvif/client.c @@ -50,7 +50,7 @@ nvif_client_resume(struct nvif_client *client) void nvif_client_dtor(struct nvif_client *client) { - nvif_object_fini(&client->object); + nvif_object_dtor(&client->object); if (client->driver) { if (client->driver->fini) client->driver->fini(client->object.priv); @@ -70,8 +70,9 @@ nvif_client_ctor(struct nvif_client *parent, const char *name, u64 device, int ret; strncpy(args.name, name, sizeof(args.name)); - ret = nvif_object_init(parent != client ? &parent->object : NULL, - 0, NVIF_CLASS_CLIENT, &args, sizeof(args), + ret = nvif_object_ctor(parent != client ? &parent->object : NULL, + name ? name : "nvifClient", 0, + NVIF_CLASS_CLIENT, &args, sizeof(args), &client->object); if (ret) return ret; diff --git a/drivers/gpu/drm/nouveau/nvif/device.c b/drivers/gpu/drm/nouveau/nvif/device.c index 0e92db44bbc8..e801c4de2a98 100644 --- a/drivers/gpu/drm/nouveau/nvif/device.c +++ b/drivers/gpu/drm/nouveau/nvif/device.c @@ -44,15 +44,15 @@ nvif_device_fini(struct nvif_device *device) nvif_user_fini(device); kfree(device->runlist); device->runlist = NULL; - nvif_object_fini(&device->object); + nvif_object_dtor(&device->object); } int nvif_device_init(struct nvif_object *parent, u32 handle, s32 oclass, void *data, u32 size, struct nvif_device *device) { - int ret = nvif_object_init(parent, handle, oclass, data, size, - &device->object); + int ret = nvif_object_ctor(parent, "nvifDevice", handle, + oclass, data, size, &device->object); device->runlist = NULL; device->user.func = NULL; if (ret == 0) { diff --git a/drivers/gpu/drm/nouveau/nvif/disp.c b/drivers/gpu/drm/nouveau/nvif/disp.c index 61638b3b9d3d..122208adcd3c 100644 --- a/drivers/gpu/drm/nouveau/nvif/disp.c +++ b/drivers/gpu/drm/nouveau/nvif/disp.c @@ -27,7 +27,7 @@ void nvif_disp_dtor(struct nvif_disp *disp) { - nvif_object_fini(&disp->object); + nvif_object_dtor(&disp->object); } int @@ -56,6 +56,6 @@ nvif_disp_ctor(struct nvif_device *device, s32 oclass, struct nvif_disp *disp) if (cid < 0) return cid; - return nvif_object_init(&device->object, 0, disps[cid].oclass, - NULL, 0, &disp->object); + return nvif_object_ctor(&device->object, "nvifDisp", 0, + disps[cid].oclass, NULL, 0, &disp->object); } diff --git a/drivers/gpu/drm/nouveau/nvif/mem.c b/drivers/gpu/drm/nouveau/nvif/mem.c index b6ebb3b58673..5241d89d7c70 100644 --- a/drivers/gpu/drm/nouveau/nvif/mem.c +++ b/drivers/gpu/drm/nouveau/nvif/mem.c @@ -40,7 +40,7 @@ nvif_mem_init_map(struct nvif_mmu *mmu, u8 type, u64 size, struct nvif_mem *mem) void nvif_mem_fini(struct nvif_mem *mem) { - nvif_object_fini(&mem->object); + nvif_object_dtor(&mem->object); } int @@ -67,7 +67,7 @@ nvif_mem_init_type(struct nvif_mmu *mmu, s32 oclass, int type, u8 page, args->size = size; memcpy(args->data, argv, argc); - ret = nvif_object_init(&mmu->object, 0, oclass, args, + ret = nvif_object_ctor(&mmu->object, "nvifMem", 0, oclass, args, sizeof(*args) + argc, &mem->object); if (ret == 0) { mem->type = mmu->type[type].type; diff --git a/drivers/gpu/drm/nouveau/nvif/mmu.c b/drivers/gpu/drm/nouveau/nvif/mmu.c index 47efc408efa6..aa6ec915d603 100644 --- a/drivers/gpu/drm/nouveau/nvif/mmu.c +++ b/drivers/gpu/drm/nouveau/nvif/mmu.c @@ -30,7 +30,7 @@ nvif_mmu_fini(struct nvif_mmu *mmu) kfree(mmu->kind); kfree(mmu->type); kfree(mmu->heap); - nvif_object_fini(&mmu->object); + nvif_object_dtor(&mmu->object); } int @@ -50,8 +50,8 @@ nvif_mmu_init(struct nvif_object *parent, s32 oclass, struct nvif_mmu *mmu) mmu->type = NULL; mmu->kind = NULL; - ret = nvif_object_init(parent, 0, oclass, &args, sizeof(args), - &mmu->object); + ret = nvif_object_ctor(parent, "nvifMmu", 0, oclass, &args, + sizeof(args), &mmu->object); if (ret) goto done; diff --git a/drivers/gpu/drm/nouveau/nvif/object.c b/drivers/gpu/drm/nouveau/nvif/object.c index ef3f62840e83..9f3348327244 100644 --- a/drivers/gpu/drm/nouveau/nvif/object.c +++ b/drivers/gpu/drm/nouveau/nvif/object.c @@ -242,7 +242,7 @@ nvif_object_map(struct nvif_object *object, void *argv, u32 argc) } void -nvif_object_fini(struct nvif_object *object) +nvif_object_dtor(struct nvif_object *object) { struct { struct nvif_ioctl_v0 ioctl; @@ -260,8 +260,8 @@ nvif_object_fini(struct nvif_object *object) } int -nvif_object_init(struct nvif_object *parent, u32 handle, s32 oclass, - void *data, u32 size, struct nvif_object *object) +nvif_object_ctor(struct nvif_object *parent, const char *name, u32 handle, + s32 oclass, void *data, u32 size, struct nvif_object *object) { struct { struct nvif_ioctl_v0 ioctl; @@ -270,6 +270,7 @@ nvif_object_init(struct nvif_object *parent, u32 handle, s32 oclass, int ret = 0; object->client = NULL; + object->name = name ? name : "nvifObject"; object->handle = handle; object->oclass = oclass; object->map.ptr = NULL; @@ -277,7 +278,7 @@ nvif_object_init(struct nvif_object *parent, u32 handle, s32 oclass, if (parent) { if (!(args = kmalloc(sizeof(*args) + size, GFP_KERNEL))) { - nvif_object_fini(object); + nvif_object_dtor(object); return -ENOMEM; } @@ -300,6 +301,6 @@ nvif_object_init(struct nvif_object *parent, u32 handle, s32 oclass, } if (ret) - nvif_object_fini(object); + nvif_object_dtor(object); return ret; } diff --git a/drivers/gpu/drm/nouveau/nvif/user.c b/drivers/gpu/drm/nouveau/nvif/user.c index 10da3cdca647..490fd18d02c0 100644 --- a/drivers/gpu/drm/nouveau/nvif/user.c +++ b/drivers/gpu/drm/nouveau/nvif/user.c @@ -28,7 +28,7 @@ void nvif_user_fini(struct nvif_device *device) { if (device->user.func) { - nvif_object_fini(&device->user.object); + nvif_object_dtor(&device->user.object); device->user.func = NULL; } } @@ -53,7 +53,8 @@ nvif_user_init(struct nvif_device *device) if (cid < 0) return cid; - ret = nvif_object_init(&device->object, 0, users[cid].oclass, NULL, 0, + ret = nvif_object_ctor(&device->object, "nvifUsermode", + 0, users[cid].oclass, NULL, 0, &device->user.object); if (ret) return ret; diff --git a/drivers/gpu/drm/nouveau/nvif/vmm.c b/drivers/gpu/drm/nouveau/nvif/vmm.c index 11487c00b909..dc82e5515fc5 100644 --- a/drivers/gpu/drm/nouveau/nvif/vmm.c +++ b/drivers/gpu/drm/nouveau/nvif/vmm.c @@ -108,7 +108,7 @@ void nvif_vmm_fini(struct nvif_vmm *vmm) { kfree(vmm->page); - nvif_object_fini(&vmm->object); + nvif_object_dtor(&vmm->object); } int @@ -130,7 +130,7 @@ nvif_vmm_init(struct nvif_mmu *mmu, s32 oclass, bool managed, u64 addr, args->size = size; memcpy(args->data, argv, argc); - ret = nvif_object_init(&mmu->object, 0, oclass, args, argn, + ret = nvif_object_ctor(&mmu->object, "nvifVmm", 0, oclass, args, argn, &vmm->object); if (ret) goto done; From bd21080eb6ca476cd64afbc3f8e5228a83080ddb Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 30 Mar 2020 13:49:05 +1000 Subject: [PATCH 030/145] drm/nouveau/nvif: give every device object a human-readable identifier Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/include/nvif/device.h | 6 +++--- drivers/gpu/drm/nouveau/nouveau_abi16.c | 6 +++--- drivers/gpu/drm/nouveau/nouveau_drm.c | 4 ++-- drivers/gpu/drm/nouveau/nvif/device.c | 8 ++++---- 4 files changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/nouveau/include/nvif/device.h b/drivers/gpu/drm/nouveau/include/nvif/device.h index c2a572c67a76..b0e59800a320 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/device.h +++ b/drivers/gpu/drm/nouveau/include/nvif/device.h @@ -18,9 +18,9 @@ struct nvif_device { struct nvif_user user; }; -int nvif_device_init(struct nvif_object *, u32 handle, s32 oclass, void *, u32, - struct nvif_device *); -void nvif_device_fini(struct nvif_device *); +int nvif_device_ctor(struct nvif_object *, const char *name, u32 handle, + s32 oclass, void *, u32, struct nvif_device *); +void nvif_device_dtor(struct nvif_device *); u64 nvif_device_time(struct nvif_device *); /*XXX*/ diff --git a/drivers/gpu/drm/nouveau/nouveau_abi16.c b/drivers/gpu/drm/nouveau/nouveau_abi16.c index ace302dc3369..21537ca1dd39 100644 --- a/drivers/gpu/drm/nouveau/nouveau_abi16.c +++ b/drivers/gpu/drm/nouveau/nouveau_abi16.c @@ -55,8 +55,8 @@ nouveau_abi16(struct drm_file *file_priv) * device (ie. the one that belongs to the fd it * opened) */ - if (nvif_device_init(&cli->base.object, 0, NV_DEVICE, - &args, sizeof(args), + if (nvif_device_ctor(&cli->base.object, "abi16Device", + 0, NV_DEVICE, &args, sizeof(args), &abi16->device) == 0) return cli->abi16; @@ -167,7 +167,7 @@ nouveau_abi16_fini(struct nouveau_abi16 *abi16) } /* destroy the device object */ - nvif_device_fini(&abi16->device); + nvif_device_dtor(&abi16->device); kfree(cli->abi16); cli->abi16 = NULL; diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c index 97604bda4a60..ed8fbc60736f 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drm.c +++ b/drivers/gpu/drm/nouveau/nouveau_drm.c @@ -179,7 +179,7 @@ nouveau_cli_fini(struct nouveau_cli *cli) nouveau_vmm_fini(&cli->svm); nouveau_vmm_fini(&cli->vmm); nvif_mmu_fini(&cli->mmu); - nvif_device_fini(&cli->device); + nvif_device_dtor(&cli->device); mutex_lock(&cli->drm->master.lock); nvif_client_dtor(&cli->base); mutex_unlock(&cli->drm->master.lock); @@ -238,7 +238,7 @@ nouveau_cli_init(struct nouveau_drm *drm, const char *sname, goto done; } - ret = nvif_device_init(&cli->base.object, 0, NV_DEVICE, + ret = nvif_device_ctor(&cli->base.object, "drmDevice", 0, NV_DEVICE, &(struct nv_device_v0) { .device = ~0, }, sizeof(struct nv_device_v0), diff --git a/drivers/gpu/drm/nouveau/nvif/device.c b/drivers/gpu/drm/nouveau/nvif/device.c index e801c4de2a98..a3aebf865931 100644 --- a/drivers/gpu/drm/nouveau/nvif/device.c +++ b/drivers/gpu/drm/nouveau/nvif/device.c @@ -39,7 +39,7 @@ nvif_device_time(struct nvif_device *device) } void -nvif_device_fini(struct nvif_device *device) +nvif_device_dtor(struct nvif_device *device) { nvif_user_fini(device); kfree(device->runlist); @@ -48,10 +48,10 @@ nvif_device_fini(struct nvif_device *device) } int -nvif_device_init(struct nvif_object *parent, u32 handle, s32 oclass, - void *data, u32 size, struct nvif_device *device) +nvif_device_ctor(struct nvif_object *parent, const char *name, u32 handle, + s32 oclass, void *data, u32 size, struct nvif_device *device) { - int ret = nvif_object_ctor(parent, "nvifDevice", handle, + int ret = nvif_object_ctor(parent, name ? name : "nvifDevice", handle, oclass, data, size, &device->object); device->runlist = NULL; device->user.func = NULL; From b495396cc9ccf579e5c7bba47137c0f867ddf580 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 30 Mar 2020 13:51:38 +1000 Subject: [PATCH 031/145] drm/nouveau/nvif: give every mmu object a human-readable identifier Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/include/nvif/mmu.h | 5 +++-- drivers/gpu/drm/nouveau/nouveau_drm.c | 5 +++-- drivers/gpu/drm/nouveau/nvif/mmu.c | 11 ++++++----- 3 files changed, 12 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/nouveau/include/nvif/mmu.h b/drivers/gpu/drm/nouveau/include/nvif/mmu.h index cec1e88a0a05..2035ef1d35f5 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/mmu.h +++ b/drivers/gpu/drm/nouveau/include/nvif/mmu.h @@ -31,8 +31,9 @@ struct nvif_mmu { u8 *kind; }; -int nvif_mmu_init(struct nvif_object *, s32 oclass, struct nvif_mmu *); -void nvif_mmu_fini(struct nvif_mmu *); +int nvif_mmu_ctor(struct nvif_object *, const char *name, s32 oclass, + struct nvif_mmu *); +void nvif_mmu_dtor(struct nvif_mmu *); static inline bool nvif_mmu_kind_valid(struct nvif_mmu *mmu, u8 kind) diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c index ed8fbc60736f..bfb8d4c1a2d8 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drm.c +++ b/drivers/gpu/drm/nouveau/nouveau_drm.c @@ -178,7 +178,7 @@ nouveau_cli_fini(struct nouveau_cli *cli) usif_client_fini(cli); nouveau_vmm_fini(&cli->svm); nouveau_vmm_fini(&cli->vmm); - nvif_mmu_fini(&cli->mmu); + nvif_mmu_dtor(&cli->mmu); nvif_device_dtor(&cli->device); mutex_lock(&cli->drm->master.lock); nvif_client_dtor(&cli->base); @@ -254,7 +254,8 @@ nouveau_cli_init(struct nouveau_drm *drm, const char *sname, goto done; } - ret = nvif_mmu_init(&cli->device.object, mmus[ret].oclass, &cli->mmu); + ret = nvif_mmu_ctor(&cli->device.object, "drmMmu", mmus[ret].oclass, + &cli->mmu); if (ret) { NV_PRINTK(err, cli, "MMU allocation failed: %d\n", ret); goto done; diff --git a/drivers/gpu/drm/nouveau/nvif/mmu.c b/drivers/gpu/drm/nouveau/nvif/mmu.c index aa6ec915d603..3709cbbc19a1 100644 --- a/drivers/gpu/drm/nouveau/nvif/mmu.c +++ b/drivers/gpu/drm/nouveau/nvif/mmu.c @@ -25,7 +25,7 @@ #include void -nvif_mmu_fini(struct nvif_mmu *mmu) +nvif_mmu_dtor(struct nvif_mmu *mmu) { kfree(mmu->kind); kfree(mmu->type); @@ -34,7 +34,8 @@ nvif_mmu_fini(struct nvif_mmu *mmu) } int -nvif_mmu_init(struct nvif_object *parent, s32 oclass, struct nvif_mmu *mmu) +nvif_mmu_ctor(struct nvif_object *parent, const char *name, s32 oclass, + struct nvif_mmu *mmu) { static const struct nvif_mclass mems[] = { { NVIF_CLASS_MEM_GF100, -1 }, @@ -50,8 +51,8 @@ nvif_mmu_init(struct nvif_object *parent, s32 oclass, struct nvif_mmu *mmu) mmu->type = NULL; mmu->kind = NULL; - ret = nvif_object_ctor(parent, "nvifMmu", 0, oclass, &args, - sizeof(args), &mmu->object); + ret = nvif_object_ctor(parent, name ? name : "nvifMmu", 0, oclass, + &args, sizeof(args), &mmu->object); if (ret) goto done; @@ -127,6 +128,6 @@ nvif_mmu_init(struct nvif_object *parent, s32 oclass, struct nvif_mmu *mmu) done: if (ret) - nvif_mmu_fini(mmu); + nvif_mmu_dtor(mmu); return ret; } From e79c9a0ba5e7e0905d191f5d75e5ead50776c64a Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 30 Mar 2020 13:56:55 +1000 Subject: [PATCH 032/145] drm/nouveau/nvif: give every mem object a human-readable identifier Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/crc.c | 6 ++--- drivers/gpu/drm/nouveau/dispnv50/disp.c | 5 ++-- drivers/gpu/drm/nouveau/dispnv50/lut.c | 6 ++--- drivers/gpu/drm/nouveau/include/nvif/mem.h | 14 ++++++----- drivers/gpu/drm/nouveau/nouveau_mem.c | 8 +++---- drivers/gpu/drm/nouveau/nvif/mem.c | 28 ++++++++++++---------- 6 files changed, 36 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/crc.c b/drivers/gpu/drm/nouveau/dispnv50/crc.c index 5fac476fe130..4a43cca96328 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/crc.c +++ b/drivers/gpu/drm/nouveau/dispnv50/crc.c @@ -510,7 +510,7 @@ nv50_crc_ctx_init(struct nv50_head *head, struct nvif_mmu *mmu, struct nv50_core *core = nv50_disp(head->base.base.dev)->core; int ret; - ret = nvif_mem_init_map(mmu, NVIF_MEM_VRAM, len, &ctx->mem); + ret = nvif_mem_ctor_map(mmu, "kmsCrcNtfy", NVIF_MEM_VRAM, len, &ctx->mem); if (ret) return ret; @@ -531,7 +531,7 @@ nv50_crc_ctx_init(struct nv50_head *head, struct nvif_mmu *mmu, return 0; fail_fini: - nvif_mem_fini(&ctx->mem); + nvif_mem_dtor(&ctx->mem); return ret; } @@ -539,7 +539,7 @@ static inline void nv50_crc_ctx_fini(struct nv50_crc_notifier_ctx *ctx) { nvif_object_dtor(&ctx->ntfy); - nvif_mem_fini(&ctx->mem); + nvif_mem_dtor(&ctx->mem); } int nv50_crc_set_source(struct drm_crtc *crtc, const char *source_str) diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c b/drivers/gpu/drm/nouveau/dispnv50/disp.c index 5bc40b5e6325..f25daf4739cb 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/disp.c +++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c @@ -113,7 +113,7 @@ nv50_dmac_destroy(struct nv50_dmac *dmac) nv50_chan_destroy(&dmac->base); - nvif_mem_fini(&dmac->push); + nvif_mem_dtor(&dmac->push); } int @@ -140,7 +140,8 @@ nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp, if (device->info.family == NV_DEVICE_INFO_V0_PASCAL) type |= NVIF_MEM_VRAM; - ret = nvif_mem_init_map(&cli->mmu, type, 0x1000, &dmac->push); + ret = nvif_mem_ctor_map(&cli->mmu, "kmsChanPush", type, 0x1000, + &dmac->push); if (ret) return ret; diff --git a/drivers/gpu/drm/nouveau/dispnv50/lut.c b/drivers/gpu/drm/nouveau/dispnv50/lut.c index 4e95ca5604ab..6b2ad1e6eab9 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/lut.c +++ b/drivers/gpu/drm/nouveau/dispnv50/lut.c @@ -60,7 +60,7 @@ nv50_lut_fini(struct nv50_lut *lut) { int i; for (i = 0; i < ARRAY_SIZE(lut->mem); i++) - nvif_mem_fini(&lut->mem[i]); + nvif_mem_dtor(&lut->mem[i]); } int @@ -70,8 +70,8 @@ nv50_lut_init(struct nv50_disp *disp, struct nvif_mmu *mmu, const u32 size = disp->disp->object.oclass < GF110_DISP ? 257 : 1025; int i; for (i = 0; i < ARRAY_SIZE(lut->mem); i++) { - int ret = nvif_mem_init_map(mmu, NVIF_MEM_VRAM, size * 8, - &lut->mem[i]); + int ret = nvif_mem_ctor_map(mmu, "kmsLut", NVIF_MEM_VRAM, + size * 8, &lut->mem[i]); if (ret) return ret; } diff --git a/drivers/gpu/drm/nouveau/include/nvif/mem.h b/drivers/gpu/drm/nouveau/include/nvif/mem.h index 80ee4ab0f016..9e1071dd56a0 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/mem.h +++ b/drivers/gpu/drm/nouveau/include/nvif/mem.h @@ -10,11 +10,13 @@ struct nvif_mem { u64 size; }; -int nvif_mem_init_type(struct nvif_mmu *mmu, s32 oclass, int type, u8 page, - u64 size, void *argv, u32 argc, struct nvif_mem *); -int nvif_mem_init(struct nvif_mmu *mmu, s32 oclass, u8 type, u8 page, - u64 size, void *argv, u32 argc, struct nvif_mem *); -void nvif_mem_fini(struct nvif_mem *); +int nvif_mem_ctor_type(struct nvif_mmu *mmu, const char *name, s32 oclass, + int type, u8 page, u64 size, void *argv, u32 argc, + struct nvif_mem *); +int nvif_mem_ctor(struct nvif_mmu *mmu, const char *name, s32 oclass, u8 type, + u8 page, u64 size, void *argv, u32 argc, struct nvif_mem *); +void nvif_mem_dtor(struct nvif_mem *); -int nvif_mem_init_map(struct nvif_mmu *, u8 type, u64 size, struct nvif_mem *); +int nvif_mem_ctor_map(struct nvif_mmu *, const char *name, u8 type, u64 size, + struct nvif_mem *); #endif diff --git a/drivers/gpu/drm/nouveau/nouveau_mem.c b/drivers/gpu/drm/nouveau/nouveau_mem.c index c002f8968507..b1bb542d3115 100644 --- a/drivers/gpu/drm/nouveau/nouveau_mem.c +++ b/drivers/gpu/drm/nouveau/nouveau_mem.c @@ -87,7 +87,7 @@ nouveau_mem_fini(struct nouveau_mem *mem) nvif_vmm_put(&mem->cli->drm->client.vmm.vmm, &mem->vma[1]); nvif_vmm_put(&mem->cli->drm->client.vmm.vmm, &mem->vma[0]); mutex_lock(&mem->cli->drm->master.lock); - nvif_mem_fini(&mem->mem); + nvif_mem_dtor(&mem->mem); mutex_unlock(&mem->cli->drm->master.lock); } @@ -121,7 +121,7 @@ nouveau_mem_host(struct ttm_mem_reg *reg, struct ttm_dma_tt *tt) mutex_lock(&drm->master.lock); cli->base.super = true; - ret = nvif_mem_init_type(mmu, cli->mem->oclass, type, PAGE_SHIFT, + ret = nvif_mem_ctor_type(mmu, "ttmHostMem", cli->mem->oclass, type, PAGE_SHIFT, reg->num_pages << PAGE_SHIFT, &args, sizeof(args), &mem->mem); cli->base.super = super; @@ -144,7 +144,7 @@ nouveau_mem_vram(struct ttm_mem_reg *reg, bool contig, u8 page) cli->base.super = true; switch (cli->mem->oclass) { case NVIF_CLASS_MEM_GF100: - ret = nvif_mem_init_type(mmu, cli->mem->oclass, + ret = nvif_mem_ctor_type(mmu, "ttmVram", cli->mem->oclass, drm->ttm.type_vram, page, size, &(struct gf100_mem_v0) { .contig = contig, @@ -152,7 +152,7 @@ nouveau_mem_vram(struct ttm_mem_reg *reg, bool contig, u8 page) &mem->mem); break; case NVIF_CLASS_MEM_NV50: - ret = nvif_mem_init_type(mmu, cli->mem->oclass, + ret = nvif_mem_ctor_type(mmu, "ttmVram", cli->mem->oclass, drm->ttm.type_vram, page, size, &(struct nv50_mem_v0) { .bankswz = mmu->kind[mem->kind] == 2, diff --git a/drivers/gpu/drm/nouveau/nvif/mem.c b/drivers/gpu/drm/nouveau/nvif/mem.c index 5241d89d7c70..0e1b7b4c2e91 100644 --- a/drivers/gpu/drm/nouveau/nvif/mem.c +++ b/drivers/gpu/drm/nouveau/nvif/mem.c @@ -25,27 +25,29 @@ #include int -nvif_mem_init_map(struct nvif_mmu *mmu, u8 type, u64 size, struct nvif_mem *mem) +nvif_mem_ctor_map(struct nvif_mmu *mmu, const char *name, u8 type, u64 size, + struct nvif_mem *mem) { - int ret = nvif_mem_init(mmu, mmu->mem, NVIF_MEM_MAPPABLE | type, 0, - size, NULL, 0, mem); + int ret = nvif_mem_ctor(mmu, name, mmu->mem, NVIF_MEM_MAPPABLE | type, + 0, size, NULL, 0, mem); if (ret == 0) { ret = nvif_object_map(&mem->object, NULL, 0); if (ret) - nvif_mem_fini(mem); + nvif_mem_dtor(mem); } return ret; } void -nvif_mem_fini(struct nvif_mem *mem) +nvif_mem_dtor(struct nvif_mem *mem) { nvif_object_dtor(&mem->object); } int -nvif_mem_init_type(struct nvif_mmu *mmu, s32 oclass, int type, u8 page, - u64 size, void *argv, u32 argc, struct nvif_mem *mem) +nvif_mem_ctor_type(struct nvif_mmu *mmu, const char *name, s32 oclass, + int type, u8 page, u64 size, void *argv, u32 argc, + struct nvif_mem *mem) { struct nvif_mem_v0 *args; u8 stack[128]; @@ -67,8 +69,8 @@ nvif_mem_init_type(struct nvif_mmu *mmu, s32 oclass, int type, u8 page, args->size = size; memcpy(args->data, argv, argc); - ret = nvif_object_ctor(&mmu->object, "nvifMem", 0, oclass, args, - sizeof(*args) + argc, &mem->object); + ret = nvif_object_ctor(&mmu->object, name ? name : "nvifMem", 0, oclass, + args, sizeof(*args) + argc, &mem->object); if (ret == 0) { mem->type = mmu->type[type].type; mem->page = args->page; @@ -83,8 +85,8 @@ nvif_mem_init_type(struct nvif_mmu *mmu, s32 oclass, int type, u8 page, } int -nvif_mem_init(struct nvif_mmu *mmu, s32 oclass, u8 type, u8 page, - u64 size, void *argv, u32 argc, struct nvif_mem *mem) +nvif_mem_ctor(struct nvif_mmu *mmu, const char *name, s32 oclass, u8 type, + u8 page, u64 size, void *argv, u32 argc, struct nvif_mem *mem) { int ret = -EINVAL, i; @@ -92,8 +94,8 @@ nvif_mem_init(struct nvif_mmu *mmu, s32 oclass, u8 type, u8 page, for (i = 0; ret && i < mmu->type_nr; i++) { if ((mmu->type[i].type & type) == type) { - ret = nvif_mem_init_type(mmu, oclass, i, page, size, - argv, argc, mem); + ret = nvif_mem_ctor_type(mmu, name, oclass, i, page, + size, argv, argc, mem); } } From 45faf3d7b64ff0abfce735d4b2cd2f2edd357485 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 30 Mar 2020 13:59:39 +1000 Subject: [PATCH 033/145] drm/nouveau/nvif: give every vmm object a human-readable identifier Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/include/nvif/vmm.h | 6 +++--- drivers/gpu/drm/nouveau/nouveau_svm.c | 3 ++- drivers/gpu/drm/nouveau/nouveau_vmm.c | 6 +++--- drivers/gpu/drm/nouveau/nvif/vmm.c | 12 ++++++------ 4 files changed, 14 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/nouveau/include/nvif/vmm.h b/drivers/gpu/drm/nouveau/include/nvif/vmm.h index 79bf85d2f43a..a2ee92201ace 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/vmm.h +++ b/drivers/gpu/drm/nouveau/include/nvif/vmm.h @@ -30,9 +30,9 @@ struct nvif_vmm { int page_nr; }; -int nvif_vmm_init(struct nvif_mmu *, s32 oclass, bool managed, u64 addr, - u64 size, void *argv, u32 argc, struct nvif_vmm *); -void nvif_vmm_fini(struct nvif_vmm *); +int nvif_vmm_ctor(struct nvif_mmu *, const char *name, s32 oclass, bool managed, + u64 addr, u64 size, void *argv, u32 argc, struct nvif_vmm *); +void nvif_vmm_dtor(struct nvif_vmm *); int nvif_vmm_get(struct nvif_vmm *, enum nvif_vmm_get, bool sparse, u8 page, u8 align, u64 size, struct nvif_vma *); void nvif_vmm_put(struct nvif_vmm *, struct nvif_vma *); diff --git a/drivers/gpu/drm/nouveau/nouveau_svm.c b/drivers/gpu/drm/nouveau/nouveau_svm.c index c1e773964eca..6f65fa73e1cd 100644 --- a/drivers/gpu/drm/nouveau/nouveau_svm.c +++ b/drivers/gpu/drm/nouveau/nouveau_svm.c @@ -347,7 +347,8 @@ nouveau_svmm_init(struct drm_device *dev, void *data, * All future channel/memory allocations will make use of this * VMM instead of the standard one. */ - ret = nvif_vmm_init(&cli->mmu, cli->vmm.vmm.object.oclass, true, + ret = nvif_vmm_ctor(&cli->mmu, "svmVmm", + cli->vmm.vmm.object.oclass, true, args->unmanaged_addr, args->unmanaged_size, &(struct gp100_vmm_v0) { .fault_replay = true, diff --git a/drivers/gpu/drm/nouveau/nouveau_vmm.c b/drivers/gpu/drm/nouveau/nouveau_vmm.c index b28c7dc13ad6..a49e88129c92 100644 --- a/drivers/gpu/drm/nouveau/nouveau_vmm.c +++ b/drivers/gpu/drm/nouveau/nouveau_vmm.c @@ -121,15 +121,15 @@ void nouveau_vmm_fini(struct nouveau_vmm *vmm) { nouveau_svmm_fini(&vmm->svmm); - nvif_vmm_fini(&vmm->vmm); + nvif_vmm_dtor(&vmm->vmm); vmm->cli = NULL; } int nouveau_vmm_init(struct nouveau_cli *cli, s32 oclass, struct nouveau_vmm *vmm) { - int ret = nvif_vmm_init(&cli->mmu, oclass, false, PAGE_SIZE, 0, NULL, 0, - &vmm->vmm); + int ret = nvif_vmm_ctor(&cli->mmu, "drmVmm", oclass, false, PAGE_SIZE, + 0, NULL, 0, &vmm->vmm); if (ret) return ret; diff --git a/drivers/gpu/drm/nouveau/nvif/vmm.c b/drivers/gpu/drm/nouveau/nvif/vmm.c index dc82e5515fc5..6053d6dc2184 100644 --- a/drivers/gpu/drm/nouveau/nvif/vmm.c +++ b/drivers/gpu/drm/nouveau/nvif/vmm.c @@ -105,15 +105,15 @@ nvif_vmm_get(struct nvif_vmm *vmm, enum nvif_vmm_get type, bool sparse, } void -nvif_vmm_fini(struct nvif_vmm *vmm) +nvif_vmm_dtor(struct nvif_vmm *vmm) { kfree(vmm->page); nvif_object_dtor(&vmm->object); } int -nvif_vmm_init(struct nvif_mmu *mmu, s32 oclass, bool managed, u64 addr, - u64 size, void *argv, u32 argc, struct nvif_vmm *vmm) +nvif_vmm_ctor(struct nvif_mmu *mmu, const char *name, s32 oclass, bool managed, + u64 addr, u64 size, void *argv, u32 argc, struct nvif_vmm *vmm) { struct nvif_vmm_v0 *args; u32 argn = sizeof(*args) + argc; @@ -130,8 +130,8 @@ nvif_vmm_init(struct nvif_mmu *mmu, s32 oclass, bool managed, u64 addr, args->size = size; memcpy(args->data, argv, argc); - ret = nvif_object_ctor(&mmu->object, "nvifVmm", 0, oclass, args, argn, - &vmm->object); + ret = nvif_object_ctor(&mmu->object, name ? name : "nvifVmm", 0, + oclass, args, argn, &vmm->object); if (ret) goto done; @@ -163,7 +163,7 @@ nvif_vmm_init(struct nvif_mmu *mmu, s32 oclass, bool managed, u64 addr, done: if (ret) - nvif_vmm_fini(vmm); + nvif_vmm_dtor(vmm); kfree(args); return ret; } From 64a0f59ab12467ace3e86b98ca47255827049d02 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 30 Mar 2020 14:01:57 +1000 Subject: [PATCH 034/145] drm/nouveau/nvif: give every usermode object a human-readable identifier Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/include/nvif/user.h | 4 ++-- drivers/gpu/drm/nouveau/nouveau_drm.c | 2 +- drivers/gpu/drm/nouveau/nvif/device.c | 2 +- drivers/gpu/drm/nouveau/nvif/user.c | 6 +++--- 4 files changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/nouveau/include/nvif/user.h b/drivers/gpu/drm/nouveau/include/nvif/user.h index 6825574d93c2..146986a9fe53 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/user.h +++ b/drivers/gpu/drm/nouveau/include/nvif/user.h @@ -13,8 +13,8 @@ struct nvif_user_func { u64 (*time)(struct nvif_user *); }; -int nvif_user_init(struct nvif_device *); -void nvif_user_fini(struct nvif_device *); +int nvif_user_ctor(struct nvif_device *, const char *name); +void nvif_user_dtor(struct nvif_device *); extern const struct nvif_user_func nvif_userc361; #endif diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c index bfb8d4c1a2d8..6f24a215ac74 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drm.c +++ b/drivers/gpu/drm/nouveau/nouveau_drm.c @@ -483,7 +483,7 @@ nouveau_accel_init(struct nouveau_drm *drm) /* Volta requires access to a doorbell register for kickoff. */ if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_VOLTA) { - ret = nvif_user_init(device); + ret = nvif_user_ctor(device, "drmUsermode"); if (ret) return; } diff --git a/drivers/gpu/drm/nouveau/nvif/device.c b/drivers/gpu/drm/nouveau/nvif/device.c index a3aebf865931..8c3d883f3313 100644 --- a/drivers/gpu/drm/nouveau/nvif/device.c +++ b/drivers/gpu/drm/nouveau/nvif/device.c @@ -41,7 +41,7 @@ nvif_device_time(struct nvif_device *device) void nvif_device_dtor(struct nvif_device *device) { - nvif_user_fini(device); + nvif_user_dtor(device); kfree(device->runlist); device->runlist = NULL; nvif_object_dtor(&device->object); diff --git a/drivers/gpu/drm/nouveau/nvif/user.c b/drivers/gpu/drm/nouveau/nvif/user.c index 490fd18d02c0..d89f5b67b304 100644 --- a/drivers/gpu/drm/nouveau/nvif/user.c +++ b/drivers/gpu/drm/nouveau/nvif/user.c @@ -25,7 +25,7 @@ #include void -nvif_user_fini(struct nvif_device *device) +nvif_user_dtor(struct nvif_device *device) { if (device->user.func) { nvif_object_dtor(&device->user.object); @@ -34,7 +34,7 @@ nvif_user_fini(struct nvif_device *device) } int -nvif_user_init(struct nvif_device *device) +nvif_user_ctor(struct nvif_device *device, const char *name) { struct { s32 oclass; @@ -53,7 +53,7 @@ nvif_user_init(struct nvif_device *device) if (cid < 0) return cid; - ret = nvif_object_ctor(&device->object, "nvifUsermode", + ret = nvif_object_ctor(&device->object, name ? name : "nvifUsermode", 0, users[cid].oclass, NULL, 0, &device->user.object); if (ret) From 54d44bfc56308d105b0da37392d8398bdc9d4745 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 30 Mar 2020 14:03:20 +1000 Subject: [PATCH 035/145] drm/nouveau/nvif: give every disp object a human-readable identifier Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/include/nvif/disp.h | 3 ++- drivers/gpu/drm/nouveau/nouveau_display.c | 3 ++- drivers/gpu/drm/nouveau/nvif/disp.c | 5 +++-- 3 files changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/nouveau/include/nvif/disp.h b/drivers/gpu/drm/nouveau/include/nvif/disp.h index 7c0eda375c01..07ac544f282f 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/disp.h +++ b/drivers/gpu/drm/nouveau/include/nvif/disp.h @@ -7,6 +7,7 @@ struct nvif_disp { struct nvif_object object; }; -int nvif_disp_ctor(struct nvif_device *, s32 oclass, struct nvif_disp *); +int nvif_disp_ctor(struct nvif_device *, const char *name, s32 oclass, + struct nvif_disp *); void nvif_disp_dtor(struct nvif_disp *); #endif diff --git a/drivers/gpu/drm/nouveau/nouveau_display.c b/drivers/gpu/drm/nouveau/nouveau_display.c index 657554cf011e..63c58f12458c 100644 --- a/drivers/gpu/drm/nouveau/nouveau_display.c +++ b/drivers/gpu/drm/nouveau/nouveau_display.c @@ -635,7 +635,8 @@ nouveau_display_create(struct drm_device *dev) drm_kms_helper_poll_disable(dev); if (nouveau_modeset != 2 && drm->vbios.dcb.entries) { - ret = nvif_disp_ctor(&drm->client.device, 0, &disp->disp); + ret = nvif_disp_ctor(&drm->client.device, "kmsDisp", 0, + &disp->disp); if (ret == 0) { nouveau_display_create_properties(dev); if (disp->disp.object.oclass < NV50_DISP) diff --git a/drivers/gpu/drm/nouveau/nvif/disp.c b/drivers/gpu/drm/nouveau/nvif/disp.c index 122208adcd3c..8d0d30e08f57 100644 --- a/drivers/gpu/drm/nouveau/nvif/disp.c +++ b/drivers/gpu/drm/nouveau/nvif/disp.c @@ -31,7 +31,8 @@ nvif_disp_dtor(struct nvif_disp *disp) } int -nvif_disp_ctor(struct nvif_device *device, s32 oclass, struct nvif_disp *disp) +nvif_disp_ctor(struct nvif_device *device, const char *name, s32 oclass, + struct nvif_disp *disp) { static const struct nvif_mclass disps[] = { { TU102_DISP, -1 }, @@ -56,6 +57,6 @@ nvif_disp_ctor(struct nvif_device *device, s32 oclass, struct nvif_disp *disp) if (cid < 0) return cid; - return nvif_object_ctor(&device->object, "nvifDisp", 0, + return nvif_object_ctor(&device->object, name ? name : "nvifDisp", 0, disps[cid].oclass, NULL, 0, &disp->object); } From f7a7d22ad6781a34ffc718865700883d3cbf6c06 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 8 Jun 2020 14:47:37 +1000 Subject: [PATCH 036/145] drm/nouveau/nvif: give every notify object a human-readable name Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv04/crtc.c | 4 ++-- drivers/gpu/drm/nouveau/dispnv04/disp.c | 4 ++-- drivers/gpu/drm/nouveau/dispnv50/base507c.c | 5 +++-- drivers/gpu/drm/nouveau/dispnv50/head.c | 4 ++-- drivers/gpu/drm/nouveau/dispnv50/ovly507e.c | 3 ++- drivers/gpu/drm/nouveau/dispnv50/wndw.c | 2 +- drivers/gpu/drm/nouveau/include/nvif/notify.h | 9 +++++---- drivers/gpu/drm/nouveau/nouveau_chan.c | 5 +++-- drivers/gpu/drm/nouveau/nouveau_connector.c | 5 +++-- drivers/gpu/drm/nouveau/nouveau_fence.c | 5 +++-- drivers/gpu/drm/nouveau/nouveau_svm.c | 6 +++--- drivers/gpu/drm/nouveau/nvif/notify.c | 11 ++++++----- 12 files changed, 35 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv04/crtc.c b/drivers/gpu/drm/nouveau/dispnv04/crtc.c index 4989627b7802..3d3348478549 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/crtc.c +++ b/drivers/gpu/drm/nouveau/dispnv04/crtc.c @@ -759,7 +759,7 @@ static void nv_crtc_destroy(struct drm_crtc *crtc) nouveau_bo_unmap(nv_crtc->cursor.nvbo); nouveau_bo_unpin(nv_crtc->cursor.nvbo); nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo); - nvif_notify_fini(&nv_crtc->vblank); + nvif_notify_dtor(&nv_crtc->vblank); kfree(nv_crtc); } @@ -1351,7 +1351,7 @@ nv04_crtc_create(struct drm_device *dev, int crtc_num) nv04_cursor_init(nv_crtc); - ret = nvif_notify_init(&disp->disp.object, nv04_crtc_vblank_handler, + ret = nvif_notify_ctor(&disp->disp.object, "kmsVbl", nv04_crtc_vblank_handler, false, NV04_DISP_NTFY_VBLANK, &(struct nvif_notify_head_req_v0) { .head = nv_crtc->index, diff --git a/drivers/gpu/drm/nouveau/dispnv04/disp.c b/drivers/gpu/drm/nouveau/dispnv04/disp.c index 76be805fc488..075fe017915d 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/disp.c +++ b/drivers/gpu/drm/nouveau/dispnv04/disp.c @@ -178,7 +178,7 @@ nv04_display_destroy(struct drm_device *dev) nouveau_hw_save_vga_fonts(dev, 0); - nvif_notify_fini(&disp->flip); + nvif_notify_dtor(&disp->flip); nouveau_display(dev)->priv = NULL; kfree(disp); @@ -215,7 +215,7 @@ nv04_display_create(struct drm_device *dev) /* Request page flip completion event. */ if (drm->nvsw.client) { - nvif_notify_init(&drm->nvsw, nv04_flip_complete, + nvif_notify_ctor(&drm->nvsw, "kmsFlip", nv04_flip_complete, false, NV04_NVSW_NTFY_UEVENT, NULL, 0, 0, &disp->flip); } diff --git a/drivers/gpu/drm/nouveau/dispnv50/base507c.c b/drivers/gpu/drm/nouveau/dispnv50/base507c.c index ba20a7722900..c37f2278ce3e 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/base507c.c +++ b/drivers/gpu/drm/nouveau/dispnv50/base507c.c @@ -282,8 +282,9 @@ base507c_new_(const struct nv50_wndw_func *func, const u32 *format, return ret; } - ret = nvif_notify_init(&wndw->wndw.base.user, wndw->notify.func, - false, NV50_DISP_BASE_CHANNEL_DMA_V0_NTFY_UEVENT, + ret = nvif_notify_ctor(&wndw->wndw.base.user, "kmsBaseNtfy", + wndw->notify.func, false, + NV50_DISP_BASE_CHANNEL_DMA_V0_NTFY_UEVENT, &(struct nvif_notify_uevent_req) {}, sizeof(struct nvif_notify_uevent_req), sizeof(struct nvif_notify_uevent_rep), diff --git a/drivers/gpu/drm/nouveau/dispnv50/head.c b/drivers/gpu/drm/nouveau/dispnv50/head.c index 9a10ec267d1f..2d84eafd7b3e 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head.c @@ -489,7 +489,7 @@ nv50_head_destroy(struct drm_crtc *crtc) { struct nv50_head *head = nv50_head(crtc); - nvif_notify_fini(&head->base.vblank); + nvif_notify_dtor(&head->base.vblank); nv50_lut_fini(&head->olut); drm_crtc_cleanup(crtc); kfree(head); @@ -598,7 +598,7 @@ nv50_head_create(struct drm_device *dev, int index) } } - ret = nvif_notify_init(&disp->disp->object, nv50_head_vblank_handler, + ret = nvif_notify_ctor(&disp->disp->object, "kmsVbl", nv50_head_vblank_handler, false, NV04_DISP_NTFY_VBLANK, &(struct nvif_notify_head_req_v0) { .head = nv_crtc->index, diff --git a/drivers/gpu/drm/nouveau/dispnv50/ovly507e.c b/drivers/gpu/drm/nouveau/dispnv50/ovly507e.c index 4cce1078140a..1371225996e9 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/ovly507e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/ovly507e.c @@ -192,7 +192,8 @@ ovly507e_new_(const struct nv50_wndw_func *func, const u32 *format, return ret; } - ret = nvif_notify_init(&wndw->wndw.base.user, wndw->notify.func, false, + ret = nvif_notify_ctor(&wndw->wndw.base.user, "kmsOvlyNtfy", + wndw->notify.func, false, NV50_DISP_OVERLAY_CHANNEL_DMA_V0_NTFY_UEVENT, &(struct nvif_notify_uevent_req) {}, sizeof(struct nvif_notify_uevent_req), diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndw.c b/drivers/gpu/drm/nouveau/dispnv50/wndw.c index be67ef0785d8..baf693e5641c 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndw.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndw.c @@ -609,7 +609,7 @@ nv50_wndw_destroy(struct drm_plane *plane) nv50_wndw_ctxdma_del(ctxdma); } - nvif_notify_fini(&wndw->notify); + nvif_notify_dtor(&wndw->notify); nv50_dmac_destroy(&wndw->wimm); nv50_dmac_destroy(&wndw->wndw); diff --git a/drivers/gpu/drm/nouveau/include/nvif/notify.h b/drivers/gpu/drm/nouveau/include/nvif/notify.h index 6863732eb286..39f6b7ee1719 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/notify.h +++ b/drivers/gpu/drm/nouveau/include/nvif/notify.h @@ -4,6 +4,7 @@ struct nvif_notify { struct nvif_object *object; + const char *name; int index; #define NVIF_NOTIFY_USER 0 @@ -24,10 +25,10 @@ struct nvif_notify { struct work_struct work; }; -int nvif_notify_init(struct nvif_object *, int (*func)(struct nvif_notify *), - bool work, u8 type, void *data, u32 size, u32 reply, - struct nvif_notify *); -int nvif_notify_fini(struct nvif_notify *); +int nvif_notify_ctor(struct nvif_object *, const char *name, + int (*func)(struct nvif_notify *), bool work, u8 type, + void *data, u32 size, u32 reply, struct nvif_notify *); +int nvif_notify_dtor(struct nvif_notify *); int nvif_notify_get(struct nvif_notify *); int nvif_notify_put(struct nvif_notify *); int nvif_notify(const void *, u32, const void *, u32); diff --git a/drivers/gpu/drm/nouveau/nouveau_chan.c b/drivers/gpu/drm/nouveau/nouveau_chan.c index 59dbea9eab36..d208ef4b158c 100644 --- a/drivers/gpu/drm/nouveau/nouveau_chan.c +++ b/drivers/gpu/drm/nouveau/nouveau_chan.c @@ -105,7 +105,7 @@ nouveau_channel_del(struct nouveau_channel **pchan) nvif_object_dtor(&chan->nvsw); nvif_object_dtor(&chan->gart); nvif_object_dtor(&chan->vram); - nvif_notify_fini(&chan->kill); + nvif_notify_dtor(&chan->kill); nvif_object_dtor(&chan->user); nvif_object_dtor(&chan->push.ctxdma); nouveau_vma_del(&chan->push.vma); @@ -366,7 +366,8 @@ nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart) nvif_object_map(&chan->user, NULL, 0); if (chan->user.oclass >= FERMI_CHANNEL_GPFIFO) { - ret = nvif_notify_init(&chan->user, nouveau_channel_killed, + ret = nvif_notify_ctor(&chan->user, "abi16ChanKilled", + nouveau_channel_killed, true, NV906F_V0_NTFY_KILLED, NULL, 0, 0, &chan->kill); if (ret == 0) diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c b/drivers/gpu/drm/nouveau/nouveau_connector.c index 471fd5ca5352..7674025a4bfe 100644 --- a/drivers/gpu/drm/nouveau/nouveau_connector.c +++ b/drivers/gpu/drm/nouveau/nouveau_connector.c @@ -409,7 +409,7 @@ static void nouveau_connector_destroy(struct drm_connector *connector) { struct nouveau_connector *nv_connector = nouveau_connector(connector); - nvif_notify_fini(&nv_connector->hpd); + nvif_notify_dtor(&nv_connector->hpd); kfree(nv_connector->edid); drm_connector_unregister(connector); drm_connector_cleanup(connector); @@ -1450,7 +1450,8 @@ nouveau_connector_create(struct drm_device *dev, break; } - ret = nvif_notify_init(&disp->disp.object, nouveau_connector_hotplug, + ret = nvif_notify_ctor(&disp->disp.object, "kmsHotplug", + nouveau_connector_hotplug, true, NV04_DISP_NTFY_CONN, &(struct nvif_notify_conn_req_v0) { .mask = NVIF_NOTIFY_CONN_V0_ANY, diff --git a/drivers/gpu/drm/nouveau/nouveau_fence.c b/drivers/gpu/drm/nouveau/nouveau_fence.c index 666f2090d92b..e5dcbf67de7e 100644 --- a/drivers/gpu/drm/nouveau/nouveau_fence.c +++ b/drivers/gpu/drm/nouveau/nouveau_fence.c @@ -108,7 +108,7 @@ void nouveau_fence_context_del(struct nouveau_fence_chan *fctx) { nouveau_fence_context_kill(fctx, 0); - nvif_notify_fini(&fctx->notify); + nvif_notify_dtor(&fctx->notify); fctx->dead = 1; /* @@ -195,7 +195,8 @@ nouveau_fence_context_new(struct nouveau_channel *chan, struct nouveau_fence_cha if (!priv->uevent) return; - ret = nvif_notify_init(&chan->user, nouveau_fence_wait_uevent_handler, + ret = nvif_notify_ctor(&chan->user, "fenceNonStallIntr", + nouveau_fence_wait_uevent_handler, false, NV826E_V0_NTFY_NON_STALL_INTERRUPT, &(struct nvif_notify_uevent_req) { }, sizeof(struct nvif_notify_uevent_req), diff --git a/drivers/gpu/drm/nouveau/nouveau_svm.c b/drivers/gpu/drm/nouveau/nouveau_svm.c index 6f65fa73e1cd..d4b4f866ab78 100644 --- a/drivers/gpu/drm/nouveau/nouveau_svm.c +++ b/drivers/gpu/drm/nouveau/nouveau_svm.c @@ -905,7 +905,7 @@ nouveau_svm_fault_buffer_dtor(struct nouveau_svm *svm, int id) nouveau_svm_fault_buffer_fini(svm, id); - nvif_notify_fini(&buffer->notify); + nvif_notify_dtor(&buffer->notify); nvif_object_dtor(&buffer->object); } @@ -932,8 +932,8 @@ nouveau_svm_fault_buffer_ctor(struct nouveau_svm *svm, s32 oclass, int id) buffer->getaddr = args.get; buffer->putaddr = args.put; - ret = nvif_notify_init(&buffer->object, nouveau_svm_fault, true, - NVB069_V0_NTFY_FAULT, NULL, 0, 0, + ret = nvif_notify_ctor(&buffer->object, "svmFault", nouveau_svm_fault, + true, NVB069_V0_NTFY_FAULT, NULL, 0, 0, &buffer->notify); if (ret) return ret; diff --git a/drivers/gpu/drm/nouveau/nvif/notify.c b/drivers/gpu/drm/nouveau/nvif/notify.c index 278b3933dc96..143c8dc6889e 100644 --- a/drivers/gpu/drm/nouveau/nvif/notify.c +++ b/drivers/gpu/drm/nouveau/nvif/notify.c @@ -142,7 +142,7 @@ nvif_notify(const void *header, u32 length, const void *data, u32 size) } int -nvif_notify_fini(struct nvif_notify *notify) +nvif_notify_dtor(struct nvif_notify *notify) { struct nvif_object *object = notify->object; struct { @@ -162,9 +162,9 @@ nvif_notify_fini(struct nvif_notify *notify) } int -nvif_notify_init(struct nvif_object *object, int (*func)(struct nvif_notify *), - bool work, u8 event, void *data, u32 size, u32 reply, - struct nvif_notify *notify) +nvif_notify_ctor(struct nvif_object *object, const char *name, + int (*func)(struct nvif_notify *), bool work, u8 event, + void *data, u32 size, u32 reply, struct nvif_notify *notify) { struct { struct nvif_ioctl_v0 ioctl; @@ -174,6 +174,7 @@ nvif_notify_init(struct nvif_object *object, int (*func)(struct nvif_notify *), int ret = -ENOMEM; notify->object = object; + notify->name = name ? name : "nvifNotify"; notify->flags = 0; atomic_set(¬ify->putcnt, 1); notify->func = func; @@ -204,6 +205,6 @@ nvif_notify_init(struct nvif_object *object, int (*func)(struct nvif_notify *), kfree(args); done: if (ret) - nvif_notify_fini(notify); + nvif_notify_dtor(notify); return ret; } From 3e176fd0600439a8a1e0b3e95e2f0545660ab59c Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 29 Jun 2020 20:49:15 +1000 Subject: [PATCH 037/145] drm/nouveau/nvif: add support for object-level debug output Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/include/nvif/object.h | 1 + drivers/gpu/drm/nouveau/include/nvif/parent.h | 25 ++++++++++++ drivers/gpu/drm/nouveau/include/nvif/printf.h | 20 ++++++++++ drivers/gpu/drm/nouveau/nouveau_drm.c | 39 +++++++++++++++++++ drivers/gpu/drm/nouveau/nouveau_drv.h | 2 + drivers/gpu/drm/nouveau/nvif/object.c | 2 + 6 files changed, 89 insertions(+) create mode 100644 drivers/gpu/drm/nouveau/include/nvif/parent.h create mode 100644 drivers/gpu/drm/nouveau/include/nvif/printf.h diff --git a/drivers/gpu/drm/nouveau/include/nvif/object.h b/drivers/gpu/drm/nouveau/include/nvif/object.h index f3e20d02b2bc..a39d2bf7064b 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/object.h +++ b/drivers/gpu/drm/nouveau/include/nvif/object.h @@ -10,6 +10,7 @@ struct nvif_sclass { }; struct nvif_object { + struct nvif_parent *parent; struct nvif_client *client; const char *name; u32 handle; diff --git a/drivers/gpu/drm/nouveau/include/nvif/parent.h b/drivers/gpu/drm/nouveau/include/nvif/parent.h new file mode 100644 index 000000000000..41cb1b0d90d3 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvif/parent.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef __NVIF_PARENT_H__ +#define __NVIF_PARENT_H__ +#include +struct nvif_object; + +struct nvif_parent { + const struct nvif_parent_func { + void (*debugf)(struct nvif_object *, const char *fmt, ...) __printf(2, 3); + void (*errorf)(struct nvif_object *, const char *fmt, ...) __printf(2, 3); + } *func; +}; + +static inline void +nvif_parent_dtor(struct nvif_parent *parent) +{ + parent->func = NULL; +} + +static inline void +nvif_parent_ctor(const struct nvif_parent_func *func, struct nvif_parent *parent) +{ + parent->func = func; +} +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvif/printf.h b/drivers/gpu/drm/nouveau/include/nvif/printf.h new file mode 100644 index 000000000000..6c299ec6be21 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvif/printf.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef __NVIF_PRINTF_H__ +#define __NVIF_PRINTF_H__ +#include +#include + +#define NVIF_PRINT(l,o,f,a...) do { \ + struct nvif_object *_o = (o); \ + struct nvif_parent *_p = _o->parent; \ + _p->func->l(_o, "[%s/%08x:%s] "f"\n", _o->client->object.name, _o->handle, _o->name, ##a); \ +} while(0) + +#ifndef NVIF_DEBUG_PRINT_DISABLE +#define NVIF_DEBUG(o,f,a...) NVIF_PRINT(debugf, (o), f, ##a) +#else +#define NVIF_DEBUG(o,f,a...) +#endif + +#define NVIF_ERROR(o,f,a...) NVIF_PRINT(errorf, (o), f, ##a) +#endif diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c index 6f24a215ac74..c1b22746a710 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drm.c +++ b/drivers/gpu/drm/nouveau/nouveau_drm.c @@ -496,6 +496,40 @@ nouveau_accel_init(struct nouveau_drm *drm) nouveau_bo_move_init(drm); } +static void __printf(2, 3) +nouveau_drm_errorf(struct nvif_object *object, const char *fmt, ...) +{ + struct nouveau_drm *drm = container_of(object->parent, typeof(*drm), parent); + struct va_format vaf; + va_list va; + + va_start(va, fmt); + vaf.fmt = fmt; + vaf.va = &va; + NV_ERROR(drm, "%pV", &vaf); + va_end(va); +} + +static void __printf(2, 3) +nouveau_drm_debugf(struct nvif_object *object, const char *fmt, ...) +{ + struct nouveau_drm *drm = container_of(object->parent, typeof(*drm), parent); + struct va_format vaf; + va_list va; + + va_start(va, fmt); + vaf.fmt = fmt; + vaf.va = &va; + NV_DEBUG(drm, "%pV", &vaf); + va_end(va); +} + +static const struct nvif_parent_func +nouveau_parent = { + .debugf = nouveau_drm_debugf, + .errorf = nouveau_drm_errorf, +}; + static int nouveau_drm_device_init(struct drm_device *dev) { @@ -507,6 +541,9 @@ nouveau_drm_device_init(struct drm_device *dev) dev->dev_private = drm; drm->dev = dev; + nvif_parent_ctor(&nouveau_parent, &drm->parent); + drm->master.base.object.parent = &drm->parent; + ret = nouveau_cli_init(drm, "DRM-master", &drm->master); if (ret) goto fail_alloc; @@ -583,6 +620,7 @@ nouveau_drm_device_init(struct drm_device *dev) fail_master: nouveau_cli_fini(&drm->master); fail_alloc: + nvif_parent_dtor(&drm->parent); kfree(drm); return ret; } @@ -616,6 +654,7 @@ nouveau_drm_device_fini(struct drm_device *dev) nouveau_cli_fini(&drm->client); nouveau_cli_fini(&drm->master); + nvif_parent_dtor(&drm->parent); kfree(drm); } diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h index 2a6519737800..30c0bb5b4dc9 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drv.h +++ b/drivers/gpu/drm/nouveau/nouveau_drv.h @@ -132,8 +132,10 @@ nouveau_cli(struct drm_file *fpriv) } #include +#include struct nouveau_drm { + struct nvif_parent parent; struct nouveau_cli master; struct nouveau_cli client; struct drm_device *dev; diff --git a/drivers/gpu/drm/nouveau/nvif/object.c b/drivers/gpu/drm/nouveau/nvif/object.c index 9f3348327244..671a5c0199e0 100644 --- a/drivers/gpu/drm/nouveau/nvif/object.c +++ b/drivers/gpu/drm/nouveau/nvif/object.c @@ -282,6 +282,8 @@ nvif_object_ctor(struct nvif_object *parent, const char *name, u32 handle, return -ENOMEM; } + object->parent = parent->parent; + args->ioctl.version = 0; args->ioctl.type = NVIF_IOCTL_V0_NEW; args->new.version = 0; From 2853ccf09255aa7eb7122dd8816dedfd0f5d3724 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sat, 20 Jun 2020 07:52:26 +1000 Subject: [PATCH 038/145] drm/nouveau/kms/nv50-: wrap existing command submission in nvif_push interface This commit pulls in a bunch of new push buffer macros which are able to support NVIDIA's class headers, and provide more useful debug output and error checking (compile-time, where possible) than we had previously. Will incrementally transition each function over to the unified interfaces. Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/Kconfig | 8 + drivers/gpu/drm/nouveau/dispnv50/disp.c | 42 ++- drivers/gpu/drm/nouveau/dispnv50/disp.h | 4 +- drivers/gpu/drm/nouveau/include/nvhw/drf.h | 208 ++++++++++++ drivers/gpu/drm/nouveau/include/nvif/push.h | 359 ++++++++++++++++++++ 5 files changed, 614 insertions(+), 7 deletions(-) create mode 100644 drivers/gpu/drm/nouveau/include/nvhw/drf.h create mode 100644 drivers/gpu/drm/nouveau/include/nvif/push.h diff --git a/drivers/gpu/drm/nouveau/Kconfig b/drivers/gpu/drm/nouveau/Kconfig index d6e4ae1ef705..5dec1e5694b7 100644 --- a/drivers/gpu/drm/nouveau/Kconfig +++ b/drivers/gpu/drm/nouveau/Kconfig @@ -76,6 +76,14 @@ config NOUVEAU_DEBUG_MMU help Say Y here if you want to enable verbose MMU debug output. +config NOUVEAU_DEBUG_PUSH + bool "Enable additional push buffer debugging" + depends on DRM_NOUVEAU + default n + help + Say Y here if you want to enable verbose push buffer debug output + and sanity checks. + config DRM_NOUVEAU_BACKLIGHT bool "Support for backlight control" depends on DRM_NOUVEAU diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c b/drivers/gpu/drm/nouveau/dispnv50/disp.c index f25daf4739cb..368a2a97a900 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/disp.c +++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c @@ -113,7 +113,29 @@ nv50_dmac_destroy(struct nv50_dmac *dmac) nv50_chan_destroy(&dmac->base); - nvif_mem_dtor(&dmac->push); + nvif_mem_dtor(&dmac->_push.mem); +} + +static void +nv50_dmac_kick(struct nvif_push *push) +{ + struct nv50_dmac *dmac = container_of(push, typeof(*dmac), _push); + evo_kick(push->cur, dmac); + push->bgn = push->cur = push->end; +} + +static int +nv50_dmac_wait(struct nvif_push *push, u32 size) +{ + struct nv50_dmac *dmac = container_of(push, typeof(*dmac), _push); + u32 *ptr = evo_wait(dmac, size); + if (!ptr) + return -ETIMEDOUT; + + push->bgn = ptr; + push->cur = ptr; + push->end = ptr + size; + return 0; } int @@ -141,13 +163,16 @@ nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp, type |= NVIF_MEM_VRAM; ret = nvif_mem_ctor_map(&cli->mmu, "kmsChanPush", type, 0x1000, - &dmac->push); + &dmac->_push.mem); if (ret) return ret; - dmac->ptr = dmac->push.object.map.ptr; + dmac->ptr = dmac->_push.mem.object.map.ptr; + dmac->_push.wait = nv50_dmac_wait; + dmac->_push.kick = nv50_dmac_kick; + dmac->push = &dmac->_push; - args->pushbuf = nvif_handle(&dmac->push.object); + args->pushbuf = nvif_handle(&dmac->_push.mem.object); ret = nv50_chan_create(device, disp, oclass, head, data, size, &dmac->base); @@ -193,7 +218,7 @@ evo_flush(struct nv50_dmac *dmac) /* Push buffer fetches are not coherent with BAR1, we need to ensure * writes have been flushed right through to VRAM before writing PUT. */ - if (dmac->push.type & NVIF_MEM_VRAM) { + if (dmac->push->mem.type & NVIF_MEM_VRAM) { struct nvif_device *device = dmac->base.device; nvif_wr32(&device->object, 0x070000, 0x00000001); nvif_msec(device, 2000, @@ -208,7 +233,12 @@ evo_wait(struct nv50_dmac *evoc, int nr) { struct nv50_dmac *dmac = evoc; struct nvif_device *device = dmac->base.device; - u32 put = nvif_rd32(&dmac->base.user, 0x0000) / 4; + u32 put; + + if (dmac->push->cur != dmac->push->bgn) + PUSH_KICK(dmac->push); + + put = nvif_rd32(&dmac->base.user, 0x0000) / 4; mutex_lock(&dmac->lock); if (put + nr >= (PAGE_SIZE / 4) - 8) { diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.h b/drivers/gpu/drm/nouveau/dispnv50/disp.h index 1968c6921f9e..746ab75d15c3 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/disp.h +++ b/drivers/gpu/drm/nouveau/dispnv50/disp.h @@ -2,6 +2,7 @@ #define __NV50_KMS_H__ #include #include +#include #include "nouveau_display.h" @@ -61,7 +62,8 @@ struct nv50_chan { struct nv50_dmac { struct nv50_chan base; - struct nvif_mem push; + struct nvif_push _push; + struct nvif_push *push; u32 *ptr; struct nvif_object sync; diff --git a/drivers/gpu/drm/nouveau/include/nvhw/drf.h b/drivers/gpu/drm/nouveau/include/nvhw/drf.h new file mode 100644 index 000000000000..bd0fc41446e2 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvhw/drf.h @@ -0,0 +1,208 @@ +/* + * Copyright 2019 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef __NVHW_DRF_H__ +#define __NVHW_DRF_H__ + +/* Helpers common to all DRF accessors. */ +#define DRF_LO(drf) (0 ? drf) +#define DRF_HI(drf) (1 ? drf) +#define DRF_BITS(drf) (DRF_HI(drf) - DRF_LO(drf) + 1) +#define DRF_MASK(drf) (~0ULL >> (64 - DRF_BITS(drf))) +#define DRF_SMASK(drf) (DRF_MASK(drf) << DRF_LO(drf)) + +/* Helpers for DRF-MW accessors. */ +#define DRF_MX_MW(drf) drf +#define DRF_MX(drf) DRF_MX_##drf +#define DRF_MW(drf) DRF_MX(drf) +#define DRF_MW_SPANS(o,drf) (DRF_LW_IDX((o),drf) != DRF_HW_IDX((o),drf)) +#define DRF_MW_SIZE(o) (sizeof((o)[0]) * 8) + +#define DRF_LW_IDX(o,drf) (DRF_LO(DRF_MW(drf)) / DRF_MW_SIZE(o)) +#define DRF_LW_LO(o,drf) (DRF_LO(DRF_MW(drf)) % DRF_MW_SIZE(o)) +#define DRF_LW_HI(o,drf) (DRF_MW_SPANS((o),drf) ? (DRF_MW_SIZE(o) - 1) : DRF_HW_HI((o),drf)) +#define DRF_LW_BITS(o,drf) (DRF_LW_HI((o),drf) - DRF_LW_LO((o),drf) + 1) +#define DRF_LW_MASK(o,drf) (~0ULL >> (64 - DRF_LW_BITS((o),drf))) +#define DRF_LW_SMASK(o,drf) (DRF_LW_MASK((o),drf) << DRF_LW_LO((o),drf)) +#define DRF_LW_GET(o,drf) (((o)[DRF_LW_IDX((o),drf)] >> DRF_LW_LO((o),drf)) & DRF_LW_MASK((o),drf)) +#define DRF_LW_VAL(o,drf,v) (((v) & DRF_LW_MASK((o),drf)) << DRF_LW_LO((o),drf)) +#define DRF_LW_CLR(o,drf) ((o)[DRF_LW_IDX((o),drf)] & ~DRF_LW_SMASK((o),drf)) +#define DRF_LW_SET(o,drf,v) (DRF_LW_CLR((o),drf) | DRF_LW_VAL((o),drf,(v))) + +#define DRF_HW_IDX(o,drf) (DRF_HI(DRF_MW(drf)) / DRF_MW_SIZE(o)) +#define DRF_HW_LO(o,drf) 0 +#define DRF_HW_HI(o,drf) (DRF_HI(DRF_MW(drf)) % DRF_MW_SIZE(o)) +#define DRF_HW_BITS(o,drf) (DRF_HW_HI((o),drf) - DRF_HW_LO((o),drf) + 1) +#define DRF_HW_MASK(o,drf) (~0ULL >> (64 - DRF_HW_BITS((o),drf))) +#define DRF_HW_SMASK(o,drf) (DRF_HW_MASK((o),drf) << DRF_HW_LO((o),drf)) +#define DRF_HW_GET(o,drf) ((o)[DRF_HW_IDX(o,drf)] & DRF_HW_SMASK((o),drf)) +#define DRF_HW_VAL(o,drf,v) (((long long)(v) >> DRF_LW_BITS((o),drf)) & DRF_HW_SMASK((o),drf)) +#define DRF_HW_CLR(o,drf) ((o)[DRF_HW_IDX((o),drf)] & ~DRF_HW_SMASK((o),drf)) +#define DRF_HW_SET(o,drf,v) (DRF_HW_CLR((o),drf) | DRF_HW_VAL((o),drf,(v))) + +/* DRF accessors. */ +#define NVVAL_X(drf,v) (((v) & DRF_MASK(drf)) << DRF_LO(drf)) +#define NVVAL_N(X,d,r,f, v) NVVAL_X(d##_##r##_##f, (v)) +#define NVVAL_I(X,d,r,f,i,v) NVVAL_X(d##_##r##_##f(i), (v)) +#define NVVAL_(X,_1,_2,_3,_4,_5,IMPL,...) IMPL +#define NVVAL(A...) NVVAL_(X, ##A, NVVAL_I, NVVAL_N)(X, ##A) + +#define NVDEF_N(X,d,r,f, v) NVVAL_X(d##_##r##_##f, d##_##r##_##f##_##v) +#define NVDEF_I(X,d,r,f,i,v) NVVAL_X(d##_##r##_##f(i), d##_##r##_##f##_##v) +#define NVDEF_(X,_1,_2,_3,_4,_5,IMPL,...) IMPL +#define NVDEF(A...) NVDEF_(X, ##A, NVDEF_I, NVDEF_N)(X, ##A) + +#define NVVAL_GET_X(o,drf) (((o) >> DRF_LO(drf)) & DRF_MASK(drf)) +#define NVVAL_GET_N(X,o,d,r,f ) NVVAL_GET_X(o, d##_##r##_##f) +#define NVVAL_GET_I(X,o,d,r,f,i) NVVAL_GET_X(o, d##_##r##_##f(i)) +#define NVVAL_GET_(X,_1,_2,_3,_4,_5,IMPL,...) IMPL +#define NVVAL_GET(A...) NVVAL_GET_(X, ##A, NVVAL_GET_I, NVVAL_GET_N)(X, ##A) + +#define NVVAL_TEST_X(o,drf,cmp,drfv) (NVVAL_GET_X((o), drf) cmp drfv) +#define NVVAL_TEST_N(X,o,d,r,f, cmp,v) NVVAL_TEST_X(o, d##_##r##_##f , cmp, (v)) +#define NVVAL_TEST_I(X,o,d,r,f,i,cmp,v) NVVAL_TEST_X(o, d##_##r##_##f(i), cmp, (v)) +#define NVVAL_TEST_(X,_1,_2,_3,_4,_5,_6,_7,IMPL,...) IMPL +#define NVVAL_TEST(A...) NVVAL_TEST_(X, ##A, NVVAL_TEST_I, NVVAL_TEST_N)(X, ##A) + +#define NVDEF_TEST_N(X,o,d,r,f, cmp,v) NVVAL_TEST_X(o, d##_##r##_##f , cmp, d##_##r##_##f##_##v) +#define NVDEF_TEST_I(X,o,d,r,f,i,cmp,v) NVVAL_TEST_X(o, d##_##r##_##f(i), cmp, d##_##r##_##f##_##v) +#define NVDEF_TEST_(X,_1,_2,_3,_4,_5,_6,_7,IMPL,...) IMPL +#define NVDEF_TEST(A...) NVDEF_TEST_(X, ##A, NVDEF_TEST_I, NVDEF_TEST_N)(X, ##A) + +#define NVVAL_SET_X(o,drf,v) (((o) & ~DRF_SMASK(drf)) | NVVAL_X(drf, (v))) +#define NVVAL_SET_N(X,o,d,r,f, v) NVVAL_SET_X(o, d##_##r##_##f, (v)) +#define NVVAL_SET_I(X,o,d,r,f,i,v) NVVAL_SET_X(o, d##_##r##_##f(i), (v)) +#define NVVAL_SET_(X,_1,_2,_3,_4,_5,_6,IMPL,...) IMPL +#define NVVAL_SET(A...) NVVAL_SET_(X, ##A, NVVAL_SET_I, NVVAL_SET_N)(X, ##A) + +#define NVDEF_SET_N(X,o,d,r,f, v) NVVAL_SET_X(o, d##_##r##_##f, d##_##r##_##f##_##v) +#define NVDEF_SET_I(X,o,d,r,f,i,v) NVVAL_SET_X(o, d##_##r##_##f(i), d##_##r##_##f##_##v) +#define NVDEF_SET_(X,_1,_2,_3,_4,_5,_6,IMPL,...) IMPL +#define NVDEF_SET(A...) NVDEF_SET_(X, ##A, NVDEF_SET_I, NVDEF_SET_N)(X, ##A) + +/* DRF-MW accessors. */ +#define NVVAL_MW_GET_X(o,drf) \ + ((DRF_MW_SPANS((o),drf) ? \ + (DRF_HW_GET((o),drf) << DRF_LW_BITS((o),drf)) : 0) | DRF_LW_GET((o),drf)) +#define NVVAL_MW_GET_N(X,o,d,r,f ) NVVAL_MW_GET_X((o), d##_##r##_##f) +#define NVVAL_MW_GET_I(X,o,d,r,f,i) NVVAL_MW_GET_X((o), d##_##r##_##f(i)) +#define NVVAL_MW_GET_(X,_1,_2,_3,_4,_5,IMPL,...) IMPL +#define NVVAL_MW_GET(A...) NVVAL_MW_GET_(X, ##A, NVVAL_MW_GET_I, NVVAL_MW_GET_N)(X, ##A) + +#define NVVAL_MW_SET_X(o,drf,v) do { \ + (o)[DRF_LW_IDX((o),drf)] = DRF_LW_SET((o),drf,(v)); \ + if (DRF_MW_SPANS((o),drf)) \ + (o)[DRF_HW_IDX((o),drf)] = DRF_HW_SET((o),drf,(v)); \ +} while(0) +#define NVVAL_MW_SET_N(X,o,d,r,f, v) NVVAL_MW_SET_X((o), d##_##r##_##f, (v)) +#define NVVAL_MW_SET_I(X,o,d,r,f,i,v) NVVAL_MW_SET_X((o), d##_##r##_##f(i), (v)) +#define NVVAL_MW_SET_(X,_1,_2,_3,_4,_5,_6,IMPL,...) IMPL +#define NVVAL_MW_SET(A...) NVVAL_MW_SET_(X, ##A, NVVAL_MW_SET_I, NVVAL_MW_SET_N)(X, ##A) + +#define NVDEF_MW_SET_N(X,o,d,r,f, v) NVVAL_MW_SET_X(o, d##_##r##_##f, d##_##r##_##f##_##v) +#define NVDEF_MW_SET_I(X,o,d,r,f,i,v) NVVAL_MW_SET_X(o, d##_##r##_##f(i), d##_##r##_##f##_##v) +#define NVDEF_MW_SET_(X,_1,_2,_3,_4,_5,_6,IMPL,...) IMPL +#define NVDEF_MW_SET(A...) NVDEF_MW_SET_(X, ##A, NVDEF_MW_SET_I, NVDEF_MW_SET_N)(X, ##A) + +/* Helper for reading an arbitrary object. */ +#define DRF_RD_X(e,p,o,dr) e((p), (o), dr) +#define DRF_RD_N(X,e,p,o,d,r ) DRF_RD_X(e, (p), (o), d##_##r) +#define DRF_RD_I(X,e,p,o,d,r,i) DRF_RD_X(e, (p), (o), d##_##r(i)) +#define DRF_RD_(X,_1,_2,_3,_4,_5,_6,IMPL,...) IMPL +#define DRF_RD(A...) DRF_RD_(X, ##A, DRF_RD_I, DRF_RD_N)(X, ##A) + +/* Helper for writing an arbitrary object. */ +#define DRF_WR_X(e,p,o,dr,v) e((p), (o), dr, (v)) +#define DRF_WR_N(X,e,p,o,d,r, v) DRF_WR_X(e, (p), (o), d##_##r , (v)) +#define DRF_WR_I(X,e,p,o,d,r,i,v) DRF_WR_X(e, (p), (o), d##_##r(i), (v)) +#define DRF_WR_(X,_1,_2,_3,_4,_5,_6,_7,IMPL,...) IMPL +#define DRF_WR(A...) DRF_WR_(X, ##A, DRF_WR_I, DRF_WR_N)(X, ##A) + +/* Helper for modifying an arbitrary object. */ +#define DRF_MR_X(er,ew,ty,p,o,dr,m,v) ({ \ + ty _t = DRF_RD_X(er, (p), (o), dr); \ + DRF_WR_X(ew, (p), (o), dr, (_t & ~(m)) | (v)); \ + _t; \ +}) +#define DRF_MR_N(X,er,ew,ty,p,o,d,r ,m,v) DRF_MR_X(er, ew, ty, (p), (o), d##_##r , (m), (v)) +#define DRF_MR_I(X,er,ew,ty,p,o,d,r,i,m,v) DRF_MR_X(er, ew, ty, (p), (o), d##_##r(i), (m), (v)) +#define DRF_MR_(X,_1,_2,_3,_4,_5,_6,_7,_8,_9,_10,IMPL,...) IMPL +#define DRF_MR(A...) DRF_MR_(X, ##A, DRF_MR_I, DRF_MR_N)(X, ##A) + +/* Helper for extracting a field value from arbitrary object. */ +#define DRF_RV_X(e,p,o,dr,drf) NVVAL_GET_X(DRF_RD_X(e, (p), (o), dr), drf) +#define DRF_RV_N(X,e,p,o,d,r, f) DRF_RV_X(e, (p), (o), d##_##r , d##_##r##_##f) +#define DRF_RV_I(X,e,p,o,d,r,i,f) DRF_RV_X(e, (p), (o), d##_##r(i), d##_##r##_##f) +#define DRF_RV_(X,_1,_2,_3,_4,_5,_6,_7,IMPL,...) IMPL +#define DRF_RV(A...) DRF_RV_(X, ##A, DRF_RV_I, DRF_RV_N)(X, ##A) + +/* Helper for writing field value to arbitrary object (all other bits cleared). */ +#define DRF_WV_N(X,e,p,o,d,r, f,v) \ + DRF_WR_X(e, (p), (o), d##_##r , NVVAL_X(d##_##r##_##f, (v))) +#define DRF_WV_I(X,e,p,o,d,r,i,f,v) \ + DRF_WR_X(e, (p), (o), d##_##r(i), NVVAL_X(d##_##r##_##f, (v))) +#define DRF_WV_(X,_1,_2,_3,_4,_5,_6,_7,_8,IMPL,...) IMPL +#define DRF_WV(A...) DRF_WV_(X, ##A, DRF_WV_I, DRF_WV_N)(X, ##A) + +/* Helper for writing field definition to arbitrary object (all other bits cleared). */ +#define DRF_WD_N(X,e,p,o,d,r, f,v) \ + DRF_WR_X(e, (p), (o), d##_##r , NVVAL_X(d##_##r##_##f, d##_##r##_##f##_##v)) +#define DRF_WD_I(X,e,p,o,d,r,i,f,v) \ + DRF_WR_X(e, (p), (o), d##_##r(i), NVVAL_X(d##_##r##_##f, d##_##r##_##f##_##v)) +#define DRF_WD_(X,_1,_2,_3,_4,_5,_6,_7,_8,IMPL,...) IMPL +#define DRF_WD(A...) DRF_WD_(X, ##A, DRF_WD_I, DRF_WD_N)(X, ##A) + +/* Helper for modifying field value in arbitrary object. */ +#define DRF_MV_N(X,er,ew,ty,p,o,d,r, f,v) \ + NVVAL_GET_X(DRF_MR_X(er, ew, ty, (p), (o), d##_##r , DRF_SMASK(d##_##r##_##f), \ + NVVAL_X(d##_##r##_##f, (v))), d##_##r##_##f) +#define DRF_MV_I(X,er,ew,ty,p,o,d,r,i,f,v) \ + NVVAL_GET_X(DRF_MR_X(er, ew, ty, (p), (o), d##_##r(i), DRF_SMASK(d##_##r##_##f), \ + NVVAL_X(d##_##r##_##f, (v))), d##_##r##_##f) +#define DRF_MV_(X,_1,_2,_3,_4,_5,_6,_7,_8,_9,_10,IMPL,...) IMPL +#define DRF_MV(A...) DRF_MV_(X, ##A, DRF_MV_I, DRF_MV_N)(X, ##A) + +/* Helper for modifying field definition in arbitrary object. */ +#define DRF_MD_N(X,er,ew,ty,p,o,d,r, f,v) \ + NVVAL_GET_X(DRF_MR_X(er, ew, ty, (p), (o), d##_##r , DRF_SMASK(d##_##r##_##f), \ + NVVAL_X(d##_##r##_##f, d##_##r##_##f##_##v)), d##_##r##_##f) +#define DRF_MD_I(X,er,ew,ty,p,o,d,r,i,f,v) \ + NVVAL_GET_X(DRF_MR_X(er, ew, ty, (p), (o), d##_##r(i), DRF_SMASK(d##_##r##_##f), \ + NVVAL_X(d##_##r##_##f, d##_##r##_##f##_##v)), d##_##r##_##f) +#define DRF_MD_(X,_1,_2,_3,_4,_5,_6,_7,_8,_9,_10,IMPL,...) IMPL +#define DRF_MD(A...) DRF_MD_(X, ##A, DRF_MD_I, DRF_MD_N)(X, ##A) + +/* Helper for testing against field value in aribtrary object */ +#define DRF_TV_N(X,e,p,o,d,r, f,cmp,v) \ + NVVAL_TEST_X(DRF_RD_X(e, (p), (o), d##_##r ), d##_##r##_##f, cmp, (v)) +#define DRF_TV_I(X,e,p,o,d,r,i,f,cmp,v) \ + NVVAL_TEST_X(DRF_RD_X(e, (p), (o), d##_##r(i)), d##_##r##_##f, cmp, (v)) +#define DRF_TV_(X,_1,_2,_3,_4,_5,_6,_7,_8,_9,IMPL,...) IMPL +#define DRF_TV(A...) DRF_TV_(X, ##A, DRF_TV_I, DRF_TV_N)(X, ##A) + +/* Helper for testing against field definition in aribtrary object */ +#define DRF_TD_N(X,e,p,o,d,r, f,cmp,v) \ + NVVAL_TEST_X(DRF_RD_X(e, (p), (o), d##_##r ), d##_##r##_##f, cmp, d##_##r##_##f##_##v) +#define DRF_TD_I(X,e,p,o,d,r,i,f,cmp,v) \ + NVVAL_TEST_X(DRF_RD_X(e, (p), (o), d##_##r(i)), d##_##r##_##f, cmp, d##_##r##_##f##_##v) +#define DRF_TD_(X,_1,_2,_3,_4,_5,_6,_7,_8,_9,IMPL,...) IMPL +#define DRF_TD(A...) DRF_TD_(X, ##A, DRF_TD_I, DRF_TD_N)(X, ##A) +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvif/push.h b/drivers/gpu/drm/nouveau/include/nvif/push.h new file mode 100644 index 000000000000..168d7694ede5 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvif/push.h @@ -0,0 +1,359 @@ +/* + * Copyright 2019 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef __NVIF_PUSH_H__ +#define __NVIF_PUSH_H__ +#include +#include + +#include + +struct nvif_push { + int (*wait)(struct nvif_push *push, u32 size); + void (*kick)(struct nvif_push *push); + + struct nvif_mem mem; + + u32 *bgn; + u32 *cur; + u32 *seg; + u32 *end; +}; + +static inline __must_check int +PUSH_WAIT(struct nvif_push *push, u32 size) +{ + if (push->cur + size >= push->end) { + int ret = push->wait(push, size); + if (ret) + return ret; + } +#ifdef CONFIG_NOUVEAU_DEBUG_PUSH + push->seg = push->cur + size; +#endif + return 0; +} + +static inline int +PUSH_KICK(struct nvif_push *push) +{ + push->kick(push); + return 0; +} + +#ifdef CONFIG_NOUVEAU_DEBUG_PUSH +#define PUSH_PRINTF(p,f,a...) do { \ + struct nvif_push *_ppp = (p); \ + u32 __o = _ppp->cur - (u32 *)_ppp->mem.object.map.ptr; \ + NVIF_DEBUG(&_ppp->mem.object, "%08x: "f, __o * 4, ##a); \ + (void)__o; \ +} while(0) +#define PUSH_ASSERT_ON(a,b) WARN((a), b) +#else +#define PUSH_PRINTF(p,f,a...) +#define PUSH_ASSERT_ON(a, b) +#endif + +#define PUSH_ASSERT(a,b) do { \ + static_assert( \ + __builtin_choose_expr(__builtin_constant_p(a), (a), 1), b \ + ); \ + PUSH_ASSERT_ON(!(a), b); \ +} while(0) + +#define PUSH_DATA__(p,d,f,a...) do { \ + struct nvif_push *_p = (p); \ + u32 _d = (d); \ + PUSH_ASSERT(_p->cur < _p->seg, "segment overrun"); \ + PUSH_ASSERT(_p->cur < _p->end, "pushbuf overrun"); \ + PUSH_PRINTF(_p, "%08x"f, _d, ##a); \ + *_p->cur++ = _d; \ +} while(0) + +#define PUSH_DATA_(X,p,m,i0,i1,d,s,f,a...) PUSH_DATA__((p), (d), "-> "#m f, ##a) +#define PUSH_DATA(p,d) PUSH_DATA__((p), (d), " data - %s", __func__) + +//XXX: error-check this against *real* pushbuffer end? +#define PUSH_RSVD(p,d) do { \ + struct nvif_push *__p = (p); \ + __p->seg++; \ + __p->end++; \ + d; \ +} while(0) + +#ifdef CONFIG_NOUVEAU_DEBUG_PUSH +#define PUSH_DATAp(X,p,m,i,o,d,s,f,a...) do { \ + struct nvif_push *_pp = (p); \ + const u32 *_dd = (d); \ + u32 _s = (s), _i = (i?PUSH_##o##_INC); \ + if (_s--) { \ + PUSH_DATA_(X, _pp, X##m, i0, i1, *_dd++, 1, "+0x%x", 0); \ + while (_s--) { \ + PUSH_DATA_(X, _pp, X##m, i0, i1, *_dd++, 1, "+0x%x", _i); \ + _i += (0?PUSH_##o##_INC); \ + } \ + } \ +} while(0) +#else +#define PUSH_DATAp(X,p,m,i,o,d,s,f,a...) do { \ + struct nvif_push *_p = (p); \ + u32 _s = (s); \ + PUSH_ASSERT(_p->cur + _s <= _p->seg, "segment overrun"); \ + PUSH_ASSERT(_p->cur + _s <= _p->end, "pushbuf overrun"); \ + memcpy(_p->cur, (d), _s << 2); \ + _p->cur += _s; \ +} while(0) +#endif + +#define PUSH_1(X,f,ds,n,c,o,p,s,mA,dA) do { \ + PUSH_##o##_HDR((p), s, mA, (c)+(n)); \ + PUSH_##f(X, (p), X##mA, 1, o, (dA), ds, ""); \ +} while(0) +#define PUSH_2(X,f,ds,n,c,o,p,s,mB,dB,mA,dA,a...) do { \ + PUSH_ASSERT((mB) - (mA) == (1?PUSH_##o##_INC), "mthd1"); \ + PUSH_1(X, DATA_, 1, ds, (c)+(n), o, (p), s, X##mA, (dA), ##a); \ + PUSH_##f(X, (p), X##mB, 0, o, (dB), ds, ""); \ +} while(0) +#define PUSH_3(X,f,ds,n,c,o,p,s,mB,dB,mA,dA,a...) do { \ + PUSH_ASSERT((mB) - (mA) == (0?PUSH_##o##_INC), "mthd2"); \ + PUSH_2(X, DATA_, 1, ds, (c)+(n), o, (p), s, X##mA, (dA), ##a); \ + PUSH_##f(X, (p), X##mB, 0, o, (dB), ds, ""); \ +} while(0) +#define PUSH_4(X,f,ds,n,c,o,p,s,mB,dB,mA,dA,a...) do { \ + PUSH_ASSERT((mB) - (mA) == (0?PUSH_##o##_INC), "mthd3"); \ + PUSH_3(X, DATA_, 1, ds, (c)+(n), o, (p), s, X##mA, (dA), ##a); \ + PUSH_##f(X, (p), X##mB, 0, o, (dB), ds, ""); \ +} while(0) +#define PUSH_5(X,f,ds,n,c,o,p,s,mB,dB,mA,dA,a...) do { \ + PUSH_ASSERT((mB) - (mA) == (0?PUSH_##o##_INC), "mthd4"); \ + PUSH_4(X, DATA_, 1, ds, (c)+(n), o, (p), s, X##mA, (dA), ##a); \ + PUSH_##f(X, (p), X##mB, 0, o, (dB), ds, ""); \ +} while(0) +#define PUSH_6(X,f,ds,n,c,o,p,s,mB,dB,mA,dA,a...) do { \ + PUSH_ASSERT((mB) - (mA) == (0?PUSH_##o##_INC), "mthd5"); \ + PUSH_5(X, DATA_, 1, ds, (c)+(n), o, (p), s, X##mA, (dA), ##a); \ + PUSH_##f(X, (p), X##mB, 0, o, (dB), ds, ""); \ +} while(0) +#define PUSH_7(X,f,ds,n,c,o,p,s,mB,dB,mA,dA,a...) do { \ + PUSH_ASSERT((mB) - (mA) == (0?PUSH_##o##_INC), "mthd6"); \ + PUSH_6(X, DATA_, 1, ds, (c)+(n), o, (p), s, X##mA, (dA), ##a); \ + PUSH_##f(X, (p), X##mB, 0, o, (dB), ds, ""); \ +} while(0) +#define PUSH_8(X,f,ds,n,c,o,p,s,mB,dB,mA,dA,a...) do { \ + PUSH_ASSERT((mB) - (mA) == (0?PUSH_##o##_INC), "mthd7"); \ + PUSH_7(X, DATA_, 1, ds, (c)+(n), o, (p), s, X##mA, (dA), ##a); \ + PUSH_##f(X, (p), X##mB, 0, o, (dB), ds, ""); \ +} while(0) +#define PUSH_9(X,f,ds,n,c,o,p,s,mB,dB,mA,dA,a...) do { \ + PUSH_ASSERT((mB) - (mA) == (0?PUSH_##o##_INC), "mthd8"); \ + PUSH_8(X, DATA_, 1, ds, (c)+(n), o, (p), s, X##mA, (dA), ##a); \ + PUSH_##f(X, (p), X##mB, 0, o, (dB), ds, ""); \ +} while(0) +#define PUSH_10(X,f,ds,n,c,o,p,s,mB,dB,mA,dA,a...) do { \ + PUSH_ASSERT((mB) - (mA) == (0?PUSH_##o##_INC), "mthd9"); \ + PUSH_9(X, DATA_, 1, ds, (c)+(n), o, (p), s, X##mA, (dA), ##a); \ + PUSH_##f(X, (p), X##mB, 0, o, (dB), ds, ""); \ +} while(0) + +#define PUSH_1D(X,o,p,s,mA,dA) \ + PUSH_1(X, DATA_, 1, 1, 0, o, (p), s, X##mA, (dA)) +#define PUSH_2D(X,o,p,s,mA,dA,mB,dB) \ + PUSH_2(X, DATA_, 1, 1, 0, o, (p), s, X##mB, (dB), \ + X##mA, (dA)) +#define PUSH_3D(X,o,p,s,mA,dA,mB,dB,mC,dC) \ + PUSH_3(X, DATA_, 1, 1, 0, o, (p), s, X##mC, (dC), \ + X##mB, (dB), \ + X##mA, (dA)) +#define PUSH_4D(X,o,p,s,mA,dA,mB,dB,mC,dC,mD,dD) \ + PUSH_4(X, DATA_, 1, 1, 0, o, (p), s, X##mD, (dD), \ + X##mC, (dC), \ + X##mB, (dB), \ + X##mA, (dA)) +#define PUSH_5D(X,o,p,s,mA,dA,mB,dB,mC,dC,mD,dD,mE,dE) \ + PUSH_5(X, DATA_, 1, 1, 0, o, (p), s, X##mE, (dE), \ + X##mD, (dD), \ + X##mC, (dC), \ + X##mB, (dB), \ + X##mA, (dA)) +#define PUSH_6D(X,o,p,s,mA,dA,mB,dB,mC,dC,mD,dD,mE,dE,mF,dF) \ + PUSH_6(X, DATA_, 1, 1, 0, o, (p), s, X##mF, (dF), \ + X##mE, (dE), \ + X##mD, (dD), \ + X##mC, (dC), \ + X##mB, (dB), \ + X##mA, (dA)) +#define PUSH_7D(X,o,p,s,mA,dA,mB,dB,mC,dC,mD,dD,mE,dE,mF,dF,mG,dG) \ + PUSH_7(X, DATA_, 1, 1, 0, o, (p), s, X##mG, (dG), \ + X##mF, (dF), \ + X##mE, (dE), \ + X##mD, (dD), \ + X##mC, (dC), \ + X##mB, (dB), \ + X##mA, (dA)) +#define PUSH_8D(X,o,p,s,mA,dA,mB,dB,mC,dC,mD,dD,mE,dE,mF,dF,mG,dG,mH,dH) \ + PUSH_8(X, DATA_, 1, 1, 0, o, (p), s, X##mH, (dH), \ + X##mG, (dG), \ + X##mF, (dF), \ + X##mE, (dE), \ + X##mD, (dD), \ + X##mC, (dC), \ + X##mB, (dB), \ + X##mA, (dA)) +#define PUSH_9D(X,o,p,s,mA,dA,mB,dB,mC,dC,mD,dD,mE,dE,mF,dF,mG,dG,mH,dH,mI,dI) \ + PUSH_9(X, DATA_, 1, 1, 0, o, (p), s, X##mI, (dI), \ + X##mH, (dH), \ + X##mG, (dG), \ + X##mF, (dF), \ + X##mE, (dE), \ + X##mD, (dD), \ + X##mC, (dC), \ + X##mB, (dB), \ + X##mA, (dA)) +#define PUSH_10D(X,o,p,s,mA,dA,mB,dB,mC,dC,mD,dD,mE,dE,mF,dF,mG,dG,mH,dH,mI,dI,mJ,dJ) \ + PUSH_10(X, DATA_, 1, 1, 0, o, (p), s, X##mJ, (dJ), \ + X##mI, (dI), \ + X##mH, (dH), \ + X##mG, (dG), \ + X##mF, (dF), \ + X##mE, (dE), \ + X##mD, (dD), \ + X##mC, (dC), \ + X##mB, (dB), \ + X##mA, (dA)) + +#define PUSH_1P(X,o,p,s,mA,dp,ds) \ + PUSH_1(X, DATAp, ds, ds, 0, o, (p), s, X##mA, (dp)) +#define PUSH_2P(X,o,p,s,mA,dA,mB,dp,ds) \ + PUSH_2(X, DATAp, ds, ds, 0, o, (p), s, X##mB, (dp), \ + X##mA, (dA)) +#define PUSH_3P(X,o,p,s,mA,dA,mB,dB,mC,dp,ds) \ + PUSH_3(X, DATAp, ds, ds, 0, o, (p), s, X##mC, (dp), \ + X##mB, (dB), \ + X##mA, (dA)) + +#define PUSH_(A,B,C,D,E,F,G,H,I,J,K,L,M,N,O,P,Q,R,S,T,U,V,W,X,IMPL,...) IMPL +#define PUSH(A...) PUSH_(A, PUSH_10P, PUSH_10D, \ + PUSH_9P , PUSH_9D, \ + PUSH_8P , PUSH_8D, \ + PUSH_7P , PUSH_7D, \ + PUSH_6P , PUSH_6D, \ + PUSH_5P , PUSH_5D, \ + PUSH_4P , PUSH_4D, \ + PUSH_3P , PUSH_3D, \ + PUSH_2P , PUSH_2D, \ + PUSH_1P , PUSH_1D)(, ##A) + +#define PUSH_NVIM(p,c,m,d) do { \ + struct nvif_push *__p = (p); \ + u32 __d = (d); \ + PUSH_IMMD_HDR(__p, c, m, __d); \ + __p->cur--; \ + PUSH_PRINTF(__p, "%08x-> "#m, __d); \ + __p->cur++; \ +} while(0) +#define PUSH_NVSQ(A...) PUSH(MTHD, ##A) +#define PUSH_NV1I(A...) PUSH(1INC, ##A) +#define PUSH_NVNI(A...) PUSH(NINC, ##A) + + +#define PUSH_NV_1(X,o,p,c,mA,d...) \ + PUSH_##o(p,c,c##_##mA,d) +#define PUSH_NV_2(X,o,p,c,mA,dA,mB,d...) \ + PUSH_##o(p,c,c##_##mA,dA, \ + c##_##mB,d) +#define PUSH_NV_3(X,o,p,c,mA,dA,mB,dB,mC,d...) \ + PUSH_##o(p,c,c##_##mA,dA, \ + c##_##mB,dB, \ + c##_##mC,d) +#define PUSH_NV_4(X,o,p,c,mA,dA,mB,dB,mC,dC,mD,d...) \ + PUSH_##o(p,c,c##_##mA,dA, \ + c##_##mB,dB, \ + c##_##mC,dC, \ + c##_##mD,d) +#define PUSH_NV_5(X,o,p,c,mA,dA,mB,dB,mC,dC,mD,dD,mE,d...) \ + PUSH_##o(p,c,c##_##mA,dA, \ + c##_##mB,dB, \ + c##_##mC,dC, \ + c##_##mD,dD, \ + c##_##mE,d) +#define PUSH_NV_6(X,o,p,c,mA,dA,mB,dB,mC,dC,mD,dD,mE,dE,mF,d...) \ + PUSH_##o(p,c,c##_##mA,dA, \ + c##_##mB,dB, \ + c##_##mC,dC, \ + c##_##mD,dD, \ + c##_##mE,dE, \ + c##_##mF,d) +#define PUSH_NV_7(X,o,p,c,mA,dA,mB,dB,mC,dC,mD,dD,mE,dE,mF,dF,mG,d...) \ + PUSH_##o(p,c,c##_##mA,dA, \ + c##_##mB,dB, \ + c##_##mC,dC, \ + c##_##mD,dD, \ + c##_##mE,dE, \ + c##_##mF,dF, \ + c##_##mG,d) +#define PUSH_NV_8(X,o,p,c,mA,dA,mB,dB,mC,dC,mD,dD,mE,dE,mF,dF,mG,dG,mH,d...) \ + PUSH_##o(p,c,c##_##mA,dA, \ + c##_##mB,dB, \ + c##_##mC,dC, \ + c##_##mD,dD, \ + c##_##mE,dE, \ + c##_##mF,dF, \ + c##_##mG,dG, \ + c##_##mH,d) +#define PUSH_NV_9(X,o,p,c,mA,dA,mB,dB,mC,dC,mD,dD,mE,dE,mF,dF,mG,dG,mH,dH,mI,d...) \ + PUSH_##o(p,c,c##_##mA,dA, \ + c##_##mB,dB, \ + c##_##mC,dC, \ + c##_##mD,dD, \ + c##_##mE,dE, \ + c##_##mF,dF, \ + c##_##mG,dG, \ + c##_##mH,dH, \ + c##_##mI,d) +#define PUSH_NV_10(X,o,p,c,mA,dA,mB,dB,mC,dC,mD,dD,mE,dE,mF,dF,mG,dG,mH,dH,mI,dI,mJ,d...) \ + PUSH_##o(p,c,c##_##mA,dA, \ + c##_##mB,dB, \ + c##_##mC,dC, \ + c##_##mD,dD, \ + c##_##mE,dE, \ + c##_##mF,dF, \ + c##_##mG,dG, \ + c##_##mH,dH, \ + c##_##mI,dI, \ + c##_##mJ,d) + +#define PUSH_NV_(A,B,C,D,E,F,G,H,I,J,K,L,M,N,O,P,Q,R,S,T,U,V,W,X,IMPL,...) IMPL +#define PUSH_NV(A...) PUSH_NV_(A, PUSH_NV_10, PUSH_NV_10, \ + PUSH_NV_9 , PUSH_NV_9, \ + PUSH_NV_8 , PUSH_NV_8, \ + PUSH_NV_7 , PUSH_NV_7, \ + PUSH_NV_6 , PUSH_NV_6, \ + PUSH_NV_5 , PUSH_NV_5, \ + PUSH_NV_4 , PUSH_NV_4, \ + PUSH_NV_3 , PUSH_NV_3, \ + PUSH_NV_2 , PUSH_NV_2, \ + PUSH_NV_1 , PUSH_NV_1)(, ##A) + +#define PUSH_IMMD(A...) PUSH_NV(NVIM, ##A) +#define PUSH_MTHD(A...) PUSH_NV(NVSQ, ##A) +#define PUSH_1INC(A...) PUSH_NV(NV1I, ##A) +#define PUSH_NINC(A...) PUSH_NV(NVNI, ##A) +#endif From bea8395ccf175b599fd3e36df56dd8a67adcea9e Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sun, 21 Jun 2020 10:19:40 +1000 Subject: [PATCH 039/145] drm/nouveau/kms/nv50-: convert wimm point() to new push macros Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/curs507a.c | 6 ++- drivers/gpu/drm/nouveau/dispnv50/cursc37a.c | 6 ++- drivers/gpu/drm/nouveau/dispnv50/wimmc37b.c | 17 ++++--- drivers/gpu/drm/nouveau/dispnv50/wndw.h | 9 +++- .../drm/nouveau/include/nvhw/class/clc37b.h | 49 +++++++++++++++++++ .../gpu/drm/nouveau/include/nvif/pushc37b.h | 18 +++++++ 6 files changed, 93 insertions(+), 12 deletions(-) create mode 100644 drivers/gpu/drm/nouveau/include/nvhw/class/clc37b.h create mode 100644 drivers/gpu/drm/nouveau/include/nvif/pushc37b.h diff --git a/drivers/gpu/drm/nouveau/dispnv50/curs507a.c b/drivers/gpu/drm/nouveau/dispnv50/curs507a.c index 2468e91b36db..babf680c25fd 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/curs507a.c +++ b/drivers/gpu/drm/nouveau/dispnv50/curs507a.c @@ -47,13 +47,15 @@ curs507a_update(struct nv50_wndw *wndw, u32 *interlock) nvif_wr32(&wndw->wimm.base.user, 0x0080, 0x00000000); } -static void +static int curs507a_point(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) { - if (curs507a_space(wndw)) { + int ret = nvif_chan_wait(&wndw->wimm, 1); + if (ret == 0) { nvif_wr32(&wndw->wimm.base.user, 0x0084, asyw->point.y << 16 | asyw->point.x); } + return ret; } const struct nv50_wimm_func diff --git a/drivers/gpu/drm/nouveau/dispnv50/cursc37a.c b/drivers/gpu/drm/nouveau/dispnv50/cursc37a.c index 96dff4f09f57..45c1c33e950a 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/cursc37a.c +++ b/drivers/gpu/drm/nouveau/dispnv50/cursc37a.c @@ -29,13 +29,15 @@ cursc37a_update(struct nv50_wndw *wndw, u32 *interlock) nvif_wr32(&wndw->wimm.base.user, 0x0200, 0x00000001); } -static void +static int cursc37a_point(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) { - if (curs507a_space(wndw)) { + int ret = nvif_chan_wait(&wndw->wimm, 1); + if (ret == 0) { nvif_wr32(&wndw->wimm.base.user, 0x0208, asyw->point.y << 16 | asyw->point.x); } + return ret; } static const struct nv50_wimm_func diff --git a/drivers/gpu/drm/nouveau/dispnv50/wimmc37b.c b/drivers/gpu/drm/nouveau/dispnv50/wimmc37b.c index f7dbd965e4e7..4eb5abfb8ebf 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wimmc37b.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wimmc37b.c @@ -24,6 +24,7 @@ #include "wndw.h" #include +#include static void wimmc37b_update(struct nv50_wndw *wndw, u32 *interlock) @@ -39,15 +40,17 @@ wimmc37b_update(struct nv50_wndw *wndw, u32 *interlock) } } -static void +static int wimmc37b_point(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) { - u32 *push; - if ((push = evo_wait(&wndw->wimm, 2))) { - evo_mthd(push, 0x0208, 1); - evo_data(push, asyw->point.y << 16 | asyw->point.x); - evo_kick(push, &wndw->wimm); - } + struct nvif_push *push = wndw->wimm.push; + int ret; + + if ((ret = PUSH_WAIT(push, 2))) + return ret; + + PUSH_NVSQ(push, NVC37B, 0x0208, asyw->point.y << 16 | asyw->point.x); + return 0; } static const struct nv50_wimm_func diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndw.h b/drivers/gpu/drm/nouveau/dispnv50/wndw.h index a7412b9d3a98..53e496bfbc9d 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndw.h +++ b/drivers/gpu/drm/nouveau/dispnv50/wndw.h @@ -91,7 +91,7 @@ void base907c_csc(struct nv50_wndw *, struct nv50_wndw_atom *, const struct drm_color_ctm *); struct nv50_wimm_func { - void (*point)(struct nv50_wndw *, struct nv50_wndw_atom *); + int (*point)(struct nv50_wndw *, struct nv50_wndw_atom *); void (*update)(struct nv50_wndw *, u32 *interlock); }; @@ -99,6 +99,13 @@ struct nv50_wimm_func { extern const struct nv50_wimm_func curs507a; bool curs507a_space(struct nv50_wndw *); +static inline __must_check int +nvif_chan_wait(struct nv50_dmac *dmac, u32 size) +{ + struct nv50_wndw *wndw = container_of(dmac, typeof(*wndw), wimm); + return curs507a_space(wndw) ? 0 : -ETIMEDOUT; +} + int wndwc37e_new(struct nouveau_drm *, enum drm_plane_type, int, s32, struct nv50_wndw **); int wndwc37e_new_(const struct nv50_wndw_func *, struct nouveau_drm *, diff --git a/drivers/gpu/drm/nouveau/include/nvhw/class/clc37b.h b/drivers/gpu/drm/nouveau/include/nvhw/class/clc37b.h new file mode 100644 index 000000000000..0f7323bfa09b --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvhw/class/clc37b.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 1993-2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _clC37b_h_ +#define _clC37b_h_ + +// dma opcode instructions +#define NVC37B_DMA +#define NVC37B_DMA_OPCODE 31:29 +#define NVC37B_DMA_OPCODE_METHOD 0x00000000 +#define NVC37B_DMA_OPCODE_JUMP 0x00000001 +#define NVC37B_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NVC37B_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NVC37B_DMA_METHOD_COUNT 27:18 +#define NVC37B_DMA_METHOD_OFFSET 13:2 +#define NVC37B_DMA_DATA 31:0 +#define NVC37B_DMA_DATA_NOP 0x00000000 +#define NVC37B_DMA_JUMP_OFFSET 11:2 +#define NVC37B_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// class methods +#define NVC37B_UPDATE (0x00000200) +#define NVC37B_UPDATE_INTERLOCK_WITH_WINDOW 1:1 +#define NVC37B_UPDATE_INTERLOCK_WITH_WINDOW_DISABLE (0x00000000) +#define NVC37B_UPDATE_INTERLOCK_WITH_WINDOW_ENABLE (0x00000001) +#define NVC37B_SET_POINT_OUT(b) (0x00000208 + (b)*0x00000004) +#define NVC37B_SET_POINT_OUT_X 15:0 +#define NVC37B_SET_POINT_OUT_Y 31:16 +#endif // _clC37b_h diff --git a/drivers/gpu/drm/nouveau/include/nvif/pushc37b.h b/drivers/gpu/drm/nouveau/include/nvif/pushc37b.h new file mode 100644 index 000000000000..8f0c45703e33 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvif/pushc37b.h @@ -0,0 +1,18 @@ +#ifndef __NVIF_PUSHC37B_H__ +#define __NVIF_PUSHC37B_H__ +#include + +#include + +#define PUSH_HDR(p,m,c) do { \ + PUSH_ASSERT(!((m) & ~DRF_SMASK(NVC37B_DMA_METHOD_OFFSET)), "mthd"); \ + PUSH_ASSERT(!((c) & ~DRF_MASK(NVC37B_DMA_METHOD_COUNT)), "size"); \ + PUSH_DATA__((p), NVDEF(NVC37B, DMA, OPCODE, METHOD) | \ + NVVAL(NVC37B, DMA, METHOD_COUNT, (c)) | \ + NVVAL(NVC37B, DMA, METHOD_OFFSET, (m) >> 2), \ + " mthd 0x%04x size %d - %s", (u32)(m), (u32)(c), __func__); \ +} while(0) + +#define PUSH_MTHD_HDR(p,s,m,c) PUSH_HDR(p,m,c) +#define PUSH_MTHD_INC 4:4 +#endif From 9659be21e8034528839216b21794da73fdbedec2 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sun, 21 Jun 2020 10:22:35 +1000 Subject: [PATCH 040/145] drm/nouveau/kms/nv50-: convert wimm update() to new push macros Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/curs507a.c | 6 ++++-- drivers/gpu/drm/nouveau/dispnv50/cursc37a.c | 6 ++++-- drivers/gpu/drm/nouveau/dispnv50/wimmc37b.c | 21 +++++++++++---------- drivers/gpu/drm/nouveau/dispnv50/wndw.h | 2 +- 4 files changed, 20 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/curs507a.c b/drivers/gpu/drm/nouveau/dispnv50/curs507a.c index babf680c25fd..47f6f01b52a0 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/curs507a.c +++ b/drivers/gpu/drm/nouveau/dispnv50/curs507a.c @@ -40,11 +40,13 @@ curs507a_space(struct nv50_wndw *wndw) return false; } -static void +static int curs507a_update(struct nv50_wndw *wndw, u32 *interlock) { - if (curs507a_space(wndw)) + int ret = nvif_chan_wait(&wndw->wimm, 1); + if (ret == 0) nvif_wr32(&wndw->wimm.base.user, 0x0080, 0x00000000); + return ret; } static int diff --git a/drivers/gpu/drm/nouveau/dispnv50/cursc37a.c b/drivers/gpu/drm/nouveau/dispnv50/cursc37a.c index 45c1c33e950a..9d96a246b39a 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/cursc37a.c +++ b/drivers/gpu/drm/nouveau/dispnv50/cursc37a.c @@ -22,11 +22,13 @@ #include "curs.h" #include "atom.h" -static void +static int cursc37a_update(struct nv50_wndw *wndw, u32 *interlock) { - if (curs507a_space(wndw)) + int ret = nvif_chan_wait(&wndw->wimm, 1); + if (ret == 0) nvif_wr32(&wndw->wimm.base.user, 0x0200, 0x00000001); + return ret; } static int diff --git a/drivers/gpu/drm/nouveau/dispnv50/wimmc37b.c b/drivers/gpu/drm/nouveau/dispnv50/wimmc37b.c index 4eb5abfb8ebf..c2009d477736 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wimmc37b.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wimmc37b.c @@ -26,18 +26,19 @@ #include #include -static void +static int wimmc37b_update(struct nv50_wndw *wndw, u32 *interlock) { - u32 *push; - if ((push = evo_wait(&wndw->wimm, 2))) { - evo_mthd(push, 0x0200, 1); - if (interlock[NV50_DISP_INTERLOCK_WNDW] & wndw->interlock.data) - evo_data(push, 0x00000003); - else - evo_data(push, 0x00000001); - evo_kick(push, &wndw->wimm); - } + struct nvif_push *push = wndw->wimm.push; + int ret; + + if ((ret = PUSH_WAIT(push, 2))) + return ret; + + PUSH_NVSQ(push, NVC37B, 0x0200, ((interlock[NV50_DISP_INTERLOCK_WNDW] & + wndw->interlock.data) ? 0x00000002 : 0x00000000) | + 0x00000001); + return PUSH_KICK(push); } static int diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndw.h b/drivers/gpu/drm/nouveau/dispnv50/wndw.h index 53e496bfbc9d..ce1b2baf9d19 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndw.h +++ b/drivers/gpu/drm/nouveau/dispnv50/wndw.h @@ -93,7 +93,7 @@ void base907c_csc(struct nv50_wndw *, struct nv50_wndw_atom *, struct nv50_wimm_func { int (*point)(struct nv50_wndw *, struct nv50_wndw_atom *); - void (*update)(struct nv50_wndw *, u32 *interlock); + int (*update)(struct nv50_wndw *, u32 *interlock); }; extern const struct nv50_wimm_func curs507a; From 34cf8cae288e3d2cee08ab17fe458aec636d9def Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sat, 20 Jun 2020 07:57:12 +1000 Subject: [PATCH 041/145] drm/nouveau/kms/nv50-: convert wndw sema_set() to new push macros Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/base.h | 2 +- drivers/gpu/drm/nouveau/dispnv50/base507c.c | 23 +-- drivers/gpu/drm/nouveau/dispnv50/wndw.h | 4 +- drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c | 23 +-- .../drm/nouveau/include/nvhw/class/cl507c.h | 165 ++++++++++++++++++ .../gpu/drm/nouveau/include/nvif/push507c.h | 25 +++ 6 files changed, 219 insertions(+), 23 deletions(-) create mode 100644 drivers/gpu/drm/nouveau/include/nvhw/class/cl507c.h create mode 100644 drivers/gpu/drm/nouveau/include/nvif/push507c.h diff --git a/drivers/gpu/drm/nouveau/dispnv50/base.h b/drivers/gpu/drm/nouveau/dispnv50/base.h index e7f14f230f35..a3e4e50c1558 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/base.h +++ b/drivers/gpu/drm/nouveau/dispnv50/base.h @@ -11,7 +11,7 @@ int base507c_acquire(struct nv50_wndw *, struct nv50_wndw_atom *, struct nv50_head_atom *); void base507c_release(struct nv50_wndw *, struct nv50_wndw_atom *, struct nv50_head_atom *); -void base507c_sema_set(struct nv50_wndw *, struct nv50_wndw_atom *); +int base507c_sema_set(struct nv50_wndw *, struct nv50_wndw_atom *); void base507c_sema_clr(struct nv50_wndw *); void base507c_ntfy_set(struct nv50_wndw *, struct nv50_wndw_atom *); void base507c_ntfy_clr(struct nv50_wndw *); diff --git a/drivers/gpu/drm/nouveau/dispnv50/base507c.c b/drivers/gpu/drm/nouveau/dispnv50/base507c.c index c37f2278ce3e..ed0e5ce2190c 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/base507c.c +++ b/drivers/gpu/drm/nouveau/dispnv50/base507c.c @@ -23,6 +23,7 @@ #include #include +#include #include #include @@ -163,18 +164,20 @@ base507c_sema_clr(struct nv50_wndw *wndw) } } -void +int base507c_sema_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) { - u32 *push; - if ((push = evo_wait(&wndw->wndw, 5))) { - evo_mthd(push, 0x0088, 4); - evo_data(push, asyw->sema.offset); - evo_data(push, asyw->sema.acquire); - evo_data(push, asyw->sema.release); - evo_data(push, asyw->sema.handle); - evo_kick(push, &wndw->wndw); - } + struct nvif_push *push = wndw->wndw.push; + int ret; + + if ((ret = PUSH_WAIT(push, 5))) + return ret; + + PUSH_NVSQ(push, NV507C, 0x0088, asyw->sema.offset, + 0x008c, asyw->sema.acquire, + 0x0090, asyw->sema.release, + 0x0094, asyw->sema.handle); + return 0; } void diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndw.h b/drivers/gpu/drm/nouveau/dispnv50/wndw.h index ce1b2baf9d19..419cc30b3c64 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndw.h +++ b/drivers/gpu/drm/nouveau/dispnv50/wndw.h @@ -57,7 +57,7 @@ struct nv50_wndw_func { void (*prepare)(struct nv50_wndw *, struct nv50_head_atom *asyh, struct nv50_wndw_atom *asyw); - void (*sema_set)(struct nv50_wndw *, struct nv50_wndw_atom *); + int (*sema_set)(struct nv50_wndw *, struct nv50_wndw_atom *); void (*sema_clr)(struct nv50_wndw *); void (*ntfy_reset)(struct nouveau_bo *, u32 offset); void (*ntfy_set)(struct nv50_wndw *, struct nv50_wndw_atom *); @@ -115,7 +115,7 @@ int wndwc37e_acquire(struct nv50_wndw *, struct nv50_wndw_atom *, struct nv50_head_atom *); void wndwc37e_release(struct nv50_wndw *, struct nv50_wndw_atom *, struct nv50_head_atom *); -void wndwc37e_sema_set(struct nv50_wndw *, struct nv50_wndw_atom *); +int wndwc37e_sema_set(struct nv50_wndw *, struct nv50_wndw_atom *); void wndwc37e_sema_clr(struct nv50_wndw *); void wndwc37e_ntfy_set(struct nv50_wndw *, struct nv50_wndw_atom *); void wndwc37e_ntfy_clr(struct nv50_wndw *); diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c index bb84e4d54a33..c135eeeeed22 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c @@ -27,6 +27,7 @@ #include #include +#include static void wndwc37e_csc_clr(struct nv50_wndw *wndw) @@ -185,18 +186,20 @@ wndwc37e_sema_clr(struct nv50_wndw *wndw) } } -void +int wndwc37e_sema_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) { - u32 *push; - if ((push = evo_wait(&wndw->wndw, 5))) { - evo_mthd(push, 0x020c, 4); - evo_data(push, asyw->sema.offset); - evo_data(push, asyw->sema.acquire); - evo_data(push, asyw->sema.release); - evo_data(push, asyw->sema.handle); - evo_kick(push, &wndw->wndw); - } + struct nvif_push *push = wndw->wndw.push; + int ret; + + if ((ret = PUSH_WAIT(push, 5))) + return ret; + + PUSH_NVSQ(push, NVC37E, 0x020c, asyw->sema.offset, + 0x0210, asyw->sema.acquire, + 0x0214, asyw->sema.release, + 0x0218, asyw->sema.handle); + return 0; } void diff --git a/drivers/gpu/drm/nouveau/include/nvhw/class/cl507c.h b/drivers/gpu/drm/nouveau/include/nvhw/class/cl507c.h new file mode 100644 index 000000000000..ada17015daf2 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvhw/class/cl507c.h @@ -0,0 +1,165 @@ +/* + * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl507c_h_ +#define _cl507c_h_ + +#define NV_DISP_BASE_NOTIFIER_1 0x00000000 +#define NV_DISP_BASE_NOTIFIER_1_SIZEOF 0x00000004 +#define NV_DISP_BASE_NOTIFIER_1__0 0x00000000 +#define NV_DISP_BASE_NOTIFIER_1__0_PRESENTATION_COUNT 15:0 +#define NV_DISP_BASE_NOTIFIER_1__0_TIMESTAMP 29:16 +#define NV_DISP_BASE_NOTIFIER_1__0_STATUS 31:30 +#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_NOT_BEGUN 0x00000000 +#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_BEGUN 0x00000001 +#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_FINISHED 0x00000002 + + +// dma opcode instructions +#define NV507C_DMA 0x00000000 +#define NV507C_DMA_OPCODE 31:29 +#define NV507C_DMA_OPCODE_METHOD 0x00000000 +#define NV507C_DMA_OPCODE_JUMP 0x00000001 +#define NV507C_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV507C_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV507C_DMA_OPCODE 31:29 +#define NV507C_DMA_OPCODE_METHOD 0x00000000 +#define NV507C_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV507C_DMA_METHOD_COUNT 27:18 +#define NV507C_DMA_METHOD_OFFSET 11:2 +#define NV507C_DMA_DATA 31:0 +#define NV507C_DMA_NOP 0x00000000 +#define NV507C_DMA_OPCODE 31:29 +#define NV507C_DMA_OPCODE_JUMP 0x00000001 +#define NV507C_DMA_JUMP_OFFSET 11:2 +#define NV507C_DMA_OPCODE 31:29 +#define NV507C_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV507C_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// class methods +#define NV507C_PUT (0x00000000) +#define NV507C_PUT_PTR 11:2 +#define NV507C_GET (0x00000004) +#define NV507C_GET_PTR 11:2 +#define NV507C_UPDATE (0x00000080) +#define NV507C_UPDATE_INTERLOCK_WITH_CORE 0:0 +#define NV507C_UPDATE_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NV507C_UPDATE_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NV507C_SET_PRESENT_CONTROL (0x00000084) +#define NV507C_SET_PRESENT_CONTROL_BEGIN_MODE 9:8 +#define NV507C_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING (0x00000000) +#define NV507C_SET_PRESENT_CONTROL_BEGIN_MODE_IMMEDIATE (0x00000001) +#define NV507C_SET_PRESENT_CONTROL_BEGIN_MODE_ON_LINE (0x00000002) +#define NV507C_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 7:4 +#define NV507C_SET_PRESENT_CONTROL_BEGIN_LINE 30:16 +#define NV507C_SET_PRESENT_CONTROL_ON_LINE_MARGIN 15:10 +#define NV507C_SET_SEMAPHORE_CONTROL (0x00000088) +#define NV507C_SET_SEMAPHORE_CONTROL_OFFSET 11:2 +#define NV507C_SET_SEMAPHORE_ACQUIRE (0x0000008C) +#define NV507C_SET_SEMAPHORE_ACQUIRE_VALUE 31:0 +#define NV507C_SET_SEMAPHORE_RELEASE (0x00000090) +#define NV507C_SET_SEMAPHORE_RELEASE_VALUE 31:0 +#define NV507C_SET_CONTEXT_DMA_SEMAPHORE (0x00000094) +#define NV507C_SET_CONTEXT_DMA_SEMAPHORE_HANDLE 31:0 +#define NV507C_SET_NOTIFIER_CONTROL (0x000000A0) +#define NV507C_SET_NOTIFIER_CONTROL_MODE 30:30 +#define NV507C_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000) +#define NV507C_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001) +#define NV507C_SET_NOTIFIER_CONTROL_OFFSET 11:2 +#define NV507C_SET_CONTEXT_DMA_NOTIFIER (0x000000A4) +#define NV507C_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0 +#define NV507C_SET_CONTEXT_DMA_ISO (0x000000C0) +#define NV507C_SET_CONTEXT_DMA_ISO_HANDLE 31:0 +#define NV507C_SET_BASE_LUT_LO (0x000000E0) +#define NV507C_SET_BASE_LUT_LO_ENABLE 31:30 +#define NV507C_SET_BASE_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV507C_SET_BASE_LUT_LO_ENABLE_USE_CORE_LUT (0x00000001) +#define NV507C_SET_BASE_LUT_LO_ENABLE_ENABLE (0x00000003) +#define NV507C_SET_BASE_LUT_LO_MODE 29:29 +#define NV507C_SET_BASE_LUT_LO_MODE_LORES (0x00000000) +#define NV507C_SET_BASE_LUT_LO_MODE_HIRES (0x00000001) +#define NV507C_SET_BASE_LUT_LO_ORIGIN 7:2 +#define NV507C_SET_PROCESSING (0x00000110) +#define NV507C_SET_PROCESSING_USE_GAIN_OFS 0:0 +#define NV507C_SET_PROCESSING_USE_GAIN_OFS_DISABLE (0x00000000) +#define NV507C_SET_PROCESSING_USE_GAIN_OFS_ENABLE (0x00000001) +#define NV507C_SET_CONVERSION (0x00000114) +#define NV507C_SET_CONVERSION_GAIN 15:0 +#define NV507C_SET_CONVERSION_OFS 31:16 + +#define NV507C_SURFACE_SET_OFFSET(a,b) (0x00000800 + (a)*0x00000020 + (b)*0x00000004) +#define NV507C_SURFACE_SET_OFFSET_ORIGIN 31:0 +#define NV507C_SURFACE_SET_SIZE(a) (0x00000808 + (a)*0x00000020) +#define NV507C_SURFACE_SET_SIZE_WIDTH 14:0 +#define NV507C_SURFACE_SET_SIZE_HEIGHT 30:16 +#define NV507C_SURFACE_SET_STORAGE(a) (0x0000080C + (a)*0x00000020) +#define NV507C_SURFACE_SET_STORAGE_BLOCK_HEIGHT 3:0 +#define NV507C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB (0x00000000) +#define NV507C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS (0x00000001) +#define NV507C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS (0x00000002) +#define NV507C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003) +#define NV507C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NV507C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NV507C_SURFACE_SET_STORAGE_PITCH 17:8 +#define NV507C_SURFACE_SET_STORAGE_MEMORY_LAYOUT 20:20 +#define NV507C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NV507C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001) +#define NV507C_SURFACE_SET_PARAMS(a) (0x00000810 + (a)*0x00000020) +#define NV507C_SURFACE_SET_PARAMS_FORMAT 15:8 +#define NV507C_SURFACE_SET_PARAMS_FORMAT_I8 (0x0000001E) +#define NV507C_SURFACE_SET_PARAMS_FORMAT_VOID16 (0x0000001F) +#define NV507C_SURFACE_SET_PARAMS_FORMAT_VOID32 (0x0000002E) +#define NV507C_SURFACE_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA) +#define NV507C_SURFACE_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF) +#define NV507C_SURFACE_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1) +#define NV507C_SURFACE_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5) +#define NV507C_SURFACE_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8) +#define NV507C_SURFACE_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9) +#define NV507C_SURFACE_SET_PARAMS_SUPER_SAMPLE 1:0 +#define NV507C_SURFACE_SET_PARAMS_SUPER_SAMPLE_X1_AA (0x00000000) +#define NV507C_SURFACE_SET_PARAMS_SUPER_SAMPLE_X4_AA (0x00000002) +#define NV507C_SURFACE_SET_PARAMS_GAMMA 2:2 +#define NV507C_SURFACE_SET_PARAMS_GAMMA_LINEAR (0x00000000) +#define NV507C_SURFACE_SET_PARAMS_GAMMA_SRGB (0x00000001) +#define NV507C_SURFACE_SET_PARAMS_LAYOUT 5:4 +#define NV507C_SURFACE_SET_PARAMS_LAYOUT_FRM (0x00000000) +#define NV507C_SURFACE_SET_PARAMS_LAYOUT_FLD1 (0x00000001) +#define NV507C_SURFACE_SET_PARAMS_LAYOUT_FLD2 (0x00000002) +#define NV507C_SURFACE_SET_PARAMS_KIND 22:16 +#define NV507C_SURFACE_SET_PARAMS_KIND_KIND_PITCH (0x00000000) +#define NV507C_SURFACE_SET_PARAMS_KIND_KIND_GENERIC_8BX2 (0x00000070) +#define NV507C_SURFACE_SET_PARAMS_KIND_KIND_GENERIC_8BX2_BANKSWIZ (0x00000072) +#define NV507C_SURFACE_SET_PARAMS_KIND_KIND_GENERIC_16BX1 (0x00000074) +#define NV507C_SURFACE_SET_PARAMS_KIND_KIND_GENERIC_16BX1_BANKSWIZ (0x00000076) +#define NV507C_SURFACE_SET_PARAMS_KIND_KIND_C32_MS4 (0x00000078) +#define NV507C_SURFACE_SET_PARAMS_KIND_KIND_C32_MS8 (0x00000079) +#define NV507C_SURFACE_SET_PARAMS_KIND_KIND_C32_MS4_BANKSWIZ (0x0000007A) +#define NV507C_SURFACE_SET_PARAMS_KIND_KIND_C32_MS8_BANKSWIZ (0x0000007B) +#define NV507C_SURFACE_SET_PARAMS_KIND_KIND_C64_MS4 (0x0000007C) +#define NV507C_SURFACE_SET_PARAMS_KIND_KIND_C64_MS8 (0x0000007D) +#define NV507C_SURFACE_SET_PARAMS_KIND_KIND_C128_MS4 (0x0000007E) +#define NV507C_SURFACE_SET_PARAMS_KIND_FROM_PTE (0x0000007F) +#define NV507C_SURFACE_SET_PARAMS_PART_STRIDE 24:24 +#define NV507C_SURFACE_SET_PARAMS_PART_STRIDE_PARTSTRIDE_256 (0x00000000) +#define NV507C_SURFACE_SET_PARAMS_PART_STRIDE_PARTSTRIDE_1024 (0x00000001) +#endif // _cl507c_h diff --git a/drivers/gpu/drm/nouveau/include/nvif/push507c.h b/drivers/gpu/drm/nouveau/include/nvif/push507c.h new file mode 100644 index 000000000000..889467f13fd9 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvif/push507c.h @@ -0,0 +1,25 @@ +#ifndef __NVIF_PUSH507C_H__ +#define __NVIF_PUSH507C_H__ +#include + +#include + +#define PUSH_HDR(p,m,c) do { \ + PUSH_ASSERT(!((m) & ~DRF_SMASK(NV507C_DMA_METHOD_OFFSET)), "mthd"); \ + PUSH_ASSERT(!((c) & ~DRF_MASK(NV507C_DMA_METHOD_COUNT)), "size"); \ + PUSH_DATA__((p), NVDEF(NV507C, DMA, OPCODE, METHOD) | \ + NVVAL(NV507C, DMA, METHOD_COUNT, (c)) | \ + NVVAL(NV507C, DMA, METHOD_OFFSET, (m) >> 2), \ + " mthd 0x%04x size %d - %s", (u32)(m), (u32)(c), __func__); \ +} while(0) + +#define PUSH_MTHD_HDR(p,s,m,c) PUSH_HDR(p,m,c) +#define PUSH_MTHD_INC 4:4 + +#define PUSH_JUMP(p,o) do { \ + PUSH_ASSERT(!((o) & ~DRF_SMASK(NV507C_DMA_JUMP_OFFSET)), "offset"); \ + PUSH_DATA__((p), NVDEF(NV507C, DMA, OPCODE, JUMP) | \ + NVVAL(NV507C, DMA, JUMP_OFFSET, (o) >> 2), \ + "jump 0x%08x - %s", (u32)(o), __func__); \ +} while(0) +#endif From c686051a5a01ed7d14ff652229af02c545d9895c Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sat, 20 Jun 2020 08:04:01 +1000 Subject: [PATCH 042/145] drm/nouveau/kms/nv50-: convert wndw sema_clr() to new push macros Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/base.h | 2 +- drivers/gpu/drm/nouveau/dispnv50/base507c.c | 16 +++++++++------- drivers/gpu/drm/nouveau/dispnv50/wndw.h | 4 ++-- drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c | 16 +++++++++------- 4 files changed, 21 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/base.h b/drivers/gpu/drm/nouveau/dispnv50/base.h index a3e4e50c1558..c59fd620f392 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/base.h +++ b/drivers/gpu/drm/nouveau/dispnv50/base.h @@ -12,7 +12,7 @@ int base507c_acquire(struct nv50_wndw *, struct nv50_wndw_atom *, void base507c_release(struct nv50_wndw *, struct nv50_wndw_atom *, struct nv50_head_atom *); int base507c_sema_set(struct nv50_wndw *, struct nv50_wndw_atom *); -void base507c_sema_clr(struct nv50_wndw *); +int base507c_sema_clr(struct nv50_wndw *); void base507c_ntfy_set(struct nv50_wndw *, struct nv50_wndw_atom *); void base507c_ntfy_clr(struct nv50_wndw *); void base507c_xlut_set(struct nv50_wndw *, struct nv50_wndw_atom *); diff --git a/drivers/gpu/drm/nouveau/dispnv50/base507c.c b/drivers/gpu/drm/nouveau/dispnv50/base507c.c index ed0e5ce2190c..c9c920358d95 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/base507c.c +++ b/drivers/gpu/drm/nouveau/dispnv50/base507c.c @@ -153,15 +153,17 @@ base507c_ntfy_reset(struct nouveau_bo *bo, u32 offset) nouveau_bo_wr32(bo, offset / 4, 0x00000000); } -void +int base507c_sema_clr(struct nv50_wndw *wndw) { - u32 *push; - if ((push = evo_wait(&wndw->wndw, 2))) { - evo_mthd(push, 0x0094, 1); - evo_data(push, 0x00000000); - evo_kick(push, &wndw->wndw); - } + struct nvif_push *push = wndw->wndw.push; + int ret; + + if ((ret = PUSH_WAIT(push, 2))) + return ret; + + PUSH_NVSQ(push, NV507C, 0x0094, 0x00000000); + return 0; } int diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndw.h b/drivers/gpu/drm/nouveau/dispnv50/wndw.h index 419cc30b3c64..84bd402f935c 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndw.h +++ b/drivers/gpu/drm/nouveau/dispnv50/wndw.h @@ -58,7 +58,7 @@ struct nv50_wndw_func { struct nv50_wndw_atom *asyw); int (*sema_set)(struct nv50_wndw *, struct nv50_wndw_atom *); - void (*sema_clr)(struct nv50_wndw *); + int (*sema_clr)(struct nv50_wndw *); void (*ntfy_reset)(struct nouveau_bo *, u32 offset); void (*ntfy_set)(struct nv50_wndw *, struct nv50_wndw_atom *); void (*ntfy_clr)(struct nv50_wndw *); @@ -116,7 +116,7 @@ int wndwc37e_acquire(struct nv50_wndw *, struct nv50_wndw_atom *, void wndwc37e_release(struct nv50_wndw *, struct nv50_wndw_atom *, struct nv50_head_atom *); int wndwc37e_sema_set(struct nv50_wndw *, struct nv50_wndw_atom *); -void wndwc37e_sema_clr(struct nv50_wndw *); +int wndwc37e_sema_clr(struct nv50_wndw *); void wndwc37e_ntfy_set(struct nv50_wndw *, struct nv50_wndw_atom *); void wndwc37e_ntfy_clr(struct nv50_wndw *); void wndwc37e_image_clr(struct nv50_wndw *); diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c index c135eeeeed22..965807f8b635 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c @@ -175,15 +175,17 @@ wndwc37e_ntfy_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) } } -void +int wndwc37e_sema_clr(struct nv50_wndw *wndw) { - u32 *push; - if ((push = evo_wait(&wndw->wndw, 2))) { - evo_mthd(push, 0x0218, 1); - evo_data(push, 0x00000000); - evo_kick(push, &wndw->wndw); - } + struct nvif_push *push = wndw->wndw.push; + int ret; + + if ((ret = PUSH_WAIT(push, 2))) + return ret; + + PUSH_NVSQ(push, NVC37E, 0x0218, 0x00000000); + return 0; } int From fe8a2eec7dd654636102dfe348aa9d37971133be Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sat, 20 Jun 2020 08:29:31 +1000 Subject: [PATCH 043/145] drm/nouveau/kms/nv50-: convert wndw ntfy_set() to new push macros Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/base.h | 1 - drivers/gpu/drm/nouveau/dispnv50/base507c.c | 19 +++++++++++-------- drivers/gpu/drm/nouveau/dispnv50/ovly.h | 1 - drivers/gpu/drm/nouveau/dispnv50/ovly507e.c | 14 +------------- drivers/gpu/drm/nouveau/dispnv50/ovly827e.c | 2 +- drivers/gpu/drm/nouveau/dispnv50/ovly907e.c | 2 +- drivers/gpu/drm/nouveau/dispnv50/wndw.h | 5 +++-- drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c | 19 +++++++++++-------- 8 files changed, 28 insertions(+), 35 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/base.h b/drivers/gpu/drm/nouveau/dispnv50/base.h index c59fd620f392..a93e2e314640 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/base.h +++ b/drivers/gpu/drm/nouveau/dispnv50/base.h @@ -13,7 +13,6 @@ void base507c_release(struct nv50_wndw *, struct nv50_wndw_atom *, struct nv50_head_atom *); int base507c_sema_set(struct nv50_wndw *, struct nv50_wndw_atom *); int base507c_sema_clr(struct nv50_wndw *); -void base507c_ntfy_set(struct nv50_wndw *, struct nv50_wndw_atom *); void base507c_ntfy_clr(struct nv50_wndw *); void base507c_xlut_set(struct nv50_wndw *, struct nv50_wndw_atom *); void base507c_xlut_clr(struct nv50_wndw *); diff --git a/drivers/gpu/drm/nouveau/dispnv50/base507c.c b/drivers/gpu/drm/nouveau/dispnv50/base507c.c index c9c920358d95..d0d6a5056171 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/base507c.c +++ b/drivers/gpu/drm/nouveau/dispnv50/base507c.c @@ -135,16 +135,19 @@ base507c_ntfy_clr(struct nv50_wndw *wndw) } } -void +int base507c_ntfy_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) { - u32 *push; - if ((push = evo_wait(&wndw->wndw, 3))) { - evo_mthd(push, 0x00a0, 2); - evo_data(push, asyw->ntfy.awaken << 30 | asyw->ntfy.offset); - evo_data(push, asyw->ntfy.handle); - evo_kick(push, &wndw->wndw); - } + struct nvif_push *push = wndw->wndw.push; + int ret; + + if ((ret = PUSH_WAIT(push, 3))) + return ret; + + PUSH_NVSQ(push, NV507C, 0x00a0, asyw->ntfy.awaken << 30 | + asyw->ntfy.offset, + 0x00a4, asyw->ntfy.handle); + return 0; } void diff --git a/drivers/gpu/drm/nouveau/dispnv50/ovly.h b/drivers/gpu/drm/nouveau/dispnv50/ovly.h index 4869d52d1786..dee606213d27 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/ovly.h +++ b/drivers/gpu/drm/nouveau/dispnv50/ovly.h @@ -10,7 +10,6 @@ int ovly507e_acquire(struct nv50_wndw *, struct nv50_wndw_atom *, struct nv50_head_atom *); void ovly507e_release(struct nv50_wndw *, struct nv50_wndw_atom *, struct nv50_head_atom *); -void ovly507e_ntfy_set(struct nv50_wndw *, struct nv50_wndw_atom *); void ovly507e_ntfy_clr(struct nv50_wndw *); void ovly507e_image_clr(struct nv50_wndw *); void ovly507e_scale_set(struct nv50_wndw *, struct nv50_wndw_atom *); diff --git a/drivers/gpu/drm/nouveau/dispnv50/ovly507e.c b/drivers/gpu/drm/nouveau/dispnv50/ovly507e.c index 1371225996e9..91ea3ea3e7fa 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/ovly507e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/ovly507e.c @@ -103,18 +103,6 @@ ovly507e_ntfy_clr(struct nv50_wndw *wndw) } } -void -ovly507e_ntfy_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) -{ - u32 *push; - if ((push = evo_wait(&wndw->wndw, 3))) { - evo_mthd(push, 0x00a0, 2); - evo_data(push, asyw->ntfy.awaken << 30 | asyw->ntfy.offset); - evo_data(push, asyw->ntfy.handle); - evo_kick(push, &wndw->wndw); - } -} - void ovly507e_release(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw, struct nv50_head_atom *asyh) @@ -146,7 +134,7 @@ static const struct nv50_wndw_func ovly507e = { .acquire = ovly507e_acquire, .release = ovly507e_release, - .ntfy_set = ovly507e_ntfy_set, + .ntfy_set = base507c_ntfy_set, .ntfy_clr = ovly507e_ntfy_clr, .ntfy_reset = base507c_ntfy_reset, .ntfy_wait_begun = base507c_ntfy_wait_begun, diff --git a/drivers/gpu/drm/nouveau/dispnv50/ovly827e.c b/drivers/gpu/drm/nouveau/dispnv50/ovly827e.c index 4f7ce57f2036..72a4117529e5 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/ovly827e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/ovly827e.c @@ -77,7 +77,7 @@ static const struct nv50_wndw_func ovly827e = { .acquire = ovly507e_acquire, .release = ovly507e_release, - .ntfy_set = ovly507e_ntfy_set, + .ntfy_set = base507c_ntfy_set, .ntfy_clr = ovly507e_ntfy_clr, .ntfy_reset = ovly827e_ntfy_reset, .ntfy_wait_begun = ovly827e_ntfy_wait_begun, diff --git a/drivers/gpu/drm/nouveau/dispnv50/ovly907e.c b/drivers/gpu/drm/nouveau/dispnv50/ovly907e.c index 9efe5e9d5ce4..255a8415eb45 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/ovly907e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/ovly907e.c @@ -51,7 +51,7 @@ const struct nv50_wndw_func ovly907e = { .acquire = ovly507e_acquire, .release = ovly507e_release, - .ntfy_set = ovly507e_ntfy_set, + .ntfy_set = base507c_ntfy_set, .ntfy_clr = ovly507e_ntfy_clr, .ntfy_reset = ovly827e_ntfy_reset, .ntfy_wait_begun = ovly827e_ntfy_wait_begun, diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndw.h b/drivers/gpu/drm/nouveau/dispnv50/wndw.h index 84bd402f935c..6c994461ea63 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndw.h +++ b/drivers/gpu/drm/nouveau/dispnv50/wndw.h @@ -60,7 +60,7 @@ struct nv50_wndw_func { int (*sema_set)(struct nv50_wndw *, struct nv50_wndw_atom *); int (*sema_clr)(struct nv50_wndw *); void (*ntfy_reset)(struct nouveau_bo *, u32 offset); - void (*ntfy_set)(struct nv50_wndw *, struct nv50_wndw_atom *); + int (*ntfy_set)(struct nv50_wndw *, struct nv50_wndw_atom *); void (*ntfy_clr)(struct nv50_wndw *); int (*ntfy_wait_begun)(struct nouveau_bo *, u32 offset, struct nvif_device *); @@ -85,6 +85,7 @@ struct nv50_wndw_func { extern const struct drm_plane_funcs nv50_wndw; void base507c_ntfy_reset(struct nouveau_bo *, u32); +int base507c_ntfy_set(struct nv50_wndw *, struct nv50_wndw_atom *); int base507c_ntfy_wait_begun(struct nouveau_bo *, u32, struct nvif_device *); void base907c_csc(struct nv50_wndw *, struct nv50_wndw_atom *, @@ -117,7 +118,7 @@ void wndwc37e_release(struct nv50_wndw *, struct nv50_wndw_atom *, struct nv50_head_atom *); int wndwc37e_sema_set(struct nv50_wndw *, struct nv50_wndw_atom *); int wndwc37e_sema_clr(struct nv50_wndw *); -void wndwc37e_ntfy_set(struct nv50_wndw *, struct nv50_wndw_atom *); +int wndwc37e_ntfy_set(struct nv50_wndw *, struct nv50_wndw_atom *); void wndwc37e_ntfy_clr(struct nv50_wndw *); void wndwc37e_image_clr(struct nv50_wndw *); void wndwc37e_blend_set(struct nv50_wndw *, struct nv50_wndw_atom *); diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c index 965807f8b635..9738205949bf 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c @@ -163,16 +163,19 @@ wndwc37e_ntfy_clr(struct nv50_wndw *wndw) } } -void +int wndwc37e_ntfy_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) { - u32 *push; - if ((push = evo_wait(&wndw->wndw, 3))) { - evo_mthd(push, 0x021c, 2); - evo_data(push, asyw->ntfy.handle); - evo_data(push, asyw->ntfy.offset | asyw->ntfy.awaken); - evo_kick(push, &wndw->wndw); - } + struct nvif_push *push = wndw->wndw.push; + int ret; + + if ((ret = PUSH_WAIT(push, 3))) + return ret; + + PUSH_NVSQ(push, NVC37E, 0x021c, asyw->ntfy.handle, + 0x0220, asyw->ntfy.offset | + asyw->ntfy.awaken); + return 0; } int From bcae99c282aad70d5aaf7b34f878c465a675089e Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sat, 20 Jun 2020 08:32:28 +1000 Subject: [PATCH 044/145] drm/nouveau/kms/nv50-: convert wndw ntfy_clr() to new push macros Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/base.h | 1 - drivers/gpu/drm/nouveau/dispnv50/base507c.c | 16 +++++++++------- drivers/gpu/drm/nouveau/dispnv50/ovly.h | 1 - drivers/gpu/drm/nouveau/dispnv50/ovly507e.c | 13 +------------ drivers/gpu/drm/nouveau/dispnv50/ovly827e.c | 2 +- drivers/gpu/drm/nouveau/dispnv50/ovly907e.c | 2 +- drivers/gpu/drm/nouveau/dispnv50/wndw.h | 5 +++-- drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c | 16 +++++++++------- 8 files changed, 24 insertions(+), 32 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/base.h b/drivers/gpu/drm/nouveau/dispnv50/base.h index a93e2e314640..03b655f02b68 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/base.h +++ b/drivers/gpu/drm/nouveau/dispnv50/base.h @@ -13,7 +13,6 @@ void base507c_release(struct nv50_wndw *, struct nv50_wndw_atom *, struct nv50_head_atom *); int base507c_sema_set(struct nv50_wndw *, struct nv50_wndw_atom *); int base507c_sema_clr(struct nv50_wndw *); -void base507c_ntfy_clr(struct nv50_wndw *); void base507c_xlut_set(struct nv50_wndw *, struct nv50_wndw_atom *); void base507c_xlut_clr(struct nv50_wndw *); void base507c_image_clr(struct nv50_wndw *); diff --git a/drivers/gpu/drm/nouveau/dispnv50/base507c.c b/drivers/gpu/drm/nouveau/dispnv50/base507c.c index d0d6a5056171..d707a75d9fdb 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/base507c.c +++ b/drivers/gpu/drm/nouveau/dispnv50/base507c.c @@ -124,15 +124,17 @@ base507c_ntfy_wait_begun(struct nouveau_bo *bo, u32 offset, return time < 0 ? time : 0; } -void +int base507c_ntfy_clr(struct nv50_wndw *wndw) { - u32 *push; - if ((push = evo_wait(&wndw->wndw, 2))) { - evo_mthd(push, 0x00a4, 1); - evo_data(push, 0x00000000); - evo_kick(push, &wndw->wndw); - } + struct nvif_push *push = wndw->wndw.push; + int ret; + + if ((ret = PUSH_WAIT(push, 2))) + return ret; + + PUSH_NVSQ(push, NV507C, 0x00a4, 0x00000000); + return 0; } int diff --git a/drivers/gpu/drm/nouveau/dispnv50/ovly.h b/drivers/gpu/drm/nouveau/dispnv50/ovly.h index dee606213d27..1048fc6bc778 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/ovly.h +++ b/drivers/gpu/drm/nouveau/dispnv50/ovly.h @@ -10,7 +10,6 @@ int ovly507e_acquire(struct nv50_wndw *, struct nv50_wndw_atom *, struct nv50_head_atom *); void ovly507e_release(struct nv50_wndw *, struct nv50_wndw_atom *, struct nv50_head_atom *); -void ovly507e_ntfy_clr(struct nv50_wndw *); void ovly507e_image_clr(struct nv50_wndw *); void ovly507e_scale_set(struct nv50_wndw *, struct nv50_wndw_atom *); void ovly507e_update(struct nv50_wndw *, u32 *); diff --git a/drivers/gpu/drm/nouveau/dispnv50/ovly507e.c b/drivers/gpu/drm/nouveau/dispnv50/ovly507e.c index 91ea3ea3e7fa..151064aa19e1 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/ovly507e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/ovly507e.c @@ -92,17 +92,6 @@ ovly507e_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) } } -void -ovly507e_ntfy_clr(struct nv50_wndw *wndw) -{ - u32 *push; - if ((push = evo_wait(&wndw->wndw, 2))) { - evo_mthd(push, 0x00a4, 1); - evo_data(push, 0x00000000); - evo_kick(push, &wndw->wndw); - } -} - void ovly507e_release(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw, struct nv50_head_atom *asyh) @@ -135,7 +124,7 @@ ovly507e = { .acquire = ovly507e_acquire, .release = ovly507e_release, .ntfy_set = base507c_ntfy_set, - .ntfy_clr = ovly507e_ntfy_clr, + .ntfy_clr = base507c_ntfy_clr, .ntfy_reset = base507c_ntfy_reset, .ntfy_wait_begun = base507c_ntfy_wait_begun, .image_set = ovly507e_image_set, diff --git a/drivers/gpu/drm/nouveau/dispnv50/ovly827e.c b/drivers/gpu/drm/nouveau/dispnv50/ovly827e.c index 72a4117529e5..37e37a7d4ba9 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/ovly827e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/ovly827e.c @@ -78,7 +78,7 @@ ovly827e = { .acquire = ovly507e_acquire, .release = ovly507e_release, .ntfy_set = base507c_ntfy_set, - .ntfy_clr = ovly507e_ntfy_clr, + .ntfy_clr = base507c_ntfy_clr, .ntfy_reset = ovly827e_ntfy_reset, .ntfy_wait_begun = ovly827e_ntfy_wait_begun, .image_set = ovly827e_image_set, diff --git a/drivers/gpu/drm/nouveau/dispnv50/ovly907e.c b/drivers/gpu/drm/nouveau/dispnv50/ovly907e.c index 255a8415eb45..73fb5d4eb343 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/ovly907e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/ovly907e.c @@ -52,7 +52,7 @@ ovly907e = { .acquire = ovly507e_acquire, .release = ovly507e_release, .ntfy_set = base507c_ntfy_set, - .ntfy_clr = ovly507e_ntfy_clr, + .ntfy_clr = base507c_ntfy_clr, .ntfy_reset = ovly827e_ntfy_reset, .ntfy_wait_begun = ovly827e_ntfy_wait_begun, .image_set = ovly907e_image_set, diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndw.h b/drivers/gpu/drm/nouveau/dispnv50/wndw.h index 6c994461ea63..d632a30022e4 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndw.h +++ b/drivers/gpu/drm/nouveau/dispnv50/wndw.h @@ -61,7 +61,7 @@ struct nv50_wndw_func { int (*sema_clr)(struct nv50_wndw *); void (*ntfy_reset)(struct nouveau_bo *, u32 offset); int (*ntfy_set)(struct nv50_wndw *, struct nv50_wndw_atom *); - void (*ntfy_clr)(struct nv50_wndw *); + int (*ntfy_clr)(struct nv50_wndw *); int (*ntfy_wait_begun)(struct nouveau_bo *, u32 offset, struct nvif_device *); bool (*ilut)(struct nv50_wndw *, struct nv50_wndw_atom *, int); @@ -86,6 +86,7 @@ extern const struct drm_plane_funcs nv50_wndw; void base507c_ntfy_reset(struct nouveau_bo *, u32); int base507c_ntfy_set(struct nv50_wndw *, struct nv50_wndw_atom *); +int base507c_ntfy_clr(struct nv50_wndw *); int base507c_ntfy_wait_begun(struct nouveau_bo *, u32, struct nvif_device *); void base907c_csc(struct nv50_wndw *, struct nv50_wndw_atom *, @@ -119,7 +120,7 @@ void wndwc37e_release(struct nv50_wndw *, struct nv50_wndw_atom *, int wndwc37e_sema_set(struct nv50_wndw *, struct nv50_wndw_atom *); int wndwc37e_sema_clr(struct nv50_wndw *); int wndwc37e_ntfy_set(struct nv50_wndw *, struct nv50_wndw_atom *); -void wndwc37e_ntfy_clr(struct nv50_wndw *); +int wndwc37e_ntfy_clr(struct nv50_wndw *); void wndwc37e_image_clr(struct nv50_wndw *); void wndwc37e_blend_set(struct nv50_wndw *, struct nv50_wndw_atom *); void wndwc37e_update(struct nv50_wndw *, u32 *); diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c index 9738205949bf..2dded1a8407a 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c @@ -152,15 +152,17 @@ wndwc37e_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) evo_kick(push, &wndw->wndw); } -void +int wndwc37e_ntfy_clr(struct nv50_wndw *wndw) { - u32 *push; - if ((push = evo_wait(&wndw->wndw, 2))) { - evo_mthd(push, 0x021c, 1); - evo_data(push, 0x00000000); - evo_kick(push, &wndw->wndw); - } + struct nvif_push *push = wndw->wndw.push; + int ret; + + if ((ret = PUSH_WAIT(push, 2))) + return ret; + + PUSH_NVSQ(push, NVC37E, 0x021c, 0x00000000); + return 0; } int From 72587dca9658a0428518e658247c4490a0e0a09f Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sat, 20 Jun 2020 08:39:21 +1000 Subject: [PATCH 045/145] drm/nouveau/kms/nv50-: convert wndw csc_set() to new push macros Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/base907c.c | 21 ++++++++++++--------- drivers/gpu/drm/nouveau/dispnv50/wndw.h | 2 +- drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c | 17 +++++++++-------- drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c | 18 ++++++++++-------- 4 files changed, 32 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/base907c.c b/drivers/gpu/drm/nouveau/dispnv50/base907c.c index 224a34c340fe..182da01fd62f 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/base907c.c +++ b/drivers/gpu/drm/nouveau/dispnv50/base907c.c @@ -21,6 +21,8 @@ */ #include "base.h" +#include + static void base907c_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) { @@ -136,17 +138,18 @@ base907c_csc_clr(struct nv50_wndw *wndw) } } -static void +static int base907c_csc_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) { - u32 *push, i; - if ((push = evo_wait(&wndw->wndw, 13))) { - evo_mthd(push, 0x0140, 12); - evo_data(push, asyw->csc.matrix[0] | 0x80000000); - for (i = 1; i < 12; i++) - evo_data(push, asyw->csc.matrix[i]); - evo_kick(push, &wndw->wndw); - } + struct nvif_push *push = wndw->wndw.push; + int ret; + + if ((ret = PUSH_WAIT(push, 13))) + return ret; + + PUSH_NVSQ(push, NV907C, 0x0140, asyw->csc.matrix[0] | 0x80000000, + 0x0144, &asyw->csc.matrix[1], 11); + return 0; } const struct nv50_wndw_func diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndw.h b/drivers/gpu/drm/nouveau/dispnv50/wndw.h index d632a30022e4..aacabd966b6c 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndw.h +++ b/drivers/gpu/drm/nouveau/dispnv50/wndw.h @@ -67,7 +67,7 @@ struct nv50_wndw_func { bool (*ilut)(struct nv50_wndw *, struct nv50_wndw_atom *, int); void (*csc)(struct nv50_wndw *, struct nv50_wndw_atom *, const struct drm_color_ctm *); - void (*csc_set)(struct nv50_wndw *, struct nv50_wndw_atom *); + int (*csc_set)(struct nv50_wndw *, struct nv50_wndw_atom *); void (*csc_clr)(struct nv50_wndw *); bool ilut_identity; int ilut_size; diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c index 2dded1a8407a..aebaf409a355 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c @@ -34,16 +34,17 @@ wndwc37e_csc_clr(struct nv50_wndw *wndw) { } -static void +static int wndwc37e_csc_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) { - u32 *push, i; - if ((push = evo_wait(&wndw->wndw, 13))) { - evo_mthd(push, 0x02bc, 12); - for (i = 0; i < 12; i++) - evo_data(push, asyw->csc.matrix[i]); - evo_kick(push, &wndw->wndw); - } + struct nvif_push *push = wndw->wndw.push; + int ret; + + if ((ret = PUSH_WAIT(push, 13))) + return ret; + + PUSH_NVSQ(push, NVC37E, 0x02bc, asyw->csc.matrix, 12); + return 0; } static void diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c b/drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c index 1d64741595ba..9d155a7f14bf 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c @@ -27,6 +27,7 @@ #include #include +#include static void wndwc57e_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) @@ -82,16 +83,17 @@ wndwc57e_csc_clr(struct nv50_wndw *wndw) } } -static void +static int wndwc57e_csc_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) { - u32 *push, i; - if ((push = evo_wait(&wndw->wndw, 13))) { - evo_mthd(push, 0x0400, 12); - for (i = 0; i < 12; i++) - evo_data(push, asyw->csc.matrix[i]); - evo_kick(push, &wndw->wndw); - } + struct nvif_push *push = wndw->wndw.push; + int ret; + + if ((ret = PUSH_WAIT(push, 13))) + return ret; + + PUSH_NVSQ(push, NVC57E, 0x0400, asyw->csc.matrix, 12); + return 0; } static void From cfb4120dae34538e0ac14c9f972d4b3b80159224 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sat, 20 Jun 2020 08:44:11 +1000 Subject: [PATCH 046/145] drm/nouveau/kms/nv50-: convert wndw csc_clr() to new push macros Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/base907c.c | 16 ++++++----- drivers/gpu/drm/nouveau/dispnv50/wndw.h | 2 +- drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c | 3 +- drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c | 32 +++++++++------------ 4 files changed, 26 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/base907c.c b/drivers/gpu/drm/nouveau/dispnv50/base907c.c index 182da01fd62f..78efecc39450 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/base907c.c +++ b/drivers/gpu/drm/nouveau/dispnv50/base907c.c @@ -127,15 +127,17 @@ base907c_csc(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw, } } -static void +static int base907c_csc_clr(struct nv50_wndw *wndw) { - u32 *push; - if ((push = evo_wait(&wndw->wndw, 2))) { - evo_mthd(push, 0x0140, 1); - evo_data(push, 0x00000000); - evo_kick(push, &wndw->wndw); - } + struct nvif_push *push = wndw->wndw.push; + int ret; + + if ((ret = PUSH_WAIT(push, 2))) + return ret; + + PUSH_NVSQ(push, NV907C, 0x0140, 0x00000000); + return 0; } static int diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndw.h b/drivers/gpu/drm/nouveau/dispnv50/wndw.h index aacabd966b6c..578715747db5 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndw.h +++ b/drivers/gpu/drm/nouveau/dispnv50/wndw.h @@ -68,7 +68,7 @@ struct nv50_wndw_func { void (*csc)(struct nv50_wndw *, struct nv50_wndw_atom *, const struct drm_color_ctm *); int (*csc_set)(struct nv50_wndw *, struct nv50_wndw_atom *); - void (*csc_clr)(struct nv50_wndw *); + int (*csc_clr)(struct nv50_wndw *); bool ilut_identity; int ilut_size; bool olut_core; diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c index aebaf409a355..8ed979836d63 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c @@ -29,9 +29,10 @@ #include #include -static void +static int wndwc37e_csc_clr(struct nv50_wndw *wndw) { + return 0; } static int diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c b/drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c index 9d155a7f14bf..1c33e18258d5 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c @@ -61,26 +61,22 @@ wndwc57e_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) evo_kick(push, &wndw->wndw); } -static void +static int wndwc57e_csc_clr(struct nv50_wndw *wndw) { - u32 *push; - if ((push = evo_wait(&wndw->wndw, 13))) { - evo_mthd(push, 0x0400, 12); - evo_data(push, 0x00010000); - evo_data(push, 0x00000000); - evo_data(push, 0x00000000); - evo_data(push, 0x00000000); - evo_data(push, 0x00000000); - evo_data(push, 0x00010000); - evo_data(push, 0x00000000); - evo_data(push, 0x00000000); - evo_data(push, 0x00000000); - evo_data(push, 0x00000000); - evo_data(push, 0x00010000); - evo_data(push, 0x00000000); - evo_kick(push, &wndw->wndw); - } + struct nvif_push *push = wndw->wndw.push; + const u32 identity[12] = { + 0x00010000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00010000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00010000, 0x00000000, + }; + int ret; + + if ((ret = PUSH_WAIT(push, 1 + ARRAY_SIZE(identity)))) + return ret; + + PUSH_NVSQ(push, NVC57E, 0x0400, identity, ARRAY_SIZE(identity)); + return 0; } static int From 222439ebe6d4ec94b013968b07334a55612f641b Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sat, 20 Jun 2020 08:47:20 +1000 Subject: [PATCH 047/145] drm/nouveau/kms/nv50-: convert wndw xlut_set() to new push macros Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/base.h | 2 +- drivers/gpu/drm/nouveau/dispnv50/base507c.c | 16 +++++++------ drivers/gpu/drm/nouveau/dispnv50/base907c.c | 25 +++++++++++---------- drivers/gpu/drm/nouveau/dispnv50/wndw.h | 2 +- drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c | 24 +++++++++++--------- drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c | 24 +++++++++++--------- 6 files changed, 50 insertions(+), 43 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/base.h b/drivers/gpu/drm/nouveau/dispnv50/base.h index 03b655f02b68..0205f08a774f 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/base.h +++ b/drivers/gpu/drm/nouveau/dispnv50/base.h @@ -13,7 +13,7 @@ void base507c_release(struct nv50_wndw *, struct nv50_wndw_atom *, struct nv50_head_atom *); int base507c_sema_set(struct nv50_wndw *, struct nv50_wndw_atom *); int base507c_sema_clr(struct nv50_wndw *); -void base507c_xlut_set(struct nv50_wndw *, struct nv50_wndw_atom *); +int base507c_xlut_set(struct nv50_wndw *, struct nv50_wndw_atom *); void base507c_xlut_clr(struct nv50_wndw *); void base507c_image_clr(struct nv50_wndw *); void base507c_update(struct nv50_wndw *, u32 *); diff --git a/drivers/gpu/drm/nouveau/dispnv50/base507c.c b/drivers/gpu/drm/nouveau/dispnv50/base507c.c index d707a75d9fdb..49eac3a79f87 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/base507c.c +++ b/drivers/gpu/drm/nouveau/dispnv50/base507c.c @@ -100,15 +100,17 @@ base507c_xlut_clr(struct nv50_wndw *wndw) } } -void +int base507c_xlut_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) { - u32 *push; - if ((push = evo_wait(&wndw->wndw, 2))) { - evo_mthd(push, 0x00e0, 1); - evo_data(push, 0x40000000); - evo_kick(push, &wndw->wndw); - } + struct nvif_push *push = wndw->wndw.push; + int ret; + + if ((ret = PUSH_WAIT(push, 2))) + return ret; + + PUSH_NVSQ(push, NV507C, 0x00e0, 0x40000000); + return 0; } int diff --git a/drivers/gpu/drm/nouveau/dispnv50/base907c.c b/drivers/gpu/drm/nouveau/dispnv50/base907c.c index 78efecc39450..91a3c60b2fcf 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/base907c.c +++ b/drivers/gpu/drm/nouveau/dispnv50/base907c.c @@ -61,20 +61,21 @@ base907c_xlut_clr(struct nv50_wndw *wndw) } } -static void +static int base907c_xlut_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) { - u32 *push; - if ((push = evo_wait(&wndw->wndw, 6))) { - evo_mthd(push, 0x00e0, 3); - evo_data(push, asyw->xlut.i.enable << 30 | - asyw->xlut.i.mode << 24); - evo_data(push, asyw->xlut.i.offset >> 8); - evo_data(push, 0x40000000); - evo_mthd(push, 0x00fc, 1); - evo_data(push, asyw->xlut.handle); - evo_kick(push, &wndw->wndw); - } + struct nvif_push *push = wndw->wndw.push; + int ret; + + if ((ret = PUSH_WAIT(push, 6))) + return ret; + + PUSH_NVSQ(push, NV907C, 0x00e0, asyw->xlut.i.enable << 30 | + asyw->xlut.i.mode << 24, + 0x00e4, asyw->xlut.i.offset >> 8, + 0x00e8, 0x40000000); + PUSH_NVSQ(push, NV907C, 0x00fc, asyw->xlut.handle); + return 0; } static bool diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndw.h b/drivers/gpu/drm/nouveau/dispnv50/wndw.h index 578715747db5..f6069a95fb41 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndw.h +++ b/drivers/gpu/drm/nouveau/dispnv50/wndw.h @@ -72,7 +72,7 @@ struct nv50_wndw_func { bool ilut_identity; int ilut_size; bool olut_core; - void (*xlut_set)(struct nv50_wndw *, struct nv50_wndw_atom *); + int (*xlut_set)(struct nv50_wndw *, struct nv50_wndw_atom *); void (*xlut_clr)(struct nv50_wndw *); void (*image_set)(struct nv50_wndw *, struct nv50_wndw_atom *); void (*image_clr)(struct nv50_wndw *); diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c index 8ed979836d63..38778cfaeca2 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c @@ -59,19 +59,21 @@ wndwc37e_ilut_clr(struct nv50_wndw *wndw) } } -static void +static int wndwc37e_ilut_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) { - u32 *push; - if ((push = evo_wait(&wndw->wndw, 4))) { - evo_mthd(push, 0x02b0, 3); - evo_data(push, asyw->xlut.i.output_mode << 8 | - asyw->xlut.i.range << 4 | - asyw->xlut.i.size); - evo_data(push, asyw->xlut.i.offset >> 8); - evo_data(push, asyw->xlut.handle); - evo_kick(push, &wndw->wndw); - } + struct nvif_push *push = wndw->wndw.push; + int ret; + + if ((ret = PUSH_WAIT(push, 4))) + return ret; + + PUSH_NVSQ(push, NVC37E, 0x02b0, asyw->xlut.i.output_mode << 8 | + asyw->xlut.i.range << 4 | + asyw->xlut.i.size, + 0x02b4, asyw->xlut.i.offset >> 8, + 0x02b8, asyw->xlut.handle); + return 0; } static bool diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c b/drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c index 1c33e18258d5..1dc5a188e6ff 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c @@ -103,19 +103,21 @@ wndwc57e_ilut_clr(struct nv50_wndw *wndw) } } -static void +static int wndwc57e_ilut_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) { - u32 *push; - if ((push = evo_wait(&wndw->wndw, 4))) { - evo_mthd(push, 0x0440, 3); - evo_data(push, asyw->xlut.i.size << 8 | - asyw->xlut.i.mode << 2 | - asyw->xlut.i.output_mode); - evo_data(push, asyw->xlut.handle); - evo_data(push, asyw->xlut.i.offset >> 8); - evo_kick(push, &wndw->wndw); - } + struct nvif_push *push = wndw->wndw.push; + int ret; + + if ((ret = PUSH_WAIT(push, 4))) + return ret; + + PUSH_NVSQ(push, NVC57E, 0x0440, asyw->xlut.i.size << 8 | + asyw->xlut.i.mode << 2 | + asyw->xlut.i.output_mode, + 0x0444, asyw->xlut.handle, + 0x0448, asyw->xlut.i.offset >> 8); + return 0; } static u16 From 34838908f62a0160d2c12c12be6c3be910d17b85 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sat, 20 Jun 2020 08:50:50 +1000 Subject: [PATCH 048/145] drm/nouveau/kms/nv50-: convert wndw xlut_clr() to new push macros Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/base.h | 2 +- drivers/gpu/drm/nouveau/dispnv50/base507c.c | 16 ++++++++------- drivers/gpu/drm/nouveau/dispnv50/base907c.c | 22 ++++++++++----------- drivers/gpu/drm/nouveau/dispnv50/wndw.h | 2 +- drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c | 16 ++++++++------- drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c | 16 ++++++++------- 6 files changed, 40 insertions(+), 34 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/base.h b/drivers/gpu/drm/nouveau/dispnv50/base.h index 0205f08a774f..fe362aa03c8e 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/base.h +++ b/drivers/gpu/drm/nouveau/dispnv50/base.h @@ -14,7 +14,7 @@ void base507c_release(struct nv50_wndw *, struct nv50_wndw_atom *, int base507c_sema_set(struct nv50_wndw *, struct nv50_wndw_atom *); int base507c_sema_clr(struct nv50_wndw *); int base507c_xlut_set(struct nv50_wndw *, struct nv50_wndw_atom *); -void base507c_xlut_clr(struct nv50_wndw *); +int base507c_xlut_clr(struct nv50_wndw *); void base507c_image_clr(struct nv50_wndw *); void base507c_update(struct nv50_wndw *, u32 *); diff --git a/drivers/gpu/drm/nouveau/dispnv50/base507c.c b/drivers/gpu/drm/nouveau/dispnv50/base507c.c index 49eac3a79f87..760ee65613a7 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/base507c.c +++ b/drivers/gpu/drm/nouveau/dispnv50/base507c.c @@ -89,15 +89,17 @@ base507c_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) } } -void +int base507c_xlut_clr(struct nv50_wndw *wndw) { - u32 *push; - if ((push = evo_wait(&wndw->wndw, 2))) { - evo_mthd(push, 0x00e0, 1); - evo_data(push, 0x00000000); - evo_kick(push, &wndw->wndw); - } + struct nvif_push *push = wndw->wndw.push; + int ret; + + if ((ret = PUSH_WAIT(push, 2))) + return ret; + + PUSH_NVSQ(push, NV507C, 0x00e0, 0x00000000); + return 0; } int diff --git a/drivers/gpu/drm/nouveau/dispnv50/base907c.c b/drivers/gpu/drm/nouveau/dispnv50/base907c.c index 91a3c60b2fcf..d50fa80f3c99 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/base907c.c +++ b/drivers/gpu/drm/nouveau/dispnv50/base907c.c @@ -46,19 +46,19 @@ base907c_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) } } -static void +static int base907c_xlut_clr(struct nv50_wndw *wndw) { - u32 *push; - if ((push = evo_wait(&wndw->wndw, 6))) { - evo_mthd(push, 0x00e0, 1); - evo_data(push, 0x00000000); - evo_mthd(push, 0x00e8, 1); - evo_data(push, 0x00000000); - evo_mthd(push, 0x00fc, 1); - evo_data(push, 0x00000000); - evo_kick(push, &wndw->wndw); - } + struct nvif_push *push = wndw->wndw.push; + int ret; + + if ((ret = PUSH_WAIT(push, 6))) + return ret; + + PUSH_NVSQ(push, NV907C, 0x00e0, 0x00000000); + PUSH_NVSQ(push, NV907C, 0x00e8, 0x00000000); + PUSH_NVSQ(push, NV907C, 0x00fc, 0x00000000); + return 0; } static int diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndw.h b/drivers/gpu/drm/nouveau/dispnv50/wndw.h index f6069a95fb41..6baf27090fc2 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndw.h +++ b/drivers/gpu/drm/nouveau/dispnv50/wndw.h @@ -73,7 +73,7 @@ struct nv50_wndw_func { int ilut_size; bool olut_core; int (*xlut_set)(struct nv50_wndw *, struct nv50_wndw_atom *); - void (*xlut_clr)(struct nv50_wndw *); + int (*xlut_clr)(struct nv50_wndw *); void (*image_set)(struct nv50_wndw *, struct nv50_wndw_atom *); void (*image_clr)(struct nv50_wndw *); void (*scale_set)(struct nv50_wndw *, struct nv50_wndw_atom *); diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c index 38778cfaeca2..eab1c322eccb 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c @@ -48,15 +48,17 @@ wndwc37e_csc_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) return 0; } -static void +static int wndwc37e_ilut_clr(struct nv50_wndw *wndw) { - u32 *push; - if ((push = evo_wait(&wndw->wndw, 2))) { - evo_mthd(push, 0x02b8, 1); - evo_data(push, 0x00000000); - evo_kick(push, &wndw->wndw); - } + struct nvif_push *push = wndw->wndw.push; + int ret; + + if ((ret = PUSH_WAIT(push, 2))) + return ret; + + PUSH_NVSQ(push, NVC37E, 0x02b8, 0x00000000); + return 0; } static int diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c b/drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c index 1dc5a188e6ff..f393399baab1 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c @@ -92,15 +92,17 @@ wndwc57e_csc_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) return 0; } -static void +static int wndwc57e_ilut_clr(struct nv50_wndw *wndw) { - u32 *push; - if ((push = evo_wait(&wndw->wndw, 2))) { - evo_mthd(push, 0x0444, 1); - evo_data(push, 0x00000000); - evo_kick(push, &wndw->wndw); - } + struct nvif_push *push = wndw->wndw.push; + int ret; + + if ((ret = PUSH_WAIT(push, 2))) + return ret; + + PUSH_NVSQ(push, NVC57E, 0x0444, 0x00000000); + return 0; } static int From 6d6e11e2844015a5f6c3d0373966fd4a459add8b Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sat, 20 Jun 2020 09:20:17 +1000 Subject: [PATCH 049/145] drm/nouveau/kms/nv50-: convert wndw image_set() to new push macros Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/base507c.c | 54 ++++++++++----------- drivers/gpu/drm/nouveau/dispnv50/base827c.c | 54 ++++++++++----------- drivers/gpu/drm/nouveau/dispnv50/base907c.c | 38 +++++++-------- drivers/gpu/drm/nouveau/dispnv50/ovly507e.c | 43 ++++++++-------- drivers/gpu/drm/nouveau/dispnv50/ovly827e.c | 41 ++++++++-------- drivers/gpu/drm/nouveau/dispnv50/ovly907e.c | 42 ++++++++-------- drivers/gpu/drm/nouveau/dispnv50/wndw.h | 2 +- drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c | 51 +++++++++---------- drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c | 49 +++++++++---------- 9 files changed, 182 insertions(+), 192 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/base507c.c b/drivers/gpu/drm/nouveau/dispnv50/base507c.c index 760ee65613a7..ae1c5cc00957 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/base507c.c +++ b/drivers/gpu/drm/nouveau/dispnv50/base507c.c @@ -56,37 +56,35 @@ base507c_image_clr(struct nv50_wndw *wndw) } } -static void +static int base507c_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) { - u32 *push; - if ((push = evo_wait(&wndw->wndw, 13))) { - evo_mthd(push, 0x0084, 1); - evo_data(push, asyw->image.mode << 8 | - asyw->image.interval << 4); - evo_mthd(push, 0x00c0, 1); - evo_data(push, asyw->image.handle[0]); - if (asyw->image.format == 0xca) { - evo_mthd(push, 0x0110, 2); - evo_data(push, 1); - evo_data(push, 0x6400); - } else { - evo_mthd(push, 0x0110, 2); - evo_data(push, 0); - evo_data(push, 0); - } - evo_mthd(push, 0x0800, 5); - evo_data(push, asyw->image.offset[0] >> 8); - evo_data(push, 0x00000000); - evo_data(push, asyw->image.h << 16 | asyw->image.w); - evo_data(push, asyw->image.layout << 20 | - (asyw->image.pitch[0] >> 8) << 8 | - asyw->image.blocks[0] << 8 | - asyw->image.blockh); - evo_data(push, asyw->image.kind << 16 | - asyw->image.format << 8); - evo_kick(push, &wndw->wndw); + struct nvif_push *push = wndw->wndw.push; + int ret; + + if ((ret = PUSH_WAIT(push, 13))) + return ret; + + PUSH_NVSQ(push, NV507C, 0x0084, asyw->image.mode << 8 | + asyw->image.interval << 4); + PUSH_NVSQ(push, NV507C, 0x00c0, asyw->image.handle[0]); + if (asyw->image.format == 0xca) { + PUSH_NVSQ(push, NV507C, 0x0110, 1, + 0x0114, 0x6400); + } else { + PUSH_NVSQ(push, NV507C, 0x0110, 0, + 0x0114, 0); } + PUSH_NVSQ(push, NV507C, 0x0800, asyw->image.offset[0] >> 8, + 0x0804, 0x00000000, + 0x0808, asyw->image.h << 16 | asyw->image.w, + 0x080c, asyw->image.layout << 20 | + (asyw->image.pitch[0] >> 8) << 8 | + asyw->image.blocks[0] << 8 | + asyw->image.blockh, + 0x0810, asyw->image.kind << 16 | + asyw->image.format << 8); + return 0; } int diff --git a/drivers/gpu/drm/nouveau/dispnv50/base827c.c b/drivers/gpu/drm/nouveau/dispnv50/base827c.c index f4c05949dd62..c1995194aa7b 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/base827c.c +++ b/drivers/gpu/drm/nouveau/dispnv50/base827c.c @@ -21,36 +21,36 @@ */ #include "base.h" -static void +#include + +static int base827c_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) { - u32 *push; - if ((push = evo_wait(&wndw->wndw, 13))) { - evo_mthd(push, 0x0084, 1); - evo_data(push, asyw->image.mode << 8 | - asyw->image.interval << 4); - evo_mthd(push, 0x00c0, 1); - evo_data(push, asyw->image.handle[0]); - if (asyw->image.format == 0xca) { - evo_mthd(push, 0x0110, 2); - evo_data(push, 1); - evo_data(push, 0x6400); - } else { - evo_mthd(push, 0x0110, 2); - evo_data(push, 0); - evo_data(push, 0); - } - evo_mthd(push, 0x0800, 5); - evo_data(push, asyw->image.offset[0] >> 8); - evo_data(push, 0x00000000); - evo_data(push, asyw->image.h << 16 | asyw->image.w); - evo_data(push, asyw->image.layout << 20 | - (asyw->image.pitch[0] >> 8) << 8 | - asyw->image.blocks[0] << 8 | - asyw->image.blockh); - evo_data(push, asyw->image.format << 8); - evo_kick(push, &wndw->wndw); + struct nvif_push *push = wndw->wndw.push; + int ret; + + if ((ret = PUSH_WAIT(push, 13))) + return ret; + + PUSH_NVSQ(push, NV827C, 0x0084, asyw->image.mode << 8 | + asyw->image.interval << 4); + PUSH_NVSQ(push, NV827C, 0x00c0, asyw->image.handle[0]); + if (asyw->image.format == 0xca) { + PUSH_NVSQ(push, NV827C, 0x0110, 1, + 0x0114, 0x6400); + } else { + PUSH_NVSQ(push, NV827C, 0x0110, 0, + 0x0114, 0); } + PUSH_NVSQ(push, NV827C, 0x0800, asyw->image.offset[0] >> 8, + 0x0804, 0x00000000, + 0x0808, asyw->image.h << 16 | asyw->image.w, + 0x080c, asyw->image.layout << 20 | + (asyw->image.pitch[0] >> 8) << 8 | + asyw->image.blocks[0] << 8 | + asyw->image.blockh, + 0x0810, asyw->image.format << 8); + return 0; } static const struct nv50_wndw_func diff --git a/drivers/gpu/drm/nouveau/dispnv50/base907c.c b/drivers/gpu/drm/nouveau/dispnv50/base907c.c index d50fa80f3c99..c88a924d7d09 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/base907c.c +++ b/drivers/gpu/drm/nouveau/dispnv50/base907c.c @@ -23,27 +23,27 @@ #include -static void +static int base907c_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) { - u32 *push; - if ((push = evo_wait(&wndw->wndw, 10))) { - evo_mthd(push, 0x0084, 1); - evo_data(push, asyw->image.mode << 8 | - asyw->image.interval << 4); - evo_mthd(push, 0x00c0, 1); - evo_data(push, asyw->image.handle[0]); - evo_mthd(push, 0x0400, 5); - evo_data(push, asyw->image.offset[0] >> 8); - evo_data(push, 0x00000000); - evo_data(push, asyw->image.h << 16 | asyw->image.w); - evo_data(push, asyw->image.layout << 24 | - (asyw->image.pitch[0] >> 8) << 8 | - asyw->image.blocks[0] << 8 | - asyw->image.blockh); - evo_data(push, asyw->image.format << 8); - evo_kick(push, &wndw->wndw); - } + struct nvif_push *push = wndw->wndw.push; + int ret; + + if ((ret = PUSH_WAIT(push, 10))) + return ret; + + PUSH_NVSQ(push, NV907C, 0x0084, asyw->image.mode << 8 | + asyw->image.interval << 4); + PUSH_NVSQ(push, NV907C, 0x00c0, asyw->image.handle[0]); + PUSH_NVSQ(push, NV907C, 0x0400, asyw->image.offset[0] >> 8, + 0x0404, 0x00000000, + 0x0408, asyw->image.h << 16 | asyw->image.w, + 0x040c, asyw->image.layout << 24 | + (asyw->image.pitch[0] >> 8) << 8 | + asyw->image.blocks[0] << 8 | + asyw->image.blockh, + 0x0410, asyw->image.format << 8); + return 0; } static int diff --git a/drivers/gpu/drm/nouveau/dispnv50/ovly507e.c b/drivers/gpu/drm/nouveau/dispnv50/ovly507e.c index 151064aa19e1..e182f376900f 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/ovly507e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/ovly507e.c @@ -28,6 +28,7 @@ #include #include +#include void ovly507e_update(struct nv50_wndw *wndw, u32 *interlock) @@ -66,30 +67,28 @@ ovly507e_image_clr(struct nv50_wndw *wndw) } } -static void +static int ovly507e_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) { - u32 *push; - if ((push = evo_wait(&wndw->wndw, 12))) { - evo_mthd(push, 0x0084, 1); - evo_data(push, asyw->image.interval << 4); - evo_mthd(push, 0x00c0, 1); - evo_data(push, asyw->image.handle[0]); - evo_mthd(push, 0x0100, 1); - evo_data(push, 0x00000002); - evo_mthd(push, 0x0800, 1); - evo_data(push, asyw->image.offset[0] >> 8); - evo_mthd(push, 0x0808, 3); - evo_data(push, asyw->image.h << 16 | asyw->image.w); - evo_data(push, asyw->image.layout << 20 | - (asyw->image.pitch[0] >> 8) << 8 | - asyw->image.blocks[0] << 8 | - asyw->image.blockh); - evo_data(push, asyw->image.kind << 16 | - asyw->image.format << 8 | - asyw->image.colorspace); - evo_kick(push, &wndw->wndw); - } + struct nvif_push *push = wndw->wndw.push; + int ret; + + if ((ret = PUSH_WAIT(push, 12))) + return ret; + + PUSH_NVSQ(push, NV507E, 0x0084, asyw->image.interval << 4); + PUSH_NVSQ(push, NV507E, 0x00c0, asyw->image.handle[0]); + PUSH_NVSQ(push, NV507E, 0x0100, 0x00000002); + PUSH_NVSQ(push, NV507E, 0x0800, asyw->image.offset[0] >> 8); + PUSH_NVSQ(push, NV507E, 0x0808, asyw->image.h << 16 | asyw->image.w, + 0x080c, asyw->image.layout << 20 | + (asyw->image.pitch[0] >> 8) << 8 | + asyw->image.blocks[0] << 8 | + asyw->image.blockh, + 0x0810, asyw->image.kind << 16 | + asyw->image.format << 8 | + asyw->image.colorspace); + return 0; } void diff --git a/drivers/gpu/drm/nouveau/dispnv50/ovly827e.c b/drivers/gpu/drm/nouveau/dispnv50/ovly827e.c index 37e37a7d4ba9..cb0f372cbcf7 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/ovly827e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/ovly827e.c @@ -24,31 +24,30 @@ #include +#include #include -static void +static int ovly827e_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) { - u32 *push; - if ((push = evo_wait(&wndw->wndw, 12))) { - evo_mthd(push, 0x0084, 1); - evo_data(push, asyw->image.interval << 4); - evo_mthd(push, 0x00c0, 1); - evo_data(push, asyw->image.handle[0]); - evo_mthd(push, 0x0100, 1); - evo_data(push, 0x00000002); - evo_mthd(push, 0x0800, 1); - evo_data(push, asyw->image.offset[0] >> 8); - evo_mthd(push, 0x0808, 3); - evo_data(push, asyw->image.h << 16 | asyw->image.w); - evo_data(push, asyw->image.layout << 20 | - (asyw->image.pitch[0] >> 8) << 8 | - asyw->image.blocks[0] << 8 | - asyw->image.blockh); - evo_data(push, asyw->image.format << 8 | - asyw->image.colorspace); - evo_kick(push, &wndw->wndw); - } + struct nvif_push *push = wndw->wndw.push; + int ret; + + if ((ret = PUSH_WAIT(push, 12))) + return ret; + + PUSH_NVSQ(push, NV827E, 0x0084, asyw->image.interval << 4); + PUSH_NVSQ(push, NV827E, 0x00c0, asyw->image.handle[0]); + PUSH_NVSQ(push, NV827E, 0x0100, 0x00000002); + PUSH_NVSQ(push, NV827E, 0x0800, asyw->image.offset[0] >> 8); + PUSH_NVSQ(push, NV827E, 0x0808, asyw->image.h << 16 | asyw->image.w, + 0x080c, asyw->image.layout << 20 | + (asyw->image.pitch[0] >> 8) << 8 | + asyw->image.blocks[0] << 8 | + asyw->image.blockh, + 0x0810, asyw->image.format << 8 | + asyw->image.colorspace); + return 0; } int diff --git a/drivers/gpu/drm/nouveau/dispnv50/ovly907e.c b/drivers/gpu/drm/nouveau/dispnv50/ovly907e.c index 73fb5d4eb343..6b83daff1560 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/ovly907e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/ovly907e.c @@ -22,29 +22,29 @@ #include "ovly.h" #include "atom.h" -static void +#include + +static int ovly907e_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) { - u32 *push; - if ((push = evo_wait(&wndw->wndw, 12))) { - evo_mthd(push, 0x0084, 1); - evo_data(push, asyw->image.interval << 4); - evo_mthd(push, 0x00c0, 1); - evo_data(push, asyw->image.handle[0]); - evo_mthd(push, 0x0100, 1); - evo_data(push, 0x00000002); - evo_mthd(push, 0x0400, 1); - evo_data(push, asyw->image.offset[0] >> 8); - evo_mthd(push, 0x0408, 3); - evo_data(push, asyw->image.h << 16 | asyw->image.w); - evo_data(push, asyw->image.layout << 24 | - (asyw->image.pitch[0] >> 8) << 8 | - asyw->image.blocks[0] << 8 | - asyw->image.blockh); - evo_data(push, asyw->image.format << 8 | - asyw->image.colorspace); - evo_kick(push, &wndw->wndw); - } + struct nvif_push *push = wndw->wndw.push; + int ret; + + if ((ret = PUSH_WAIT(push, 12))) + return ret; + + PUSH_NVSQ(push, NV907E, 0x0084, asyw->image.interval << 4); + PUSH_NVSQ(push, NV907E, 0x00c0, asyw->image.handle[0]); + PUSH_NVSQ(push, NV907E, 0x0100, 0x00000002); + PUSH_NVSQ(push, NV907E, 0x0400, asyw->image.offset[0] >> 8); + PUSH_NVSQ(push, NV907E, 0x0408, asyw->image.h << 16 | asyw->image.w, + 0x040c, asyw->image.layout << 24 | + (asyw->image.pitch[0] >> 8) << 8 | + asyw->image.blocks[0] << 8 | + asyw->image.blockh, + 0x0410, asyw->image.format << 8 | + asyw->image.colorspace); + return 0; } const struct nv50_wndw_func diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndw.h b/drivers/gpu/drm/nouveau/dispnv50/wndw.h index 6baf27090fc2..d6e1c29da379 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndw.h +++ b/drivers/gpu/drm/nouveau/dispnv50/wndw.h @@ -74,7 +74,7 @@ struct nv50_wndw_func { bool olut_core; int (*xlut_set)(struct nv50_wndw *, struct nv50_wndw_atom *); int (*xlut_clr)(struct nv50_wndw *); - void (*image_set)(struct nv50_wndw *, struct nv50_wndw_atom *); + int (*image_set)(struct nv50_wndw *, struct nv50_wndw_atom *); void (*image_clr)(struct nv50_wndw *); void (*scale_set)(struct nv50_wndw *, struct nv50_wndw_atom *); void (*blend_set)(struct nv50_wndw *, struct nv50_wndw_atom *); diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c index eab1c322eccb..24cb4e9b356e 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c @@ -125,37 +125,34 @@ wndwc37e_image_clr(struct nv50_wndw *wndw) } } -static void +static int wndwc37e_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) { - u32 *push; + struct nvif_push *push = wndw->wndw.push; + int ret; - if (!(push = evo_wait(&wndw->wndw, 17))) - return; + if ((ret = PUSH_WAIT(push, 17))) + return ret; - evo_mthd(push, 0x0308, 1); - evo_data(push, asyw->image.mode << 4 | asyw->image.interval); - evo_mthd(push, 0x0224, 4); - evo_data(push, asyw->image.h << 16 | asyw->image.w); - evo_data(push, asyw->image.layout << 4 | asyw->image.blockh); - evo_data(push, asyw->csc.valid << 17 | - asyw->image.colorspace << 8 | - asyw->image.format); - evo_data(push, asyw->image.blocks[0] | (asyw->image.pitch[0] >> 6)); - evo_mthd(push, 0x0240, 1); - evo_data(push, asyw->image.handle[0]); - evo_mthd(push, 0x0260, 1); - evo_data(push, asyw->image.offset[0] >> 8); - evo_mthd(push, 0x0290, 1); - evo_data(push, (asyw->state.src_y >> 16) << 16 | - (asyw->state.src_x >> 16)); - evo_mthd(push, 0x0298, 1); - evo_data(push, (asyw->state.src_h >> 16) << 16 | - (asyw->state.src_w >> 16)); - evo_mthd(push, 0x02a4, 1); - evo_data(push, asyw->state.crtc_h << 16 | - asyw->state.crtc_w); - evo_kick(push, &wndw->wndw); + PUSH_NVSQ(push, NVC37E, 0x0308, asyw->image.mode << 4 | + asyw->image.interval); + PUSH_NVSQ(push, NVC37E, 0x0224, asyw->image.h << 16 | asyw->image.w, + 0x0228, asyw->image.layout << 4 | + asyw->image.blockh, + 0x022c, asyw->csc.valid << 17 | + asyw->image.colorspace << 8 | + asyw->image.format, + 0x0230, asyw->image.blocks[0] | + (asyw->image.pitch[0] >> 6)); + PUSH_NVSQ(push, NVC37E, 0x0240, asyw->image.handle[0]); + PUSH_NVSQ(push, NVC37E, 0x0260, asyw->image.offset[0] >> 8); + PUSH_NVSQ(push, NVC37E, 0x0290,(asyw->state.src_y >> 16) << 16 | + (asyw->state.src_x >> 16)); + PUSH_NVSQ(push, NVC37E, 0x0298,(asyw->state.src_h >> 16) << 16 | + (asyw->state.src_w >> 16)); + PUSH_NVSQ(push, NVC37E, 0x02a4, asyw->state.crtc_h << 16 | + asyw->state.crtc_w); + return 0; } int diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c b/drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c index f393399baab1..687cb7378c69 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c @@ -29,36 +29,33 @@ #include #include -static void +static int wndwc57e_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) { - u32 *push; + struct nvif_push *push = wndw->wndw.push; + int ret; - if (!(push = evo_wait(&wndw->wndw, 17))) - return; + if ((ret = PUSH_WAIT(push, 17))) + return ret; - evo_mthd(push, 0x0308, 1); - evo_data(push, asyw->image.mode << 4 | asyw->image.interval); - evo_mthd(push, 0x0224, 4); - evo_data(push, asyw->image.h << 16 | asyw->image.w); - evo_data(push, asyw->image.layout << 4 | asyw->image.blockh); - evo_data(push, asyw->image.colorspace << 8 | - asyw->image.format); - evo_data(push, asyw->image.blocks[0] | (asyw->image.pitch[0] >> 6)); - evo_mthd(push, 0x0240, 1); - evo_data(push, asyw->image.handle[0]); - evo_mthd(push, 0x0260, 1); - evo_data(push, asyw->image.offset[0] >> 8); - evo_mthd(push, 0x0290, 1); - evo_data(push, (asyw->state.src_y >> 16) << 16 | - (asyw->state.src_x >> 16)); - evo_mthd(push, 0x0298, 1); - evo_data(push, (asyw->state.src_h >> 16) << 16 | - (asyw->state.src_w >> 16)); - evo_mthd(push, 0x02a4, 1); - evo_data(push, asyw->state.crtc_h << 16 | - asyw->state.crtc_w); - evo_kick(push, &wndw->wndw); + PUSH_NVSQ(push, NVC57E, 0x0308, asyw->image.mode << 4 | + asyw->image.interval); + PUSH_NVSQ(push, NVC57E, 0x0224, asyw->image.h << 16 | asyw->image.w, + 0x0228, asyw->image.layout << 4 | + asyw->image.blockh, + 0x022c, asyw->image.colorspace << 8 | + asyw->image.format, + 0x0230, asyw->image.blocks[0] | + (asyw->image.pitch[0] >> 6)); + PUSH_NVSQ(push, NVC57E, 0x0240, asyw->image.handle[0]); + PUSH_NVSQ(push, NVC57E, 0x0260, asyw->image.offset[0] >> 8); + PUSH_NVSQ(push, NVC57E, 0x0290,(asyw->state.src_y >> 16) << 16 | + (asyw->state.src_x >> 16)); + PUSH_NVSQ(push, NVC57E, 0x0298,(asyw->state.src_h >> 16) << 16 | + (asyw->state.src_w >> 16)); + PUSH_NVSQ(push, NVC57E, 0x02a4, asyw->state.crtc_h << 16 | + asyw->state.crtc_w); + return 0; } static int From 8944d8b37ac9eecfff5706e9a11d5fcb3df64dbb Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sat, 20 Jun 2020 09:23:10 +1000 Subject: [PATCH 050/145] drm/nouveau/kms/nv50-: convert wndw image_clr() to new push macros Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/base.h | 1 - drivers/gpu/drm/nouveau/dispnv50/base507c.c | 19 ++++++++++--------- drivers/gpu/drm/nouveau/dispnv50/ovly.h | 1 - drivers/gpu/drm/nouveau/dispnv50/ovly507e.c | 15 +-------------- drivers/gpu/drm/nouveau/dispnv50/ovly827e.c | 2 +- drivers/gpu/drm/nouveau/dispnv50/ovly907e.c | 2 +- drivers/gpu/drm/nouveau/dispnv50/wndw.h | 5 +++-- drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c | 19 ++++++++++--------- 8 files changed, 26 insertions(+), 38 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/base.h b/drivers/gpu/drm/nouveau/dispnv50/base.h index fe362aa03c8e..826f141d0d94 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/base.h +++ b/drivers/gpu/drm/nouveau/dispnv50/base.h @@ -15,7 +15,6 @@ int base507c_sema_set(struct nv50_wndw *, struct nv50_wndw_atom *); int base507c_sema_clr(struct nv50_wndw *); int base507c_xlut_set(struct nv50_wndw *, struct nv50_wndw_atom *); int base507c_xlut_clr(struct nv50_wndw *); -void base507c_image_clr(struct nv50_wndw *); void base507c_update(struct nv50_wndw *, u32 *); int base827c_new(struct nouveau_drm *, int, s32, struct nv50_wndw **); diff --git a/drivers/gpu/drm/nouveau/dispnv50/base507c.c b/drivers/gpu/drm/nouveau/dispnv50/base507c.c index ae1c5cc00957..40c2f0712203 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/base507c.c +++ b/drivers/gpu/drm/nouveau/dispnv50/base507c.c @@ -43,17 +43,18 @@ base507c_update(struct nv50_wndw *wndw, u32 *interlock) } } -void +int base507c_image_clr(struct nv50_wndw *wndw) { - u32 *push; - if ((push = evo_wait(&wndw->wndw, 4))) { - evo_mthd(push, 0x0084, 1); - evo_data(push, 0x00000000); - evo_mthd(push, 0x00c0, 1); - evo_data(push, 0x00000000); - evo_kick(push, &wndw->wndw); - } + struct nvif_push *push = wndw->wndw.push; + int ret; + + if ((ret = PUSH_WAIT(push, 4))) + return ret; + + PUSH_NVSQ(push, NV507C, 0x0084, 0x00000000); + PUSH_NVSQ(push, NV507C, 0x00c0, 0x00000000); + return 0; } static int diff --git a/drivers/gpu/drm/nouveau/dispnv50/ovly.h b/drivers/gpu/drm/nouveau/dispnv50/ovly.h index 1048fc6bc778..89e84c66a081 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/ovly.h +++ b/drivers/gpu/drm/nouveau/dispnv50/ovly.h @@ -10,7 +10,6 @@ int ovly507e_acquire(struct nv50_wndw *, struct nv50_wndw_atom *, struct nv50_head_atom *); void ovly507e_release(struct nv50_wndw *, struct nv50_wndw_atom *, struct nv50_head_atom *); -void ovly507e_image_clr(struct nv50_wndw *); void ovly507e_scale_set(struct nv50_wndw *, struct nv50_wndw_atom *); void ovly507e_update(struct nv50_wndw *, u32 *); diff --git a/drivers/gpu/drm/nouveau/dispnv50/ovly507e.c b/drivers/gpu/drm/nouveau/dispnv50/ovly507e.c index e182f376900f..1460dc529420 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/ovly507e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/ovly507e.c @@ -54,19 +54,6 @@ ovly507e_scale_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) } } -void -ovly507e_image_clr(struct nv50_wndw *wndw) -{ - u32 *push; - if ((push = evo_wait(&wndw->wndw, 4))) { - evo_mthd(push, 0x0084, 1); - evo_data(push, 0x00000000); - evo_mthd(push, 0x00c0, 1); - evo_data(push, 0x00000000); - evo_kick(push, &wndw->wndw); - } -} - static int ovly507e_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) { @@ -127,7 +114,7 @@ ovly507e = { .ntfy_reset = base507c_ntfy_reset, .ntfy_wait_begun = base507c_ntfy_wait_begun, .image_set = ovly507e_image_set, - .image_clr = ovly507e_image_clr, + .image_clr = base507c_image_clr, .scale_set = ovly507e_scale_set, .update = ovly507e_update, }; diff --git a/drivers/gpu/drm/nouveau/dispnv50/ovly827e.c b/drivers/gpu/drm/nouveau/dispnv50/ovly827e.c index cb0f372cbcf7..77e19a024ac8 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/ovly827e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/ovly827e.c @@ -81,7 +81,7 @@ ovly827e = { .ntfy_reset = ovly827e_ntfy_reset, .ntfy_wait_begun = ovly827e_ntfy_wait_begun, .image_set = ovly827e_image_set, - .image_clr = ovly507e_image_clr, + .image_clr = base507c_image_clr, .scale_set = ovly507e_scale_set, .update = ovly507e_update, }; diff --git a/drivers/gpu/drm/nouveau/dispnv50/ovly907e.c b/drivers/gpu/drm/nouveau/dispnv50/ovly907e.c index 6b83daff1560..c77a3b4b3cc9 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/ovly907e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/ovly907e.c @@ -56,7 +56,7 @@ ovly907e = { .ntfy_reset = ovly827e_ntfy_reset, .ntfy_wait_begun = ovly827e_ntfy_wait_begun, .image_set = ovly907e_image_set, - .image_clr = ovly507e_image_clr, + .image_clr = base507c_image_clr, .scale_set = ovly507e_scale_set, .update = ovly507e_update, }; diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndw.h b/drivers/gpu/drm/nouveau/dispnv50/wndw.h index d6e1c29da379..41b418177646 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndw.h +++ b/drivers/gpu/drm/nouveau/dispnv50/wndw.h @@ -75,7 +75,7 @@ struct nv50_wndw_func { int (*xlut_set)(struct nv50_wndw *, struct nv50_wndw_atom *); int (*xlut_clr)(struct nv50_wndw *); int (*image_set)(struct nv50_wndw *, struct nv50_wndw_atom *); - void (*image_clr)(struct nv50_wndw *); + int (*image_clr)(struct nv50_wndw *); void (*scale_set)(struct nv50_wndw *, struct nv50_wndw_atom *); void (*blend_set)(struct nv50_wndw *, struct nv50_wndw_atom *); @@ -88,6 +88,7 @@ void base507c_ntfy_reset(struct nouveau_bo *, u32); int base507c_ntfy_set(struct nv50_wndw *, struct nv50_wndw_atom *); int base507c_ntfy_clr(struct nv50_wndw *); int base507c_ntfy_wait_begun(struct nouveau_bo *, u32, struct nvif_device *); +int base507c_image_clr(struct nv50_wndw *); void base907c_csc(struct nv50_wndw *, struct nv50_wndw_atom *, const struct drm_color_ctm *); @@ -121,7 +122,7 @@ int wndwc37e_sema_set(struct nv50_wndw *, struct nv50_wndw_atom *); int wndwc37e_sema_clr(struct nv50_wndw *); int wndwc37e_ntfy_set(struct nv50_wndw *, struct nv50_wndw_atom *); int wndwc37e_ntfy_clr(struct nv50_wndw *); -void wndwc37e_image_clr(struct nv50_wndw *); +int wndwc37e_image_clr(struct nv50_wndw *); void wndwc37e_blend_set(struct nv50_wndw *, struct nv50_wndw_atom *); void wndwc37e_update(struct nv50_wndw *, u32 *); diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c index 24cb4e9b356e..8b9afc6c6924 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c @@ -112,17 +112,18 @@ wndwc37e_blend_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) } } -void +int wndwc37e_image_clr(struct nv50_wndw *wndw) { - u32 *push; - if ((push = evo_wait(&wndw->wndw, 4))) { - evo_mthd(push, 0x0308, 1); - evo_data(push, 0x00000000); - evo_mthd(push, 0x0240, 1); - evo_data(push, 0x00000000); - evo_kick(push, &wndw->wndw); - } + struct nvif_push *push = wndw->wndw.push; + int ret; + + if ((ret = PUSH_WAIT(push, 4))) + return ret; + + PUSH_NVSQ(push, NVC37E, 0x0308, 0x00000000); + PUSH_NVSQ(push, NVC37E, 0x0240, 0x00000000); + return 0; } static int From 0a4693e80dc9a57f2133439e58a697f2d7730c4d Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sat, 20 Jun 2020 09:24:21 +1000 Subject: [PATCH 051/145] drm/nouveau/kms/nv50-: convert wndw scale_set() to new push macros Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/ovly.h | 2 +- drivers/gpu/drm/nouveau/dispnv50/ovly507e.c | 20 +++++++++++--------- drivers/gpu/drm/nouveau/dispnv50/wndw.h | 2 +- 3 files changed, 13 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/ovly.h b/drivers/gpu/drm/nouveau/dispnv50/ovly.h index 89e84c66a081..71710fdaf1fa 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/ovly.h +++ b/drivers/gpu/drm/nouveau/dispnv50/ovly.h @@ -10,7 +10,7 @@ int ovly507e_acquire(struct nv50_wndw *, struct nv50_wndw_atom *, struct nv50_head_atom *); void ovly507e_release(struct nv50_wndw *, struct nv50_wndw_atom *, struct nv50_head_atom *); -void ovly507e_scale_set(struct nv50_wndw *, struct nv50_wndw_atom *); +int ovly507e_scale_set(struct nv50_wndw *, struct nv50_wndw_atom *); void ovly507e_update(struct nv50_wndw *, u32 *); extern const u32 ovly827e_format[]; diff --git a/drivers/gpu/drm/nouveau/dispnv50/ovly507e.c b/drivers/gpu/drm/nouveau/dispnv50/ovly507e.c index 1460dc529420..77f3c9789717 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/ovly507e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/ovly507e.c @@ -41,17 +41,19 @@ ovly507e_update(struct nv50_wndw *wndw, u32 *interlock) } } -void +int ovly507e_scale_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) { - u32 *push; - if ((push = evo_wait(&wndw->wndw, 4))) { - evo_mthd(push, 0x00e0, 3); - evo_data(push, asyw->scale.sy << 16 | asyw->scale.sx); - evo_data(push, asyw->scale.sh << 16 | asyw->scale.sw); - evo_data(push, asyw->scale.dw); - evo_kick(push, &wndw->wndw); - } + struct nvif_push *push = wndw->wndw.push; + int ret; + + if ((ret = PUSH_WAIT(push, 4))) + return ret; + + PUSH_NVSQ(push, NV507E, 0x00e0, asyw->scale.sy << 16 | asyw->scale.sx, + 0x00e4, asyw->scale.sh << 16 | asyw->scale.sw, + 0x00e8, asyw->scale.dw); + return 0; } static int diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndw.h b/drivers/gpu/drm/nouveau/dispnv50/wndw.h index 41b418177646..92985e332531 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndw.h +++ b/drivers/gpu/drm/nouveau/dispnv50/wndw.h @@ -76,7 +76,7 @@ struct nv50_wndw_func { int (*xlut_clr)(struct nv50_wndw *); int (*image_set)(struct nv50_wndw *, struct nv50_wndw_atom *); int (*image_clr)(struct nv50_wndw *); - void (*scale_set)(struct nv50_wndw *, struct nv50_wndw_atom *); + int (*scale_set)(struct nv50_wndw *, struct nv50_wndw_atom *); void (*blend_set)(struct nv50_wndw *, struct nv50_wndw_atom *); void (*update)(struct nv50_wndw *, u32 *interlock); From 85bdfcd4358832fd7185b27343ad305bf78b4269 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sat, 20 Jun 2020 09:25:55 +1000 Subject: [PATCH 052/145] drm/nouveau/kms/nv50-: convert wndw blend_set() to new push macros Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/wndw.h | 4 +-- drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c | 34 +++++++++++---------- 2 files changed, 20 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndw.h b/drivers/gpu/drm/nouveau/dispnv50/wndw.h index 92985e332531..89c1d5602495 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndw.h +++ b/drivers/gpu/drm/nouveau/dispnv50/wndw.h @@ -77,7 +77,7 @@ struct nv50_wndw_func { int (*image_set)(struct nv50_wndw *, struct nv50_wndw_atom *); int (*image_clr)(struct nv50_wndw *); int (*scale_set)(struct nv50_wndw *, struct nv50_wndw_atom *); - void (*blend_set)(struct nv50_wndw *, struct nv50_wndw_atom *); + int (*blend_set)(struct nv50_wndw *, struct nv50_wndw_atom *); void (*update)(struct nv50_wndw *, u32 *interlock); }; @@ -123,7 +123,7 @@ int wndwc37e_sema_clr(struct nv50_wndw *); int wndwc37e_ntfy_set(struct nv50_wndw *, struct nv50_wndw_atom *); int wndwc37e_ntfy_clr(struct nv50_wndw *); int wndwc37e_image_clr(struct nv50_wndw *); -void wndwc37e_blend_set(struct nv50_wndw *, struct nv50_wndw_atom *); +int wndwc37e_blend_set(struct nv50_wndw *, struct nv50_wndw_atom *); void wndwc37e_update(struct nv50_wndw *, u32 *); int wndwc57e_new(struct nouveau_drm *, enum drm_plane_type, int, s32, diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c index 8b9afc6c6924..8c9b0a0c289a 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c @@ -92,24 +92,26 @@ wndwc37e_ilut(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw, int size) return true; } -void +int wndwc37e_blend_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) { - u32 *push; - if ((push = evo_wait(&wndw->wndw, 8))) { - evo_mthd(push, 0x02ec, 7); - evo_data(push, asyw->blend.depth << 4); - evo_data(push, asyw->blend.k1); - evo_data(push, asyw->blend.dst_color << 12 | - asyw->blend.dst_color << 8 | - asyw->blend.src_color << 4 | - asyw->blend.src_color); - evo_data(push, 0xffff0000); - evo_data(push, 0xffff0000); - evo_data(push, 0xffff0000); - evo_data(push, 0xffff0000); - evo_kick(push, &wndw->wndw); - } + struct nvif_push *push = wndw->wndw.push; + int ret; + + if ((ret = PUSH_WAIT(push, 8))) + return ret; + + PUSH_NVSQ(push, NVC37E, 0x02ec, asyw->blend.depth << 4, + 0x02f0, asyw->blend.k1, + 0x02f4, asyw->blend.dst_color << 12 | + asyw->blend.dst_color << 8 | + asyw->blend.src_color << 4 | + asyw->blend.src_color, + 0x02f8, 0xffff0000, + 0x02fc, 0xffff0000, + 0x0300, 0xffff0000, + 0x0304, 0xffff0000); + return 0; } int From 3afb4db782a3bf4e6f14912d7aeb534264d2d2e3 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sat, 20 Jun 2020 09:32:58 +1000 Subject: [PATCH 053/145] drm/nouveau/kms/nv50-: convert wndw update() to new push macros Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/base.h | 1 - drivers/gpu/drm/nouveau/dispnv50/base507c.c | 16 ++++++------ drivers/gpu/drm/nouveau/dispnv50/ovly.h | 1 - drivers/gpu/drm/nouveau/dispnv50/ovly507e.c | 13 +--------- drivers/gpu/drm/nouveau/dispnv50/ovly827e.c | 2 +- drivers/gpu/drm/nouveau/dispnv50/ovly907e.c | 2 +- drivers/gpu/drm/nouveau/dispnv50/wndw.h | 5 ++-- drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c | 28 ++++++++++----------- 8 files changed, 29 insertions(+), 39 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/base.h b/drivers/gpu/drm/nouveau/dispnv50/base.h index 826f141d0d94..085bd3aeb40b 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/base.h +++ b/drivers/gpu/drm/nouveau/dispnv50/base.h @@ -15,7 +15,6 @@ int base507c_sema_set(struct nv50_wndw *, struct nv50_wndw_atom *); int base507c_sema_clr(struct nv50_wndw *); int base507c_xlut_set(struct nv50_wndw *, struct nv50_wndw_atom *); int base507c_xlut_clr(struct nv50_wndw *); -void base507c_update(struct nv50_wndw *, u32 *); int base827c_new(struct nouveau_drm *, int, s32, struct nv50_wndw **); diff --git a/drivers/gpu/drm/nouveau/dispnv50/base507c.c b/drivers/gpu/drm/nouveau/dispnv50/base507c.c index 40c2f0712203..e5f189859bde 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/base507c.c +++ b/drivers/gpu/drm/nouveau/dispnv50/base507c.c @@ -32,15 +32,17 @@ #include "nouveau_bo.h" -void +int base507c_update(struct nv50_wndw *wndw, u32 *interlock) { - u32 *push; - if ((push = evo_wait(&wndw->wndw, 2))) { - evo_mthd(push, 0x0080, 1); - evo_data(push, interlock[NV50_DISP_INTERLOCK_CORE]); - evo_kick(push, &wndw->wndw); - } + struct nvif_push *push = wndw->wndw.push; + int ret; + + if ((ret = PUSH_WAIT(push, 2))) + return ret; + + PUSH_NVSQ(push, NV507C, 0x0080, interlock[NV50_DISP_INTERLOCK_CORE]); + return PUSH_KICK(push); } int diff --git a/drivers/gpu/drm/nouveau/dispnv50/ovly.h b/drivers/gpu/drm/nouveau/dispnv50/ovly.h index 71710fdaf1fa..6ae1fbe12ca7 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/ovly.h +++ b/drivers/gpu/drm/nouveau/dispnv50/ovly.h @@ -11,7 +11,6 @@ int ovly507e_acquire(struct nv50_wndw *, struct nv50_wndw_atom *, void ovly507e_release(struct nv50_wndw *, struct nv50_wndw_atom *, struct nv50_head_atom *); int ovly507e_scale_set(struct nv50_wndw *, struct nv50_wndw_atom *); -void ovly507e_update(struct nv50_wndw *, u32 *); extern const u32 ovly827e_format[]; void ovly827e_ntfy_reset(struct nouveau_bo *, u32); diff --git a/drivers/gpu/drm/nouveau/dispnv50/ovly507e.c b/drivers/gpu/drm/nouveau/dispnv50/ovly507e.c index 77f3c9789717..b46c95e71e49 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/ovly507e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/ovly507e.c @@ -30,17 +30,6 @@ #include #include -void -ovly507e_update(struct nv50_wndw *wndw, u32 *interlock) -{ - u32 *push; - if ((push = evo_wait(&wndw->wndw, 2))) { - evo_mthd(push, 0x0080, 1); - evo_data(push, interlock[NV50_DISP_INTERLOCK_CORE]); - evo_kick(push, &wndw->wndw); - } -} - int ovly507e_scale_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) { @@ -118,7 +107,7 @@ ovly507e = { .image_set = ovly507e_image_set, .image_clr = base507c_image_clr, .scale_set = ovly507e_scale_set, - .update = ovly507e_update, + .update = base507c_update, }; static const u32 diff --git a/drivers/gpu/drm/nouveau/dispnv50/ovly827e.c b/drivers/gpu/drm/nouveau/dispnv50/ovly827e.c index 77e19a024ac8..40b89f8648c4 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/ovly827e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/ovly827e.c @@ -83,7 +83,7 @@ ovly827e = { .image_set = ovly827e_image_set, .image_clr = base507c_image_clr, .scale_set = ovly507e_scale_set, - .update = ovly507e_update, + .update = base507c_update, }; const u32 diff --git a/drivers/gpu/drm/nouveau/dispnv50/ovly907e.c b/drivers/gpu/drm/nouveau/dispnv50/ovly907e.c index c77a3b4b3cc9..b2780f5f6e64 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/ovly907e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/ovly907e.c @@ -58,7 +58,7 @@ ovly907e = { .image_set = ovly907e_image_set, .image_clr = base507c_image_clr, .scale_set = ovly507e_scale_set, - .update = ovly507e_update, + .update = base507c_update, }; static const u32 diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndw.h b/drivers/gpu/drm/nouveau/dispnv50/wndw.h index 89c1d5602495..3278e2880034 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndw.h +++ b/drivers/gpu/drm/nouveau/dispnv50/wndw.h @@ -79,7 +79,7 @@ struct nv50_wndw_func { int (*scale_set)(struct nv50_wndw *, struct nv50_wndw_atom *); int (*blend_set)(struct nv50_wndw *, struct nv50_wndw_atom *); - void (*update)(struct nv50_wndw *, u32 *interlock); + int (*update)(struct nv50_wndw *, u32 *interlock); }; extern const struct drm_plane_funcs nv50_wndw; @@ -89,6 +89,7 @@ int base507c_ntfy_set(struct nv50_wndw *, struct nv50_wndw_atom *); int base507c_ntfy_clr(struct nv50_wndw *); int base507c_ntfy_wait_begun(struct nouveau_bo *, u32, struct nvif_device *); int base507c_image_clr(struct nv50_wndw *); +int base507c_update(struct nv50_wndw *, u32 *); void base907c_csc(struct nv50_wndw *, struct nv50_wndw_atom *, const struct drm_color_ctm *); @@ -124,7 +125,7 @@ int wndwc37e_ntfy_set(struct nv50_wndw *, struct nv50_wndw_atom *); int wndwc37e_ntfy_clr(struct nv50_wndw *); int wndwc37e_image_clr(struct nv50_wndw *); int wndwc37e_blend_set(struct nv50_wndw *, struct nv50_wndw_atom *); -void wndwc37e_update(struct nv50_wndw *, u32 *); +int wndwc37e_update(struct nv50_wndw *, u32 *); int wndwc57e_new(struct nouveau_drm *, enum drm_plane_type, int, s32, struct nv50_wndw **); diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c index 8c9b0a0c289a..b000b3a86371 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c @@ -215,22 +215,22 @@ wndwc37e_sema_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) return 0; } -void +int wndwc37e_update(struct nv50_wndw *wndw, u32 *interlock) { - u32 *push; - if ((push = evo_wait(&wndw->wndw, 5))) { - evo_mthd(push, 0x0370, 2); - evo_data(push, interlock[NV50_DISP_INTERLOCK_CURS] << 1 | - interlock[NV50_DISP_INTERLOCK_CORE]); - evo_data(push, interlock[NV50_DISP_INTERLOCK_WNDW]); - evo_mthd(push, 0x0200, 1); - if (interlock[NV50_DISP_INTERLOCK_WIMM] & wndw->interlock.data) - evo_data(push, 0x00001001); - else - evo_data(push, 0x00000001); - evo_kick(push, &wndw->wndw); - } + struct nvif_push *push = wndw->wndw.push; + int ret; + + if ((ret = PUSH_WAIT(push, 5))) + return ret; + + PUSH_NVSQ(push, NVC37E, 0x0370, interlock[NV50_DISP_INTERLOCK_CURS] << 1 | + interlock[NV50_DISP_INTERLOCK_CORE], + 0x0374, interlock[NV50_DISP_INTERLOCK_WNDW]); + PUSH_NVSQ(push, NVC37E, 0x0200,((interlock[NV50_DISP_INTERLOCK_WIMM] & + wndw->interlock.data) ? 0x00001000 : 0x00000000) | + 0x00000001); + return PUSH_KICK(push); } void From 5e691222eac66e730e0fa6bd10e7564f3db202d5 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sat, 20 Jun 2020 17:04:57 +1000 Subject: [PATCH 054/145] drm/nouveau/kms/nv50-: convert core init() to new push macros Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/core.h | 4 +-- drivers/gpu/drm/nouveau/dispnv50/core507d.c | 17 +++++----- drivers/gpu/drm/nouveau/dispnv50/corec37d.c | 35 +++++++++++---------- drivers/gpu/drm/nouveau/dispnv50/corec57d.c | 32 ++++++++++--------- 4 files changed, 49 insertions(+), 39 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/core.h b/drivers/gpu/drm/nouveau/dispnv50/core.h index e021cb340569..15a4ce92fa25 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/core.h +++ b/drivers/gpu/drm/nouveau/dispnv50/core.h @@ -15,7 +15,7 @@ int nv50_core_new(struct nouveau_drm *, struct nv50_core **); void nv50_core_del(struct nv50_core **); struct nv50_core_func { - void (*init)(struct nv50_core *); + int (*init)(struct nv50_core *); void (*ntfy_init)(struct nouveau_bo *, u32 offset); int (*caps_init)(struct nouveau_drm *, struct nv50_disp *); int (*ntfy_wait_done)(struct nouveau_bo *, u32 offset, @@ -42,7 +42,7 @@ struct nv50_core_func { int core507d_new(struct nouveau_drm *, s32, struct nv50_core **); int core507d_new_(const struct nv50_core_func *, struct nouveau_drm *, s32, struct nv50_core **); -void core507d_init(struct nv50_core *); +int core507d_init(struct nv50_core *); void core507d_ntfy_init(struct nouveau_bo *, u32); int core507d_caps_init(struct nouveau_drm *, struct nv50_disp *); int core507d_ntfy_wait_done(struct nouveau_bo *, u32, struct nvif_device *); diff --git a/drivers/gpu/drm/nouveau/dispnv50/core507d.c b/drivers/gpu/drm/nouveau/dispnv50/core507d.c index 1d66f694b945..ce6f6494d445 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/core507d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/core507d.c @@ -23,6 +23,7 @@ #include "head.h" #include +#include #include #include "nouveau_bo.h" @@ -76,15 +77,17 @@ core507d_caps_init(struct nouveau_drm *drm, struct nv50_disp *disp) return 0; } -void +int core507d_init(struct nv50_core *core) { - u32 *push; - if ((push = evo_wait(&core->chan, 2))) { - evo_mthd(push, 0x0088, 1); - evo_data(push, core->chan.sync.handle); - evo_kick(push, &core->chan); - } + struct nvif_push *push = core->chan.push; + int ret; + + if ((ret = PUSH_WAIT(push, 2))) + return ret; + + PUSH_NVSQ(push, NV507D, 0x0088, core->chan.sync.handle); + return PUSH_KICK(push); } static const struct nv50_core_func diff --git a/drivers/gpu/drm/nouveau/dispnv50/corec37d.c b/drivers/gpu/drm/nouveau/dispnv50/corec37d.c index a4a307e13b9f..59eef8de793f 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/corec37d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/corec37d.c @@ -23,10 +23,11 @@ #include "head.h" #include -#include - +#include #include +#include + void corec37d_wndw_owner(struct nv50_core *core) { @@ -112,24 +113,26 @@ int corec37d_caps_init(struct nouveau_drm *drm, struct nv50_disp *disp) return 0; } -static void +static int corec37d_init(struct nv50_core *core) { + struct nvif_push *push = core->chan.push; const u32 windows = 8; /*XXX*/ - u32 *push, i; - if ((push = evo_wait(&core->chan, 2 + 5 * windows))) { - evo_mthd(push, 0x0208, 1); - evo_data(push, core->chan.sync.handle); - for (i = 0; i < windows; i++) { - evo_mthd(push, 0x1004 + (i * 0x080), 2); - evo_data(push, 0x0000001f); - evo_data(push, 0x00000000); - evo_mthd(push, 0x1010 + (i * 0x080), 1); - evo_data(push, 0x00127fff); - } - evo_kick(push, &core->chan); - core->assign_windows = true; + int ret, i; + + if ((ret = PUSH_WAIT(push, 2 + windows * 5))) + return ret; + + PUSH_NVSQ(push, NVC37D, 0x0208, core->chan.sync.handle); + + for (i = 0; i < windows; i++) { + PUSH_NVSQ(push, NVC37D, 0x1004 + (i * 0x080), 0x0000001f, + 0x1008 + (i * 0x080), 0x00000000); + PUSH_NVSQ(push, NVC37D, 0x1010 + (i * 0x080), 0x00127fff); } + + core->assign_windows = true; + return PUSH_KICK(push); } static const struct nv50_core_func diff --git a/drivers/gpu/drm/nouveau/dispnv50/corec57d.c b/drivers/gpu/drm/nouveau/dispnv50/corec57d.c index e1c11eba0ce1..afc703a05fea 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/corec57d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/corec57d.c @@ -22,24 +22,28 @@ #include "core.h" #include "head.h" -static void +#include + +static int corec57d_init(struct nv50_core *core) { + struct nvif_push *push = core->chan.push; const u32 windows = 8; /*XXX*/ - u32 *push, i; - if ((push = evo_wait(&core->chan, 2 + 5 * windows))) { - evo_mthd(push, 0x0208, 1); - evo_data(push, core->chan.sync.handle); - for (i = 0; i < windows; i++) { - evo_mthd(push, 0x1004 + (i * 0x080), 2); - evo_data(push, 0x0000000f); - evo_data(push, 0x00000000); - evo_mthd(push, 0x1010 + (i * 0x080), 1); - evo_data(push, 0x00117fff); - } - evo_kick(push, &core->chan); - core->assign_windows = true; + int ret, i; + + if ((ret = PUSH_WAIT(push, 2 + windows * 5))) + return ret; + + PUSH_NVSQ(push, NVC57D, 0x0208, core->chan.sync.handle); + + for (i = 0; i < windows; i++) { + PUSH_NVSQ(push, NVC57D, 0x1004 + (i * 0x080), 0x0000000f, + 0x1008 + (i * 0x080), 0x00000000); + PUSH_NVSQ(push, NVC57D, 0x1010 + (i * 0x080), 0x00117fff); } + + core->assign_windows = true; + return PUSH_KICK(push); } static const struct nv50_core_func From 3c43c362b3a50a0e7d2cd5d6dc721a74d9e27694 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sat, 20 Jun 2020 17:06:41 +1000 Subject: [PATCH 055/145] drm/nouveau/kms/nv50-: convert core caps_init() to new push macros Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/core507d.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/core507d.c b/drivers/gpu/drm/nouveau/dispnv50/core507d.c index ce6f6494d445..455509c74d48 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/core507d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/core507d.c @@ -66,15 +66,14 @@ core507d_ntfy_init(struct nouveau_bo *bo, u32 offset) int core507d_caps_init(struct nouveau_drm *drm, struct nv50_disp *disp) { - u32 *push = evo_wait(&disp->core->chan, 2); + struct nvif_push *push = disp->core->chan.push; + int ret; - if (push) { - evo_mthd(push, 0x008c, 1); - evo_data(push, 0x0); - evo_kick(push, &disp->core->chan); - } + if ((ret = PUSH_WAIT(push, 2))) + return ret; - return 0; + PUSH_NVSQ(push, NV507D, 0x008c, 0x00000000); + return PUSH_KICK(push); } int From 203f6eaf4182bce0031888c5b7505750b8836758 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sat, 20 Jun 2020 17:10:46 +1000 Subject: [PATCH 056/145] drm/nouveau/kms/nv50-: convert core update() to new push macros Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/core.h | 6 ++-- drivers/gpu/drm/nouveau/dispnv50/core507d.c | 27 ++++++++-------- drivers/gpu/drm/nouveau/dispnv50/corec37d.c | 34 ++++++++++----------- 3 files changed, 33 insertions(+), 34 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/core.h b/drivers/gpu/drm/nouveau/dispnv50/core.h index 15a4ce92fa25..113368d62f02 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/core.h +++ b/drivers/gpu/drm/nouveau/dispnv50/core.h @@ -20,7 +20,7 @@ struct nv50_core_func { int (*caps_init)(struct nouveau_drm *, struct nv50_disp *); int (*ntfy_wait_done)(struct nouveau_bo *, u32 offset, struct nvif_device *); - void (*update)(struct nv50_core *, u32 *interlock, bool ntfy); + int (*update)(struct nv50_core *, u32 *interlock, bool ntfy); struct { void (*owner)(struct nv50_core *); @@ -46,7 +46,7 @@ int core507d_init(struct nv50_core *); void core507d_ntfy_init(struct nouveau_bo *, u32); int core507d_caps_init(struct nouveau_drm *, struct nv50_disp *); int core507d_ntfy_wait_done(struct nouveau_bo *, u32, struct nvif_device *); -void core507d_update(struct nv50_core *, u32 *, bool); +int core507d_update(struct nv50_core *, u32 *, bool); extern const struct nv50_outp_func dac507d; extern const struct nv50_outp_func sor507d; @@ -63,7 +63,7 @@ int core917d_new(struct nouveau_drm *, s32, struct nv50_core **); int corec37d_new(struct nouveau_drm *, s32, struct nv50_core **); int corec37d_caps_init(struct nouveau_drm *, struct nv50_disp *); int corec37d_ntfy_wait_done(struct nouveau_bo *, u32, struct nvif_device *); -void corec37d_update(struct nv50_core *, u32 *, bool); +int corec37d_update(struct nv50_core *, u32 *, bool); void corec37d_wndw_owner(struct nv50_core *); extern const struct nv50_outp_func sorc37d; diff --git a/drivers/gpu/drm/nouveau/dispnv50/core507d.c b/drivers/gpu/drm/nouveau/dispnv50/core507d.c index 455509c74d48..4938e4b751a4 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/core507d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/core507d.c @@ -28,21 +28,22 @@ #include "nouveau_bo.h" -void +int core507d_update(struct nv50_core *core, u32 *interlock, bool ntfy) { - u32 *push; - if ((push = evo_wait(&core->chan, 5))) { - if (ntfy) { - evo_mthd(push, 0x0084, 1); - evo_data(push, 0x80000000 | NV50_DISP_CORE_NTFY); - } - evo_mthd(push, 0x0080, 2); - evo_data(push, interlock[NV50_DISP_INTERLOCK_BASE] | - interlock[NV50_DISP_INTERLOCK_OVLY]); - evo_data(push, 0x00000000); - evo_kick(push, &core->chan); - } + struct nvif_push *push = core->chan.push; + int ret; + + if ((ret = PUSH_WAIT(push, 5))) + return ret; + + if (ntfy) + PUSH_NVSQ(push, NV507D, 0x0084, 0x80000000 | NV50_DISP_CORE_NTFY); + + PUSH_NVSQ(push, NV507D, 0x0080, interlock[NV50_DISP_INTERLOCK_BASE] | + interlock[NV50_DISP_INTERLOCK_OVLY], + 0x0084, 0x00000000); + return PUSH_KICK(push); } int diff --git a/drivers/gpu/drm/nouveau/dispnv50/corec37d.c b/drivers/gpu/drm/nouveau/dispnv50/corec37d.c index 59eef8de793f..38604f5a5d8b 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/corec37d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/corec37d.c @@ -42,28 +42,26 @@ corec37d_wndw_owner(struct nv50_core *core) } } -void +int corec37d_update(struct nv50_core *core, u32 *interlock, bool ntfy) { - u32 *push; - if ((push = evo_wait(&core->chan, 9))) { - if (ntfy) { - evo_mthd(push, 0x020c, 1); - evo_data(push, 0x00001000 | NV50_DISP_CORE_NTFY); - } + struct nvif_push *push = core->chan.push; + int ret; - evo_mthd(push, 0x0218, 2); - evo_data(push, interlock[NV50_DISP_INTERLOCK_CURS]); - evo_data(push, interlock[NV50_DISP_INTERLOCK_WNDW]); - evo_mthd(push, 0x0200, 1); - evo_data(push, 0x00000001); + if ((ret = PUSH_WAIT(push, 9))) + return ret; - if (ntfy) { - evo_mthd(push, 0x020c, 1); - evo_data(push, 0x00000000); - } - evo_kick(push, &core->chan); - } + if (ntfy) + PUSH_NVSQ(push, NVC37D, 0x020c, 0x00001000 | NV50_DISP_CORE_NTFY); + + PUSH_NVSQ(push, NVC37D, 0x0218, interlock[NV50_DISP_INTERLOCK_CURS], + 0x021c, interlock[NV50_DISP_INTERLOCK_WNDW]); + PUSH_NVSQ(push, NVC37D, 0x0200, 0x00000001); + + if (ntfy) + PUSH_NVSQ(push, NVC37D, 0x020c, 0x00000000); + + return PUSH_KICK(push); } int From b505935e56b299a82e153ddd4cacebb8fc9697ec Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sat, 20 Jun 2020 17:12:16 +1000 Subject: [PATCH 057/145] drm/nouveau/kms/nv50-: convert core wndw_owner() to new push macros Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/core.h | 4 ++-- drivers/gpu/drm/nouveau/dispnv50/corec37d.c | 20 +++++++++++--------- 2 files changed, 13 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/core.h b/drivers/gpu/drm/nouveau/dispnv50/core.h index 113368d62f02..7e061b8c9719 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/core.h +++ b/drivers/gpu/drm/nouveau/dispnv50/core.h @@ -23,7 +23,7 @@ struct nv50_core_func { int (*update)(struct nv50_core *, u32 *interlock, bool ntfy); struct { - void (*owner)(struct nv50_core *); + int (*owner)(struct nv50_core *); } wndw; const struct nv50_head_func *head; @@ -64,7 +64,7 @@ int corec37d_new(struct nouveau_drm *, s32, struct nv50_core **); int corec37d_caps_init(struct nouveau_drm *, struct nv50_disp *); int corec37d_ntfy_wait_done(struct nouveau_bo *, u32, struct nvif_device *); int corec37d_update(struct nv50_core *, u32 *, bool); -void corec37d_wndw_owner(struct nv50_core *); +int corec37d_wndw_owner(struct nv50_core *); extern const struct nv50_outp_func sorc37d; int corec57d_new(struct nouveau_drm *, s32, struct nv50_core **); diff --git a/drivers/gpu/drm/nouveau/dispnv50/corec37d.c b/drivers/gpu/drm/nouveau/dispnv50/corec37d.c index 38604f5a5d8b..1b3d5896640e 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/corec37d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/corec37d.c @@ -28,18 +28,20 @@ #include -void +int corec37d_wndw_owner(struct nv50_core *core) { + struct nvif_push *push = core->chan.push; const u32 windows = 8; /*XXX*/ - u32 *push, i; - if ((push = evo_wait(&core->chan, 2 * windows))) { - for (i = 0; i < windows; i++) { - evo_mthd(push, 0x1000 + (i * 0x080), 1); - evo_data(push, i >> 1); - } - evo_kick(push, &core->chan); - } + int ret, i; + + if ((ret = PUSH_WAIT(push, windows * 2))) + return ret; + + for (i = 0; i < windows; i++) + PUSH_NVSQ(push, NVC37D, 0x1000 + (i * 0x080), i >> 1); + + return 0; } int From 9ec5e8204053a46f9e0b6107844641eb4b3426a4 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sat, 20 Jun 2020 17:20:39 +1000 Subject: [PATCH 058/145] drm/nouveau/kms/nv50-: convert core or_ctrl() to new push macros Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/core.h | 2 +- drivers/gpu/drm/nouveau/dispnv50/dac507d.c | 28 +++++++++++++-------- drivers/gpu/drm/nouveau/dispnv50/dac907d.c | 18 +++++++------ drivers/gpu/drm/nouveau/dispnv50/pior507d.c | 27 ++++++++++++-------- drivers/gpu/drm/nouveau/dispnv50/sor507d.c | 27 ++++++++++++-------- drivers/gpu/drm/nouveau/dispnv50/sor907d.c | 20 +++++++++------ drivers/gpu/drm/nouveau/dispnv50/sorc37d.c | 18 +++++++------ 7 files changed, 84 insertions(+), 56 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/core.h b/drivers/gpu/drm/nouveau/dispnv50/core.h index 7e061b8c9719..498622c0c670 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/core.h +++ b/drivers/gpu/drm/nouveau/dispnv50/core.h @@ -31,7 +31,7 @@ struct nv50_core_func { const struct nv50_crc_func *crc; #endif const struct nv50_outp_func { - void (*ctrl)(struct nv50_core *, int or, u32 ctrl, + int (*ctrl)(struct nv50_core *, int or, u32 ctrl, struct nv50_head_atom *); /* XXX: Only used by SORs and PIORs for now */ void (*get_caps)(struct nv50_disp *, diff --git a/drivers/gpu/drm/nouveau/dispnv50/dac507d.c b/drivers/gpu/drm/nouveau/dispnv50/dac507d.c index 2a10ef7d30a8..4f424c65ebf9 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/dac507d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/dac507d.c @@ -21,21 +21,27 @@ */ #include "core.h" -static void +#include + +static int dac507d_ctrl(struct nv50_core *core, int or, u32 ctrl, struct nv50_head_atom *asyh) { - u32 *push, sync = 0; - if ((push = evo_wait(&core->chan, 3))) { - if (asyh) { - sync |= asyh->or.nvsync << 1; - sync |= asyh->or.nhsync; - } - evo_mthd(push, 0x0400 + (or * 0x080), 2); - evo_data(push, ctrl); - evo_data(push, sync); - evo_kick(push, &core->chan); + struct nvif_push *push = core->chan.push; + u32 sync = 0; + int ret; + + if (asyh) { + sync |= asyh->or.nvsync << 1; + sync |= asyh->or.nhsync; } + + if ((ret = PUSH_WAIT(push, 3))) + return ret; + + PUSH_NVSQ(push, NV507D, 0x0400 + (or * 0x080), ctrl, + 0x0404 + (or * 0x080), sync); + return 0; } const struct nv50_outp_func diff --git a/drivers/gpu/drm/nouveau/dispnv50/dac907d.c b/drivers/gpu/drm/nouveau/dispnv50/dac907d.c index 11e87fa53fac..f32e470b9358 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/dac907d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/dac907d.c @@ -21,16 +21,20 @@ */ #include "core.h" -static void +#include + +static int dac907d_ctrl(struct nv50_core *core, int or, u32 ctrl, struct nv50_head_atom *asyh) { - u32 *push; - if ((push = evo_wait(&core->chan, 2))) { - evo_mthd(push, 0x0180 + (or * 0x020), 1); - evo_data(push, ctrl); - evo_kick(push, &core->chan); - } + struct nvif_push *push = core->chan.push; + int ret; + + if ((ret = PUSH_WAIT(push, 2))) + return ret; + + PUSH_NVSQ(push, NV907D, 0x0180 + (or * 0x020), ctrl); + return 0; } const struct nv50_outp_func diff --git a/drivers/gpu/drm/nouveau/dispnv50/pior507d.c b/drivers/gpu/drm/nouveau/dispnv50/pior507d.c index 45d8ce7d2c28..6af30c1617e5 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/pior507d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/pior507d.c @@ -21,21 +21,26 @@ */ #include "core.h" -static void +#include + +static int pior507d_ctrl(struct nv50_core *core, int or, u32 ctrl, struct nv50_head_atom *asyh) { - u32 *push; - if ((push = evo_wait(&core->chan, 2))) { - if (asyh) { - ctrl |= asyh->or.depth << 16; - ctrl |= asyh->or.nvsync << 13; - ctrl |= asyh->or.nhsync << 12; - } - evo_mthd(push, 0x0700 + (or * 0x040), 1); - evo_data(push, ctrl); - evo_kick(push, &core->chan); + struct nvif_push *push = core->chan.push; + int ret; + + if (asyh) { + ctrl |= asyh->or.depth << 16; + ctrl |= asyh->or.nvsync << 13; + ctrl |= asyh->or.nhsync << 12; } + + if ((ret = PUSH_WAIT(push, 2))) + return ret; + + PUSH_NVSQ(push, NV507D, 0x0700 + (or * 0x040), ctrl); + return 0; } static void diff --git a/drivers/gpu/drm/nouveau/dispnv50/sor507d.c b/drivers/gpu/drm/nouveau/dispnv50/sor507d.c index 9a59fa7da00d..ead66163ff4f 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/sor507d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/sor507d.c @@ -21,21 +21,26 @@ */ #include "core.h" -static void +#include + +static int sor507d_ctrl(struct nv50_core *core, int or, u32 ctrl, struct nv50_head_atom *asyh) { - u32 *push; - if ((push = evo_wait(&core->chan, 2))) { - if (asyh) { - ctrl |= asyh->or.depth << 16; - ctrl |= asyh->or.nvsync << 13; - ctrl |= asyh->or.nhsync << 12; - } - evo_mthd(push, 0x0600 + (or * 0x40), 1); - evo_data(push, ctrl); - evo_kick(push, &core->chan); + struct nvif_push *push = core->chan.push; + int ret; + + if (asyh) { + ctrl |= asyh->or.depth << 16; + ctrl |= asyh->or.nvsync << 13; + ctrl |= asyh->or.nhsync << 12; } + + if ((ret = PUSH_WAIT(push, 2))) + return ret; + + PUSH_NVSQ(push, NV507D, 0x0600 + (or * 0x40), ctrl); + return 0; } static void diff --git a/drivers/gpu/drm/nouveau/dispnv50/sor907d.c b/drivers/gpu/drm/nouveau/dispnv50/sor907d.c index 9577ccf1c809..ea5da300cc11 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/sor907d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/sor907d.c @@ -21,19 +21,23 @@ */ #include "core.h" -#include #include +#include -static void +#include + +static int sor907d_ctrl(struct nv50_core *core, int or, u32 ctrl, struct nv50_head_atom *asyh) { - u32 *push; - if ((push = evo_wait(&core->chan, 2))) { - evo_mthd(push, 0x0200 + (or * 0x20), 1); - evo_data(push, ctrl); - evo_kick(push, &core->chan); - } + struct nvif_push *push = core->chan.push; + int ret; + + if ((ret = PUSH_WAIT(push, 2))) + return ret; + + PUSH_NVSQ(push, NV907D, 0x0200 + (or * 0x20), ctrl); + return 0; } static void diff --git a/drivers/gpu/drm/nouveau/dispnv50/sorc37d.c b/drivers/gpu/drm/nouveau/dispnv50/sorc37d.c index c86ca955fdcd..734944864198 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/sorc37d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/sorc37d.c @@ -21,16 +21,20 @@ */ #include "core.h" -static void +#include + +static int sorc37d_ctrl(struct nv50_core *core, int or, u32 ctrl, struct nv50_head_atom *asyh) { - u32 *push; - if ((push = evo_wait(&core->chan, 2))) { - evo_mthd(push, 0x0300 + (or * 0x20), 1); - evo_data(push, ctrl); - evo_kick(push, &core->chan); - } + struct nvif_push *push = core->chan.push; + int ret; + + if ((ret = PUSH_WAIT(push, 2))) + return ret; + + PUSH_NVSQ(push, NVC37D, 0x0300 + (or * 0x20), ctrl); + return 0; } static void From 1f772f5a08b28fd3d6fc385af70133952a202725 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sat, 20 Jun 2020 18:34:00 +1000 Subject: [PATCH 059/145] drm/nouveau/kms/nv50-: convert core head_view() to new push macros Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/head.h | 8 +++--- drivers/gpu/drm/nouveau/dispnv50/head507d.c | 28 ++++++++++--------- drivers/gpu/drm/nouveau/dispnv50/head907d.c | 30 +++++++++++---------- drivers/gpu/drm/nouveau/dispnv50/headc37d.c | 23 +++++++++------- 4 files changed, 48 insertions(+), 41 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/head.h b/drivers/gpu/drm/nouveau/dispnv50/head.h index 30501ad1824e..dfd4d2c758d8 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head.h +++ b/drivers/gpu/drm/nouveau/dispnv50/head.h @@ -25,7 +25,7 @@ void nv50_head_flush_clr(struct nv50_head *head, struct nv50_head_atom *asyh, bool flush); struct nv50_head_func { - void (*view)(struct nv50_head *, struct nv50_head_atom *); + int (*view)(struct nv50_head *, struct nv50_head_atom *); void (*mode)(struct nv50_head *, struct nv50_head_atom *); bool (*olut)(struct nv50_head *, struct nv50_head_atom *, int); bool olut_identity; @@ -50,7 +50,7 @@ struct nv50_head_func { }; extern const struct nv50_head_func head507d; -void head507d_view(struct nv50_head *, struct nv50_head_atom *); +int head507d_view(struct nv50_head *, struct nv50_head_atom *); void head507d_mode(struct nv50_head *, struct nv50_head_atom *); bool head507d_olut(struct nv50_head *, struct nv50_head_atom *, int); void head507d_core_calc(struct nv50_head *, struct nv50_head_atom *); @@ -67,7 +67,7 @@ void head507d_procamp(struct nv50_head *, struct nv50_head_atom *); extern const struct nv50_head_func head827d; extern const struct nv50_head_func head907d; -void head907d_view(struct nv50_head *, struct nv50_head_atom *); +int head907d_view(struct nv50_head *, struct nv50_head_atom *); void head907d_mode(struct nv50_head *, struct nv50_head_atom *); bool head907d_olut(struct nv50_head *, struct nv50_head_atom *, int); void head907d_olut_set(struct nv50_head *, struct nv50_head_atom *); @@ -85,7 +85,7 @@ int head917d_curs_layout(struct nv50_head *, struct nv50_wndw_atom *, struct nv50_head_atom *); extern const struct nv50_head_func headc37d; -void headc37d_view(struct nv50_head *, struct nv50_head_atom *); +int headc37d_view(struct nv50_head *, struct nv50_head_atom *); void headc37d_core_set(struct nv50_head *, struct nv50_head_atom *); void headc37d_core_clr(struct nv50_head *); int headc37d_curs_format(struct nv50_head *, struct nv50_wndw_atom *, diff --git a/drivers/gpu/drm/nouveau/dispnv50/head507d.c b/drivers/gpu/drm/nouveau/dispnv50/head507d.c index 66ccf36b56a2..df0bc706bdbe 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head507d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head507d.c @@ -22,6 +22,8 @@ #include "head.h" #include "core.h" +#include + void head507d_procamp(struct nv50_head *head, struct nv50_head_atom *asyh) { @@ -310,21 +312,21 @@ head507d_mode(struct nv50_head *head, struct nv50_head_atom *asyh) } } -void +int head507d_view(struct nv50_head *head, struct nv50_head_atom *asyh) { - struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; - u32 *push; - if ((push = evo_wait(core, 7))) { - evo_mthd(push, 0x08a4 + (head->base.index * 0x400), 1); - evo_data(push, 0x00000000); - evo_mthd(push, 0x08c8 + (head->base.index * 0x400), 1); - evo_data(push, asyh->view.iH << 16 | asyh->view.iW); - evo_mthd(push, 0x08d8 + (head->base.index * 0x400), 2); - evo_data(push, asyh->view.oH << 16 | asyh->view.oW); - evo_data(push, asyh->view.oH << 16 | asyh->view.oW); - evo_kick(push, core); - } + struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push; + const int i = head->base.index; + int ret; + + if ((ret = PUSH_WAIT(push, 7))) + return ret; + + PUSH_NVSQ(push, NV507D, 0x08a4 + (i * 0x400), 0x00000000); + PUSH_NVSQ(push, NV507D, 0x08c8 + (i * 0x400), asyh->view.iH << 16 | asyh->view.iW); + PUSH_NVSQ(push, NV507D, 0x08d8 + (i * 0x400), asyh->view.oH << 16 | asyh->view.oW, + 0x08dc + (i * 0x400), asyh->view.oH << 16 | asyh->view.oW); + return 0; } const struct nv50_head_func diff --git a/drivers/gpu/drm/nouveau/dispnv50/head907d.c b/drivers/gpu/drm/nouveau/dispnv50/head907d.c index 63a0b45d96d6..6682a677b462 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head907d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head907d.c @@ -29,6 +29,8 @@ #include "core.h" #include "crc.h" +#include + void head907d_or(struct nv50_head *head, struct nv50_head_atom *asyh) { @@ -274,22 +276,22 @@ head907d_mode(struct nv50_head *head, struct nv50_head_atom *asyh) } } -void +int head907d_view(struct nv50_head *head, struct nv50_head_atom *asyh) { - struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; - u32 *push; - if ((push = evo_wait(core, 8))) { - evo_mthd(push, 0x0494 + (head->base.index * 0x300), 1); - evo_data(push, 0x00000000); - evo_mthd(push, 0x04b8 + (head->base.index * 0x300), 1); - evo_data(push, asyh->view.iH << 16 | asyh->view.iW); - evo_mthd(push, 0x04c0 + (head->base.index * 0x300), 3); - evo_data(push, asyh->view.oH << 16 | asyh->view.oW); - evo_data(push, asyh->view.oH << 16 | asyh->view.oW); - evo_data(push, asyh->view.oH << 16 | asyh->view.oW); - evo_kick(push, core); - } + struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push; + const int i = head->base.index; + int ret; + + if ((ret = PUSH_WAIT(push, 8))) + return ret; + + PUSH_NVSQ(push, NV907D, 0x0494 + (i * 0x300), 0x00000000); + PUSH_NVSQ(push, NV907D, 0x04b8 + (i * 0x300), asyh->view.iH << 16 | asyh->view.iW); + PUSH_NVSQ(push, NV907D, 0x04c0 + (i * 0x300), asyh->view.oH << 16 | asyh->view.oW, + 0x04c4 + (i * 0x300), asyh->view.oH << 16 | asyh->view.oW, + 0x04c8 + (i * 0x300), asyh->view.oH << 16 | asyh->view.oW); + return 0; } const struct nv50_head_func diff --git a/drivers/gpu/drm/nouveau/dispnv50/headc37d.c b/drivers/gpu/drm/nouveau/dispnv50/headc37d.c index 35fcdf8825b5..0bdf2d2725bc 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/headc37d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/headc37d.c @@ -23,6 +23,8 @@ #include "atom.h" #include "core.h" +#include + static void headc37d_or(struct nv50_head *head, struct nv50_head_atom *asyh) { @@ -190,18 +192,19 @@ headc37d_mode(struct nv50_head *head, struct nv50_head_atom *asyh) } } -void +int headc37d_view(struct nv50_head *head, struct nv50_head_atom *asyh) { - struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; - u32 *push; - if ((push = evo_wait(core, 4))) { - evo_mthd(push, 0x204c + (head->base.index * 0x400), 1); - evo_data(push, (asyh->view.iH << 16) | asyh->view.iW); - evo_mthd(push, 0x2058 + (head->base.index * 0x400), 1); - evo_data(push, (asyh->view.oH << 16) | asyh->view.oW); - evo_kick(push, core); - } + struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push; + const int i = head->base.index; + int ret; + + if ((ret = PUSH_WAIT(push, 4))) + return ret; + + PUSH_NVSQ(push, NVC37D, 0x204c + (i * 0x400), asyh->view.iH << 16 | asyh->view.iW); + PUSH_NVSQ(push, NVC37D, 0x2058 + (i * 0x400), asyh->view.oH << 16 | asyh->view.oW); + return 0; } void From caa966a7a6e57c61181e38de34d145df76a4f00b Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sun, 21 Jun 2020 08:51:03 +1000 Subject: [PATCH 060/145] drm/nouveau/kms/nv50-: convert core head_mode() to new push macros Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/head.h | 6 +-- drivers/gpu/drm/nouveau/dispnv50/head507d.c | 38 +++++++++---------- drivers/gpu/drm/nouveau/dispnv50/head907d.c | 40 ++++++++++---------- drivers/gpu/drm/nouveau/dispnv50/headc37d.c | 40 ++++++++++---------- drivers/gpu/drm/nouveau/dispnv50/headc57d.c | 42 +++++++++++---------- 5 files changed, 84 insertions(+), 82 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/head.h b/drivers/gpu/drm/nouveau/dispnv50/head.h index dfd4d2c758d8..2d376e368372 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head.h +++ b/drivers/gpu/drm/nouveau/dispnv50/head.h @@ -26,7 +26,7 @@ void nv50_head_flush_clr(struct nv50_head *head, struct nv50_head_func { int (*view)(struct nv50_head *, struct nv50_head_atom *); - void (*mode)(struct nv50_head *, struct nv50_head_atom *); + int (*mode)(struct nv50_head *, struct nv50_head_atom *); bool (*olut)(struct nv50_head *, struct nv50_head_atom *, int); bool olut_identity; int olut_size; @@ -51,7 +51,7 @@ struct nv50_head_func { extern const struct nv50_head_func head507d; int head507d_view(struct nv50_head *, struct nv50_head_atom *); -void head507d_mode(struct nv50_head *, struct nv50_head_atom *); +int head507d_mode(struct nv50_head *, struct nv50_head_atom *); bool head507d_olut(struct nv50_head *, struct nv50_head_atom *, int); void head507d_core_calc(struct nv50_head *, struct nv50_head_atom *); void head507d_core_clr(struct nv50_head *); @@ -68,7 +68,7 @@ extern const struct nv50_head_func head827d; extern const struct nv50_head_func head907d; int head907d_view(struct nv50_head *, struct nv50_head_atom *); -void head907d_mode(struct nv50_head *, struct nv50_head_atom *); +int head907d_mode(struct nv50_head *, struct nv50_head_atom *); bool head907d_olut(struct nv50_head *, struct nv50_head_atom *, int); void head907d_olut_set(struct nv50_head *, struct nv50_head_atom *); void head907d_olut_clr(struct nv50_head *); diff --git a/drivers/gpu/drm/nouveau/dispnv50/head507d.c b/drivers/gpu/drm/nouveau/dispnv50/head507d.c index df0bc706bdbe..516c07501524 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head507d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head507d.c @@ -288,28 +288,28 @@ head507d_olut(struct nv50_head *head, struct nv50_head_atom *asyh, int size) return true; } -void +int head507d_mode(struct nv50_head *head, struct nv50_head_atom *asyh) { - struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; + struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push; struct nv50_head_mode *m = &asyh->mode; - u32 *push; - if ((push = evo_wait(core, 13))) { - evo_mthd(push, 0x0804 + (head->base.index * 0x400), 2); - evo_data(push, 0x00800000 | m->clock); - evo_data(push, m->interlace ? 0x00000002 : 0x00000000); - evo_mthd(push, 0x0810 + (head->base.index * 0x400), 7); - evo_data(push, 0x00000000); - evo_data(push, m->v.active << 16 | m->h.active ); - evo_data(push, m->v.synce << 16 | m->h.synce ); - evo_data(push, m->v.blanke << 16 | m->h.blanke ); - evo_data(push, m->v.blanks << 16 | m->h.blanks ); - evo_data(push, m->v.blank2e << 16 | m->v.blank2s); - evo_data(push, asyh->mode.v.blankus); - evo_mthd(push, 0x082c + (head->base.index * 0x400), 1); - evo_data(push, 0x00000000); - evo_kick(push, core); - } + const int i = head->base.index; + int ret; + + if ((ret = PUSH_WAIT(push, 13))) + return ret; + + PUSH_NVSQ(push, NV507D, 0x0804 + (i * 0x400), 0x00800000 | m->clock, + 0x0808 + (i * 0x400), m->interlace ? 0x00000002 : 0x00000000); + PUSH_NVSQ(push, NV507D, 0x0810 + (i * 0x400), 0x00000000, + 0x0814 + (i * 0x400), m->v.active << 16 | m->h.active, + 0x0818 + (i * 0x400), m->v.synce << 16 | m->h.synce, + 0x081c + (i * 0x400), m->v.blanke << 16 | m->h.blanke, + 0x0820 + (i * 0x400), m->v.blanks << 16 | m->h.blanks, + 0x0824 + (i * 0x400), m->v.blank2e << 16 | m->v.blank2s, + 0x0828 + (i * 0x400), asyh->mode.v.blankus); + PUSH_NVSQ(push, NV507D, 0x082c + (i * 0x400), 0x00000000); + return 0; } int diff --git a/drivers/gpu/drm/nouveau/dispnv50/head907d.c b/drivers/gpu/drm/nouveau/dispnv50/head907d.c index 6682a677b462..2ee1931477bf 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head907d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head907d.c @@ -251,29 +251,29 @@ head907d_olut(struct nv50_head *head, struct nv50_head_atom *asyh, int size) return true; } -void +int head907d_mode(struct nv50_head *head, struct nv50_head_atom *asyh) { - struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; + struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push; struct nv50_head_mode *m = &asyh->mode; - u32 *push; - if ((push = evo_wait(core, 14))) { - evo_mthd(push, 0x0410 + (head->base.index * 0x300), 6); - evo_data(push, 0x00000000); - evo_data(push, m->v.active << 16 | m->h.active ); - evo_data(push, m->v.synce << 16 | m->h.synce ); - evo_data(push, m->v.blanke << 16 | m->h.blanke ); - evo_data(push, m->v.blanks << 16 | m->h.blanks ); - evo_data(push, m->v.blank2e << 16 | m->v.blank2s); - evo_mthd(push, 0x042c + (head->base.index * 0x300), 2); - evo_data(push, 0x00000000); /* ??? */ - evo_data(push, 0xffffff00); - evo_mthd(push, 0x0450 + (head->base.index * 0x300), 3); - evo_data(push, m->clock * 1000); - evo_data(push, 0x00200000); /* ??? */ - evo_data(push, m->clock * 1000); - evo_kick(push, core); - } + const int i = head->base.index; + int ret; + + if ((ret = PUSH_WAIT(push, 14))) + return ret; + + PUSH_NVSQ(push, NV907D, 0x0410 + (i * 0x300), 0x00000000, + 0x0414 + (i * 0x300), m->v.active << 16 | m->h.active, + 0x0418 + (i * 0x300), m->v.synce << 16 | m->h.synce, + 0x041c + (i * 0x300), m->v.blanke << 16 | m->h.blanke, + 0x0420 + (i * 0x300), m->v.blanks << 16 | m->h.blanks, + 0x0424 + (i * 0x300), m->v.blank2e << 16 | m->v.blank2s); + PUSH_NVSQ(push, NV907D, 0x042c + (i * 0x300), 0x00000000, + 0x0430 + (i * 0x300), 0xffffff00); + PUSH_NVSQ(push, NV907D, 0x0450 + (i * 0x300), m->clock * 1000, + 0x0454 + (i * 0x300), 0x00200000, + 0x0458 + (i * 0x300), m->clock * 1000); + return 0; } int diff --git a/drivers/gpu/drm/nouveau/dispnv50/headc37d.c b/drivers/gpu/drm/nouveau/dispnv50/headc37d.c index 0bdf2d2725bc..e15a4d3afa4e 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/headc37d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/headc37d.c @@ -167,29 +167,29 @@ headc37d_olut(struct nv50_head *head, struct nv50_head_atom *asyh, int size) return true; } -static void +static int headc37d_mode(struct nv50_head *head, struct nv50_head_atom *asyh) { - struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; + struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push; struct nv50_head_mode *m = &asyh->mode; - u32 *push; - if ((push = evo_wait(core, 13))) { - evo_mthd(push, 0x2064 + (head->base.index * 0x400), 5); - evo_data(push, (m->v.active << 16) | m->h.active ); - evo_data(push, (m->v.synce << 16) | m->h.synce ); - evo_data(push, (m->v.blanke << 16) | m->h.blanke ); - evo_data(push, (m->v.blanks << 16) | m->h.blanks ); - evo_data(push, (m->v.blank2e << 16) | m->v.blank2s); - evo_mthd(push, 0x2008 + (head->base.index * 0x400), 2); - evo_data(push, m->interlace); - evo_data(push, m->clock * 1000); - evo_mthd(push, 0x2028 + (head->base.index * 0x400), 1); - evo_data(push, m->clock * 1000); - /*XXX: HEAD_USAGE_BOUNDS, doesn't belong here. */ - evo_mthd(push, 0x2030 + (head->base.index * 0x400), 1); - evo_data(push, 0x00000124); - evo_kick(push, core); - } + const int i = head->base.index; + int ret; + + if ((ret = PUSH_WAIT(push, 13))) + return ret; + + PUSH_NVSQ(push, NVC37D, 0x2064 + (i * 0x400), m->v.active << 16 | m->h.active, + 0x2068 + (i * 0x400), m->v.synce << 16 | m->h.synce, + 0x206c + (i * 0x400), m->v.blanke << 16 | m->h.blanke, + 0x2070 + (i * 0x400), m->v.blanks << 16 | m->h.blanks, + 0x2074 + (i * 0x400), m->v.blank2e << 16 | m->v.blank2s); + PUSH_NVSQ(push, NVC37D, 0x2008 + (i * 0x400), m->interlace, + 0x200c + (i * 0x400), m->clock * 1000); + PUSH_NVSQ(push, NVC37D, 0x2028 + (i * 0x400), m->clock * 1000); + + /*XXX: HEAD_USAGE_BOUNDS, doesn't belong here. */ + PUSH_NVSQ(push, NVC37D, 0x2030 + (i * 0x400), 0x00000124); + return 0; } int diff --git a/drivers/gpu/drm/nouveau/dispnv50/headc57d.c b/drivers/gpu/drm/nouveau/dispnv50/headc57d.c index 28d4431bba1b..1024436650c2 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/headc57d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/headc57d.c @@ -23,6 +23,8 @@ #include "atom.h" #include "core.h" +#include + static void headc57d_or(struct nv50_head *head, struct nv50_head_atom *asyh) { @@ -171,29 +173,29 @@ headc57d_olut(struct nv50_head *head, struct nv50_head_atom *asyh, int size) return true; } -static void +static int headc57d_mode(struct nv50_head *head, struct nv50_head_atom *asyh) { - struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; + struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push; struct nv50_head_mode *m = &asyh->mode; - u32 *push; - if ((push = evo_wait(core, 13))) { - evo_mthd(push, 0x2064 + (head->base.index * 0x400), 5); - evo_data(push, (m->v.active << 16) | m->h.active ); - evo_data(push, (m->v.synce << 16) | m->h.synce ); - evo_data(push, (m->v.blanke << 16) | m->h.blanke ); - evo_data(push, (m->v.blanks << 16) | m->h.blanks ); - evo_data(push, (m->v.blank2e << 16) | m->v.blank2s); - evo_mthd(push, 0x2008 + (head->base.index * 0x400), 2); - evo_data(push, m->interlace); - evo_data(push, m->clock * 1000); - evo_mthd(push, 0x2028 + (head->base.index * 0x400), 1); - evo_data(push, m->clock * 1000); - /*XXX: HEAD_USAGE_BOUNDS, doesn't belong here. */ - evo_mthd(push, 0x2030 + (head->base.index * 0x400), 1); - evo_data(push, 0x00001114); - evo_kick(push, core); - } + const int i = head->base.index; + int ret; + + if ((ret = PUSH_WAIT(push, 13))) + return ret; + + PUSH_NVSQ(push, NVC57D, 0x2064 + (i * 0x400), m->v.active << 16 | m->h.active, + 0x2068 + (i * 0x400), m->v.synce << 16 | m->h.synce, + 0x206c + (i * 0x400), m->v.blanke << 16 | m->h.blanke, + 0x2070 + (i * 0x400), m->v.blanks << 16 | m->h.blanks, + 0x2074 + (i * 0x400), m->v.blank2e << 16 | m->v.blank2s); + PUSH_NVSQ(push, NVC57D, 0x2008 + (i * 0x400), m->interlace, + 0x200c + (i * 0x400), m->clock * 1000); + PUSH_NVSQ(push, NVC57D, 0x2028 + (i * 0x400), m->clock * 1000); + + /*XXX: HEAD_USAGE_BOUNDS, doesn't belong here. */ + PUSH_NVSQ(push, NVC57D, 0x2030 + (i * 0x400), 0x00001114); + return 0; } const struct nv50_head_func From a5df76301caedcb60bc5db6909547391277e7950 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sun, 21 Jun 2020 08:58:11 +1000 Subject: [PATCH 061/145] drm/nouveau/kms/nv50-: convert core head_olut_set() to new push macros Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/head.h | 4 +-- drivers/gpu/drm/nouveau/dispnv50/head507d.c | 20 ++++++++------- drivers/gpu/drm/nouveau/dispnv50/head827d.c | 25 ++++++++++-------- drivers/gpu/drm/nouveau/dispnv50/head907d.c | 23 +++++++++-------- drivers/gpu/drm/nouveau/dispnv50/headc37d.c | 26 ++++++++++--------- drivers/gpu/drm/nouveau/dispnv50/headc57d.c | 28 +++++++++++---------- 6 files changed, 68 insertions(+), 58 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/head.h b/drivers/gpu/drm/nouveau/dispnv50/head.h index 2d376e368372..be1dafba16da 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head.h +++ b/drivers/gpu/drm/nouveau/dispnv50/head.h @@ -30,7 +30,7 @@ struct nv50_head_func { bool (*olut)(struct nv50_head *, struct nv50_head_atom *, int); bool olut_identity; int olut_size; - void (*olut_set)(struct nv50_head *, struct nv50_head_atom *); + int (*olut_set)(struct nv50_head *, struct nv50_head_atom *); void (*olut_clr)(struct nv50_head *); void (*core_calc)(struct nv50_head *, struct nv50_head_atom *); void (*core_set)(struct nv50_head *, struct nv50_head_atom *); @@ -70,7 +70,7 @@ extern const struct nv50_head_func head907d; int head907d_view(struct nv50_head *, struct nv50_head_atom *); int head907d_mode(struct nv50_head *, struct nv50_head_atom *); bool head907d_olut(struct nv50_head *, struct nv50_head_atom *, int); -void head907d_olut_set(struct nv50_head *, struct nv50_head_atom *); +int head907d_olut_set(struct nv50_head *, struct nv50_head_atom *); void head907d_olut_clr(struct nv50_head *); void head907d_core_set(struct nv50_head *, struct nv50_head_atom *); void head907d_core_clr(struct nv50_head *); diff --git a/drivers/gpu/drm/nouveau/dispnv50/head507d.c b/drivers/gpu/drm/nouveau/dispnv50/head507d.c index 516c07501524..50ff8bc84222 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head507d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head507d.c @@ -243,17 +243,19 @@ head507d_olut_clr(struct nv50_head *head) } } -static void +static int head507d_olut_set(struct nv50_head *head, struct nv50_head_atom *asyh) { - struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; - u32 *push; - if ((push = evo_wait(core, 3))) { - evo_mthd(push, 0x0840 + (head->base.index * 0x400), 2); - evo_data(push, 0x80000000 | asyh->olut.mode << 30); - evo_data(push, asyh->olut.offset >> 8); - evo_kick(push, core); - } + struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push; + const int i = head->base.index; + int ret; + + if ((ret = PUSH_WAIT(push, 3))) + return ret; + + PUSH_NVSQ(push, NV507D, 0x0840 + (i * 0x400), 0x80000000 | asyh->olut.mode << 30, + 0x0844 + (i * 0x400), asyh->olut.offset >> 8); + return 0; } static void diff --git a/drivers/gpu/drm/nouveau/dispnv50/head827d.c b/drivers/gpu/drm/nouveau/dispnv50/head827d.c index 11877119eea4..30939bc6f734 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head827d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head827d.c @@ -22,6 +22,8 @@ #include "head.h" #include "core.h" +#include + static void head827d_curs_clr(struct nv50_head *head) { @@ -88,19 +90,20 @@ head827d_olut_clr(struct nv50_head *head) } } -static void +static int head827d_olut_set(struct nv50_head *head, struct nv50_head_atom *asyh) { - struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; - u32 *push; - if ((push = evo_wait(core, 5))) { - evo_mthd(push, 0x0840 + (head->base.index * 0x400), 2); - evo_data(push, 0x80000000 | asyh->olut.mode << 30); - evo_data(push, asyh->olut.offset >> 8); - evo_mthd(push, 0x085c + (head->base.index * 0x400), 1); - evo_data(push, asyh->olut.handle); - evo_kick(push, core); - } + struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push; + const int i = head->base.index; + int ret; + + if ((ret = PUSH_WAIT(push, 5))) + return ret; + + PUSH_NVSQ(push, NV827D, 0x0840 + (i * 0x400), 0x80000000 | asyh->olut.mode << 30, + 0x0844 + (i * 0x400), asyh->olut.offset >> 8); + PUSH_NVSQ(push, NV827D, 0x085c + (i * 0x400), asyh->olut.handle); + return 0; } const struct nv50_head_func diff --git a/drivers/gpu/drm/nouveau/dispnv50/head907d.c b/drivers/gpu/drm/nouveau/dispnv50/head907d.c index 2ee1931477bf..24e0d7c7a540 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head907d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head907d.c @@ -208,19 +208,20 @@ head907d_olut_clr(struct nv50_head *head) } } -void +int head907d_olut_set(struct nv50_head *head, struct nv50_head_atom *asyh) { - struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; - u32 *push; - if ((push = evo_wait(core, 5))) { - evo_mthd(push, 0x0448 + (head->base.index * 0x300), 2); - evo_data(push, 0x80000000 | asyh->olut.mode << 24); - evo_data(push, asyh->olut.offset >> 8); - evo_mthd(push, 0x045c + (head->base.index * 0x300), 1); - evo_data(push, asyh->olut.handle); - evo_kick(push, core); - } + struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push; + const int i = head->base.index; + int ret; + + if ((ret = PUSH_WAIT(push, 5))) + return ret; + + PUSH_NVSQ(push, NV907D, 0x0448 + (i * 0x300), 0x80000000 | asyh->olut.mode << 24, + 0x044c + (i * 0x300), asyh->olut.offset >> 8); + PUSH_NVSQ(push, NV907D, 0x045c + (i * 0x300), asyh->olut.handle); + return 0; } void diff --git a/drivers/gpu/drm/nouveau/dispnv50/headc37d.c b/drivers/gpu/drm/nouveau/dispnv50/headc37d.c index e15a4d3afa4e..4363fccdaf73 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/headc37d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/headc37d.c @@ -137,20 +137,22 @@ headc37d_olut_clr(struct nv50_head *head) } } -static void +static int headc37d_olut_set(struct nv50_head *head, struct nv50_head_atom *asyh) { - struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; - u32 *push; - if ((push = evo_wait(core, 4))) { - evo_mthd(push, 0x20a4 + (head->base.index * 0x400), 3); - evo_data(push, asyh->olut.output_mode << 8 | - asyh->olut.range << 4 | - asyh->olut.size); - evo_data(push, asyh->olut.offset >> 8); - evo_data(push, asyh->olut.handle); - evo_kick(push, core); - } + struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push; + const int i = head->base.index; + int ret; + + if ((ret = PUSH_WAIT(push, 4))) + return ret; + + PUSH_NVSQ(push, NVC37D, 0x20a4 + (i * 0x400), asyh->olut.output_mode << 8 | + asyh->olut.range << 4 | + asyh->olut.size, + 0x20a8 + (i * 0x400), asyh->olut.offset >> 8, + 0x20ac + (i * 0x400), asyh->olut.handle); + return 0; } static bool diff --git a/drivers/gpu/drm/nouveau/dispnv50/headc57d.c b/drivers/gpu/drm/nouveau/dispnv50/headc57d.c index 1024436650c2..2f90a249b948 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/headc57d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/headc57d.c @@ -87,21 +87,23 @@ headc57d_olut_clr(struct nv50_head *head) } } -void +static int headc57d_olut_set(struct nv50_head *head, struct nv50_head_atom *asyh) { - struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; - u32 *push; - if ((push = evo_wait(core, 4))) { - evo_mthd(push, 0x2280 + (head->base.index * 0x400), 4); - evo_data(push, asyh->olut.size << 8 | - asyh->olut.mode << 2 | - asyh->olut.output_mode); - evo_data(push, 0xffffffff); /* FP_NORM_SCALE. */ - evo_data(push, asyh->olut.handle); - evo_data(push, asyh->olut.offset >> 8); - evo_kick(push, core); - } + struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push; + const int i = head->base.index; + int ret; + + if ((ret = PUSH_WAIT(push, 5))) + return ret; + + PUSH_NVSQ(push, NVC57D, 0x2280 + (i * 0x400), asyh->olut.size << 8 | + asyh->olut.mode << 2 | + asyh->olut.output_mode, + 0x2284 + (i * 0x400), 0xffffffff, + 0x2288 + (i * 0x400), asyh->olut.handle, + 0x228c + (i * 0x400), asyh->olut.offset >> 8); + return 0; } static void From 4fbf03a32fd8625749059b21a1b3e6501d4912d4 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sun, 21 Jun 2020 09:00:52 +1000 Subject: [PATCH 062/145] drm/nouveau/kms/nv50-: convert core head_olut_clr() to new push macros Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/head.h | 4 ++-- drivers/gpu/drm/nouveau/dispnv50/head507d.c | 18 ++++++++++-------- drivers/gpu/drm/nouveau/dispnv50/head827d.c | 21 +++++++++++---------- drivers/gpu/drm/nouveau/dispnv50/head907d.c | 21 +++++++++++---------- drivers/gpu/drm/nouveau/dispnv50/headc37d.c | 18 ++++++++++-------- drivers/gpu/drm/nouveau/dispnv50/headc57d.c | 18 ++++++++++-------- 6 files changed, 54 insertions(+), 46 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/head.h b/drivers/gpu/drm/nouveau/dispnv50/head.h index be1dafba16da..779f81b42d6c 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head.h +++ b/drivers/gpu/drm/nouveau/dispnv50/head.h @@ -31,7 +31,7 @@ struct nv50_head_func { bool olut_identity; int olut_size; int (*olut_set)(struct nv50_head *, struct nv50_head_atom *); - void (*olut_clr)(struct nv50_head *); + int (*olut_clr)(struct nv50_head *); void (*core_calc)(struct nv50_head *, struct nv50_head_atom *); void (*core_set)(struct nv50_head *, struct nv50_head_atom *); void (*core_clr)(struct nv50_head *); @@ -71,7 +71,7 @@ int head907d_view(struct nv50_head *, struct nv50_head_atom *); int head907d_mode(struct nv50_head *, struct nv50_head_atom *); bool head907d_olut(struct nv50_head *, struct nv50_head_atom *, int); int head907d_olut_set(struct nv50_head *, struct nv50_head_atom *); -void head907d_olut_clr(struct nv50_head *); +int head907d_olut_clr(struct nv50_head *); void head907d_core_set(struct nv50_head *, struct nv50_head_atom *); void head907d_core_clr(struct nv50_head *); void head907d_curs_set(struct nv50_head *, struct nv50_head_atom *); diff --git a/drivers/gpu/drm/nouveau/dispnv50/head507d.c b/drivers/gpu/drm/nouveau/dispnv50/head507d.c index 50ff8bc84222..f653c5cb233c 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head507d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head507d.c @@ -231,16 +231,18 @@ head507d_core_calc(struct nv50_head *head, struct nv50_head_atom *asyh) asyh->core.pitch = ALIGN(asyh->core.w, 64) * 4; } -static void +static int head507d_olut_clr(struct nv50_head *head) { - struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; - u32 *push; - if ((push = evo_wait(core, 2))) { - evo_mthd(push, 0x0840 + (head->base.index * 0x400), 1); - evo_data(push, 0x00000000); - evo_kick(push, core); - } + struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push; + const int i = head->base.index; + int ret; + + if ((ret = PUSH_WAIT(push, 2))) + return ret; + + PUSH_NVSQ(push, NV507D, 0x0840 + (i * 0x400), 0x00000000); + return 0; } static int diff --git a/drivers/gpu/drm/nouveau/dispnv50/head827d.c b/drivers/gpu/drm/nouveau/dispnv50/head827d.c index 30939bc6f734..7cb81d9f3b7f 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head827d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head827d.c @@ -76,18 +76,19 @@ head827d_core_set(struct nv50_head *head, struct nv50_head_atom *asyh) } } -static void +static int head827d_olut_clr(struct nv50_head *head) { - struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; - u32 *push; - if ((push = evo_wait(core, 4))) { - evo_mthd(push, 0x0840 + (head->base.index * 0x400), 1); - evo_data(push, 0x00000000); - evo_mthd(push, 0x085c + (head->base.index * 0x400), 1); - evo_data(push, 0x00000000); - evo_kick(push, core); - } + struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push; + const int i = head->base.index; + int ret; + + if ((ret = PUSH_WAIT(push, 4))) + return ret; + + PUSH_NVSQ(push, NV827D, 0x0840 + (i * 0x400), 0x00000000); + PUSH_NVSQ(push, NV827D, 0x085c + (i * 0x400), 0x00000000); + return 0; } static int diff --git a/drivers/gpu/drm/nouveau/dispnv50/head907d.c b/drivers/gpu/drm/nouveau/dispnv50/head907d.c index 24e0d7c7a540..01be2b93a70a 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head907d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head907d.c @@ -194,18 +194,19 @@ head907d_core_set(struct nv50_head *head, struct nv50_head_atom *asyh) } } -void +int head907d_olut_clr(struct nv50_head *head) { - struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; - u32 *push; - if ((push = evo_wait(core, 4))) { - evo_mthd(push, 0x0448 + (head->base.index * 0x300), 1); - evo_data(push, 0x00000000); - evo_mthd(push, 0x045c + (head->base.index * 0x300), 1); - evo_data(push, 0x00000000); - evo_kick(push, core); - } + struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push; + const int i = head->base.index; + int ret; + + if ((ret = PUSH_WAIT(push, 4))) + return ret; + + PUSH_NVSQ(push, NV907D, 0x0448 + (i * 0x300), 0x00000000); + PUSH_NVSQ(push, NV907D, 0x045c + (i * 0x300), 0x00000000); + return 0; } int diff --git a/drivers/gpu/drm/nouveau/dispnv50/headc37d.c b/drivers/gpu/drm/nouveau/dispnv50/headc37d.c index 4363fccdaf73..d3e72344024b 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/headc37d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/headc37d.c @@ -125,16 +125,18 @@ headc37d_curs_format(struct nv50_head *head, struct nv50_wndw_atom *asyw, return 0; } -static void +static int headc37d_olut_clr(struct nv50_head *head) { - struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; - u32 *push; - if ((push = evo_wait(core, 2))) { - evo_mthd(push, 0x20ac + (head->base.index * 0x400), 1); - evo_data(push, 0x00000000); - evo_kick(push, core); - } + struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push; + const int i = head->base.index; + int ret; + + if ((ret = PUSH_WAIT(push, 2))) + return ret; + + PUSH_NVSQ(push, NVC37D, 0x20ac + (i * 0x400), 0x00000000); + return 0; } static int diff --git a/drivers/gpu/drm/nouveau/dispnv50/headc57d.c b/drivers/gpu/drm/nouveau/dispnv50/headc57d.c index 2f90a249b948..a39f7447c8a8 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/headc57d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/headc57d.c @@ -75,16 +75,18 @@ headc57d_procamp(struct nv50_head *head, struct nv50_head_atom *asyh) } } -void +static int headc57d_olut_clr(struct nv50_head *head) { - struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; - u32 *push; - if ((push = evo_wait(core, 2))) { - evo_mthd(push, 0x2288 + (head->base.index * 0x400), 1); - evo_data(push, 0x00000000); - evo_kick(push, core); - } + struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push; + const int i = head->base.index; + int ret; + + if ((ret = PUSH_WAIT(push, 2))) + return ret; + + PUSH_NVSQ(push, NVC57D, 0x2288 + (i * 0x400), 0x00000000); + return 0; } static int From a38870a21c16a6acf0c7827905be072b0785ae9c Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sun, 21 Jun 2020 09:06:18 +1000 Subject: [PATCH 063/145] drm/nouveau/kms/nv50-: convert core head_core_set() to new push macros Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/head.h | 5 +-- drivers/gpu/drm/nouveau/dispnv50/head507d.c | 50 ++++++++++----------- drivers/gpu/drm/nouveau/dispnv50/head827d.c | 36 +++++++-------- drivers/gpu/drm/nouveau/dispnv50/head907d.c | 36 +++++++-------- 4 files changed, 63 insertions(+), 64 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/head.h b/drivers/gpu/drm/nouveau/dispnv50/head.h index 779f81b42d6c..17c5fc77848a 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head.h +++ b/drivers/gpu/drm/nouveau/dispnv50/head.h @@ -33,7 +33,7 @@ struct nv50_head_func { int (*olut_set)(struct nv50_head *, struct nv50_head_atom *); int (*olut_clr)(struct nv50_head *); void (*core_calc)(struct nv50_head *, struct nv50_head_atom *); - void (*core_set)(struct nv50_head *, struct nv50_head_atom *); + int (*core_set)(struct nv50_head *, struct nv50_head_atom *); void (*core_clr)(struct nv50_head *); int (*curs_layout)(struct nv50_head *, struct nv50_wndw_atom *, struct nv50_head_atom *); @@ -72,7 +72,7 @@ int head907d_mode(struct nv50_head *, struct nv50_head_atom *); bool head907d_olut(struct nv50_head *, struct nv50_head_atom *, int); int head907d_olut_set(struct nv50_head *, struct nv50_head_atom *); int head907d_olut_clr(struct nv50_head *); -void head907d_core_set(struct nv50_head *, struct nv50_head_atom *); +int head907d_core_set(struct nv50_head *, struct nv50_head_atom *); void head907d_core_clr(struct nv50_head *); void head907d_curs_set(struct nv50_head *, struct nv50_head_atom *); void head907d_curs_clr(struct nv50_head *); @@ -86,7 +86,6 @@ int head917d_curs_layout(struct nv50_head *, struct nv50_wndw_atom *, extern const struct nv50_head_func headc37d; int headc37d_view(struct nv50_head *, struct nv50_head_atom *); -void headc37d_core_set(struct nv50_head *, struct nv50_head_atom *); void headc37d_core_clr(struct nv50_head *); int headc37d_curs_format(struct nv50_head *, struct nv50_wndw_atom *, struct nv50_head_atom *); diff --git a/drivers/gpu/drm/nouveau/dispnv50/head507d.c b/drivers/gpu/drm/nouveau/dispnv50/head507d.c index f653c5cb233c..3b280607bfc6 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head507d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head507d.c @@ -169,34 +169,34 @@ head507d_core_clr(struct nv50_head *head) } } -static void +static int head507d_core_set(struct nv50_head *head, struct nv50_head_atom *asyh) { - struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; - u32 *push; - if ((push = evo_wait(core, 9))) { - evo_mthd(push, 0x0860 + head->base.index * 0x400, 1); - evo_data(push, asyh->core.offset >> 8); - evo_mthd(push, 0x0868 + head->base.index * 0x400, 4); - evo_data(push, asyh->core.h << 16 | asyh->core.w); - evo_data(push, asyh->core.layout << 20 | - (asyh->core.pitch >> 8) << 8 | - asyh->core.blocks << 8 | - asyh->core.blockh); - evo_data(push, asyh->core.kind << 16 | - asyh->core.format << 8); - evo_data(push, asyh->core.handle); - evo_mthd(push, 0x08c0 + head->base.index * 0x400, 1); - evo_data(push, asyh->core.y << 16 | asyh->core.x); - evo_kick(push, core); + struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push; + const int i = head->base.index; + int ret; - /* EVO will complain with INVALID_STATE if we have an - * active cursor and (re)specify HeadSetContextDmaIso - * without also updating HeadSetOffsetCursor. - */ - asyh->set.curs = asyh->curs.visible; - asyh->set.olut = asyh->olut.handle != 0; - } + if ((ret = PUSH_WAIT(push, 9))) + return ret; + + PUSH_NVSQ(push, NV507D, 0x0860 + (i * 0x400), asyh->core.offset >> 8); + PUSH_NVSQ(push, NV507D, 0x0868 + (i * 0x400), asyh->core.h << 16 | asyh->core.w, + 0x086c + (i * 0x400), asyh->core.layout << 20 | + (asyh->core.pitch >> 8) << 8 | + asyh->core.blocks << 8 | + asyh->core.blockh, + 0x0870 + (i * 0x400), asyh->core.kind << 16 | + asyh->core.format << 8, + 0x0874 + (i * 0x400), asyh->core.handle); + PUSH_NVSQ(push, NV507D, 0x08c0 + (i * 0x400), asyh->core.y << 16 | asyh->core.x); + + /* EVO will complain with INVALID_STATE if we have an + * active cursor and (re)specify HeadSetContextDmaIso + * without also updating HeadSetOffsetCursor. + */ + asyh->set.curs = asyh->curs.visible; + asyh->set.olut = asyh->olut.handle != 0; + return 0; } void diff --git a/drivers/gpu/drm/nouveau/dispnv50/head827d.c b/drivers/gpu/drm/nouveau/dispnv50/head827d.c index 7cb81d9f3b7f..3361eea6259b 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head827d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head827d.c @@ -54,26 +54,26 @@ head827d_curs_set(struct nv50_head *head, struct nv50_head_atom *asyh) } } -static void +static int head827d_core_set(struct nv50_head *head, struct nv50_head_atom *asyh) { - struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; - u32 *push; - if ((push = evo_wait(core, 9))) { - evo_mthd(push, 0x0860 + head->base.index * 0x400, 1); - evo_data(push, asyh->core.offset >> 8); - evo_mthd(push, 0x0868 + head->base.index * 0x400, 4); - evo_data(push, asyh->core.h << 16 | asyh->core.w); - evo_data(push, asyh->core.layout << 20 | - (asyh->core.pitch >> 8) << 8 | - asyh->core.blocks << 8 | - asyh->core.blockh); - evo_data(push, asyh->core.format << 8); - evo_data(push, asyh->core.handle); - evo_mthd(push, 0x08c0 + head->base.index * 0x400, 1); - evo_data(push, asyh->core.y << 16 | asyh->core.x); - evo_kick(push, core); - } + struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push; + const int i = head->base.index; + int ret; + + if ((ret = PUSH_WAIT(push, 9))) + return ret; + + PUSH_NVSQ(push, NV827D, 0x0860 + (i * 0x400), asyh->core.offset >> 8); + PUSH_NVSQ(push, NV827D, 0x0868 + (i * 0x400), asyh->core.h << 16 | asyh->core.w, + 0x086c + (i * 0x400), asyh->core.layout << 20 | + (asyh->core.pitch >> 8) << 8 | + asyh->core.blocks << 8 | + asyh->core.blockh, + 0x0870 + (i * 0x400), asyh->core.format << 8, + 0x0874 + (i * 0x400), asyh->core.handle); + PUSH_NVSQ(push, NV827D, 0x08c0 + (i * 0x400), asyh->core.y << 16 | asyh->core.x); + return 0; } static int diff --git a/drivers/gpu/drm/nouveau/dispnv50/head907d.c b/drivers/gpu/drm/nouveau/dispnv50/head907d.c index 01be2b93a70a..0957e25f30bd 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head907d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head907d.c @@ -172,26 +172,26 @@ head907d_core_clr(struct nv50_head *head) } } -void +int head907d_core_set(struct nv50_head *head, struct nv50_head_atom *asyh) { - struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; - u32 *push; - if ((push = evo_wait(core, 9))) { - evo_mthd(push, 0x0460 + head->base.index * 0x300, 1); - evo_data(push, asyh->core.offset >> 8); - evo_mthd(push, 0x0468 + head->base.index * 0x300, 4); - evo_data(push, asyh->core.h << 16 | asyh->core.w); - evo_data(push, asyh->core.layout << 24 | - (asyh->core.pitch >> 8) << 8 | - asyh->core.blocks << 8 | - asyh->core.blockh); - evo_data(push, asyh->core.format << 8); - evo_data(push, asyh->core.handle); - evo_mthd(push, 0x04b0 + head->base.index * 0x300, 1); - evo_data(push, asyh->core.y << 16 | asyh->core.x); - evo_kick(push, core); - } + struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push; + const int i = head->base.index; + int ret; + + if ((ret = PUSH_WAIT(push, 9))) + return ret; + + PUSH_NVSQ(push, NV907D, 0x0460 + (i * 0x300), asyh->core.offset >> 8); + PUSH_NVSQ(push, NV907D, 0x0468 + (i * 0x300), asyh->core.h << 16 | asyh->core.w, + 0x046c + (i * 0x300), asyh->core.layout << 24 | + (asyh->core.pitch >> 8) << 8 | + asyh->core.blocks << 8 | + asyh->core.blockh, + 0x0470 + (i * 0x300), asyh->core.format << 8, + 0x0474 + (i * 0x300), asyh->core.handle); + PUSH_NVSQ(push, NV907D, 0x04b0 + (i * 0x300), asyh->core.y << 16 | asyh->core.x); + return 0; } int From aabe253e382444996a20463c6822e8f6a0343b60 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sun, 21 Jun 2020 09:07:28 +1000 Subject: [PATCH 064/145] drm/nouveau/kms/nv50-: convert core head_core_clr() to new push macros Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/head.h | 7 +++---- drivers/gpu/drm/nouveau/dispnv50/head507d.c | 18 ++++++++++-------- drivers/gpu/drm/nouveau/dispnv50/head907d.c | 18 ++++++++++-------- 3 files changed, 23 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/head.h b/drivers/gpu/drm/nouveau/dispnv50/head.h index 17c5fc77848a..e30c9bbd7bfc 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head.h +++ b/drivers/gpu/drm/nouveau/dispnv50/head.h @@ -34,7 +34,7 @@ struct nv50_head_func { int (*olut_clr)(struct nv50_head *); void (*core_calc)(struct nv50_head *, struct nv50_head_atom *); int (*core_set)(struct nv50_head *, struct nv50_head_atom *); - void (*core_clr)(struct nv50_head *); + int (*core_clr)(struct nv50_head *); int (*curs_layout)(struct nv50_head *, struct nv50_wndw_atom *, struct nv50_head_atom *); int (*curs_format)(struct nv50_head *, struct nv50_wndw_atom *, @@ -54,7 +54,7 @@ int head507d_view(struct nv50_head *, struct nv50_head_atom *); int head507d_mode(struct nv50_head *, struct nv50_head_atom *); bool head507d_olut(struct nv50_head *, struct nv50_head_atom *, int); void head507d_core_calc(struct nv50_head *, struct nv50_head_atom *); -void head507d_core_clr(struct nv50_head *); +int head507d_core_clr(struct nv50_head *); int head507d_curs_layout(struct nv50_head *, struct nv50_wndw_atom *, struct nv50_head_atom *); int head507d_curs_format(struct nv50_head *, struct nv50_wndw_atom *, @@ -73,7 +73,7 @@ bool head907d_olut(struct nv50_head *, struct nv50_head_atom *, int); int head907d_olut_set(struct nv50_head *, struct nv50_head_atom *); int head907d_olut_clr(struct nv50_head *); int head907d_core_set(struct nv50_head *, struct nv50_head_atom *); -void head907d_core_clr(struct nv50_head *); +int head907d_core_clr(struct nv50_head *); void head907d_curs_set(struct nv50_head *, struct nv50_head_atom *); void head907d_curs_clr(struct nv50_head *); void head907d_ovly(struct nv50_head *, struct nv50_head_atom *); @@ -86,7 +86,6 @@ int head917d_curs_layout(struct nv50_head *, struct nv50_wndw_atom *, extern const struct nv50_head_func headc37d; int headc37d_view(struct nv50_head *, struct nv50_head_atom *); -void headc37d_core_clr(struct nv50_head *); int headc37d_curs_format(struct nv50_head *, struct nv50_wndw_atom *, struct nv50_head_atom *); void headc37d_curs_set(struct nv50_head *, struct nv50_head_atom *); diff --git a/drivers/gpu/drm/nouveau/dispnv50/head507d.c b/drivers/gpu/drm/nouveau/dispnv50/head507d.c index 3b280607bfc6..f062cd1b19df 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head507d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head507d.c @@ -157,16 +157,18 @@ head507d_curs_layout(struct nv50_head *head, struct nv50_wndw_atom *asyw, return 0; } -void +int head507d_core_clr(struct nv50_head *head) { - struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; - u32 *push; - if ((push = evo_wait(core, 2))) { - evo_mthd(push, 0x0874 + head->base.index * 0x400, 1); - evo_data(push, 0x00000000); - evo_kick(push, core); - } + struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push; + const int i = head->base.index; + int ret; + + if ((ret = PUSH_WAIT(push, 2))) + return ret; + + PUSH_NVSQ(push, NV507D, 0x0874 + (i * 0x400), 0x00000000); + return 0; } static int diff --git a/drivers/gpu/drm/nouveau/dispnv50/head907d.c b/drivers/gpu/drm/nouveau/dispnv50/head907d.c index 0957e25f30bd..2e2b33b84c57 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head907d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head907d.c @@ -160,16 +160,18 @@ head907d_curs_set(struct nv50_head *head, struct nv50_head_atom *asyh) } } -void +int head907d_core_clr(struct nv50_head *head) { - struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; - u32 *push; - if ((push = evo_wait(core, 2))) { - evo_mthd(push, 0x0474 + head->base.index * 0x300, 1); - evo_data(push, 0x00000000); - evo_kick(push, core); - } + struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push; + const int i = head->base.index; + int ret; + + if ((ret = PUSH_WAIT(push, 2))) + return ret; + + PUSH_NVSQ(push, NV907D, 0x0474 + (i * 0x300), 0x00000000); + return 0; } int From 9549c14b32295a483bbd7604c46aa7b7f2bc0a8b Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sun, 21 Jun 2020 09:14:25 +1000 Subject: [PATCH 065/145] drm/nouveau/kms/nv50-: convert core head_curs_set() to new push macros Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/head.h | 6 ++--- drivers/gpu/drm/nouveau/dispnv50/head507d.c | 23 +++++++++------- drivers/gpu/drm/nouveau/dispnv50/head827d.c | 26 +++++++++--------- drivers/gpu/drm/nouveau/dispnv50/head907d.c | 26 +++++++++--------- drivers/gpu/drm/nouveau/dispnv50/headc37d.c | 30 ++++++++++----------- 5 files changed, 59 insertions(+), 52 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/head.h b/drivers/gpu/drm/nouveau/dispnv50/head.h index e30c9bbd7bfc..e49ef06e8f5f 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head.h +++ b/drivers/gpu/drm/nouveau/dispnv50/head.h @@ -39,7 +39,7 @@ struct nv50_head_func { struct nv50_head_atom *); int (*curs_format)(struct nv50_head *, struct nv50_wndw_atom *, struct nv50_head_atom *); - void (*curs_set)(struct nv50_head *, struct nv50_head_atom *); + int (*curs_set)(struct nv50_head *, struct nv50_head_atom *); void (*curs_clr)(struct nv50_head *); void (*base)(struct nv50_head *, struct nv50_head_atom *); void (*ovly)(struct nv50_head *, struct nv50_head_atom *); @@ -74,7 +74,7 @@ int head907d_olut_set(struct nv50_head *, struct nv50_head_atom *); int head907d_olut_clr(struct nv50_head *); int head907d_core_set(struct nv50_head *, struct nv50_head_atom *); int head907d_core_clr(struct nv50_head *); -void head907d_curs_set(struct nv50_head *, struct nv50_head_atom *); +int head907d_curs_set(struct nv50_head *, struct nv50_head_atom *); void head907d_curs_clr(struct nv50_head *); void head907d_ovly(struct nv50_head *, struct nv50_head_atom *); void head907d_procamp(struct nv50_head *, struct nv50_head_atom *); @@ -88,7 +88,7 @@ extern const struct nv50_head_func headc37d; int headc37d_view(struct nv50_head *, struct nv50_head_atom *); int headc37d_curs_format(struct nv50_head *, struct nv50_wndw_atom *, struct nv50_head_atom *); -void headc37d_curs_set(struct nv50_head *, struct nv50_head_atom *); +int headc37d_curs_set(struct nv50_head *, struct nv50_head_atom *); void headc37d_curs_clr(struct nv50_head *); void headc37d_dither(struct nv50_head *, struct nv50_head_atom *); void headc37d_static_wndw_map(struct nv50_head *, struct nv50_head_atom *); diff --git a/drivers/gpu/drm/nouveau/dispnv50/head507d.c b/drivers/gpu/drm/nouveau/dispnv50/head507d.c index f062cd1b19df..2cdbf498c555 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head507d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head507d.c @@ -117,18 +117,21 @@ head507d_curs_clr(struct nv50_head *head) } } -static void +static int head507d_curs_set(struct nv50_head *head, struct nv50_head_atom *asyh) { - struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; - u32 *push; - if ((push = evo_wait(core, 3))) { - evo_mthd(push, 0x0880 + head->base.index * 0x400, 2); - evo_data(push, 0x80000000 | asyh->curs.layout << 26 | - asyh->curs.format << 24); - evo_data(push, asyh->curs.offset >> 8); - evo_kick(push, core); - } + struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push; + const int i = head->base.index; + int ret; + + if ((ret = PUSH_WAIT(push, 3))) + return ret; + + PUSH_NVSQ(push, NV507D, 0x0880 + (i * 0x400), 0x80000000 | + asyh->curs.layout << 26 | + asyh->curs.format << 24, + 0x0884 + (i * 0x400), asyh->curs.offset >> 8); + return 0; } int diff --git a/drivers/gpu/drm/nouveau/dispnv50/head827d.c b/drivers/gpu/drm/nouveau/dispnv50/head827d.c index 3361eea6259b..6b1b683331b9 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head827d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head827d.c @@ -38,20 +38,22 @@ head827d_curs_clr(struct nv50_head *head) } } -static void +static int head827d_curs_set(struct nv50_head *head, struct nv50_head_atom *asyh) { - struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; - u32 *push; - if ((push = evo_wait(core, 5))) { - evo_mthd(push, 0x0880 + head->base.index * 0x400, 2); - evo_data(push, 0x80000000 | asyh->curs.layout << 26 | - asyh->curs.format << 24); - evo_data(push, asyh->curs.offset >> 8); - evo_mthd(push, 0x089c + head->base.index * 0x400, 1); - evo_data(push, asyh->curs.handle); - evo_kick(push, core); - } + struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push; + const int i = head->base.index; + int ret; + + if ((ret = PUSH_WAIT(push, 5))) + return ret; + + PUSH_NVSQ(push, NV827D, 0x0880 + (i * 0x400), 0x80000000 | + asyh->curs.layout << 26 | + asyh->curs.format << 24, + 0x0884 + (i * 0x400), asyh->curs.offset >> 8); + PUSH_NVSQ(push, NV827D, 0x089c + (i * 0x400), asyh->curs.handle); + return 0; } static int diff --git a/drivers/gpu/drm/nouveau/dispnv50/head907d.c b/drivers/gpu/drm/nouveau/dispnv50/head907d.c index 2e2b33b84c57..32dd0de81219 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head907d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head907d.c @@ -144,20 +144,22 @@ head907d_curs_clr(struct nv50_head *head) } } -void +int head907d_curs_set(struct nv50_head *head, struct nv50_head_atom *asyh) { - struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; - u32 *push; - if ((push = evo_wait(core, 5))) { - evo_mthd(push, 0x0480 + head->base.index * 0x300, 2); - evo_data(push, 0x80000000 | asyh->curs.layout << 26 | - asyh->curs.format << 24); - evo_data(push, asyh->curs.offset >> 8); - evo_mthd(push, 0x048c + head->base.index * 0x300, 1); - evo_data(push, asyh->curs.handle); - evo_kick(push, core); - } + struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push; + const int i = head->base.index; + int ret; + + if ((ret = PUSH_WAIT(push, 5))) + return ret; + + PUSH_NVSQ(push, NV907D, 0x0480 + (i * 0x300), 0x80000000 | + asyh->curs.layout << 26 | + asyh->curs.format << 24, + 0x0484 + (i * 0x300), asyh->curs.offset >> 8); + PUSH_NVSQ(push, NV907D, 0x048c + (i * 0x300), asyh->curs.handle); + return 0; } int diff --git a/drivers/gpu/drm/nouveau/dispnv50/headc37d.c b/drivers/gpu/drm/nouveau/dispnv50/headc37d.c index d3e72344024b..89ac5d7e83c0 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/headc37d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/headc37d.c @@ -98,23 +98,23 @@ headc37d_curs_clr(struct nv50_head *head) } } -void +int headc37d_curs_set(struct nv50_head *head, struct nv50_head_atom *asyh) { - struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; - u32 *push; - if ((push = evo_wait(core, 7))) { - evo_mthd(push, 0x209c + head->base.index * 0x400, 2); - evo_data(push, 0x80000000 | - asyh->curs.layout << 8 | - asyh->curs.format << 0); - evo_data(push, 0x000072ff); - evo_mthd(push, 0x2088 + head->base.index * 0x400, 1); - evo_data(push, asyh->curs.handle); - evo_mthd(push, 0x2090 + head->base.index * 0x400, 1); - evo_data(push, asyh->curs.offset >> 8); - evo_kick(push, core); - } + struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push; + const int i = head->base.index; + int ret; + + if ((ret = PUSH_WAIT(push, 7))) + return ret; + + PUSH_NVSQ(push, NVC37D, 0x209c + (i * 0x400), 0x80000000 | + asyh->curs.layout << 8 | + asyh->curs.format << 0, + 0x20a0 + (i * 0x400), 0x000072ff); + PUSH_NVSQ(push, NVC37D, 0x2088 + (i * 0x400), asyh->curs.handle); + PUSH_NVSQ(push, NVC37D, 0x2090 + (i * 0x400), asyh->curs.offset >> 8); + return 0; } int From bc5af56a8f184dd8acdaa7faea245cdf677f4a03 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sun, 21 Jun 2020 09:17:11 +1000 Subject: [PATCH 066/145] drm/nouveau/kms/nv50-: convert core head_curs_clr() to new push macros Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/head.h | 6 +++--- drivers/gpu/drm/nouveau/dispnv50/head507d.c | 18 ++++++++++-------- drivers/gpu/drm/nouveau/dispnv50/head827d.c | 21 +++++++++++---------- drivers/gpu/drm/nouveau/dispnv50/head907d.c | 21 +++++++++++---------- drivers/gpu/drm/nouveau/dispnv50/headc37d.c | 21 +++++++++++---------- 5 files changed, 46 insertions(+), 41 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/head.h b/drivers/gpu/drm/nouveau/dispnv50/head.h index e49ef06e8f5f..6e1067f89938 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head.h +++ b/drivers/gpu/drm/nouveau/dispnv50/head.h @@ -40,7 +40,7 @@ struct nv50_head_func { int (*curs_format)(struct nv50_head *, struct nv50_wndw_atom *, struct nv50_head_atom *); int (*curs_set)(struct nv50_head *, struct nv50_head_atom *); - void (*curs_clr)(struct nv50_head *); + int (*curs_clr)(struct nv50_head *); void (*base)(struct nv50_head *, struct nv50_head_atom *); void (*ovly)(struct nv50_head *, struct nv50_head_atom *); void (*dither)(struct nv50_head *, struct nv50_head_atom *); @@ -75,7 +75,7 @@ int head907d_olut_clr(struct nv50_head *); int head907d_core_set(struct nv50_head *, struct nv50_head_atom *); int head907d_core_clr(struct nv50_head *); int head907d_curs_set(struct nv50_head *, struct nv50_head_atom *); -void head907d_curs_clr(struct nv50_head *); +int head907d_curs_clr(struct nv50_head *); void head907d_ovly(struct nv50_head *, struct nv50_head_atom *); void head907d_procamp(struct nv50_head *, struct nv50_head_atom *); void head907d_or(struct nv50_head *, struct nv50_head_atom *); @@ -89,7 +89,7 @@ int headc37d_view(struct nv50_head *, struct nv50_head_atom *); int headc37d_curs_format(struct nv50_head *, struct nv50_wndw_atom *, struct nv50_head_atom *); int headc37d_curs_set(struct nv50_head *, struct nv50_head_atom *); -void headc37d_curs_clr(struct nv50_head *); +int headc37d_curs_clr(struct nv50_head *); void headc37d_dither(struct nv50_head *, struct nv50_head_atom *); void headc37d_static_wndw_map(struct nv50_head *, struct nv50_head_atom *); diff --git a/drivers/gpu/drm/nouveau/dispnv50/head507d.c b/drivers/gpu/drm/nouveau/dispnv50/head507d.c index 2cdbf498c555..8b9ec5beef8f 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head507d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head507d.c @@ -105,16 +105,18 @@ head507d_base(struct nv50_head *head, struct nv50_head_atom *asyh) } } -static void +static int head507d_curs_clr(struct nv50_head *head) { - struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; - u32 *push; - if ((push = evo_wait(core, 2))) { - evo_mthd(push, 0x0880 + head->base.index * 0x400, 1); - evo_data(push, 0x05000000); - evo_kick(push, core); - } + struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push; + const int i = head->base.index; + int ret; + + if ((ret = PUSH_WAIT(push, 2))) + return ret; + + PUSH_NVSQ(push, NV507D, 0x0880 + (i * 0x400), 0x05000000); + return 0; } static int diff --git a/drivers/gpu/drm/nouveau/dispnv50/head827d.c b/drivers/gpu/drm/nouveau/dispnv50/head827d.c index 6b1b683331b9..66bacb4bb712 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head827d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head827d.c @@ -24,18 +24,19 @@ #include -static void +static int head827d_curs_clr(struct nv50_head *head) { - struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; - u32 *push; - if ((push = evo_wait(core, 4))) { - evo_mthd(push, 0x0880 + head->base.index * 0x400, 1); - evo_data(push, 0x05000000); - evo_mthd(push, 0x089c + head->base.index * 0x400, 1); - evo_data(push, 0x00000000); - evo_kick(push, core); - } + struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push; + const int i = head->base.index; + int ret; + + if ((ret = PUSH_WAIT(push, 4))) + return ret; + + PUSH_NVSQ(push, NV827D, 0x0880 + (i * 0x400), 0x05000000); + PUSH_NVSQ(push, NV827D, 0x089c + (i * 0x400), 0x00000000); + return 0; } static int diff --git a/drivers/gpu/drm/nouveau/dispnv50/head907d.c b/drivers/gpu/drm/nouveau/dispnv50/head907d.c index 32dd0de81219..e3b30142b6f5 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head907d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head907d.c @@ -130,18 +130,19 @@ head907d_base(struct nv50_head *head, struct nv50_head_atom *asyh) } } -void +int head907d_curs_clr(struct nv50_head *head) { - struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; - u32 *push; - if ((push = evo_wait(core, 4))) { - evo_mthd(push, 0x0480 + head->base.index * 0x300, 1); - evo_data(push, 0x05000000); - evo_mthd(push, 0x048c + head->base.index * 0x300, 1); - evo_data(push, 0x00000000); - evo_kick(push, core); - } + struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push; + const int i = head->base.index; + int ret; + + if ((ret = PUSH_WAIT(push, 4))) + return ret; + + PUSH_NVSQ(push, NV907D, 0x0480 + (i * 0x300), 0x05000000); + PUSH_NVSQ(push, NV907D, 0x048c + (i * 0x300), 0x00000000); + return 0; } int diff --git a/drivers/gpu/drm/nouveau/dispnv50/headc37d.c b/drivers/gpu/drm/nouveau/dispnv50/headc37d.c index 89ac5d7e83c0..2ecfcf45f8a8 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/headc37d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/headc37d.c @@ -84,18 +84,19 @@ headc37d_dither(struct nv50_head *head, struct nv50_head_atom *asyh) } } -void +int headc37d_curs_clr(struct nv50_head *head) { - struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; - u32 *push; - if ((push = evo_wait(core, 4))) { - evo_mthd(push, 0x209c + head->base.index * 0x400, 1); - evo_data(push, 0x000000cf); - evo_mthd(push, 0x2088 + head->base.index * 0x400, 1); - evo_data(push, 0x00000000); - evo_kick(push, core); - } + struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push; + const int i = head->base.index; + int ret; + + if ((ret = PUSH_WAIT(push, 4))) + return ret; + + PUSH_NVSQ(push, NVC37D, 0x209c + (i * 0x400), 0x000000cf); + PUSH_NVSQ(push, NVC37D, 0x2088 + (i * 0x400), 0x00000000); + return 0; } int From 93f7f054574271a9254d90e2906a34520d59b722 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sun, 21 Jun 2020 09:19:28 +1000 Subject: [PATCH 067/145] drm/nouveau/kms/nv50-: convert core head_base() to new push macros Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/head.h | 4 ++-- drivers/gpu/drm/nouveau/dispnv50/head507d.c | 17 +++++++++-------- drivers/gpu/drm/nouveau/dispnv50/head907d.c | 17 +++++++++-------- drivers/gpu/drm/nouveau/dispnv50/head917d.c | 19 +++++++++++-------- 4 files changed, 31 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/head.h b/drivers/gpu/drm/nouveau/dispnv50/head.h index 6e1067f89938..d8d6cf798769 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head.h +++ b/drivers/gpu/drm/nouveau/dispnv50/head.h @@ -41,7 +41,7 @@ struct nv50_head_func { struct nv50_head_atom *); int (*curs_set)(struct nv50_head *, struct nv50_head_atom *); int (*curs_clr)(struct nv50_head *); - void (*base)(struct nv50_head *, struct nv50_head_atom *); + int (*base)(struct nv50_head *, struct nv50_head_atom *); void (*ovly)(struct nv50_head *, struct nv50_head_atom *); void (*dither)(struct nv50_head *, struct nv50_head_atom *); void (*procamp)(struct nv50_head *, struct nv50_head_atom *); @@ -59,7 +59,7 @@ int head507d_curs_layout(struct nv50_head *, struct nv50_wndw_atom *, struct nv50_head_atom *); int head507d_curs_format(struct nv50_head *, struct nv50_wndw_atom *, struct nv50_head_atom *); -void head507d_base(struct nv50_head *, struct nv50_head_atom *); +int head507d_base(struct nv50_head *, struct nv50_head_atom *); void head507d_ovly(struct nv50_head *, struct nv50_head_atom *); void head507d_dither(struct nv50_head *, struct nv50_head_atom *); void head507d_procamp(struct nv50_head *, struct nv50_head_atom *); diff --git a/drivers/gpu/drm/nouveau/dispnv50/head507d.c b/drivers/gpu/drm/nouveau/dispnv50/head507d.c index 8b9ec5beef8f..3e56c3da504b 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head507d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head507d.c @@ -78,12 +78,13 @@ head507d_ovly(struct nv50_head *head, struct nv50_head_atom *asyh) } } -void +int head507d_base(struct nv50_head *head, struct nv50_head_atom *asyh) { - struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; + struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push; + const int i = head->base.index; u32 bounds = 0; - u32 *push; + int ret; if (asyh->base.cpp) { switch (asyh->base.cpp) { @@ -98,11 +99,11 @@ head507d_base(struct nv50_head *head, struct nv50_head_atom *asyh) bounds |= 0x00000001; } - if ((push = evo_wait(core, 2))) { - evo_mthd(push, 0x0900 + head->base.index * 0x400, 1); - evo_data(push, bounds); - evo_kick(push, core); - } + if ((ret = PUSH_WAIT(push, 2))) + return ret; + + PUSH_NVSQ(push, NV507D, 0x0900 + (i * 0x400), bounds); + return 0; } static int diff --git a/drivers/gpu/drm/nouveau/dispnv50/head907d.c b/drivers/gpu/drm/nouveau/dispnv50/head907d.c index e3b30142b6f5..a7202794d9c4 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head907d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head907d.c @@ -103,12 +103,13 @@ head907d_ovly(struct nv50_head *head, struct nv50_head_atom *asyh) } } -static void +static int head907d_base(struct nv50_head *head, struct nv50_head_atom *asyh) { - struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; + struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push; + const int i = head->base.index; u32 bounds = 0; - u32 *push; + int ret; if (asyh->base.cpp) { switch (asyh->base.cpp) { @@ -123,11 +124,11 @@ head907d_base(struct nv50_head *head, struct nv50_head_atom *asyh) bounds |= 0x00000001; } - if ((push = evo_wait(core, 2))) { - evo_mthd(push, 0x04d0 + head->base.index * 0x300, 1); - evo_data(push, bounds); - evo_kick(push, core); - } + if ((ret = PUSH_WAIT(push, 2))) + return ret; + + PUSH_NVSQ(push, NV907D, 0x04d0 + (i * 0x300), bounds); + return 0; } int diff --git a/drivers/gpu/drm/nouveau/dispnv50/head917d.c b/drivers/gpu/drm/nouveau/dispnv50/head917d.c index 76958cedd51f..ec7511f47c71 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head917d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head917d.c @@ -22,6 +22,8 @@ #include "head.h" #include "core.h" +#include + static void head917d_dither(struct nv50_head *head, struct nv50_head_atom *asyh) { @@ -36,12 +38,13 @@ head917d_dither(struct nv50_head *head, struct nv50_head_atom *asyh) } } -static void +static int head917d_base(struct nv50_head *head, struct nv50_head_atom *asyh) { - struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; + struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push; + const int i = head->base.index; u32 bounds = 0; - u32 *push; + int ret; if (asyh->base.cpp) { switch (asyh->base.cpp) { @@ -56,11 +59,11 @@ head917d_base(struct nv50_head *head, struct nv50_head_atom *asyh) bounds |= 0x00020001; } - if ((push = evo_wait(core, 2))) { - evo_mthd(push, 0x04d0 + head->base.index * 0x300, 1); - evo_data(push, bounds); - evo_kick(push, core); - } + if ((ret = PUSH_WAIT(push, 2))) + return ret; + + PUSH_NVSQ(push, NV917D, 0x04d0 + (i * 0x300), bounds); + return 0; } int From db2a20693ef9e3cd1d7a2b6c5695f572b29b1251 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sun, 21 Jun 2020 09:20:29 +1000 Subject: [PATCH 068/145] drm/nouveau/kms/nv50-: convert core head_ovly() to new push macros Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/head.h | 6 +++--- drivers/gpu/drm/nouveau/dispnv50/head507d.c | 17 +++++++++-------- drivers/gpu/drm/nouveau/dispnv50/head907d.c | 17 +++++++++-------- 3 files changed, 21 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/head.h b/drivers/gpu/drm/nouveau/dispnv50/head.h index d8d6cf798769..b5b08b4a6cf7 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head.h +++ b/drivers/gpu/drm/nouveau/dispnv50/head.h @@ -42,7 +42,7 @@ struct nv50_head_func { int (*curs_set)(struct nv50_head *, struct nv50_head_atom *); int (*curs_clr)(struct nv50_head *); int (*base)(struct nv50_head *, struct nv50_head_atom *); - void (*ovly)(struct nv50_head *, struct nv50_head_atom *); + int (*ovly)(struct nv50_head *, struct nv50_head_atom *); void (*dither)(struct nv50_head *, struct nv50_head_atom *); void (*procamp)(struct nv50_head *, struct nv50_head_atom *); void (*or)(struct nv50_head *, struct nv50_head_atom *); @@ -60,7 +60,7 @@ int head507d_curs_layout(struct nv50_head *, struct nv50_wndw_atom *, int head507d_curs_format(struct nv50_head *, struct nv50_wndw_atom *, struct nv50_head_atom *); int head507d_base(struct nv50_head *, struct nv50_head_atom *); -void head507d_ovly(struct nv50_head *, struct nv50_head_atom *); +int head507d_ovly(struct nv50_head *, struct nv50_head_atom *); void head507d_dither(struct nv50_head *, struct nv50_head_atom *); void head507d_procamp(struct nv50_head *, struct nv50_head_atom *); @@ -76,7 +76,7 @@ int head907d_core_set(struct nv50_head *, struct nv50_head_atom *); int head907d_core_clr(struct nv50_head *); int head907d_curs_set(struct nv50_head *, struct nv50_head_atom *); int head907d_curs_clr(struct nv50_head *); -void head907d_ovly(struct nv50_head *, struct nv50_head_atom *); +int head907d_ovly(struct nv50_head *, struct nv50_head_atom *); void head907d_procamp(struct nv50_head *, struct nv50_head_atom *); void head907d_or(struct nv50_head *, struct nv50_head_atom *); diff --git a/drivers/gpu/drm/nouveau/dispnv50/head507d.c b/drivers/gpu/drm/nouveau/dispnv50/head507d.c index 3e56c3da504b..16598e100795 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head507d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head507d.c @@ -51,12 +51,13 @@ head507d_dither(struct nv50_head *head, struct nv50_head_atom *asyh) } } -void +int head507d_ovly(struct nv50_head *head, struct nv50_head_atom *asyh) { - struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; + struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push; + const int i = head->base.index; u32 bounds = 0; - u32 *push; + int ret; if (asyh->ovly.cpp) { switch (asyh->ovly.cpp) { @@ -71,11 +72,11 @@ head507d_ovly(struct nv50_head *head, struct nv50_head_atom *asyh) bounds |= 0x00000100; } - if ((push = evo_wait(core, 2))) { - evo_mthd(push, 0x0904 + head->base.index * 0x400, 1); - evo_data(push, bounds); - evo_kick(push, core); - } + if ((ret = PUSH_WAIT(push, 2))) + return ret; + + PUSH_NVSQ(push, NV507D, 0x0904 + (i * 0x400), bounds); + return 0; } int diff --git a/drivers/gpu/drm/nouveau/dispnv50/head907d.c b/drivers/gpu/drm/nouveau/dispnv50/head907d.c index a7202794d9c4..fe5f1a9d59b3 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head907d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head907d.c @@ -75,12 +75,13 @@ head907d_dither(struct nv50_head *head, struct nv50_head_atom *asyh) } } -void +int head907d_ovly(struct nv50_head *head, struct nv50_head_atom *asyh) { - struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; + struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push; + const int i = head->base.index; u32 bounds = 0; - u32 *push; + int ret; if (asyh->ovly.cpp) { switch (asyh->ovly.cpp) { @@ -96,11 +97,11 @@ head907d_ovly(struct nv50_head *head, struct nv50_head_atom *asyh) bounds |= 0x00000100; } - if ((push = evo_wait(core, 2))) { - evo_mthd(push, 0x04d4 + head->base.index * 0x300, 1); - evo_data(push, bounds); - evo_kick(push, core); - } + if ((ret = PUSH_WAIT(push, 2))) + return ret; + + PUSH_NVSQ(push, NV907D, 0x04d4 + (i * 0x300), bounds); + return 0; } static int From 2f819f2be061c984005020f8dc45aee1e6af19a4 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sun, 21 Jun 2020 09:22:47 +1000 Subject: [PATCH 069/145] drm/nouveau/kms/nv50-: convert core head_dither() to new push macros Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/head.h | 6 +++--- drivers/gpu/drm/nouveau/dispnv50/head507d.c | 22 +++++++++++---------- drivers/gpu/drm/nouveau/dispnv50/head907d.c | 22 +++++++++++---------- drivers/gpu/drm/nouveau/dispnv50/head917d.c | 22 +++++++++++---------- drivers/gpu/drm/nouveau/dispnv50/headc37d.c | 22 +++++++++++---------- 5 files changed, 51 insertions(+), 43 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/head.h b/drivers/gpu/drm/nouveau/dispnv50/head.h index b5b08b4a6cf7..5cc65ca2c14b 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head.h +++ b/drivers/gpu/drm/nouveau/dispnv50/head.h @@ -43,7 +43,7 @@ struct nv50_head_func { int (*curs_clr)(struct nv50_head *); int (*base)(struct nv50_head *, struct nv50_head_atom *); int (*ovly)(struct nv50_head *, struct nv50_head_atom *); - void (*dither)(struct nv50_head *, struct nv50_head_atom *); + int (*dither)(struct nv50_head *, struct nv50_head_atom *); void (*procamp)(struct nv50_head *, struct nv50_head_atom *); void (*or)(struct nv50_head *, struct nv50_head_atom *); void (*static_wndw_map)(struct nv50_head *, struct nv50_head_atom *); @@ -61,7 +61,7 @@ int head507d_curs_format(struct nv50_head *, struct nv50_wndw_atom *, struct nv50_head_atom *); int head507d_base(struct nv50_head *, struct nv50_head_atom *); int head507d_ovly(struct nv50_head *, struct nv50_head_atom *); -void head507d_dither(struct nv50_head *, struct nv50_head_atom *); +int head507d_dither(struct nv50_head *, struct nv50_head_atom *); void head507d_procamp(struct nv50_head *, struct nv50_head_atom *); extern const struct nv50_head_func head827d; @@ -90,7 +90,7 @@ int headc37d_curs_format(struct nv50_head *, struct nv50_wndw_atom *, struct nv50_head_atom *); int headc37d_curs_set(struct nv50_head *, struct nv50_head_atom *); int headc37d_curs_clr(struct nv50_head *); -void headc37d_dither(struct nv50_head *, struct nv50_head_atom *); +int headc37d_dither(struct nv50_head *, struct nv50_head_atom *); void headc37d_static_wndw_map(struct nv50_head *, struct nv50_head_atom *); extern const struct nv50_head_func headc57d; diff --git a/drivers/gpu/drm/nouveau/dispnv50/head507d.c b/drivers/gpu/drm/nouveau/dispnv50/head507d.c index 16598e100795..34300607fc53 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head507d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head507d.c @@ -37,18 +37,20 @@ head507d_procamp(struct nv50_head *head, struct nv50_head_atom *asyh) } } -void +int head507d_dither(struct nv50_head *head, struct nv50_head_atom *asyh) { - struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; - u32 *push; - if ((push = evo_wait(core, 2))) { - evo_mthd(push, 0x08a0 + (head->base.index * 0x0400), 1); - evo_data(push, asyh->dither.mode << 3 | - asyh->dither.bits << 1 | - asyh->dither.enable); - evo_kick(push, core); - } + struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push; + const int i = head->base.index; + int ret; + + if ((ret = PUSH_WAIT(push, 2))) + return ret; + + PUSH_NVSQ(push, NV507D, 0x08a0 + (i * 0x400), asyh->dither.mode << 3 | + asyh->dither.bits << 1 | + asyh->dither.enable); + return 0; } int diff --git a/drivers/gpu/drm/nouveau/dispnv50/head907d.c b/drivers/gpu/drm/nouveau/dispnv50/head907d.c index fe5f1a9d59b3..b7fda2284e17 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head907d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head907d.c @@ -61,18 +61,20 @@ head907d_procamp(struct nv50_head *head, struct nv50_head_atom *asyh) } } -static void +static int head907d_dither(struct nv50_head *head, struct nv50_head_atom *asyh) { - struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; - u32 *push; - if ((push = evo_wait(core, 2))) { - evo_mthd(push, 0x0490 + (head->base.index * 0x0300), 1); - evo_data(push, asyh->dither.mode << 3 | - asyh->dither.bits << 1 | - asyh->dither.enable); - evo_kick(push, core); - } + struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push; + const int i = head->base.index; + int ret; + + if ((ret = PUSH_WAIT(push, 2))) + return ret; + + PUSH_NVSQ(push, NV907D, 0x0490 + (i * 0x300), asyh->dither.mode << 3 | + asyh->dither.bits << 1 | + asyh->dither.enable); + return 0; } int diff --git a/drivers/gpu/drm/nouveau/dispnv50/head917d.c b/drivers/gpu/drm/nouveau/dispnv50/head917d.c index ec7511f47c71..07d12f3ba333 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head917d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head917d.c @@ -24,18 +24,20 @@ #include -static void +static int head917d_dither(struct nv50_head *head, struct nv50_head_atom *asyh) { - struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; - u32 *push; - if ((push = evo_wait(core, 2))) { - evo_mthd(push, 0x04a0 + (head->base.index * 0x0300), 1); - evo_data(push, asyh->dither.mode << 3 | - asyh->dither.bits << 1 | - asyh->dither.enable); - evo_kick(push, core); - } + struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push; + const int i = head->base.index; + int ret; + + if ((ret = PUSH_WAIT(push, 2))) + return ret; + + PUSH_NVSQ(push, NV917D, 0x04a0 + (i * 0x300), asyh->dither.mode << 3 | + asyh->dither.bits << 1 | + asyh->dither.enable); + return 0; } static int diff --git a/drivers/gpu/drm/nouveau/dispnv50/headc37d.c b/drivers/gpu/drm/nouveau/dispnv50/headc37d.c index 2ecfcf45f8a8..0accc19991a4 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/headc37d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/headc37d.c @@ -70,18 +70,20 @@ headc37d_procamp(struct nv50_head *head, struct nv50_head_atom *asyh) } } -void +int headc37d_dither(struct nv50_head *head, struct nv50_head_atom *asyh) { - struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; - u32 *push; - if ((push = evo_wait(core, 2))) { - evo_mthd(push, 0x2018 + (head->base.index * 0x0400), 1); - evo_data(push, asyh->dither.mode << 8 | - asyh->dither.bits << 4 | - asyh->dither.enable); - evo_kick(push, core); - } + struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push; + const int i = head->base.index; + int ret; + + if ((ret = PUSH_WAIT(push, 2))) + return ret; + + PUSH_NVSQ(push, NV907D, 0x2018 + (i * 0x400), asyh->dither.mode << 8 | + asyh->dither.bits << 4 | + asyh->dither.enable); + return 0; } int From 246db5fd38b934fb6aefc31172e3afc3e613d20d Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sun, 21 Jun 2020 09:25:19 +1000 Subject: [PATCH 070/145] drm/nouveau/kms/nv50-: convert core head_procamp() to new push macros Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/head.h | 6 ++--- drivers/gpu/drm/nouveau/dispnv50/head507d.c | 20 +++++++++-------- drivers/gpu/drm/nouveau/dispnv50/head907d.c | 20 +++++++++-------- drivers/gpu/drm/nouveau/dispnv50/headc37d.c | 22 +++++++++--------- drivers/gpu/drm/nouveau/dispnv50/headc57d.c | 25 +++++++++------------ 5 files changed, 48 insertions(+), 45 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/head.h b/drivers/gpu/drm/nouveau/dispnv50/head.h index 5cc65ca2c14b..5fca0b725fe4 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head.h +++ b/drivers/gpu/drm/nouveau/dispnv50/head.h @@ -44,7 +44,7 @@ struct nv50_head_func { int (*base)(struct nv50_head *, struct nv50_head_atom *); int (*ovly)(struct nv50_head *, struct nv50_head_atom *); int (*dither)(struct nv50_head *, struct nv50_head_atom *); - void (*procamp)(struct nv50_head *, struct nv50_head_atom *); + int (*procamp)(struct nv50_head *, struct nv50_head_atom *); void (*or)(struct nv50_head *, struct nv50_head_atom *); void (*static_wndw_map)(struct nv50_head *, struct nv50_head_atom *); }; @@ -62,7 +62,7 @@ int head507d_curs_format(struct nv50_head *, struct nv50_wndw_atom *, int head507d_base(struct nv50_head *, struct nv50_head_atom *); int head507d_ovly(struct nv50_head *, struct nv50_head_atom *); int head507d_dither(struct nv50_head *, struct nv50_head_atom *); -void head507d_procamp(struct nv50_head *, struct nv50_head_atom *); +int head507d_procamp(struct nv50_head *, struct nv50_head_atom *); extern const struct nv50_head_func head827d; @@ -77,7 +77,7 @@ int head907d_core_clr(struct nv50_head *); int head907d_curs_set(struct nv50_head *, struct nv50_head_atom *); int head907d_curs_clr(struct nv50_head *); int head907d_ovly(struct nv50_head *, struct nv50_head_atom *); -void head907d_procamp(struct nv50_head *, struct nv50_head_atom *); +int head907d_procamp(struct nv50_head *, struct nv50_head_atom *); void head907d_or(struct nv50_head *, struct nv50_head_atom *); extern const struct nv50_head_func head917d; diff --git a/drivers/gpu/drm/nouveau/dispnv50/head507d.c b/drivers/gpu/drm/nouveau/dispnv50/head507d.c index 34300607fc53..2e72ee410fa7 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head507d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head507d.c @@ -24,17 +24,19 @@ #include -void +int head507d_procamp(struct nv50_head *head, struct nv50_head_atom *asyh) { - struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; - u32 *push; - if ((push = evo_wait(core, 2))) { - evo_mthd(push, 0x08a8 + (head->base.index * 0x400), 1); - evo_data(push, asyh->procamp.sat.sin << 20 | - asyh->procamp.sat.cos << 8); - evo_kick(push, core); - } + struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push; + const int i = head->base.index; + int ret; + + if ((ret = PUSH_WAIT(push, 2))) + return ret; + + PUSH_NVSQ(push, NV507D, 0x08a8 + (i * 0x400), asyh->procamp.sat.sin << 20 | + asyh->procamp.sat.cos << 8); + return 0; } int diff --git a/drivers/gpu/drm/nouveau/dispnv50/head907d.c b/drivers/gpu/drm/nouveau/dispnv50/head907d.c index b7fda2284e17..b6b406d60b81 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head907d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head907d.c @@ -48,17 +48,19 @@ head907d_or(struct nv50_head *head, struct nv50_head_atom *asyh) } } -void +int head907d_procamp(struct nv50_head *head, struct nv50_head_atom *asyh) { - struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; - u32 *push; - if ((push = evo_wait(core, 2))) { - evo_mthd(push, 0x0498 + (head->base.index * 0x300), 1); - evo_data(push, asyh->procamp.sat.sin << 20 | - asyh->procamp.sat.cos << 8); - evo_kick(push, core); - } + struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push; + const int i = head->base.index; + int ret; + + if ((ret = PUSH_WAIT(push, 2))) + return ret; + + PUSH_NVSQ(push, NV907D, 0x0498 + (i * 0x300), asyh->procamp.sat.sin << 20 | + asyh->procamp.sat.cos << 8); + return 0; } static int diff --git a/drivers/gpu/drm/nouveau/dispnv50/headc37d.c b/drivers/gpu/drm/nouveau/dispnv50/headc37d.c index 0accc19991a4..20d3ce45c00f 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/headc37d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/headc37d.c @@ -56,18 +56,20 @@ headc37d_or(struct nv50_head *head, struct nv50_head_atom *asyh) } } -static void +static int headc37d_procamp(struct nv50_head *head, struct nv50_head_atom *asyh) { - struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; - u32 *push; - if ((push = evo_wait(core, 2))) { - evo_mthd(push, 0x2000 + (head->base.index * 0x400), 1); - evo_data(push, 0x80000000 | - asyh->procamp.sat.sin << 16 | - asyh->procamp.sat.cos << 4); - evo_kick(push, core); - } + struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push; + const int i = head->base.index; + int ret; + + if ((ret = PUSH_WAIT(push, 2))) + return ret; + + PUSH_NVSQ(push, NVC37D, 0x2000 + (i * 0x400), 0x80000000 | + asyh->procamp.sat.sin << 16 | + asyh->procamp.sat.cos << 4); + return 0; } int diff --git a/drivers/gpu/drm/nouveau/dispnv50/headc57d.c b/drivers/gpu/drm/nouveau/dispnv50/headc57d.c index a39f7447c8a8..751ffefd3055 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/headc57d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/headc57d.c @@ -57,22 +57,19 @@ headc57d_or(struct nv50_head *head, struct nv50_head_atom *asyh) } } -static void +static int headc57d_procamp(struct nv50_head *head, struct nv50_head_atom *asyh) { - struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; - u32 *push; - if ((push = evo_wait(core, 2))) { - evo_mthd(push, 0x2000 + (head->base.index * 0x400), 1); -#if 0 - evo_data(push, 0x80000000 | - asyh->procamp.sat.sin << 16 | - asyh->procamp.sat.cos << 4); -#else - evo_data(push, 0); -#endif - evo_kick(push, core); - } + struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push; + const int i = head->base.index; + int ret; + + if ((ret = PUSH_WAIT(push, 2))) + return ret; + + //TODO: + PUSH_NVSQ(push, NVC57D, 0x2000 + (i * 0x400), 0x00000000); + return 0; } static int From ff37116ea421ed62e99e310b793214f95f1f8eb0 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sun, 21 Jun 2020 09:28:36 +1000 Subject: [PATCH 071/145] drm/nouveau/kms/nv50-: convert core head_or() to new push macros Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/head.h | 4 +- drivers/gpu/drm/nouveau/dispnv50/head907d.c | 29 ++++++------ drivers/gpu/drm/nouveau/dispnv50/headc37d.c | 49 ++++++++++---------- drivers/gpu/drm/nouveau/dispnv50/headc57d.c | 51 +++++++++++---------- 4 files changed, 69 insertions(+), 64 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/head.h b/drivers/gpu/drm/nouveau/dispnv50/head.h index 5fca0b725fe4..dae841dc05fd 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head.h +++ b/drivers/gpu/drm/nouveau/dispnv50/head.h @@ -45,7 +45,7 @@ struct nv50_head_func { int (*ovly)(struct nv50_head *, struct nv50_head_atom *); int (*dither)(struct nv50_head *, struct nv50_head_atom *); int (*procamp)(struct nv50_head *, struct nv50_head_atom *); - void (*or)(struct nv50_head *, struct nv50_head_atom *); + int (*or)(struct nv50_head *, struct nv50_head_atom *); void (*static_wndw_map)(struct nv50_head *, struct nv50_head_atom *); }; @@ -78,7 +78,7 @@ int head907d_curs_set(struct nv50_head *, struct nv50_head_atom *); int head907d_curs_clr(struct nv50_head *); int head907d_ovly(struct nv50_head *, struct nv50_head_atom *); int head907d_procamp(struct nv50_head *, struct nv50_head_atom *); -void head907d_or(struct nv50_head *, struct nv50_head_atom *); +int head907d_or(struct nv50_head *, struct nv50_head_atom *); extern const struct nv50_head_func head917d; int head917d_curs_layout(struct nv50_head *, struct nv50_wndw_atom *, diff --git a/drivers/gpu/drm/nouveau/dispnv50/head907d.c b/drivers/gpu/drm/nouveau/dispnv50/head907d.c index b6b406d60b81..3be63f09dfa6 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head907d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head907d.c @@ -31,21 +31,24 @@ #include -void +int head907d_or(struct nv50_head *head, struct nv50_head_atom *asyh) { - struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; - u32 *push; - if ((push = evo_wait(core, 3))) { - evo_mthd(push, 0x0404 + (head->base.index * 0x300), 2); - evo_data(push, asyh->or.depth << 6 | - asyh->or.nvsync << 4 | - asyh->or.nhsync << 3 | - asyh->or.crc_raster); - evo_data(push, 0x31ec6000 | head->base.index << 25 | - asyh->mode.interlace); - evo_kick(push, core); - } + struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push; + const int i = head->base.index; + int ret; + + if ((ret = PUSH_WAIT(push, 3))) + return ret; + + PUSH_NVSQ(push, NV907D, 0x0404 + (i * 0x300), asyh->or.depth << 6 | + asyh->or.nvsync << 4 | + asyh->or.nhsync << 3 | + asyh->or.crc_raster, + 0x0408 + (i * 0x300), 0x31ec6000 | + head->base.index << 25 | + asyh->mode.interlace); + return 0; } int diff --git a/drivers/gpu/drm/nouveau/dispnv50/headc37d.c b/drivers/gpu/drm/nouveau/dispnv50/headc37d.c index 20d3ce45c00f..bd63245caf6b 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/headc37d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/headc37d.c @@ -25,35 +25,36 @@ #include -static void +static int headc37d_or(struct nv50_head *head, struct nv50_head_atom *asyh) { - struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; + struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push; + const int i = head->base.index; u8 depth; - u32 *push; + int ret; - if ((push = evo_wait(core, 2))) { - /*XXX: This is a dirty hack until OR depth handling is - * improved later for deep colour etc. - */ - switch (asyh->or.depth) { - case 6: depth = 5; break; - case 5: depth = 4; break; - case 2: depth = 1; break; - case 0: depth = 4; break; - default: - depth = asyh->or.depth; - WARN_ON(1); - break; - } - - evo_mthd(push, 0x2004 + (head->base.index * 0x400), 1); - evo_data(push, depth << 4 | - asyh->or.nvsync << 3 | - asyh->or.nhsync << 2 | - asyh->or.crc_raster); - evo_kick(push, core); + /*XXX: This is a dirty hack until OR depth handling is + * improved later for deep colour etc. + */ + switch (asyh->or.depth) { + case 6: depth = 5; break; + case 5: depth = 4; break; + case 2: depth = 1; break; + case 0: depth = 4; break; + default: + depth = asyh->or.depth; + WARN_ON(1); + break; } + + if ((ret = PUSH_WAIT(push, 2))) + return ret; + + PUSH_NVSQ(push, NVC37D, 0x2004 + (i * 0x400), depth << 4 | + asyh->or.nvsync << 3 | + asyh->or.nhsync << 2 | + asyh->or.crc_raster); + return 0; } static int diff --git a/drivers/gpu/drm/nouveau/dispnv50/headc57d.c b/drivers/gpu/drm/nouveau/dispnv50/headc57d.c index 751ffefd3055..e38087bf7171 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/headc57d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/headc57d.c @@ -25,36 +25,37 @@ #include -static void +static int headc57d_or(struct nv50_head *head, struct nv50_head_atom *asyh) { - struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; + struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push; + const int i = head->base.index; u8 depth; - u32 *push; + int ret; - if ((push = evo_wait(core, 2))) { - /*XXX: This is a dirty hack until OR depth handling is - * improved later for deep colour etc. - */ - switch (asyh->or.depth) { - case 6: depth = 5; break; - case 5: depth = 4; break; - case 2: depth = 1; break; - case 0: depth = 4; break; - default: - depth = asyh->or.depth; - WARN_ON(1); - break; - } - - evo_mthd(push, 0x2004 + (head->base.index * 0x400), 1); - evo_data(push, 0xfc000000 | - depth << 4 | - asyh->or.nvsync << 3 | - asyh->or.nhsync << 2 | - asyh->or.crc_raster); - evo_kick(push, core); + /*XXX: This is a dirty hack until OR depth handling is + * improved later for deep colour etc. + */ + switch (asyh->or.depth) { + case 6: depth = 5; break; + case 5: depth = 4; break; + case 2: depth = 1; break; + case 0: depth = 4; break; + default: + depth = asyh->or.depth; + WARN_ON(1); + break; } + + if ((ret = PUSH_WAIT(push, 2))) + return ret; + + PUSH_NVSQ(push, NVC57D, 0x2004 + (i * 0x400), 0xfc000000 | + depth << 4 | + asyh->or.nvsync << 3 | + asyh->or.nhsync << 2 | + asyh->or.crc_raster); + return 0; } static int From c4b27bc8682c5d919a7e95c7cb3e2021d8b37c92 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sat, 18 Jul 2020 17:39:15 +1000 Subject: [PATCH 072/145] drm/nouveau/kms/nv50-: convert core crc_set_src() to new push macros Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/crc.h | 4 +-- drivers/gpu/drm/nouveau/dispnv50/crc907d.c | 30 ++++++++++------------ drivers/gpu/drm/nouveau/dispnv50/crcc37d.c | 29 ++++++++++----------- 3 files changed, 29 insertions(+), 34 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/crc.h b/drivers/gpu/drm/nouveau/dispnv50/crc.h index 4bc59e779315..0c10f84b1d62 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/crc.h +++ b/drivers/gpu/drm/nouveau/dispnv50/crc.h @@ -50,8 +50,8 @@ struct nv50_crc_atom { }; struct nv50_crc_func { - void (*set_src)(struct nv50_head *, int or, enum nv50_crc_source_type, - struct nv50_crc_notifier_ctx *, u32 wndw); + int (*set_src)(struct nv50_head *, int or, enum nv50_crc_source_type, + struct nv50_crc_notifier_ctx *, u32 wndw); void (*set_ctx)(struct nv50_head *, struct nv50_crc_notifier_ctx *); u32 (*get_entry)(struct nv50_head *, struct nv50_crc_notifier_ctx *, enum nv50_crc_source, int idx); diff --git a/drivers/gpu/drm/nouveau/dispnv50/crc907d.c b/drivers/gpu/drm/nouveau/dispnv50/crc907d.c index 92e907de7645..1401cf245a4e 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/crc907d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/crc907d.c @@ -6,6 +6,8 @@ #include "disp.h" #include "head.h" +#include + #define CRC907D_MAX_ENTRIES 255 struct crc907d_notifier { @@ -18,16 +20,16 @@ struct crc907d_notifier { } entries[CRC907D_MAX_ENTRIES]; } __packed; -static void +static int crc907d_set_src(struct nv50_head *head, int or, enum nv50_crc_source_type source, struct nv50_crc_notifier_ctx *ctx, u32 wndw) { struct drm_crtc *crtc = &head->base.base; - struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; - const u32 hoff = head->base.index * 0x300; - u32 *push; + struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push; + const int i = head->base.index; u32 crc_args = 0xfff00000; + int ret; switch (source) { case NV50_CRC_SOURCE_TYPE_SOR: @@ -50,22 +52,18 @@ crc907d_set_src(struct nv50_head *head, int or, break; } - push = evo_wait(core, 4); - if (!push) - return; + if ((ret = PUSH_WAIT(push, 4))) + return ret; if (source) { - evo_mthd(push, 0x0438 + hoff, 1); - evo_data(push, ctx->ntfy.handle); - evo_mthd(push, 0x0430 + hoff, 1); - evo_data(push, crc_args); + PUSH_NVSQ(push, NV907D, 0x0438 + (i * 0x300), ctx->ntfy.handle); + PUSH_NVSQ(push, NV907D, 0x0430 + (i * 0x300), crc_args); } else { - evo_mthd(push, 0x0430 + hoff, 1); - evo_data(push, crc_args); - evo_mthd(push, 0x0438 + hoff, 1); - evo_data(push, 0); + PUSH_NVSQ(push, NV907D, 0x0430 + (i * 0x300), crc_args); + PUSH_NVSQ(push, NV907D, 0x0438 + (i * 0x300), 0); } - evo_kick(push, core); + + return 0; } static void crc907d_set_ctx(struct nv50_head *head, diff --git a/drivers/gpu/drm/nouveau/dispnv50/crcc37d.c b/drivers/gpu/drm/nouveau/dispnv50/crcc37d.c index 940cefd5517d..ab78f7ca85a3 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/crcc37d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/crcc37d.c @@ -6,6 +6,8 @@ #include "disp.h" #include "head.h" +#include + #define CRCC37D_MAX_ENTRIES 2047 struct crcc37d_notifier { @@ -30,15 +32,15 @@ struct crcc37d_notifier { } entries[CRCC37D_MAX_ENTRIES]; } __packed; -static void +static int crcc37d_set_src(struct nv50_head *head, int or, enum nv50_crc_source_type source, struct nv50_crc_notifier_ctx *ctx, u32 wndw) { - struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; - const u32 hoff = head->base.index * 0x400; - u32 *push; + struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push; + const int i = head->base.index; u32 crc_args; + int ret; switch (source) { case NV50_CRC_SOURCE_TYPE_SOR: @@ -55,23 +57,18 @@ crcc37d_set_src(struct nv50_head *head, int or, break; } - push = evo_wait(core, 4); - if (!push) - return; + if ((ret = PUSH_WAIT(push, 4))) + return ret; if (source) { - evo_mthd(push, 0x2180 + hoff, 1); - evo_data(push, ctx->ntfy.handle); - evo_mthd(push, 0x2184 + hoff, 1); - evo_data(push, crc_args | wndw); + PUSH_NVSQ(push, NVC37D, 0x2180 + (i * 0x400), ctx->ntfy.handle); + PUSH_NVSQ(push, NVC37D, 0x2184 + (i * 0x400), crc_args | wndw); } else { - evo_mthd(push, 0x2184 + hoff, 1); - evo_data(push, 0); - evo_mthd(push, 0x2180 + hoff, 1); - evo_data(push, 0); + PUSH_NVSQ(push, NVC37D, 0x2184 + (i * 0x400), 0); + PUSH_NVSQ(push, NVC37D, 0x2180 + (i * 0x400), 0); } - evo_kick(push, core); + return 0; } static void crcc37d_set_ctx(struct nv50_head *head, From ae09163ac27ce7d576d7bd2e941eacaef8d491c1 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sat, 18 Jul 2020 17:42:27 +1000 Subject: [PATCH 073/145] drm/nouveau/kms/nv50-: convert core crc_set_ctx() to new push macros Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/crc.h | 2 +- drivers/gpu/drm/nouveau/dispnv50/crc907d.c | 18 +++++++++--------- drivers/gpu/drm/nouveau/dispnv50/crcc37d.c | 18 +++++++++--------- drivers/gpu/drm/nouveau/dispnv50/disp.h | 14 -------------- 4 files changed, 19 insertions(+), 33 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/crc.h b/drivers/gpu/drm/nouveau/dispnv50/crc.h index 0c10f84b1d62..ffb7b7c19570 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/crc.h +++ b/drivers/gpu/drm/nouveau/dispnv50/crc.h @@ -52,7 +52,7 @@ struct nv50_crc_atom { struct nv50_crc_func { int (*set_src)(struct nv50_head *, int or, enum nv50_crc_source_type, struct nv50_crc_notifier_ctx *, u32 wndw); - void (*set_ctx)(struct nv50_head *, struct nv50_crc_notifier_ctx *); + int (*set_ctx)(struct nv50_head *, struct nv50_crc_notifier_ctx *); u32 (*get_entry)(struct nv50_head *, struct nv50_crc_notifier_ctx *, enum nv50_crc_source, int idx); bool (*ctx_finished)(struct nv50_head *, diff --git a/drivers/gpu/drm/nouveau/dispnv50/crc907d.c b/drivers/gpu/drm/nouveau/dispnv50/crc907d.c index 1401cf245a4e..75728dc99b64 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/crc907d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/crc907d.c @@ -66,18 +66,18 @@ crc907d_set_src(struct nv50_head *head, int or, return 0; } -static void crc907d_set_ctx(struct nv50_head *head, - struct nv50_crc_notifier_ctx *ctx) +static int +crc907d_set_ctx(struct nv50_head *head, struct nv50_crc_notifier_ctx *ctx) { - struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; - u32 *push = evo_wait(core, 2); + struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push; + const int i = head->base.index; + int ret; - if (!push) - return; + if ((ret = PUSH_WAIT(push, 2))) + return ret; - evo_mthd(push, 0x0438 + (head->base.index * 0x300), 1); - evo_data(push, ctx ? ctx->ntfy.handle : 0); - evo_kick(push, core); + PUSH_NVSQ(push, NV907D, 0x0438 + (i * 0x300), ctx ? ctx->ntfy.handle : 0); + return 0; } static u32 crc907d_get_entry(struct nv50_head *head, diff --git a/drivers/gpu/drm/nouveau/dispnv50/crcc37d.c b/drivers/gpu/drm/nouveau/dispnv50/crcc37d.c index ab78f7ca85a3..dd818931db09 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/crcc37d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/crcc37d.c @@ -71,18 +71,18 @@ crcc37d_set_src(struct nv50_head *head, int or, return 0; } -static void crcc37d_set_ctx(struct nv50_head *head, - struct nv50_crc_notifier_ctx *ctx) +static int +crcc37d_set_ctx(struct nv50_head *head, struct nv50_crc_notifier_ctx *ctx) { - struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->core->chan; - u32 *push = evo_wait(core, 2); + struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push; + const int i = head->base.index; + int ret; - if (!push) - return; + if ((ret = PUSH_WAIT(push, 2))) + return ret; - evo_mthd(push, 0x2180 + (head->base.index * 0x400), 1); - evo_data(push, ctx ? ctx->ntfy.handle : 0); - evo_kick(push, core); + PUSH_NVSQ(push, NVC37D, 0x2180 + (i * 0x400), ctx ? ctx->ntfy.handle : 0); + return 0; } static u32 crcc37d_get_entry(struct nv50_head *head, diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.h b/drivers/gpu/drm/nouveau/dispnv50/disp.h index 746ab75d15c3..fbf573a01f58 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/disp.h +++ b/drivers/gpu/drm/nouveau/dispnv50/disp.h @@ -108,18 +108,4 @@ void evo_kick(u32 *, struct nv50_dmac *); extern const u64 disp50xx_modifiers[]; extern const u64 disp90xx_modifiers[]; extern const u64 wndwc57e_modifiers[]; - -#define evo_mthd(p, m, s) do { \ - const u32 _m = (m), _s = (s); \ - if (drm_debug_enabled(DRM_UT_KMS)) \ - pr_err("%04x %d %s\n", _m, _s, __func__); \ - *((p)++) = ((_s << 18) | _m); \ -} while(0) - -#define evo_data(p, d) do { \ - const u32 _d = (d); \ - if (drm_debug_enabled(DRM_UT_KMS)) \ - pr_err("\t%08x\n", _d); \ - *((p)++) = _d; \ -} while(0) #endif From 0a96099691c8cd1ac0744ef30b6846869dc2b566 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Tue, 21 Jul 2020 11:34:07 +1000 Subject: [PATCH 074/145] drm/nouveau/kms/nv50-: implement proper push buffer control logic We had a, what was supposed to be temporary, hack in the KMS code where we'd completely drain an EVO/NVD channel's push buffer when wrapping to the start again, instead of treating it as a ring buffer. Let's fix that, finally. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/dispnv50/disp.c | 159 ++++++++++-------- drivers/gpu/drm/nouveau/dispnv50/disp.h | 4 + drivers/gpu/drm/nouveau/include/nvif/object.h | 13 ++ .../drm/nouveau/nvkm/engine/disp/channv50.h | 2 + .../drm/nouveau/nvkm/engine/disp/coregf119.c | 4 +- .../drm/nouveau/nvkm/engine/disp/coregp102.c | 2 +- .../drm/nouveau/nvkm/engine/disp/coregv100.c | 3 +- .../drm/nouveau/nvkm/engine/disp/corenv50.c | 4 +- .../drm/nouveau/nvkm/engine/disp/dmacgf119.c | 4 +- .../drm/nouveau/nvkm/engine/disp/dmacgp102.c | 2 +- .../drm/nouveau/nvkm/engine/disp/dmacgv100.c | 4 +- .../drm/nouveau/nvkm/engine/disp/dmacnv50.c | 4 +- 12 files changed, 126 insertions(+), 79 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c b/drivers/gpu/drm/nouveau/dispnv50/disp.c index 368a2a97a900..0b3751c0d2a4 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/disp.c +++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c @@ -41,6 +41,8 @@ #include #include +#include + #include #include #include @@ -48,6 +50,8 @@ #include #include +#include + #include "nouveau_drv.h" #include "nouveau_dma.h" #include "nouveau_gem.h" @@ -120,21 +124,93 @@ static void nv50_dmac_kick(struct nvif_push *push) { struct nv50_dmac *dmac = container_of(push, typeof(*dmac), _push); - evo_kick(push->cur, dmac); - push->bgn = push->cur = push->end; + + dmac->cur = push->cur - (u32 *)dmac->_push.mem.object.map.ptr; + if (dmac->put != dmac->cur) { + /* Push buffer fetches are not coherent with BAR1, we need to ensure + * writes have been flushed right through to VRAM before writing PUT. + */ + if (dmac->push->mem.type & NVIF_MEM_VRAM) { + struct nvif_device *device = dmac->base.device; + nvif_wr32(&device->object, 0x070000, 0x00000001); + nvif_msec(device, 2000, + if (!(nvif_rd32(&device->object, 0x070000) & 0x00000002)) + break; + ); + } + + NVIF_WV32(&dmac->base.user, NV507C, PUT, PTR, dmac->cur); + dmac->put = dmac->cur; + } + + push->bgn = push->cur; +} + +static int +nv50_dmac_free(struct nv50_dmac *dmac) +{ + u32 get = NVIF_RV32(&dmac->base.user, NV507C, GET, PTR); + if (get > dmac->cur) /* NVIDIA stay 5 away from GET, do the same. */ + return get - dmac->cur - 5; + return dmac->max - dmac->cur; +} + +static int +nv50_dmac_wind(struct nv50_dmac *dmac) +{ + /* Wait for GET to depart from the beginning of the push buffer to + * prevent writing PUT == GET, which would be ignored by HW. + */ + u32 get = NVIF_RV32(&dmac->base.user, NV507C, GET, PTR); + if (get == 0) { + /* Corner-case, HW idle, but non-committed work pending. */ + if (dmac->put == 0) + nv50_dmac_kick(dmac->push); + + if (nvif_msec(dmac->base.device, 2000, + if (NVIF_TV32(&dmac->base.user, NV507C, GET, PTR, >, 0)) + break; + ) < 0) + return -ETIMEDOUT; + } + + PUSH_RSVD(dmac->push, PUSH_JUMP(dmac->push, 0)); + dmac->cur = 0; + return 0; } static int nv50_dmac_wait(struct nvif_push *push, u32 size) { struct nv50_dmac *dmac = container_of(push, typeof(*dmac), _push); - u32 *ptr = evo_wait(dmac, size); - if (!ptr) - return -ETIMEDOUT; + int free; - push->bgn = ptr; - push->cur = ptr; - push->end = ptr + size; + if (WARN_ON(size > dmac->max)) + return -EINVAL; + + dmac->cur = push->cur - (u32 *)dmac->_push.mem.object.map.ptr; + if (dmac->cur + size >= dmac->max) { + int ret = nv50_dmac_wind(dmac); + if (ret) + return ret; + + push->cur = dmac->_push.mem.object.map.ptr; + push->cur = push->cur + dmac->cur; + nv50_dmac_kick(push); + } + + if (nvif_msec(dmac->base.device, 2000, + if ((free = nv50_dmac_free(dmac)) >= size) + break; + ) < 0) { + WARN_ON(1); + return -ETIMEDOUT; + } + + push->bgn = dmac->_push.mem.object.map.ptr; + push->bgn = push->bgn + dmac->cur; + push->cur = push->bgn; + push->end = push->cur + free; return 0; } @@ -171,6 +247,10 @@ nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp, dmac->_push.wait = nv50_dmac_wait; dmac->_push.kick = nv50_dmac_kick; dmac->push = &dmac->_push; + dmac->push->bgn = dmac->_push.mem.object.map.ptr; + dmac->push->cur = dmac->push->bgn; + dmac->push->end = dmac->push->bgn; + dmac->max = 0x1000/4 - 1; args->pushbuf = nvif_handle(&dmac->_push.mem.object); @@ -209,69 +289,6 @@ nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp, return ret; } -/****************************************************************************** - * EVO channel helpers - *****************************************************************************/ -static void -evo_flush(struct nv50_dmac *dmac) -{ - /* Push buffer fetches are not coherent with BAR1, we need to ensure - * writes have been flushed right through to VRAM before writing PUT. - */ - if (dmac->push->mem.type & NVIF_MEM_VRAM) { - struct nvif_device *device = dmac->base.device; - nvif_wr32(&device->object, 0x070000, 0x00000001); - nvif_msec(device, 2000, - if (!(nvif_rd32(&device->object, 0x070000) & 0x00000002)) - break; - ); - } -} - -u32 * -evo_wait(struct nv50_dmac *evoc, int nr) -{ - struct nv50_dmac *dmac = evoc; - struct nvif_device *device = dmac->base.device; - u32 put; - - if (dmac->push->cur != dmac->push->bgn) - PUSH_KICK(dmac->push); - - put = nvif_rd32(&dmac->base.user, 0x0000) / 4; - - mutex_lock(&dmac->lock); - if (put + nr >= (PAGE_SIZE / 4) - 8) { - dmac->ptr[put] = 0x20000000; - evo_flush(dmac); - - nvif_wr32(&dmac->base.user, 0x0000, 0x00000000); - if (nvif_msec(device, 2000, - if (!nvif_rd32(&dmac->base.user, 0x0004)) - break; - ) < 0) { - mutex_unlock(&dmac->lock); - pr_err("nouveau: evo channel stalled\n"); - return NULL; - } - - put = 0; - } - - return dmac->ptr + put; -} - -void -evo_kick(u32 *push, struct nv50_dmac *evoc) -{ - struct nv50_dmac *dmac = evoc; - - evo_flush(dmac); - - nvif_wr32(&dmac->base.user, 0x0000, (push - dmac->ptr) << 2); - mutex_unlock(&dmac->lock); -} - /****************************************************************************** * Output path helpers *****************************************************************************/ diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.h b/drivers/gpu/drm/nouveau/dispnv50/disp.h index fbf573a01f58..92bddc083617 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/disp.h +++ b/drivers/gpu/drm/nouveau/dispnv50/disp.h @@ -73,6 +73,10 @@ struct nv50_dmac { * grabbed by evo_wait (if the pushbuf reservation is successful) and * dropped again by evo_kick. */ struct mutex lock; + + u32 cur; + u32 put; + u32 max; }; struct nv50_outp_atom { diff --git a/drivers/gpu/drm/nouveau/include/nvif/object.h b/drivers/gpu/drm/nouveau/include/nvif/object.h index a39d2bf7064b..1e4c158d20fa 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/object.h +++ b/drivers/gpu/drm/nouveau/include/nvif/object.h @@ -116,6 +116,19 @@ struct nvif_mclass { _cid; \ }) +#define NVIF_RD32_(p,o,dr) nvif_rd32((p), (o) + (dr)) +#define NVIF_WR32_(p,o,dr,f) nvif_wr32((p), (o) + (dr), (f)) +#define NVIF_RD32(p,A...) DRF_RD(NVIF_RD32_, (p), 0, ##A) +#define NVIF_RV32(p,A...) DRF_RV(NVIF_RD32_, (p), 0, ##A) +#define NVIF_TV32(p,A...) DRF_TV(NVIF_RD32_, (p), 0, ##A) +#define NVIF_TD32(p,A...) DRF_TD(NVIF_RD32_, (p), 0, ##A) +#define NVIF_WR32(p,A...) DRF_WR( NVIF_WR32_, (p), 0, ##A) +#define NVIF_WV32(p,A...) DRF_WV( NVIF_WR32_, (p), 0, ##A) +#define NVIF_WD32(p,A...) DRF_WD( NVIF_WR32_, (p), 0, ##A) +#define NVIF_MR32(p,A...) DRF_MR(NVIF_RD32_, NVIF_WR32_, u32, (p), 0, ##A) +#define NVIF_MV32(p,A...) DRF_MV(NVIF_RD32_, NVIF_WR32_, u32, (p), 0, ##A) +#define NVIF_MD32(p,A...) DRF_MD(NVIF_RD32_, NVIF_WR32_, u32, (p), 0, ##A) + /*XXX*/ #include #define nvxx_object(a) ({ \ diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.h b/drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.h index e55054b7329f..9cf2cfe2010c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.h @@ -21,6 +21,8 @@ struct nv50_disp_chan { struct nvkm_memory *memory; u64 push; + + u32 suspend_put; }; struct nv50_disp_chan_func { diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/coregf119.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/coregf119.c index d162b9cf4eac..689e3cdd959a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/coregf119.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/coregf119.c @@ -182,6 +182,8 @@ gf119_disp_core_fini(struct nv50_disp_chan *chan) nvkm_error(subdev, "core fini: %08x\n", nvkm_rd32(device, 0x610490)); } + + chan->suspend_put = nvkm_rd32(device, 0x640000); } static int @@ -195,7 +197,7 @@ gf119_disp_core_init(struct nv50_disp_chan *chan) nvkm_wr32(device, 0x610498, 0x00010000); nvkm_wr32(device, 0x61049c, 0x00000001); nvkm_mask(device, 0x610490, 0x00000010, 0x00000010); - nvkm_wr32(device, 0x640000, 0x00000000); + nvkm_wr32(device, 0x640000, chan->suspend_put); nvkm_wr32(device, 0x610490, 0x01000013); /* wait for it to go inactive */ diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/coregp102.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/coregp102.c index 5b7f993c73c7..1b435beef3bf 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/coregp102.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/coregp102.c @@ -36,7 +36,7 @@ gp102_disp_core_init(struct nv50_disp_chan *chan) nvkm_wr32(device, 0x611498, 0x00010000); nvkm_wr32(device, 0x61149c, 0x00000001); nvkm_mask(device, 0x610490, 0x00000010, 0x00000010); - nvkm_wr32(device, 0x640000, 0x00000000); + nvkm_wr32(device, 0x640000, chan->suspend_put); nvkm_wr32(device, 0x610490, 0x01000013); /* wait for it to go inactive */ diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/coregv100.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/coregv100.c index 4592d0e69fec..e20a48f201f6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/coregv100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/coregv100.c @@ -167,6 +167,7 @@ gv100_disp_core_fini(struct nv50_disp_chan *chan) nvkm_mask(device, 0x6104e0, 0x00000010, 0x00000000); gv100_disp_core_idle(chan); nvkm_mask(device, 0x6104e0, 0x00000002, 0x00000000); + chan->suspend_put = nvkm_rd32(device, 0x680000); } static int @@ -181,7 +182,7 @@ gv100_disp_core_init(struct nv50_disp_chan *chan) nvkm_wr32(device, 0x610b2c, 0x00000040); nvkm_mask(device, 0x6104e0, 0x00000010, 0x00000010); - nvkm_wr32(device, 0x680000, 0x00000000); + nvkm_wr32(device, 0x680000, chan->suspend_put); nvkm_wr32(device, 0x6104e0, 0x00000013); return gv100_disp_core_idle(chan); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/corenv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/corenv50.c index 55db9a22b4be..660310b27f9c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/corenv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/corenv50.c @@ -179,6 +179,8 @@ nv50_disp_core_fini(struct nv50_disp_chan *chan) nvkm_error(subdev, "core fini: %08x\n", nvkm_rd32(device, 0x610200)); } + + chan->suspend_put = nvkm_rd32(device, 0x640000); } static int @@ -198,7 +200,7 @@ nv50_disp_core_init(struct nv50_disp_chan *chan) nvkm_wr32(device, 0x610208, 0x00010000); nvkm_wr32(device, 0x61020c, 0x00000000); nvkm_mask(device, 0x610200, 0x00000010, 0x00000010); - nvkm_wr32(device, 0x640000, 0x00000000); + nvkm_wr32(device, 0x640000, chan->suspend_put); nvkm_wr32(device, 0x610200, 0x01000013); /* wait for it to go inactive */ diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacgf119.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacgf119.c index edf7dd0d931d..76425e8586da 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacgf119.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacgf119.c @@ -53,6 +53,8 @@ gf119_disp_dmac_fini(struct nv50_disp_chan *chan) nvkm_error(subdev, "ch %d fini: %08x\n", user, nvkm_rd32(device, 0x610490 + (ctrl * 0x10))); } + + chan->suspend_put = nvkm_rd32(device, 0x640000 + (ctrl * 0x1000)); } static int @@ -68,7 +70,7 @@ gf119_disp_dmac_init(struct nv50_disp_chan *chan) nvkm_wr32(device, 0x610498 + (ctrl * 0x0010), 0x00010000); nvkm_wr32(device, 0x61049c + (ctrl * 0x0010), 0x00000001); nvkm_mask(device, 0x610490 + (ctrl * 0x0010), 0x00000010, 0x00000010); - nvkm_wr32(device, 0x640000 + (ctrl * 0x1000), 0x00000000); + nvkm_wr32(device, 0x640000 + (ctrl * 0x1000), chan->suspend_put); nvkm_wr32(device, 0x610490 + (ctrl * 0x0010), 0x00000013); /* wait for it to go inactive */ diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacgp102.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacgp102.c index f21a433199aa..da258df268d7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacgp102.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacgp102.c @@ -38,7 +38,7 @@ gp102_disp_dmac_init(struct nv50_disp_chan *chan) nvkm_wr32(device, 0x611498 + (ctrl * 0x0010), 0x00010000); nvkm_wr32(device, 0x61149c + (ctrl * 0x0010), 0x00000001); nvkm_mask(device, 0x610490 + (ctrl * 0x0010), 0x00000010, 0x00000010); - nvkm_wr32(device, 0x640000 + (ctrl * 0x1000), 0x00000000); + nvkm_wr32(device, 0x640000 + (ctrl * 0x1000), chan->suspend_put); nvkm_wr32(device, 0x610490 + (ctrl * 0x0010), 0x00000013); /* wait for it to go inactive */ diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacgv100.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacgv100.c index eac0e42da354..fdb624ac6b87 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacgv100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacgv100.c @@ -50,10 +50,12 @@ void gv100_disp_dmac_fini(struct nv50_disp_chan *chan) { struct nvkm_device *device = chan->disp->base.engine.subdev.device; + const u32 uoff = (chan->chid.ctrl - 1) * 0x1000; const u32 coff = chan->chid.ctrl * 0x04; nvkm_mask(device, 0x6104e0 + coff, 0x00000010, 0x00000000); gv100_disp_dmac_idle(chan); nvkm_mask(device, 0x6104e0 + coff, 0x00000002, 0x00000000); + chan->suspend_put = nvkm_rd32(device, 0x690000 + uoff); } int @@ -71,7 +73,7 @@ gv100_disp_dmac_init(struct nv50_disp_chan *chan) nvkm_wr32(device, 0x610b2c + poff, 0x00000040); nvkm_mask(device, 0x6104e0 + coff, 0x00000010, 0x00000010); - nvkm_wr32(device, 0x690000 + uoff, 0x00000000); + nvkm_wr32(device, 0x690000 + uoff, chan->suspend_put); nvkm_wr32(device, 0x6104e0 + coff, 0x00000013); return gv100_disp_dmac_idle(chan); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacnv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacnv50.c index 9e8a9d7a9b68..d0a7da96d62b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacnv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacnv50.c @@ -94,6 +94,8 @@ nv50_disp_dmac_fini(struct nv50_disp_chan *chan) nvkm_error(subdev, "ch %d fini timeout, %08x\n", user, nvkm_rd32(device, 0x610200 + (ctrl * 0x10))); } + + chan->suspend_put = nvkm_rd32(device, 0x640000 + (ctrl * 0x1000)); } static int @@ -109,7 +111,7 @@ nv50_disp_dmac_init(struct nv50_disp_chan *chan) nvkm_wr32(device, 0x610208 + (ctrl * 0x0010), 0x00010000); nvkm_wr32(device, 0x61020c + (ctrl * 0x0010), ctrl); nvkm_mask(device, 0x610200 + (ctrl * 0x0010), 0x00000010, 0x00000010); - nvkm_wr32(device, 0x640000 + (ctrl * 0x1000), 0x00000000); + nvkm_wr32(device, 0x640000 + (ctrl * 0x1000), chan->suspend_put); nvkm_wr32(device, 0x610200 + (ctrl * 0x0010), 0x00000013); /* wait for it to go inactive */ From fdb06e2b2a18b3650526857ccb1ea95333282b90 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sat, 18 Jul 2020 18:06:30 +1000 Subject: [PATCH 075/145] drm/nouveau: interop with new push macros Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/nouveau_chan.c | 33 ++++++++++++++++++++++++++ drivers/gpu/drm/nouveau/nouveau_chan.h | 6 +++++ 2 files changed, 39 insertions(+) diff --git a/drivers/gpu/drm/nouveau/nouveau_chan.c b/drivers/gpu/drm/nouveau/nouveau_chan.c index d208ef4b158c..27092a6933ee 100644 --- a/drivers/gpu/drm/nouveau/nouveau_chan.c +++ b/drivers/gpu/drm/nouveau/nouveau_chan.c @@ -121,6 +121,31 @@ nouveau_channel_del(struct nouveau_channel **pchan) *pchan = NULL; } +static void +nouveau_channel_kick(struct nvif_push *push) +{ + struct nouveau_channel *chan = container_of(push, typeof(*chan), chan._push); + chan->dma.cur = chan->dma.cur + (chan->chan._push.cur - chan->chan._push.bgn); + FIRE_RING(chan); + chan->chan._push.bgn = chan->chan._push.cur; +} + +static int +nouveau_channel_wait(struct nvif_push *push, u32 size) +{ + struct nouveau_channel *chan = container_of(push, typeof(*chan), chan._push); + int ret; + chan->dma.cur = chan->dma.cur + (chan->chan._push.cur - chan->chan._push.bgn); + ret = RING_SPACE(chan, size); + if (ret == 0) { + chan->chan._push.bgn = chan->chan._push.mem.object.map.ptr; + chan->chan._push.bgn = chan->chan._push.bgn + chan->dma.cur; + chan->chan._push.cur = chan->chan._push.bgn; + chan->chan._push.end = chan->chan._push.bgn + size; + } + return ret; +} + static int nouveau_channel_prep(struct nouveau_drm *drm, struct nvif_device *device, u32 size, struct nouveau_channel **pchan) @@ -158,6 +183,14 @@ nouveau_channel_prep(struct nouveau_drm *drm, struct nvif_device *device, return ret; } + chan->chan._push.mem.object.parent = cli->base.object.parent; + chan->chan._push.mem.object.client = &cli->base; + chan->chan._push.mem.object.name = "chanPush"; + chan->chan._push.mem.object.map.ptr = chan->push.buffer->kmap.virtual; + chan->chan._push.wait = nouveau_channel_wait; + chan->chan._push.kick = nouveau_channel_kick; + chan->chan.push = &chan->chan._push; + /* create dma object covering the *entire* memory space that the * pushbuf lives in, this is because the GEM code requires that * we be able to call out to other (indirect) push buffers diff --git a/drivers/gpu/drm/nouveau/nouveau_chan.h b/drivers/gpu/drm/nouveau/nouveau_chan.h index 9307357e1361..98ba9d27e6b4 100644 --- a/drivers/gpu/drm/nouveau/nouveau_chan.h +++ b/drivers/gpu/drm/nouveau/nouveau_chan.h @@ -3,9 +3,15 @@ #define __NOUVEAU_CHAN_H__ #include #include +#include struct nvif_device; struct nouveau_channel { + struct { + struct nvif_push _push; + struct nvif_push *push; + } chan; + struct nvif_device *device; struct nouveau_drm *drm; struct nouveau_vmm *vmm; From d9a91300ae21bb886b05014cfb1a3ad0dfff04b8 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 22 Jun 2020 11:08:51 +1000 Subject: [PATCH 076/145] drm/nouveau/fbcon: convert accel_init() to new push macros Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- .../drm/nouveau/include/nvhw/class/cl006c.h | 46 +++++++ .../drm/nouveau/include/nvhw/class/cl206e.h | 35 ++++++ .../drm/nouveau/include/nvhw/class/cl906f.h | 74 ++++++++++++ .../gpu/drm/nouveau/include/nvif/push006c.h | 73 +++++++++++ .../gpu/drm/nouveau/include/nvif/push206e.h | 13 ++ .../gpu/drm/nouveau/include/nvif/push906f.h | 48 ++++++++ drivers/gpu/drm/nouveau/nouveau_dma.h | 1 - drivers/gpu/drm/nouveau/nv04_fbcon.c | 101 +++++++--------- drivers/gpu/drm/nouveau/nv50_fbcon.c | 113 ++++++++---------- drivers/gpu/drm/nouveau/nvc0_fbcon.c | 109 ++++++++--------- 10 files changed, 431 insertions(+), 182 deletions(-) create mode 100644 drivers/gpu/drm/nouveau/include/nvhw/class/cl006c.h create mode 100644 drivers/gpu/drm/nouveau/include/nvhw/class/cl206e.h create mode 100644 drivers/gpu/drm/nouveau/include/nvhw/class/cl906f.h create mode 100644 drivers/gpu/drm/nouveau/include/nvif/push006c.h create mode 100644 drivers/gpu/drm/nouveau/include/nvif/push206e.h create mode 100644 drivers/gpu/drm/nouveau/include/nvif/push906f.h diff --git a/drivers/gpu/drm/nouveau/include/nvhw/class/cl006c.h b/drivers/gpu/drm/nouveau/include/nvhw/class/cl006c.h new file mode 100644 index 000000000000..9ab2a22659e4 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvhw/class/cl006c.h @@ -0,0 +1,46 @@ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ +#ifndef _cl006c_h_ +#define _cl006c_h_ + +/* fields and values */ +#define NV06C_PUT (0x00000040) +#define NV06C_PUT_PTR 31:2 +#define NV06C_GET (0x00000044) +#define NV06C_GET_PTR 31:2 + +/* dma method descriptor format */ +#define NV06C_METHOD_ADDRESS 12:2 +#define NV06C_METHOD_SUBCHANNEL 15:13 +#define NV06C_METHOD_COUNT 28:18 +#define NV06C_OPCODE 31:29 +#define NV06C_OPCODE_METHOD (0x00000000) +#define NV06C_OPCODE_NONINC_METHOD (0x00000002) + +/* dma data format */ +#define NV06C_DATA 31:0 + +/* dma jump format */ +#define NV06C_OPCODE_JUMP (0x00000001) +#define NV06C_JUMP_OFFSET 28:2 +#endif /* _cl006c_h_ */ diff --git a/drivers/gpu/drm/nouveau/include/nvhw/class/cl206e.h b/drivers/gpu/drm/nouveau/include/nvhw/class/cl206e.h new file mode 100644 index 000000000000..27313c7c43cd --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvhw/class/cl206e.h @@ -0,0 +1,35 @@ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ +#ifndef _cl206e_h_ +#define _cl206e_h_ + +/* dma opcode2 format */ +#define NV206E_DMA_OPCODE2 1:0 +#define NV206E_DMA_OPCODE2_NONE (0x00000000) +/* dma jump_long format */ +#define NV206E_DMA_OPCODE2_JUMP_LONG (0x00000001) +#define NV206E_DMA_JUMP_LONG_OFFSET 31:2 +/* dma call format */ +#define NV206E_DMA_OPCODE2_CALL (0x00000002) +#define NV206E_DMA_CALL_OFFSET 31:2 +#endif /* _cl206e_h_ */ diff --git a/drivers/gpu/drm/nouveau/include/nvhw/class/cl906f.h b/drivers/gpu/drm/nouveau/include/nvhw/class/cl906f.h new file mode 100644 index 000000000000..673d668885bb --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvhw/class/cl906f.h @@ -0,0 +1,74 @@ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ +#ifndef _cl906f_h_ +#define _cl906f_h_ + +/* fields and values */ +#define NV906F_SEMAPHOREA (0x00000010) +#define NV906F_SEMAPHOREA_OFFSET_UPPER 7:0 +#define NV906F_SEMAPHOREB (0x00000014) +#define NV906F_SEMAPHOREB_OFFSET_LOWER 31:2 +#define NV906F_SEMAPHOREC (0x00000018) +#define NV906F_SEMAPHOREC_PAYLOAD 31:0 +#define NV906F_SEMAPHORED (0x0000001C) +#define NV906F_SEMAPHORED_OPERATION 3:0 +#define NV906F_SEMAPHORED_OPERATION_ACQUIRE 0x00000001 +#define NV906F_SEMAPHORED_OPERATION_RELEASE 0x00000002 +#define NV906F_SEMAPHORED_OPERATION_ACQ_GEQ 0x00000004 +#define NV906F_SEMAPHORED_OPERATION_ACQ_AND 0x00000008 +#define NV906F_SEMAPHORED_ACQUIRE_SWITCH 12:12 +#define NV906F_SEMAPHORED_ACQUIRE_SWITCH_DISABLED 0x00000000 +#define NV906F_SEMAPHORED_ACQUIRE_SWITCH_ENABLED 0x00000001 +#define NV906F_SEMAPHORED_RELEASE_WFI 20:20 +#define NV906F_SEMAPHORED_RELEASE_WFI_EN 0x00000000 +#define NV906F_SEMAPHORED_RELEASE_WFI_DIS 0x00000001 +#define NV906F_SEMAPHORED_RELEASE_SIZE 24:24 +#define NV906F_SEMAPHORED_RELEASE_SIZE_16BYTE 0x00000000 +#define NV906F_SEMAPHORED_RELEASE_SIZE_4BYTE 0x00000001 +#define NV906F_NON_STALL_INTERRUPT (0x00000020) +#define NV906F_NON_STALL_INTERRUPT_HANDLE 31:0 +#define NV906F_SET_REFERENCE (0x00000050) +#define NV906F_SET_REFERENCE_COUNT 31:0 + +/* dma method formats */ +#define NV906F_DMA_METHOD_ADDRESS 11:0 +#define NV906F_DMA_SUBDEVICE_MASK 15:4 +#define NV906F_DMA_METHOD_SUBCHANNEL 15:13 +#define NV906F_DMA_TERT_OP 17:16 +#define NV906F_DMA_TERT_OP_GRP0_INC_METHOD (0x00000000) +#define NV906F_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK (0x00000001) +#define NV906F_DMA_TERT_OP_GRP0_STORE_SUB_DEV_MASK (0x00000002) +#define NV906F_DMA_TERT_OP_GRP0_USE_SUB_DEV_MASK (0x00000003) +#define NV906F_DMA_TERT_OP_GRP2_NON_INC_METHOD (0x00000000) +#define NV906F_DMA_METHOD_COUNT 28:16 +#define NV906F_DMA_IMMD_DATA 28:16 +#define NV906F_DMA_SEC_OP 31:29 +#define NV906F_DMA_SEC_OP_GRP0_USE_TERT (0x00000000) +#define NV906F_DMA_SEC_OP_INC_METHOD (0x00000001) +#define NV906F_DMA_SEC_OP_GRP2_USE_TERT (0x00000002) +#define NV906F_DMA_SEC_OP_NON_INC_METHOD (0x00000003) +#define NV906F_DMA_SEC_OP_IMMD_DATA_METHOD (0x00000004) +#define NV906F_DMA_SEC_OP_ONE_INC (0x00000005) +#define NV906F_DMA_SEC_OP_RESERVED6 (0x00000006) +#define NV906F_DMA_SEC_OP_END_PB_SEGMENT (0x00000007) +#endif /* _cl906f_h_ */ diff --git a/drivers/gpu/drm/nouveau/include/nvif/push006c.h b/drivers/gpu/drm/nouveau/include/nvif/push006c.h new file mode 100644 index 000000000000..a31c147e72c7 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvif/push006c.h @@ -0,0 +1,73 @@ +#ifndef __NVIF_PUSH006C_H__ +#define __NVIF_PUSH006C_H__ +#include + +#include + +#ifndef PUSH006C_SUBC +// Host methods +#define PUSH006C_SUBC_NV06E 0 +#define PUSH006C_SUBC_NV176E 0 +#define PUSH006C_SUBC_NV826F 0 + +// ContextSurfaces2d +#define PUSH006C_SUBC_NV042 0 +#define PUSH006C_SUBC_NV062 0 + +// ContextClipRectangle +#define PUSH006C_SUBC_NV019 0 + +// ContextRop +#define PUSH006C_SUBC_NV043 0 + +// ContextPattern +#define PUSH006C_SUBC_NV044 0 + +// Misc dodginess... +#define PUSH006C_SUBC_NV_SW 1 + +// ImageBlit +#define PUSH006C_SUBC_NV05F 2 +#define PUSH006C_SUBC_NV09F 2 + +// GdiRectangleText +#define PUSH006C_SUBC_NV04A 3 + +// Twod +#define PUSH006C_SUBC_NV502D 3 + +// MemoryToMemoryFormat +#define PUSH006C_SUBC_NV039 4 +#define PUSH006C_SUBC_NV5039 4 + +// DmaCopy +#define PUSH006C_SUBC_NV85B5 4 + +// Cipher +#define PUSH006C_SUBC_NV74C1 4 +#endif + +#define PUSH_HDR(p,o,n,s,m,c) do { \ + PUSH_ASSERT(!((s) & ~DRF_MASK(NV06C_METHOD_SUBCHANNEL)), "subc"); \ + PUSH_ASSERT(!((m) & ~DRF_SMASK(NV06C_METHOD_ADDRESS)), "mthd"); \ + PUSH_ASSERT(!((c) & ~DRF_MASK(NV06C_METHOD_COUNT)), "count"); \ + PUSH_DATA__((p), NVVAL_X(NV06C_METHOD_ADDRESS, (m) >> 2) | \ + NVVAL_X(NV06C_METHOD_SUBCHANNEL, (s)) | \ + NVVAL_X(NV06C_METHOD_COUNT, (c)) | \ + NVVAL_X(NV06C_OPCODE, NV06C_OPCODE_##o), \ + " "n" subc %d mthd 0x%04x size %d - %s", \ + (u32)(s), (u32)(m), (u32)(c), __func__); \ +} while(0) + +#define PUSH_MTHD_HDR(p,c,m,n) PUSH_HDR(p, METHOD, "incr", PUSH006C_SUBC_##c, m, n) +#define PUSH_MTHD_INC 4:4 +#define PUSH_NINC_HDR(p,c,m,n) PUSH_HDR(p, NONINC_METHOD, "ninc", PUSH006C_SUBC_##c, m, n) +#define PUSH_NINC_INC 0:0 + +#define PUSH_JUMP(p,o) do { \ + PUSH_ASSERT(!((o) & ~0x1fffffffcULL), "offset"); \ + PUSH_DATA__((p), NVVAL_X(NV06C_OPCODE, NV06C_OPCODE_JUMP) | \ + NVVAL_X(NV06C_JUMP_OFFSET, (o) >> 2), \ + " jump 0x%08x - %s", (u32)(o), __func__); \ +} while(0) +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvif/push206e.h b/drivers/gpu/drm/nouveau/include/nvif/push206e.h new file mode 100644 index 000000000000..1dfb8a35423e --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvif/push206e.h @@ -0,0 +1,13 @@ +#ifndef __NVIF_PUSH206E_H__ +#define __NVIF_PUSH206E_H__ +#include + +#include + +#define PUSH_CALL(p,o) do { \ + PUSH_ASSERT(!((o) & ~0xffffffffcULL), "offset"); \ + PUSH_DATA__((p), NVDEF(NV206E, DMA, OPCODE2, CALL) | \ + NVVAL(NV206E, DMA, CALL_OFFSET, (o) >> 2), \ + " call 0x%08x - %s", (u32)(o), __func__); \ +} while(0) +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvif/push906f.h b/drivers/gpu/drm/nouveau/include/nvif/push906f.h new file mode 100644 index 000000000000..cc2866bc8b0a --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvif/push906f.h @@ -0,0 +1,48 @@ +#ifndef __NVIF_PUSH906F_H__ +#define __NVIF_PUSH906F_H__ +#include + +#include + +#ifndef PUSH906F_SUBC +// Host methods +#define PUSH906F_SUBC_NV906F 0 + +// Twod +#define PUSH906F_SUBC_NV902D 3 + +// MemoryToMemoryFormat +#define PUSH906F_SUBC_NV9039 4 + +// DmaCopy +#define PUSH906F_SUBC_NV90B5 4 +#define PUSH906F_SUBC_NVA0B5 4 +#endif + +#define PUSH_HDR(p,o,n,f,s,m,c) do { \ + PUSH_ASSERT(!((s) & ~DRF_MASK(NV906F_DMA_METHOD_SUBCHANNEL)), "subc"); \ + PUSH_ASSERT(!((m) & ~(DRF_MASK(NV906F_DMA_METHOD_ADDRESS) << 2)), "mthd"); \ + PUSH_ASSERT(!((c) & ~DRF_MASK(NV906F_DMA_METHOD_COUNT)), "count/immd"); \ + PUSH_DATA__((p), NVVAL(NV906F, DMA, METHOD_ADDRESS, (m) >> 2) | \ + NVVAL(NV906F, DMA, METHOD_SUBCHANNEL, (s)) | \ + NVVAL(NV906F, DMA, METHOD_COUNT, (c)) | \ + NVDEF(NV906F, DMA, SEC_OP, o), \ + " "n" subc %d mthd 0x%04x "f" - %s", \ + (u32)(s), (u32)(m), (u32)(c), __func__); \ +} while(0) + +#define PUSH_MTHD_INC 4:4 +#define PUSH_MTHD_HDR(p,c,m,n) \ + PUSH_HDR(p, INC_METHOD, "incr", "size %d", PUSH906F_SUBC_##c, m, n) + +#define PUSH_NINC_INC 0:0 +#define PUSH_NINC_HDR(p,c,m,n) \ + PUSH_HDR(p, NON_INC_METHOD, "ninc", "size %d", PUSH906F_SUBC_##c, m, n) + +#define PUSH_IMMD_HDR(p,c,m,n) \ + PUSH_HDR(p, IMMD_DATA_METHOD, "immd", "data 0x%04x", PUSH906F_SUBC_##c, m, n) + +#define PUSH_1INC_INC 4:0 +#define PUSH_1INC_HDR(p,c,m,n) \ + PUSH_HDR(p, ONE_INC, "oinc", "size %d", PUSH906F_SUBC_##c, m, n) +#endif diff --git a/drivers/gpu/drm/nouveau/nouveau_dma.h b/drivers/gpu/drm/nouveau/nouveau_dma.h index fc5e3f41282d..d00cf7bd220c 100644 --- a/drivers/gpu/drm/nouveau/nouveau_dma.h +++ b/drivers/gpu/drm/nouveau/nouveau_dma.h @@ -47,7 +47,6 @@ void nv50_dma_push(struct nouveau_channel *, u64 addr, int length); /* Hardcoded object assignments to subchannels (subchannel id). */ enum { - NvSubCtxSurf2D = 0, NvSubSw = 1, NvSubImageBlit = 2, NvSubGdiRect = 3, diff --git a/drivers/gpu/drm/nouveau/nv04_fbcon.c b/drivers/gpu/drm/nouveau/nv04_fbcon.c index 936e11f526b6..a254e5f7fad1 100644 --- a/drivers/gpu/drm/nouveau/nv04_fbcon.c +++ b/drivers/gpu/drm/nouveau/nv04_fbcon.c @@ -21,11 +21,13 @@ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ - +#define NVIF_DEBUG_PRINT_DISABLE #include "nouveau_drv.h" #include "nouveau_dma.h" #include "nouveau_fbcon.h" +#include + int nv04_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *region) { @@ -137,6 +139,7 @@ nv04_fbcon_accel_init(struct fb_info *info) struct nouveau_drm *drm = nouveau_drm(dev); struct nouveau_channel *chan = drm->channel; struct nvif_device *device = &drm->client.device; + struct nvif_push *push = chan->chan.push; int surface_fmt, pattern_fmt, rect_fmt; int ret; @@ -200,78 +203,58 @@ nv04_fbcon_accel_init(struct fb_info *info) if (ret) return ret; - if (RING_SPACE(chan, 49 + (device->info.chipset >= 0x11 ? 4 : 0))) { + if (PUSH_WAIT(push, 49 + (device->info.chipset >= 0x11 ? 4 : 0))) { nouveau_fbcon_gpu_lockup(info); return 0; } - BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1); - OUT_RING(chan, nfbdev->surf2d.handle); - BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0184, 2); - OUT_RING(chan, chan->vram.handle); - OUT_RING(chan, chan->vram.handle); - BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 4); - OUT_RING(chan, surface_fmt); - OUT_RING(chan, info->fix.line_length | (info->fix.line_length << 16)); - OUT_RING(chan, info->fix.smem_start - dev->mode_config.fb_base); - OUT_RING(chan, info->fix.smem_start - dev->mode_config.fb_base); + PUSH_NVSQ(push, NV042, 0x0000, nfbdev->surf2d.handle); + PUSH_NVSQ(push, NV042, 0x0184, chan->vram.handle, + 0x0188, chan->vram.handle); + PUSH_NVSQ(push, NV042, 0x0300, surface_fmt, + 0x0304, info->fix.line_length | (info->fix.line_length << 16), + 0x0308, info->fix.smem_start - dev->mode_config.fb_base, + 0x030c, info->fix.smem_start - dev->mode_config.fb_base); - BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1); - OUT_RING(chan, nfbdev->rop.handle); - BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 1); - OUT_RING(chan, 0x55); + PUSH_NVSQ(push, NV043, 0x0000, nfbdev->rop.handle); + PUSH_NVSQ(push, NV043, 0x0300, 0x55); - BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1); - OUT_RING(chan, nfbdev->patt.handle); - BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 8); - OUT_RING(chan, pattern_fmt); + PUSH_NVSQ(push, NV044, 0x0000, nfbdev->patt.handle); + PUSH_NVSQ(push, NV044, 0x0300, pattern_fmt, #ifdef __BIG_ENDIAN - OUT_RING(chan, 2); + 0x0304, 2, #else - OUT_RING(chan, 1); + 0x0304, 1, #endif - OUT_RING(chan, 0); - OUT_RING(chan, 1); - OUT_RING(chan, ~0); - OUT_RING(chan, ~0); - OUT_RING(chan, ~0); - OUT_RING(chan, ~0); + 0x0308, 0, + 0x030c, 1, + 0x0310, ~0, + 0x0314, ~0, + 0x0318, ~0, + 0x031c, ~0); - BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1); - OUT_RING(chan, nfbdev->clip.handle); - BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 2); - OUT_RING(chan, 0); - OUT_RING(chan, (info->var.yres_virtual << 16) | info->var.xres_virtual); + PUSH_NVSQ(push, NV019, 0x0000, nfbdev->clip.handle); + PUSH_NVSQ(push, NV019, 0x0300, 0, + 0x0304, (info->var.yres_virtual << 16) | info->var.xres_virtual); - BEGIN_NV04(chan, NvSubImageBlit, 0x0000, 1); - OUT_RING(chan, nfbdev->blit.handle); - BEGIN_NV04(chan, NvSubImageBlit, 0x019c, 1); - OUT_RING(chan, nfbdev->surf2d.handle); - BEGIN_NV04(chan, NvSubImageBlit, 0x02fc, 1); - OUT_RING(chan, 3); - if (device->info.chipset >= 0x11 /*XXX: oclass == 0x009f*/) { - BEGIN_NV04(chan, NvSubImageBlit, 0x0120, 3); - OUT_RING(chan, 0); - OUT_RING(chan, 1); - OUT_RING(chan, 2); + PUSH_NVSQ(push, NV05F, 0x0000, nfbdev->blit.handle); + PUSH_NVSQ(push, NV05F, 0x019c, nfbdev->surf2d.handle); + PUSH_NVSQ(push, NV05F, 0x02fc, 3); + if (nfbdev->blit.oclass == 0x009f) { + PUSH_NVSQ(push, NV09F, 0x0120, 0, + 0x0124, 1, + 0x0128, 2); } - BEGIN_NV04(chan, NvSubGdiRect, 0x0000, 1); - OUT_RING(chan, nfbdev->gdi.handle); - BEGIN_NV04(chan, NvSubGdiRect, 0x0198, 1); - OUT_RING(chan, nfbdev->surf2d.handle); - BEGIN_NV04(chan, NvSubGdiRect, 0x0188, 2); - OUT_RING(chan, nfbdev->patt.handle); - OUT_RING(chan, nfbdev->rop.handle); - BEGIN_NV04(chan, NvSubGdiRect, 0x0304, 1); - OUT_RING(chan, 1); - BEGIN_NV04(chan, NvSubGdiRect, 0x0300, 1); - OUT_RING(chan, rect_fmt); - BEGIN_NV04(chan, NvSubGdiRect, 0x02fc, 1); - OUT_RING(chan, 3); - - FIRE_RING(chan); + PUSH_NVSQ(push, NV04A, 0x0000, nfbdev->gdi.handle); + PUSH_NVSQ(push, NV04A, 0x0198, nfbdev->surf2d.handle); + PUSH_NVSQ(push, NV04A, 0x0188, nfbdev->patt.handle, + 0x018c, nfbdev->rop.handle); + PUSH_NVSQ(push, NV04A, 0x0304, 1); + PUSH_NVSQ(push, NV04A, 0x0300, rect_fmt); + PUSH_NVSQ(push, NV04A, 0x02fc, 3); + PUSH_KICK(push); return 0; } diff --git a/drivers/gpu/drm/nouveau/nv50_fbcon.c b/drivers/gpu/drm/nouveau/nv50_fbcon.c index 31d8dca54f9f..36348f72ecb3 100644 --- a/drivers/gpu/drm/nouveau/nv50_fbcon.c +++ b/drivers/gpu/drm/nouveau/nv50_fbcon.c @@ -21,12 +21,14 @@ * * Authors: Ben Skeggs */ - +#define NVIF_DEBUG_PRINT_DISABLE #include "nouveau_drv.h" #include "nouveau_dma.h" #include "nouveau_fbcon.h" #include "nouveau_vmm.h" +#include + int nv50_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect) { @@ -152,6 +154,7 @@ nv50_fbcon_accel_init(struct fb_info *info) struct drm_device *dev = nfbdev->helper.dev; struct nouveau_drm *drm = nouveau_drm(dev); struct nouveau_channel *chan = drm->channel; + struct nvif_push *push = chan->chan.push; int ret, format; switch (info->var.bits_per_pixel) { @@ -186,72 +189,60 @@ nv50_fbcon_accel_init(struct fb_info *info) if (ret) return ret; - ret = RING_SPACE(chan, 58); + ret = PUSH_WAIT(push, 56); if (ret) { nouveau_fbcon_gpu_lockup(info); return ret; } - BEGIN_NV04(chan, NvSub2D, 0x0000, 1); - OUT_RING(chan, nfbdev->twod.handle); - BEGIN_NV04(chan, NvSub2D, 0x0184, 3); - OUT_RING(chan, chan->vram.handle); - OUT_RING(chan, chan->vram.handle); - OUT_RING(chan, chan->vram.handle); - BEGIN_NV04(chan, NvSub2D, 0x0290, 1); - OUT_RING(chan, 0); - BEGIN_NV04(chan, NvSub2D, 0x0888, 1); - OUT_RING(chan, 1); - BEGIN_NV04(chan, NvSub2D, 0x02ac, 1); - OUT_RING(chan, 3); - BEGIN_NV04(chan, NvSub2D, 0x02a0, 1); - OUT_RING(chan, 0x55); - BEGIN_NV04(chan, NvSub2D, 0x08c0, 4); - OUT_RING(chan, 0); - OUT_RING(chan, 1); - OUT_RING(chan, 0); - OUT_RING(chan, 1); - BEGIN_NV04(chan, NvSub2D, 0x0580, 2); - OUT_RING(chan, 4); - OUT_RING(chan, format); - BEGIN_NV04(chan, NvSub2D, 0x02e8, 2); - OUT_RING(chan, 2); - OUT_RING(chan, 1); - BEGIN_NV04(chan, NvSub2D, 0x0804, 1); - OUT_RING(chan, format); - BEGIN_NV04(chan, NvSub2D, 0x0800, 1); - OUT_RING(chan, 1); - BEGIN_NV04(chan, NvSub2D, 0x0808, 3); - OUT_RING(chan, 0); - OUT_RING(chan, 0); - OUT_RING(chan, 1); - BEGIN_NV04(chan, NvSub2D, 0x081c, 1); - OUT_RING(chan, 1); - BEGIN_NV04(chan, NvSub2D, 0x0840, 4); - OUT_RING(chan, 0); - OUT_RING(chan, 1); - OUT_RING(chan, 0); - OUT_RING(chan, 1); - BEGIN_NV04(chan, NvSub2D, 0x0200, 2); - OUT_RING(chan, format); - OUT_RING(chan, 1); - BEGIN_NV04(chan, NvSub2D, 0x0214, 5); - OUT_RING(chan, info->fix.line_length); - OUT_RING(chan, info->var.xres_virtual); - OUT_RING(chan, info->var.yres_virtual); - OUT_RING(chan, upper_32_bits(nfbdev->vma->addr)); - OUT_RING(chan, lower_32_bits(nfbdev->vma->addr)); - BEGIN_NV04(chan, NvSub2D, 0x0230, 2); - OUT_RING(chan, format); - OUT_RING(chan, 1); - BEGIN_NV04(chan, NvSub2D, 0x0244, 5); - OUT_RING(chan, info->fix.line_length); - OUT_RING(chan, info->var.xres_virtual); - OUT_RING(chan, info->var.yres_virtual); - OUT_RING(chan, upper_32_bits(nfbdev->vma->addr)); - OUT_RING(chan, lower_32_bits(nfbdev->vma->addr)); - FIRE_RING(chan); + PUSH_NVSQ(push, NV502D, 0x0000, nfbdev->twod.handle); + PUSH_NVSQ(push, NV502D, 0x0184, chan->vram.handle, + 0x0188, chan->vram.handle, + 0x018c, chan->vram.handle); + PUSH_NVSQ(push, NV502D, 0x0200, format, + 0x0204, 1); + PUSH_NVSQ(push, NV502D, 0x0214, info->fix.line_length, + 0x0218, info->var.xres_virtual, + 0x021c, info->var.yres_virtual, + 0x0220, upper_32_bits(nfbdev->vma->addr), + 0x0224, lower_32_bits(nfbdev->vma->addr)); + + PUSH_NVSQ(push, NV502D, 0x0230, format, + 0x0234, 1); + PUSH_NVSQ(push, NV502D, 0x0244, info->fix.line_length, + 0x0248, info->var.xres_virtual, + 0x024c, info->var.yres_virtual, + 0x0250, upper_32_bits(nfbdev->vma->addr), + 0x0254, lower_32_bits(nfbdev->vma->addr)); + + PUSH_NVSQ(push, NV502D, 0x0290, 0); + PUSH_NVSQ(push, NV502D, 0x02a0, 0x55); + PUSH_NVSQ(push, NV502D, 0x02ac, 3); + PUSH_NVSQ(push, NV502D, 0x02e8, 2, + 0x02ec, 1); + + PUSH_NVSQ(push, NV502D, 0X0580, 4, + 0x0584, format); + + PUSH_NVSQ(push, NV502D, 0x0800, 1, + 0x0804, format, + 0x0808, 0, + 0x080c, 0, + 0x0810, 1); + PUSH_NVSQ(push, NV502D, 0x081c, 1); + PUSH_NVSQ(push, NV502D, 0x0840, 0, + 0x0844, 1, + 0x0848, 0, + 0x084c, 1); + + PUSH_NVSQ(push, NV502D, 0x0888, 1); + PUSH_NVSQ(push, NV502D, 0x08c0, 0, + 0x08c4, 1, + 0x08c8, 0, + 0x08cc, 1); + + PUSH_KICK(push); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvc0_fbcon.c b/drivers/gpu/drm/nouveau/nvc0_fbcon.c index d6ce6323bf41..2d213c365a43 100644 --- a/drivers/gpu/drm/nouveau/nvc0_fbcon.c +++ b/drivers/gpu/drm/nouveau/nvc0_fbcon.c @@ -21,12 +21,14 @@ * * Authors: Ben Skeggs */ - +#define NVIF_DEBUG_PRINT_DISABLE #include "nouveau_drv.h" #include "nouveau_dma.h" #include "nouveau_fbcon.h" #include "nouveau_vmm.h" +#include + int nvc0_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect) { @@ -152,6 +154,7 @@ nvc0_fbcon_accel_init(struct fb_info *info) struct drm_device *dev = nfbdev->helper.dev; struct nouveau_drm *drm = nouveau_drm(dev); struct nouveau_channel *chan = drm->channel; + struct nvif_push *push = chan->chan.push; int ret, format; ret = nvif_object_ctor(&chan->user, "fbconTwoD", 0x902d, 0x902d, @@ -186,74 +189,58 @@ nvc0_fbcon_accel_init(struct fb_info *info) return -EINVAL; } - ret = RING_SPACE(chan, 58); + ret = PUSH_WAIT(push, 52); if (ret) { WARN_ON(1); nouveau_fbcon_gpu_lockup(info); return ret; } - BEGIN_NVC0(chan, NvSub2D, 0x0000, 1); - OUT_RING (chan, nfbdev->twod.handle); - BEGIN_NVC0(chan, NvSub2D, 0x0290, 1); - OUT_RING (chan, 0); - BEGIN_NVC0(chan, NvSub2D, 0x0888, 1); - OUT_RING (chan, 1); - BEGIN_NVC0(chan, NvSub2D, 0x02ac, 1); - OUT_RING (chan, 3); - BEGIN_NVC0(chan, NvSub2D, 0x02a0, 1); - OUT_RING (chan, 0x55); - BEGIN_NVC0(chan, NvSub2D, 0x08c0, 4); - OUT_RING (chan, 0); - OUT_RING (chan, 1); - OUT_RING (chan, 0); - OUT_RING (chan, 1); - BEGIN_NVC0(chan, NvSub2D, 0x0580, 2); - OUT_RING (chan, 4); - OUT_RING (chan, format); - BEGIN_NVC0(chan, NvSub2D, 0x02e8, 2); - OUT_RING (chan, 2); - OUT_RING (chan, 1); + PUSH_NVSQ(push, NV902D, 0x0000, nfbdev->twod.handle); - BEGIN_NVC0(chan, NvSub2D, 0x0804, 1); - OUT_RING (chan, format); - BEGIN_NVC0(chan, NvSub2D, 0x0800, 1); - OUT_RING (chan, 1); - BEGIN_NVC0(chan, NvSub2D, 0x0808, 3); - OUT_RING (chan, 0); - OUT_RING (chan, 0); - OUT_RING (chan, 1); - BEGIN_NVC0(chan, NvSub2D, 0x081c, 1); - OUT_RING (chan, 1); - BEGIN_NVC0(chan, NvSub2D, 0x0840, 4); - OUT_RING (chan, 0); - OUT_RING (chan, 1); - OUT_RING (chan, 0); - OUT_RING (chan, 1); - BEGIN_NVC0(chan, NvSub2D, 0x0200, 10); - OUT_RING (chan, format); - OUT_RING (chan, 1); - OUT_RING (chan, 0); - OUT_RING (chan, 1); - OUT_RING (chan, 0); - OUT_RING (chan, info->fix.line_length); - OUT_RING (chan, info->var.xres_virtual); - OUT_RING (chan, info->var.yres_virtual); - OUT_RING (chan, upper_32_bits(nfbdev->vma->addr)); - OUT_RING (chan, lower_32_bits(nfbdev->vma->addr)); - BEGIN_NVC0(chan, NvSub2D, 0x0230, 10); - OUT_RING (chan, format); - OUT_RING (chan, 1); - OUT_RING (chan, 0); - OUT_RING (chan, 1); - OUT_RING (chan, 0); - OUT_RING (chan, info->fix.line_length); - OUT_RING (chan, info->var.xres_virtual); - OUT_RING (chan, info->var.yres_virtual); - OUT_RING (chan, upper_32_bits(nfbdev->vma->addr)); - OUT_RING (chan, lower_32_bits(nfbdev->vma->addr)); - FIRE_RING (chan); + PUSH_NVSQ(push, NV902D, 0x0200, format, + 0x0204, 1); + PUSH_NVSQ(push, NV902D, 0x0214, info->fix.line_length, + 0x0218, info->var.xres_virtual, + 0x021c, info->var.yres_virtual, + 0x0220, upper_32_bits(nfbdev->vma->addr), + 0x0224, lower_32_bits(nfbdev->vma->addr)); + PUSH_NVSQ(push, NV902D, 0x0230, format, + 0x0234, 1); + PUSH_NVSQ(push, NV902D, 0x0244, info->fix.line_length, + 0x0248, info->var.xres_virtual, + 0x024c, info->var.yres_virtual, + 0x0250, upper_32_bits(nfbdev->vma->addr), + 0x0254, lower_32_bits(nfbdev->vma->addr)); + + PUSH_NVIM(push, NV902D, 0x0290, 0); + PUSH_NVIM(push, NV902D, 0x02a0, 0x55); + PUSH_NVIM(push, NV902D, 0x02ac, 3); + PUSH_NVSQ(push, NV902D, 0x02e8, 2, + 0x02ec, 1); + + PUSH_NVSQ(push, NV902D, 0X0580, 4, + 0x0584, format); + + PUSH_NVSQ(push, NV902D, 0x0800, 1, + 0x0804, format, + 0x0808, 0, + 0x080c, 0, + 0x0810, 1); + PUSH_NVIM(push, NV902D, 0x081c, 1); + PUSH_NVSQ(push, NV902D, 0x0840, 0, + 0x0844, 1, + 0x0848, 0, + 0x084c, 1); + + PUSH_NVIM(push, NV902D, 0x0888, 1); + PUSH_NVSQ(push, NV902D, 0x08c0, 0, + 0x08c4, 1, + 0x08c8, 0, + 0x08cc, 1); + + PUSH_KICK(push); return 0; } From 1d04a64a0a7a0ae5162ce42f27cfad37f6bc60ee Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 22 Jun 2020 11:22:28 +1000 Subject: [PATCH 077/145] drm/nouveau/fbcon: convert imageblit() to new push macros Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/nouveau_dma.c | 13 ------- drivers/gpu/drm/nouveau/nouveau_dma.h | 15 -------- drivers/gpu/drm/nouveau/nv04_fbcon.c | 27 +++++++------- drivers/gpu/drm/nouveau/nv50_fbcon.c | 52 +++++++++++++-------------- drivers/gpu/drm/nouveau/nvc0_fbcon.c | 52 +++++++++++++-------------- 5 files changed, 65 insertions(+), 94 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nouveau_dma.c b/drivers/gpu/drm/nouveau/nouveau_dma.c index 3c430a550a51..ddb75d80bc53 100644 --- a/drivers/gpu/drm/nouveau/nouveau_dma.c +++ b/drivers/gpu/drm/nouveau/nouveau_dma.c @@ -30,19 +30,6 @@ #include -void -OUT_RINGp(struct nouveau_channel *chan, const void *data, unsigned nr_dwords) -{ - bool is_iomem; - u32 *mem = ttm_kmap_obj_virtual(&chan->push.buffer->kmap, &is_iomem); - mem = &mem[chan->dma.cur]; - if (is_iomem) - memcpy_toio((void __force __iomem *)mem, data, nr_dwords * 4); - else - memcpy(mem, data, nr_dwords * 4); - chan->dma.cur += nr_dwords; -} - /* Fetch and adjust GPU GET pointer * * Returns: diff --git a/drivers/gpu/drm/nouveau/nouveau_dma.h b/drivers/gpu/drm/nouveau/nouveau_dma.h index d00cf7bd220c..edc5a3b722e6 100644 --- a/drivers/gpu/drm/nouveau/nouveau_dma.h +++ b/drivers/gpu/drm/nouveau/nouveau_dma.h @@ -101,33 +101,18 @@ OUT_RING(struct nouveau_channel *chan, int data) nouveau_bo_wr32(chan->push.buffer, chan->dma.cur++, data); } -extern void -OUT_RINGp(struct nouveau_channel *chan, const void *data, unsigned nr_dwords); - static inline void BEGIN_NV04(struct nouveau_channel *chan, int subc, int mthd, int size) { OUT_RING(chan, 0x00000000 | (subc << 13) | (size << 18) | mthd); } -static inline void -BEGIN_NI04(struct nouveau_channel *chan, int subc, int mthd, int size) -{ - OUT_RING(chan, 0x40000000 | (subc << 13) | (size << 18) | mthd); -} - static inline void BEGIN_NVC0(struct nouveau_channel *chan, int subc, int mthd, int size) { OUT_RING(chan, 0x20000000 | (size << 16) | (subc << 13) | (mthd >> 2)); } -static inline void -BEGIN_NIC0(struct nouveau_channel *chan, int subc, int mthd, int size) -{ - OUT_RING(chan, 0x60000000 | (size << 16) | (subc << 13) | (mthd >> 2)); -} - static inline void BEGIN_IMC0(struct nouveau_channel *chan, int subc, int mthd, u16 data) { diff --git a/drivers/gpu/drm/nouveau/nv04_fbcon.c b/drivers/gpu/drm/nouveau/nv04_fbcon.c index a254e5f7fad1..91be0d1827c3 100644 --- a/drivers/gpu/drm/nouveau/nv04_fbcon.c +++ b/drivers/gpu/drm/nouveau/nv04_fbcon.c @@ -81,6 +81,7 @@ nv04_fbcon_imageblit(struct fb_info *info, const struct fb_image *image) struct nouveau_fbdev *nfbdev = info->par; struct nouveau_drm *drm = nouveau_drm(nfbdev->helper.dev); struct nouveau_channel *chan = drm->channel; + struct nvif_push *push = chan->chan.push; uint32_t fg; uint32_t bg; uint32_t dsize; @@ -90,7 +91,7 @@ nv04_fbcon_imageblit(struct fb_info *info, const struct fb_image *image) if (image->depth != 1) return -ENODEV; - ret = RING_SPACE(chan, 8); + ret = PUSH_WAIT(push, 8); if (ret) return ret; @@ -103,31 +104,29 @@ nv04_fbcon_imageblit(struct fb_info *info, const struct fb_image *image) bg = image->bg_color; } - BEGIN_NV04(chan, NvSubGdiRect, 0x0be4, 7); - OUT_RING(chan, (image->dy << 16) | (image->dx & 0xffff)); - OUT_RING(chan, ((image->dy + image->height) << 16) | - ((image->dx + image->width) & 0xffff)); - OUT_RING(chan, bg); - OUT_RING(chan, fg); - OUT_RING(chan, (image->height << 16) | ALIGN(image->width, 8)); - OUT_RING(chan, (image->height << 16) | image->width); - OUT_RING(chan, (image->dy << 16) | (image->dx & 0xffff)); + PUSH_NVSQ(push, NV04A, 0x0be4, (image->dy << 16) | (image->dx & 0xffff), + 0x0be8, ((image->dy + image->height) << 16) | + ((image->dx + image->width) & 0xffff), + 0x0bec, bg, + 0x0bf0, fg, + 0x0bf4, (image->height << 16) | ALIGN(image->width, 8), + 0x0bf8, (image->height << 16) | image->width, + 0x0bfc, (image->dy << 16) | (image->dx & 0xffff)); dsize = ALIGN(ALIGN(image->width, 8) * image->height, 32) >> 5; while (dsize) { int iter_len = dsize > 128 ? 128 : dsize; - ret = RING_SPACE(chan, iter_len + 1); + ret = PUSH_WAIT(push, iter_len + 1); if (ret) return ret; - BEGIN_NV04(chan, NvSubGdiRect, 0x0c00, iter_len); - OUT_RINGp(chan, data, iter_len); + PUSH_NVSQ(push, NV04A, 0x0c00, data, iter_len); data += iter_len; dsize -= iter_len; } - FIRE_RING(chan); + PUSH_KICK(push); return 0; } diff --git a/drivers/gpu/drm/nouveau/nv50_fbcon.c b/drivers/gpu/drm/nouveau/nv50_fbcon.c index 36348f72ecb3..dd20485e38d9 100644 --- a/drivers/gpu/drm/nouveau/nv50_fbcon.c +++ b/drivers/gpu/drm/nouveau/nv50_fbcon.c @@ -98,52 +98,52 @@ nv50_fbcon_imageblit(struct fb_info *info, const struct fb_image *image) struct nouveau_fbdev *nfbdev = info->par; struct nouveau_drm *drm = nouveau_drm(nfbdev->helper.dev); struct nouveau_channel *chan = drm->channel; + struct nvif_push *push = chan->chan.push; uint32_t dwords, *data = (uint32_t *)image->data; uint32_t mask = ~(~0 >> (32 - info->var.bits_per_pixel)); - uint32_t *palette = info->pseudo_palette; + uint32_t *palette = info->pseudo_palette, bg, fg; int ret; if (image->depth != 1) return -ENODEV; - ret = RING_SPACE(chan, 11); + if (info->fix.visual == FB_VISUAL_TRUECOLOR || + info->fix.visual == FB_VISUAL_DIRECTCOLOR) { + bg = palette[image->bg_color] | mask; + fg = palette[image->fg_color] | mask; + } else { + bg = image->bg_color; + fg = image->fg_color; + } + + ret = PUSH_WAIT(push, 11); if (ret) return ret; - BEGIN_NV04(chan, NvSub2D, 0x0814, 2); - if (info->fix.visual == FB_VISUAL_TRUECOLOR || - info->fix.visual == FB_VISUAL_DIRECTCOLOR) { - OUT_RING(chan, palette[image->bg_color] | mask); - OUT_RING(chan, palette[image->fg_color] | mask); - } else { - OUT_RING(chan, image->bg_color); - OUT_RING(chan, image->fg_color); - } - BEGIN_NV04(chan, NvSub2D, 0x0838, 2); - OUT_RING(chan, image->width); - OUT_RING(chan, image->height); - BEGIN_NV04(chan, NvSub2D, 0x0850, 4); - OUT_RING(chan, 0); - OUT_RING(chan, image->dx); - OUT_RING(chan, 0); - OUT_RING(chan, image->dy); + PUSH_NVSQ(push, NV502D, 0x0814, bg, + 0x0818, fg); + PUSH_NVSQ(push, NV502D, 0x0838, image->width, + 0x083c, image->height); + PUSH_NVSQ(push, NV502D, 0x0850, 0, + 0x0854, image->dx, + 0x0858, 0, + 0x085c, image->dy); dwords = ALIGN(ALIGN(image->width, 8) * image->height, 32) >> 5; while (dwords) { - int push = dwords > 2047 ? 2047 : dwords; + int count = dwords > 2047 ? 2047 : dwords; - ret = RING_SPACE(chan, push + 1); + ret = PUSH_WAIT(push, count + 1); if (ret) return ret; - dwords -= push; + dwords -= count; - BEGIN_NI04(chan, NvSub2D, 0x0860, push); - OUT_RINGp(chan, data, push); - data += push; + PUSH_NVNI(push, NV502D, 0x0860, data, count); + data += count; } - FIRE_RING(chan); + PUSH_KICK(push); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvc0_fbcon.c b/drivers/gpu/drm/nouveau/nvc0_fbcon.c index 2d213c365a43..ae88f6683f62 100644 --- a/drivers/gpu/drm/nouveau/nvc0_fbcon.c +++ b/drivers/gpu/drm/nouveau/nvc0_fbcon.c @@ -98,52 +98,52 @@ nvc0_fbcon_imageblit(struct fb_info *info, const struct fb_image *image) struct nouveau_fbdev *nfbdev = info->par; struct nouveau_drm *drm = nouveau_drm(nfbdev->helper.dev); struct nouveau_channel *chan = drm->channel; + struct nvif_push *push = chan->chan.push; uint32_t dwords, *data = (uint32_t *)image->data; uint32_t mask = ~(~0 >> (32 - info->var.bits_per_pixel)); - uint32_t *palette = info->pseudo_palette; + uint32_t *palette = info->pseudo_palette, bg, fg; int ret; if (image->depth != 1) return -ENODEV; - ret = RING_SPACE(chan, 11); + if (info->fix.visual == FB_VISUAL_TRUECOLOR || + info->fix.visual == FB_VISUAL_DIRECTCOLOR) { + bg = palette[image->bg_color] | mask; + fg = palette[image->fg_color] | mask; + } else { + bg = image->bg_color; + fg = image->fg_color; + } + + ret = PUSH_WAIT(push, 11); if (ret) return ret; - BEGIN_NVC0(chan, NvSub2D, 0x0814, 2); - if (info->fix.visual == FB_VISUAL_TRUECOLOR || - info->fix.visual == FB_VISUAL_DIRECTCOLOR) { - OUT_RING (chan, palette[image->bg_color] | mask); - OUT_RING (chan, palette[image->fg_color] | mask); - } else { - OUT_RING (chan, image->bg_color); - OUT_RING (chan, image->fg_color); - } - BEGIN_NVC0(chan, NvSub2D, 0x0838, 2); - OUT_RING (chan, image->width); - OUT_RING (chan, image->height); - BEGIN_NVC0(chan, NvSub2D, 0x0850, 4); - OUT_RING (chan, 0); - OUT_RING (chan, image->dx); - OUT_RING (chan, 0); - OUT_RING (chan, image->dy); + PUSH_NVSQ(push, NV902D, 0x0814, bg, + 0x0818, fg); + PUSH_NVSQ(push, NV902D, 0x0838, image->width, + 0x083c, image->height); + PUSH_NVSQ(push, NV902D, 0x0850, 0, + 0x0854, image->dx, + 0x0858, 0, + 0x085c, image->dy); dwords = ALIGN(ALIGN(image->width, 8) * image->height, 32) >> 5; while (dwords) { - int push = dwords > 2047 ? 2047 : dwords; + int count = dwords > 2047 ? 2047 : dwords; - ret = RING_SPACE(chan, push + 1); + ret = PUSH_WAIT(push, count + 1); if (ret) return ret; - dwords -= push; + dwords -= count; - BEGIN_NIC0(chan, NvSub2D, 0x0860, push); - OUT_RINGp(chan, data, push); - data += push; + PUSH_NVNI(push, NV902D, 0x0860, data, count); + data += count; } - FIRE_RING(chan); + PUSH_KICK(push); return 0; } From 9ec525729f59e2885e6f06f6c1cd56665d519b1b Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 22 Jun 2020 11:31:56 +1000 Subject: [PATCH 078/145] drm/nouveau/fbcon: convert fillrect() to new push macros Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/nouveau_dma.h | 1 - drivers/gpu/drm/nouveau/nv04_fbcon.c | 18 ++++++------- drivers/gpu/drm/nouveau/nv50_fbcon.c | 37 +++++++++++++++------------ drivers/gpu/drm/nouveau/nvc0_fbcon.c | 37 +++++++++++++++------------ 4 files changed, 48 insertions(+), 45 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nouveau_dma.h b/drivers/gpu/drm/nouveau/nouveau_dma.h index edc5a3b722e6..bb1b89adaf73 100644 --- a/drivers/gpu/drm/nouveau/nouveau_dma.h +++ b/drivers/gpu/drm/nouveau/nouveau_dma.h @@ -49,7 +49,6 @@ void nv50_dma_push(struct nouveau_channel *, u64 addr, int length); enum { NvSubSw = 1, NvSubImageBlit = 2, - NvSubGdiRect = 3, NvSub2D = 3, /* DO NOT CHANGE - hardcoded for kepler gr fifo */ NvSubCopy = 4, /* DO NOT CHANGE - hardcoded for kepler gr fifo */ diff --git a/drivers/gpu/drm/nouveau/nv04_fbcon.c b/drivers/gpu/drm/nouveau/nv04_fbcon.c index 91be0d1827c3..397dd1799613 100644 --- a/drivers/gpu/drm/nouveau/nv04_fbcon.c +++ b/drivers/gpu/drm/nouveau/nv04_fbcon.c @@ -54,24 +54,22 @@ nv04_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect) struct nouveau_fbdev *nfbdev = info->par; struct nouveau_drm *drm = nouveau_drm(nfbdev->helper.dev); struct nouveau_channel *chan = drm->channel; + struct nvif_push *push = chan->chan.push; int ret; - ret = RING_SPACE(chan, 7); + ret = PUSH_WAIT(push, 7); if (ret) return ret; - BEGIN_NV04(chan, NvSubGdiRect, 0x02fc, 1); - OUT_RING(chan, (rect->rop != ROP_COPY) ? 1 : 3); - BEGIN_NV04(chan, NvSubGdiRect, 0x03fc, 1); + PUSH_NVSQ(push, NV04A, 0x02fc, (rect->rop != ROP_COPY) ? 1 : 3); if (info->fix.visual == FB_VISUAL_TRUECOLOR || info->fix.visual == FB_VISUAL_DIRECTCOLOR) - OUT_RING(chan, ((uint32_t *)info->pseudo_palette)[rect->color]); + PUSH_NVSQ(push, NV04A, 0x03fc, ((uint32_t *)info->pseudo_palette)[rect->color]); else - OUT_RING(chan, rect->color); - BEGIN_NV04(chan, NvSubGdiRect, 0x0400, 2); - OUT_RING(chan, (rect->dx << 16) | rect->dy); - OUT_RING(chan, (rect->width << 16) | rect->height); - FIRE_RING(chan); + PUSH_NVSQ(push, NV04A, 0x03fc, rect->color); + PUSH_NVSQ(push, NV04A, 0x0400, (rect->dx << 16) | rect->dy, + 0x0404, (rect->width << 16) | rect->height); + PUSH_KICK(push); return 0; } diff --git a/drivers/gpu/drm/nouveau/nv50_fbcon.c b/drivers/gpu/drm/nouveau/nv50_fbcon.c index dd20485e38d9..6d122b045f4c 100644 --- a/drivers/gpu/drm/nouveau/nv50_fbcon.c +++ b/drivers/gpu/drm/nouveau/nv50_fbcon.c @@ -35,32 +35,35 @@ nv50_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect) struct nouveau_fbdev *nfbdev = info->par; struct nouveau_drm *drm = nouveau_drm(nfbdev->helper.dev); struct nouveau_channel *chan = drm->channel; + struct nvif_push *push = chan->chan.push; + u32 colour; int ret; - ret = RING_SPACE(chan, rect->rop == ROP_COPY ? 7 : 11); + if (info->fix.visual == FB_VISUAL_TRUECOLOR || + info->fix.visual == FB_VISUAL_DIRECTCOLOR) + colour = ((uint32_t *)info->pseudo_palette)[rect->color]; + else + colour = rect->color; + + ret = PUSH_WAIT(push, rect->rop == ROP_COPY ? 7 : 11); if (ret) return ret; if (rect->rop != ROP_COPY) { - BEGIN_NV04(chan, NvSub2D, 0x02ac, 1); - OUT_RING(chan, 1); + PUSH_NVSQ(push, NV502D, 0x02ac, 1); } - BEGIN_NV04(chan, NvSub2D, 0x0588, 1); - if (info->fix.visual == FB_VISUAL_TRUECOLOR || - info->fix.visual == FB_VISUAL_DIRECTCOLOR) - OUT_RING(chan, ((uint32_t *)info->pseudo_palette)[rect->color]); - else - OUT_RING(chan, rect->color); - BEGIN_NV04(chan, NvSub2D, 0x0600, 4); - OUT_RING(chan, rect->dx); - OUT_RING(chan, rect->dy); - OUT_RING(chan, rect->dx + rect->width); - OUT_RING(chan, rect->dy + rect->height); + + PUSH_NVSQ(push, NV502D, 0x0588, colour); + PUSH_NVSQ(push, NV502D, 0x0600, rect->dx, + 0x0604, rect->dy, + 0x0608, rect->dx + rect->width, + 0x060c, rect->dy + rect->height); + if (rect->rop != ROP_COPY) { - BEGIN_NV04(chan, NvSub2D, 0x02ac, 1); - OUT_RING(chan, 3); + PUSH_NVSQ(push, NV502D, 0x02ac, 3); } - FIRE_RING(chan); + + PUSH_KICK(push); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvc0_fbcon.c b/drivers/gpu/drm/nouveau/nvc0_fbcon.c index ae88f6683f62..414025a43540 100644 --- a/drivers/gpu/drm/nouveau/nvc0_fbcon.c +++ b/drivers/gpu/drm/nouveau/nvc0_fbcon.c @@ -35,32 +35,35 @@ nvc0_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect) struct nouveau_fbdev *nfbdev = info->par; struct nouveau_drm *drm = nouveau_drm(nfbdev->helper.dev); struct nouveau_channel *chan = drm->channel; + struct nvif_push *push = chan->chan.push; + u32 colour; int ret; - ret = RING_SPACE(chan, rect->rop == ROP_COPY ? 7 : 11); + if (info->fix.visual == FB_VISUAL_TRUECOLOR || + info->fix.visual == FB_VISUAL_DIRECTCOLOR) + colour = ((uint32_t *)info->pseudo_palette)[rect->color]; + else + colour = rect->color; + + ret = PUSH_WAIT(push, rect->rop == ROP_COPY ? 7 : 9); if (ret) return ret; if (rect->rop != ROP_COPY) { - BEGIN_NVC0(chan, NvSub2D, 0x02ac, 1); - OUT_RING (chan, 1); + PUSH_NVIM(push, NV902D, 0x02ac, 1); } - BEGIN_NVC0(chan, NvSub2D, 0x0588, 1); - if (info->fix.visual == FB_VISUAL_TRUECOLOR || - info->fix.visual == FB_VISUAL_DIRECTCOLOR) - OUT_RING (chan, ((uint32_t *)info->pseudo_palette)[rect->color]); - else - OUT_RING (chan, rect->color); - BEGIN_NVC0(chan, NvSub2D, 0x0600, 4); - OUT_RING (chan, rect->dx); - OUT_RING (chan, rect->dy); - OUT_RING (chan, rect->dx + rect->width); - OUT_RING (chan, rect->dy + rect->height); + + PUSH_NVSQ(push, NV902D, 0x0588, colour); + PUSH_NVSQ(push, NV902D, 0x0600, rect->dx, + 0x0604, rect->dy, + 0x0608, rect->dx + rect->width, + 0x060c, rect->dy + rect->height); + if (rect->rop != ROP_COPY) { - BEGIN_NVC0(chan, NvSub2D, 0x02ac, 1); - OUT_RING (chan, 3); + PUSH_NVIM(push, NV902D, 0x02ac, 3); } - FIRE_RING(chan); + + PUSH_KICK(push); return 0; } From a535aa677521f63acbca3804ae42e062a912add0 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 22 Jun 2020 11:31:45 +1000 Subject: [PATCH 079/145] drm/nouveau/fbcon: convert copyarea() to new push macros Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/nouveau_dma.h | 1 - drivers/gpu/drm/nouveau/nv04_fbcon.c | 12 ++++++------ drivers/gpu/drm/nouveau/nv50_fbcon.c | 26 ++++++++++++-------------- drivers/gpu/drm/nouveau/nvc0_fbcon.c | 26 ++++++++++++-------------- 4 files changed, 30 insertions(+), 35 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nouveau_dma.h b/drivers/gpu/drm/nouveau/nouveau_dma.h index bb1b89adaf73..72de20437542 100644 --- a/drivers/gpu/drm/nouveau/nouveau_dma.h +++ b/drivers/gpu/drm/nouveau/nouveau_dma.h @@ -50,7 +50,6 @@ enum { NvSubSw = 1, NvSubImageBlit = 2, - NvSub2D = 3, /* DO NOT CHANGE - hardcoded for kepler gr fifo */ NvSubCopy = 4, /* DO NOT CHANGE - hardcoded for kepler gr fifo */ }; diff --git a/drivers/gpu/drm/nouveau/nv04_fbcon.c b/drivers/gpu/drm/nouveau/nv04_fbcon.c index 397dd1799613..92f3fb6765ab 100644 --- a/drivers/gpu/drm/nouveau/nv04_fbcon.c +++ b/drivers/gpu/drm/nouveau/nv04_fbcon.c @@ -34,17 +34,17 @@ nv04_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *region) struct nouveau_fbdev *nfbdev = info->par; struct nouveau_drm *drm = nouveau_drm(nfbdev->helper.dev); struct nouveau_channel *chan = drm->channel; + struct nvif_push *push = chan->chan.push; int ret; - ret = RING_SPACE(chan, 4); + ret = PUSH_WAIT(push, 4); if (ret) return ret; - BEGIN_NV04(chan, NvSubImageBlit, 0x0300, 3); - OUT_RING(chan, (region->sy << 16) | region->sx); - OUT_RING(chan, (region->dy << 16) | region->dx); - OUT_RING(chan, (region->height << 16) | region->width); - FIRE_RING(chan); + PUSH_NVSQ(push, NV05F, 0x0300, (region->sy << 16) | region->sx, + 0x0304, (region->dy << 16) | region->dx, + 0x0308, (region->height << 16) | region->width); + PUSH_KICK(push); return 0; } diff --git a/drivers/gpu/drm/nouveau/nv50_fbcon.c b/drivers/gpu/drm/nouveau/nv50_fbcon.c index 6d122b045f4c..cbdd473acd9f 100644 --- a/drivers/gpu/drm/nouveau/nv50_fbcon.c +++ b/drivers/gpu/drm/nouveau/nv50_fbcon.c @@ -73,25 +73,23 @@ nv50_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *region) struct nouveau_fbdev *nfbdev = info->par; struct nouveau_drm *drm = nouveau_drm(nfbdev->helper.dev); struct nouveau_channel *chan = drm->channel; + struct nvif_push *push = chan->chan.push; int ret; - ret = RING_SPACE(chan, 12); + ret = PUSH_WAIT(push, 12); if (ret) return ret; - BEGIN_NV04(chan, NvSub2D, 0x0110, 1); - OUT_RING(chan, 0); - BEGIN_NV04(chan, NvSub2D, 0x08b0, 4); - OUT_RING(chan, region->dx); - OUT_RING(chan, region->dy); - OUT_RING(chan, region->width); - OUT_RING(chan, region->height); - BEGIN_NV04(chan, NvSub2D, 0x08d0, 4); - OUT_RING(chan, 0); - OUT_RING(chan, region->sx); - OUT_RING(chan, 0); - OUT_RING(chan, region->sy); - FIRE_RING(chan); + PUSH_NVSQ(push, NV502D, 0x0110, 0); + PUSH_NVSQ(push, NV502D, 0x08b0, region->dx, + 0x08b4, region->dy, + 0x08b8, region->width, + 0x08bc, region->height); + PUSH_NVSQ(push, NV502D, 0x08d0, 0, + 0x08d4, region->sx, + 0x08d8, 0, + 0x08dc, region->sy); + PUSH_KICK(push); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvc0_fbcon.c b/drivers/gpu/drm/nouveau/nvc0_fbcon.c index 414025a43540..ab1dbf03de7b 100644 --- a/drivers/gpu/drm/nouveau/nvc0_fbcon.c +++ b/drivers/gpu/drm/nouveau/nvc0_fbcon.c @@ -73,25 +73,23 @@ nvc0_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *region) struct nouveau_fbdev *nfbdev = info->par; struct nouveau_drm *drm = nouveau_drm(nfbdev->helper.dev); struct nouveau_channel *chan = drm->channel; + struct nvif_push *push = chan->chan.push; int ret; - ret = RING_SPACE(chan, 12); + ret = PUSH_WAIT(push, 11); if (ret) return ret; - BEGIN_NVC0(chan, NvSub2D, 0x0110, 1); - OUT_RING (chan, 0); - BEGIN_NVC0(chan, NvSub2D, 0x08b0, 4); - OUT_RING (chan, region->dx); - OUT_RING (chan, region->dy); - OUT_RING (chan, region->width); - OUT_RING (chan, region->height); - BEGIN_NVC0(chan, NvSub2D, 0x08d0, 4); - OUT_RING (chan, 0); - OUT_RING (chan, region->sx); - OUT_RING (chan, 0); - OUT_RING (chan, region->sy); - FIRE_RING(chan); + PUSH_NVIM(push, NV902D, 0x0110, 0); + PUSH_NVSQ(push, NV902D, 0x08b0, region->dx, + 0x08b4, region->dy, + 0x08b8, region->width, + 0x08bc, region->height); + PUSH_NVSQ(push, NV902D, 0x08d0, 0, + 0x08d4, region->sx, + 0x08d8, 0, + 0x08dc, region->sy); + PUSH_KICK(push); return 0; } From 8b9d5d63a7193156b6b397c4f5078efbc200695f Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 22 Jun 2020 15:37:19 +1000 Subject: [PATCH 080/145] drm/nouveau/bo: split buffer move functions into their own source files Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/Kbuild | 7 + drivers/gpu/drm/nouveau/nouveau_bo.c | 357 +---------------------- drivers/gpu/drm/nouveau/nouveau_bo.h | 31 +- drivers/gpu/drm/nouveau/nouveau_bo0039.c | 100 +++++++ drivers/gpu/drm/nouveau/nouveau_bo5039.c | 121 ++++++++ drivers/gpu/drm/nouveau/nouveau_bo74c1.c | 49 ++++ drivers/gpu/drm/nouveau/nouveau_bo85b5.c | 73 +++++ drivers/gpu/drm/nouveau/nouveau_bo9039.c | 81 +++++ drivers/gpu/drm/nouveau/nouveau_bo90b5.c | 66 +++++ drivers/gpu/drm/nouveau/nouveau_boa0b5.c | 64 ++++ 10 files changed, 591 insertions(+), 358 deletions(-) create mode 100644 drivers/gpu/drm/nouveau/nouveau_bo0039.c create mode 100644 drivers/gpu/drm/nouveau/nouveau_bo5039.c create mode 100644 drivers/gpu/drm/nouveau/nouveau_bo74c1.c create mode 100644 drivers/gpu/drm/nouveau/nouveau_bo85b5.c create mode 100644 drivers/gpu/drm/nouveau/nouveau_bo9039.c create mode 100644 drivers/gpu/drm/nouveau/nouveau_bo90b5.c create mode 100644 drivers/gpu/drm/nouveau/nouveau_boa0b5.c diff --git a/drivers/gpu/drm/nouveau/Kbuild b/drivers/gpu/drm/nouveau/Kbuild index 49e57fba4925..60586fb8275e 100644 --- a/drivers/gpu/drm/nouveau/Kbuild +++ b/drivers/gpu/drm/nouveau/Kbuild @@ -32,6 +32,13 @@ nouveau-y += nouveau_vga.o # DRM - memory management nouveau-y += nouveau_bo.o +nouveau-y += nouveau_bo0039.o +nouveau-y += nouveau_bo5039.o +nouveau-y += nouveau_bo74c1.o +nouveau-y += nouveau_bo85b5.o +nouveau-y += nouveau_bo9039.o +nouveau-y += nouveau_bo90b5.o +nouveau-y += nouveau_boa0b5.o nouveau-y += nouveau_gem.o nouveau-$(CONFIG_DRM_NOUVEAU_SVM) += nouveau_svm.o nouveau-$(CONFIG_DRM_NOUVEAU_SVM) += nouveau_dmem.o diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c index dea090c176ef..7806278dce57 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c @@ -31,7 +31,7 @@ #include #include "nouveau_drv.h" -#include "nouveau_dma.h" +#include "nouveau_chan.h" #include "nouveau_fence.h" #include "nouveau_bo.h" @@ -724,360 +724,6 @@ nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl) *pl = nvbo->placement; } - -static int -nve0_bo_move_init(struct nouveau_channel *chan, u32 handle) -{ - int ret = RING_SPACE(chan, 2); - if (ret == 0) { - BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1); - OUT_RING (chan, handle & 0x0000ffff); - FIRE_RING (chan); - } - return ret; -} - -static int -nve0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo, - struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) -{ - struct nouveau_mem *mem = nouveau_mem(old_reg); - int ret = RING_SPACE(chan, 10); - if (ret == 0) { - BEGIN_NVC0(chan, NvSubCopy, 0x0400, 8); - OUT_RING (chan, upper_32_bits(mem->vma[0].addr)); - OUT_RING (chan, lower_32_bits(mem->vma[0].addr)); - OUT_RING (chan, upper_32_bits(mem->vma[1].addr)); - OUT_RING (chan, lower_32_bits(mem->vma[1].addr)); - OUT_RING (chan, PAGE_SIZE); - OUT_RING (chan, PAGE_SIZE); - OUT_RING (chan, PAGE_SIZE); - OUT_RING (chan, new_reg->num_pages); - BEGIN_IMC0(chan, NvSubCopy, 0x0300, 0x0386); - } - return ret; -} - -static int -nvc0_bo_move_init(struct nouveau_channel *chan, u32 handle) -{ - int ret = RING_SPACE(chan, 2); - if (ret == 0) { - BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1); - OUT_RING (chan, handle); - } - return ret; -} - -static int -nvc0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo, - struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) -{ - struct nouveau_mem *mem = nouveau_mem(old_reg); - u64 src_offset = mem->vma[0].addr; - u64 dst_offset = mem->vma[1].addr; - u32 page_count = new_reg->num_pages; - int ret; - - page_count = new_reg->num_pages; - while (page_count) { - int line_count = (page_count > 8191) ? 8191 : page_count; - - ret = RING_SPACE(chan, 11); - if (ret) - return ret; - - BEGIN_NVC0(chan, NvSubCopy, 0x030c, 8); - OUT_RING (chan, upper_32_bits(src_offset)); - OUT_RING (chan, lower_32_bits(src_offset)); - OUT_RING (chan, upper_32_bits(dst_offset)); - OUT_RING (chan, lower_32_bits(dst_offset)); - OUT_RING (chan, PAGE_SIZE); - OUT_RING (chan, PAGE_SIZE); - OUT_RING (chan, PAGE_SIZE); - OUT_RING (chan, line_count); - BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1); - OUT_RING (chan, 0x00000110); - - page_count -= line_count; - src_offset += (PAGE_SIZE * line_count); - dst_offset += (PAGE_SIZE * line_count); - } - - return 0; -} - -static int -nvc0_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, - struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) -{ - struct nouveau_mem *mem = nouveau_mem(old_reg); - u64 src_offset = mem->vma[0].addr; - u64 dst_offset = mem->vma[1].addr; - u32 page_count = new_reg->num_pages; - int ret; - - page_count = new_reg->num_pages; - while (page_count) { - int line_count = (page_count > 2047) ? 2047 : page_count; - - ret = RING_SPACE(chan, 12); - if (ret) - return ret; - - BEGIN_NVC0(chan, NvSubCopy, 0x0238, 2); - OUT_RING (chan, upper_32_bits(dst_offset)); - OUT_RING (chan, lower_32_bits(dst_offset)); - BEGIN_NVC0(chan, NvSubCopy, 0x030c, 6); - OUT_RING (chan, upper_32_bits(src_offset)); - OUT_RING (chan, lower_32_bits(src_offset)); - OUT_RING (chan, PAGE_SIZE); /* src_pitch */ - OUT_RING (chan, PAGE_SIZE); /* dst_pitch */ - OUT_RING (chan, PAGE_SIZE); /* line_length */ - OUT_RING (chan, line_count); - BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1); - OUT_RING (chan, 0x00100110); - - page_count -= line_count; - src_offset += (PAGE_SIZE * line_count); - dst_offset += (PAGE_SIZE * line_count); - } - - return 0; -} - -static int -nva3_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo, - struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) -{ - struct nouveau_mem *mem = nouveau_mem(old_reg); - u64 src_offset = mem->vma[0].addr; - u64 dst_offset = mem->vma[1].addr; - u32 page_count = new_reg->num_pages; - int ret; - - page_count = new_reg->num_pages; - while (page_count) { - int line_count = (page_count > 8191) ? 8191 : page_count; - - ret = RING_SPACE(chan, 11); - if (ret) - return ret; - - BEGIN_NV04(chan, NvSubCopy, 0x030c, 8); - OUT_RING (chan, upper_32_bits(src_offset)); - OUT_RING (chan, lower_32_bits(src_offset)); - OUT_RING (chan, upper_32_bits(dst_offset)); - OUT_RING (chan, lower_32_bits(dst_offset)); - OUT_RING (chan, PAGE_SIZE); - OUT_RING (chan, PAGE_SIZE); - OUT_RING (chan, PAGE_SIZE); - OUT_RING (chan, line_count); - BEGIN_NV04(chan, NvSubCopy, 0x0300, 1); - OUT_RING (chan, 0x00000110); - - page_count -= line_count; - src_offset += (PAGE_SIZE * line_count); - dst_offset += (PAGE_SIZE * line_count); - } - - return 0; -} - -static int -nv98_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo, - struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) -{ - struct nouveau_mem *mem = nouveau_mem(old_reg); - int ret = RING_SPACE(chan, 7); - if (ret == 0) { - BEGIN_NV04(chan, NvSubCopy, 0x0320, 6); - OUT_RING (chan, upper_32_bits(mem->vma[0].addr)); - OUT_RING (chan, lower_32_bits(mem->vma[0].addr)); - OUT_RING (chan, upper_32_bits(mem->vma[1].addr)); - OUT_RING (chan, lower_32_bits(mem->vma[1].addr)); - OUT_RING (chan, 0x00000000 /* COPY */); - OUT_RING (chan, new_reg->num_pages << PAGE_SHIFT); - } - return ret; -} - -static int -nv84_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo, - struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) -{ - struct nouveau_mem *mem = nouveau_mem(old_reg); - int ret = RING_SPACE(chan, 7); - if (ret == 0) { - BEGIN_NV04(chan, NvSubCopy, 0x0304, 6); - OUT_RING (chan, new_reg->num_pages << PAGE_SHIFT); - OUT_RING (chan, upper_32_bits(mem->vma[0].addr)); - OUT_RING (chan, lower_32_bits(mem->vma[0].addr)); - OUT_RING (chan, upper_32_bits(mem->vma[1].addr)); - OUT_RING (chan, lower_32_bits(mem->vma[1].addr)); - OUT_RING (chan, 0x00000000 /* MODE_COPY, QUERY_NONE */); - } - return ret; -} - -static int -nv50_bo_move_init(struct nouveau_channel *chan, u32 handle) -{ - int ret = RING_SPACE(chan, 6); - if (ret == 0) { - BEGIN_NV04(chan, NvSubCopy, 0x0000, 1); - OUT_RING (chan, handle); - BEGIN_NV04(chan, NvSubCopy, 0x0180, 3); - OUT_RING (chan, chan->drm->ntfy.handle); - OUT_RING (chan, chan->vram.handle); - OUT_RING (chan, chan->vram.handle); - } - - return ret; -} - -static int -nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, - struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) -{ - struct nouveau_mem *mem = nouveau_mem(old_reg); - u64 length = (new_reg->num_pages << PAGE_SHIFT); - u64 src_offset = mem->vma[0].addr; - u64 dst_offset = mem->vma[1].addr; - int src_tiled = !!mem->kind; - int dst_tiled = !!nouveau_mem(new_reg)->kind; - int ret; - - while (length) { - u32 amount, stride, height; - - ret = RING_SPACE(chan, 18 + 6 * (src_tiled + dst_tiled)); - if (ret) - return ret; - - amount = min(length, (u64)(4 * 1024 * 1024)); - stride = 16 * 4; - height = amount / stride; - - if (src_tiled) { - BEGIN_NV04(chan, NvSubCopy, 0x0200, 7); - OUT_RING (chan, 0); - OUT_RING (chan, 0); - OUT_RING (chan, stride); - OUT_RING (chan, height); - OUT_RING (chan, 1); - OUT_RING (chan, 0); - OUT_RING (chan, 0); - } else { - BEGIN_NV04(chan, NvSubCopy, 0x0200, 1); - OUT_RING (chan, 1); - } - if (dst_tiled) { - BEGIN_NV04(chan, NvSubCopy, 0x021c, 7); - OUT_RING (chan, 0); - OUT_RING (chan, 0); - OUT_RING (chan, stride); - OUT_RING (chan, height); - OUT_RING (chan, 1); - OUT_RING (chan, 0); - OUT_RING (chan, 0); - } else { - BEGIN_NV04(chan, NvSubCopy, 0x021c, 1); - OUT_RING (chan, 1); - } - - BEGIN_NV04(chan, NvSubCopy, 0x0238, 2); - OUT_RING (chan, upper_32_bits(src_offset)); - OUT_RING (chan, upper_32_bits(dst_offset)); - BEGIN_NV04(chan, NvSubCopy, 0x030c, 8); - OUT_RING (chan, lower_32_bits(src_offset)); - OUT_RING (chan, lower_32_bits(dst_offset)); - OUT_RING (chan, stride); - OUT_RING (chan, stride); - OUT_RING (chan, stride); - OUT_RING (chan, height); - OUT_RING (chan, 0x00000101); - OUT_RING (chan, 0x00000000); - BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1); - OUT_RING (chan, 0); - - length -= amount; - src_offset += amount; - dst_offset += amount; - } - - return 0; -} - -static int -nv04_bo_move_init(struct nouveau_channel *chan, u32 handle) -{ - int ret = RING_SPACE(chan, 4); - if (ret == 0) { - BEGIN_NV04(chan, NvSubCopy, 0x0000, 1); - OUT_RING (chan, handle); - BEGIN_NV04(chan, NvSubCopy, 0x0180, 1); - OUT_RING (chan, chan->drm->ntfy.handle); - } - - return ret; -} - -static inline uint32_t -nouveau_bo_mem_ctxdma(struct ttm_buffer_object *bo, - struct nouveau_channel *chan, struct ttm_mem_reg *reg) -{ - if (reg->mem_type == TTM_PL_TT) - return NvDmaTT; - return chan->vram.handle; -} - -static int -nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, - struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) -{ - u32 src_offset = old_reg->start << PAGE_SHIFT; - u32 dst_offset = new_reg->start << PAGE_SHIFT; - u32 page_count = new_reg->num_pages; - int ret; - - ret = RING_SPACE(chan, 3); - if (ret) - return ret; - - BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE, 2); - OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, old_reg)); - OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, new_reg)); - - page_count = new_reg->num_pages; - while (page_count) { - int line_count = (page_count > 2047) ? 2047 : page_count; - - ret = RING_SPACE(chan, 11); - if (ret) - return ret; - - BEGIN_NV04(chan, NvSubCopy, - NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8); - OUT_RING (chan, src_offset); - OUT_RING (chan, dst_offset); - OUT_RING (chan, PAGE_SIZE); /* src_pitch */ - OUT_RING (chan, PAGE_SIZE); /* dst_pitch */ - OUT_RING (chan, PAGE_SIZE); /* line_length */ - OUT_RING (chan, line_count); - OUT_RING (chan, 0x00000101); - OUT_RING (chan, 0x00000000); - BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1); - OUT_RING (chan, 0); - - page_count -= line_count; - src_offset += (PAGE_SIZE * line_count); - dst_offset += (PAGE_SIZE * line_count); - } - - return 0; -} - static int nouveau_bo_move_prep(struct nouveau_drm *drm, struct ttm_buffer_object *bo, struct ttm_mem_reg *reg) @@ -1181,7 +827,6 @@ nouveau_bo_move_init(struct nouveau_drm *drm) { "M2MF", 0, 0x5039, nv50_bo_move_m2mf, nv50_bo_move_init }, { "M2MF", 0, 0x0039, nv04_bo_move_m2mf, nv04_bo_move_init }, {}, - { "CRYPT", 0, 0x88b4, nv98_bo_move_exec, nv50_bo_move_init }, }; const struct _method_table *mthd = _methods; const char *name = "CPU"; diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.h b/drivers/gpu/drm/nouveau/nouveau_bo.h index e944b4aa5547..951ef6fa76d8 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo.h +++ b/drivers/gpu/drm/nouveau/nouveau_bo.h @@ -1,12 +1,13 @@ /* SPDX-License-Identifier: MIT */ #ifndef __NOUVEAU_BO_H__ #define __NOUVEAU_BO_H__ - +#include #include struct nouveau_channel; +struct nouveau_cli; +struct nouveau_drm; struct nouveau_fence; -struct nvkm_vma; struct nouveau_bo { struct ttm_buffer_object bo; @@ -135,4 +136,30 @@ nouveau_bo_new_pin_map(struct nouveau_cli *cli, u64 size, int align, u32 flags, } return ret; } + +int nv04_bo_move_init(struct nouveau_channel *, u32); +int nv04_bo_move_m2mf(struct nouveau_channel *, struct ttm_buffer_object *, + struct ttm_mem_reg *, struct ttm_mem_reg *); + +int nv50_bo_move_init(struct nouveau_channel *, u32); +int nv50_bo_move_m2mf(struct nouveau_channel *, struct ttm_buffer_object *, + struct ttm_mem_reg *, struct ttm_mem_reg *); + +int nv84_bo_move_exec(struct nouveau_channel *, struct ttm_buffer_object *, + struct ttm_mem_reg *, struct ttm_mem_reg *); + +int nva3_bo_move_copy(struct nouveau_channel *, struct ttm_buffer_object *, + struct ttm_mem_reg *, struct ttm_mem_reg *); + +int nvc0_bo_move_init(struct nouveau_channel *, u32); +int nvc0_bo_move_m2mf(struct nouveau_channel *, struct ttm_buffer_object *, + struct ttm_mem_reg *, struct ttm_mem_reg *); + +int nvc0_bo_move_copy(struct nouveau_channel *, struct ttm_buffer_object *, + struct ttm_mem_reg *, struct ttm_mem_reg *); + +int nve0_bo_move_init(struct nouveau_channel *, u32); +int nve0_bo_move_copy(struct nouveau_channel *, struct ttm_buffer_object *, + struct ttm_mem_reg *, struct ttm_mem_reg *); + #endif diff --git a/drivers/gpu/drm/nouveau/nouveau_bo0039.c b/drivers/gpu/drm/nouveau/nouveau_bo0039.c new file mode 100644 index 000000000000..d5e9a200a64c --- /dev/null +++ b/drivers/gpu/drm/nouveau/nouveau_bo0039.c @@ -0,0 +1,100 @@ +/* + * Copyright 2007 Dave Airlied + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/* + * Authors: Dave Airlied + * Ben Skeggs + * Jeremy Kolb + */ +#include "nouveau_bo.h" +#include "nouveau_dma.h" +#include "nouveau_drv.h" + +static inline uint32_t +nouveau_bo_mem_ctxdma(struct ttm_buffer_object *bo, + struct nouveau_channel *chan, struct ttm_mem_reg *reg) +{ + if (reg->mem_type == TTM_PL_TT) + return NvDmaTT; + return chan->vram.handle; +} + +int +nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, + struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) +{ + u32 src_offset = old_reg->start << PAGE_SHIFT; + u32 dst_offset = new_reg->start << PAGE_SHIFT; + u32 page_count = new_reg->num_pages; + int ret; + + ret = RING_SPACE(chan, 3); + if (ret) + return ret; + + BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE, 2); + OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, old_reg)); + OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, new_reg)); + + page_count = new_reg->num_pages; + while (page_count) { + int line_count = (page_count > 2047) ? 2047 : page_count; + + ret = RING_SPACE(chan, 11); + if (ret) + return ret; + + BEGIN_NV04(chan, NvSubCopy, + NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8); + OUT_RING (chan, src_offset); + OUT_RING (chan, dst_offset); + OUT_RING (chan, PAGE_SIZE); /* src_pitch */ + OUT_RING (chan, PAGE_SIZE); /* dst_pitch */ + OUT_RING (chan, PAGE_SIZE); /* line_length */ + OUT_RING (chan, line_count); + OUT_RING (chan, 0x00000101); + OUT_RING (chan, 0x00000000); + BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1); + OUT_RING (chan, 0); + + page_count -= line_count; + src_offset += (PAGE_SIZE * line_count); + dst_offset += (PAGE_SIZE * line_count); + } + + return 0; +} + +int +nv04_bo_move_init(struct nouveau_channel *chan, u32 handle) +{ + int ret = RING_SPACE(chan, 4); + if (ret == 0) { + BEGIN_NV04(chan, NvSubCopy, 0x0000, 1); + OUT_RING (chan, handle); + BEGIN_NV04(chan, NvSubCopy, 0x0180, 1); + OUT_RING (chan, chan->drm->ntfy.handle); + } + + return ret; +} diff --git a/drivers/gpu/drm/nouveau/nouveau_bo5039.c b/drivers/gpu/drm/nouveau/nouveau_bo5039.c new file mode 100644 index 000000000000..a047f7943e6d --- /dev/null +++ b/drivers/gpu/drm/nouveau/nouveau_bo5039.c @@ -0,0 +1,121 @@ +/* + * Copyright 2007 Dave Airlied + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/* + * Authors: Dave Airlied + * Ben Skeggs + * Jeremy Kolb + */ +#include "nouveau_bo.h" +#include "nouveau_dma.h" +#include "nouveau_drv.h" +#include "nouveau_mem.h" + +int +nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, + struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) +{ + struct nouveau_mem *mem = nouveau_mem(old_reg); + u64 length = (new_reg->num_pages << PAGE_SHIFT); + u64 src_offset = mem->vma[0].addr; + u64 dst_offset = mem->vma[1].addr; + int src_tiled = !!mem->kind; + int dst_tiled = !!nouveau_mem(new_reg)->kind; + int ret; + + while (length) { + u32 amount, stride, height; + + ret = RING_SPACE(chan, 18 + 6 * (src_tiled + dst_tiled)); + if (ret) + return ret; + + amount = min(length, (u64)(4 * 1024 * 1024)); + stride = 16 * 4; + height = amount / stride; + + if (src_tiled) { + BEGIN_NV04(chan, NvSubCopy, 0x0200, 7); + OUT_RING (chan, 0); + OUT_RING (chan, 0); + OUT_RING (chan, stride); + OUT_RING (chan, height); + OUT_RING (chan, 1); + OUT_RING (chan, 0); + OUT_RING (chan, 0); + } else { + BEGIN_NV04(chan, NvSubCopy, 0x0200, 1); + OUT_RING (chan, 1); + } + if (dst_tiled) { + BEGIN_NV04(chan, NvSubCopy, 0x021c, 7); + OUT_RING (chan, 0); + OUT_RING (chan, 0); + OUT_RING (chan, stride); + OUT_RING (chan, height); + OUT_RING (chan, 1); + OUT_RING (chan, 0); + OUT_RING (chan, 0); + } else { + BEGIN_NV04(chan, NvSubCopy, 0x021c, 1); + OUT_RING (chan, 1); + } + + BEGIN_NV04(chan, NvSubCopy, 0x0238, 2); + OUT_RING (chan, upper_32_bits(src_offset)); + OUT_RING (chan, upper_32_bits(dst_offset)); + BEGIN_NV04(chan, NvSubCopy, 0x030c, 8); + OUT_RING (chan, lower_32_bits(src_offset)); + OUT_RING (chan, lower_32_bits(dst_offset)); + OUT_RING (chan, stride); + OUT_RING (chan, stride); + OUT_RING (chan, stride); + OUT_RING (chan, height); + OUT_RING (chan, 0x00000101); + OUT_RING (chan, 0x00000000); + BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1); + OUT_RING (chan, 0); + + length -= amount; + src_offset += amount; + dst_offset += amount; + } + + return 0; +} + +int +nv50_bo_move_init(struct nouveau_channel *chan, u32 handle) +{ + int ret = RING_SPACE(chan, 6); + if (ret == 0) { + BEGIN_NV04(chan, NvSubCopy, 0x0000, 1); + OUT_RING (chan, handle); + BEGIN_NV04(chan, NvSubCopy, 0x0180, 3); + OUT_RING (chan, chan->drm->ntfy.handle); + OUT_RING (chan, chan->vram.handle); + OUT_RING (chan, chan->vram.handle); + } + + return ret; +} diff --git a/drivers/gpu/drm/nouveau/nouveau_bo74c1.c b/drivers/gpu/drm/nouveau/nouveau_bo74c1.c new file mode 100644 index 000000000000..7528a03229b2 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nouveau_bo74c1.c @@ -0,0 +1,49 @@ +/* + * Copyright 2007 Dave Airlied + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/* + * Authors: Dave Airlied + * Ben Skeggs + * Jeremy Kolb + */ +#include "nouveau_bo.h" +#include "nouveau_dma.h" +#include "nouveau_mem.h" + +int +nv84_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo, + struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) +{ + struct nouveau_mem *mem = nouveau_mem(old_reg); + int ret = RING_SPACE(chan, 7); + if (ret == 0) { + BEGIN_NV04(chan, NvSubCopy, 0x0304, 6); + OUT_RING (chan, new_reg->num_pages << PAGE_SHIFT); + OUT_RING (chan, upper_32_bits(mem->vma[0].addr)); + OUT_RING (chan, lower_32_bits(mem->vma[0].addr)); + OUT_RING (chan, upper_32_bits(mem->vma[1].addr)); + OUT_RING (chan, lower_32_bits(mem->vma[1].addr)); + OUT_RING (chan, 0x00000000 /* MODE_COPY, QUERY_NONE */); + } + return ret; +} diff --git a/drivers/gpu/drm/nouveau/nouveau_bo85b5.c b/drivers/gpu/drm/nouveau/nouveau_bo85b5.c new file mode 100644 index 000000000000..c658c5e5fe04 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nouveau_bo85b5.c @@ -0,0 +1,73 @@ +/* + * Copyright 2007 Dave Airlied + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/* + * Authors: Dave Airlied + * Ben Skeggs + * Jeremy Kolb + */ +#include "nouveau_bo.h" +#include "nouveau_dma.h" +#include "nouveau_mem.h" + +/*XXX: Fixup class to be compatible with NVIDIA's, which will allow sharing + * code with KeplerDmaCopyA. + */ + +int +nva3_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo, + struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) +{ + struct nouveau_mem *mem = nouveau_mem(old_reg); + u64 src_offset = mem->vma[0].addr; + u64 dst_offset = mem->vma[1].addr; + u32 page_count = new_reg->num_pages; + int ret; + + page_count = new_reg->num_pages; + while (page_count) { + int line_count = (page_count > 8191) ? 8191 : page_count; + + ret = RING_SPACE(chan, 11); + if (ret) + return ret; + + BEGIN_NV04(chan, NvSubCopy, 0x030c, 8); + OUT_RING (chan, upper_32_bits(src_offset)); + OUT_RING (chan, lower_32_bits(src_offset)); + OUT_RING (chan, upper_32_bits(dst_offset)); + OUT_RING (chan, lower_32_bits(dst_offset)); + OUT_RING (chan, PAGE_SIZE); + OUT_RING (chan, PAGE_SIZE); + OUT_RING (chan, PAGE_SIZE); + OUT_RING (chan, line_count); + BEGIN_NV04(chan, NvSubCopy, 0x0300, 1); + OUT_RING (chan, 0x00000110); + + page_count -= line_count; + src_offset += (PAGE_SIZE * line_count); + dst_offset += (PAGE_SIZE * line_count); + } + + return 0; +} diff --git a/drivers/gpu/drm/nouveau/nouveau_bo9039.c b/drivers/gpu/drm/nouveau/nouveau_bo9039.c new file mode 100644 index 000000000000..14424f6c3f59 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nouveau_bo9039.c @@ -0,0 +1,81 @@ +/* + * Copyright 2007 Dave Airlied + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/* + * Authors: Dave Airlied + * Ben Skeggs + * Jeremy Kolb + */ +#include "nouveau_bo.h" +#include "nouveau_dma.h" +#include "nouveau_mem.h" + +int +nvc0_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, + struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) +{ + struct nouveau_mem *mem = nouveau_mem(old_reg); + u64 src_offset = mem->vma[0].addr; + u64 dst_offset = mem->vma[1].addr; + u32 page_count = new_reg->num_pages; + int ret; + + page_count = new_reg->num_pages; + while (page_count) { + int line_count = (page_count > 2047) ? 2047 : page_count; + + ret = RING_SPACE(chan, 12); + if (ret) + return ret; + + BEGIN_NVC0(chan, NvSubCopy, 0x0238, 2); + OUT_RING (chan, upper_32_bits(dst_offset)); + OUT_RING (chan, lower_32_bits(dst_offset)); + BEGIN_NVC0(chan, NvSubCopy, 0x030c, 6); + OUT_RING (chan, upper_32_bits(src_offset)); + OUT_RING (chan, lower_32_bits(src_offset)); + OUT_RING (chan, PAGE_SIZE); /* src_pitch */ + OUT_RING (chan, PAGE_SIZE); /* dst_pitch */ + OUT_RING (chan, PAGE_SIZE); /* line_length */ + OUT_RING (chan, line_count); + BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1); + OUT_RING (chan, 0x00100110); + + page_count -= line_count; + src_offset += (PAGE_SIZE * line_count); + dst_offset += (PAGE_SIZE * line_count); + } + + return 0; +} + +int +nvc0_bo_move_init(struct nouveau_channel *chan, u32 handle) +{ + int ret = RING_SPACE(chan, 2); + if (ret == 0) { + BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1); + OUT_RING (chan, handle); + } + return ret; +} diff --git a/drivers/gpu/drm/nouveau/nouveau_bo90b5.c b/drivers/gpu/drm/nouveau/nouveau_bo90b5.c new file mode 100644 index 000000000000..4c014f9a641f --- /dev/null +++ b/drivers/gpu/drm/nouveau/nouveau_bo90b5.c @@ -0,0 +1,66 @@ +/* + * Copyright 2020 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include "nouveau_bo.h" +#include "nouveau_dma.h" +#include "nouveau_mem.h" + +/*XXX: Fixup class to be compatible with NVIDIA's, which will allow sharing + * code with KeplerDmaCopyA. + */ + +int +nvc0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo, + struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) +{ + struct nouveau_mem *mem = nouveau_mem(old_reg); + u64 src_offset = mem->vma[0].addr; + u64 dst_offset = mem->vma[1].addr; + u32 page_count = new_reg->num_pages; + int ret; + + page_count = new_reg->num_pages; + while (page_count) { + int line_count = (page_count > 8191) ? 8191 : page_count; + + ret = RING_SPACE(chan, 11); + if (ret) + return ret; + + BEGIN_NVC0(chan, NvSubCopy, 0x030c, 8); + OUT_RING (chan, upper_32_bits(src_offset)); + OUT_RING (chan, lower_32_bits(src_offset)); + OUT_RING (chan, upper_32_bits(dst_offset)); + OUT_RING (chan, lower_32_bits(dst_offset)); + OUT_RING (chan, PAGE_SIZE); + OUT_RING (chan, PAGE_SIZE); + OUT_RING (chan, PAGE_SIZE); + OUT_RING (chan, line_count); + BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1); + OUT_RING (chan, 0x00000110); + + page_count -= line_count; + src_offset += (PAGE_SIZE * line_count); + dst_offset += (PAGE_SIZE * line_count); + } + + return 0; +} diff --git a/drivers/gpu/drm/nouveau/nouveau_boa0b5.c b/drivers/gpu/drm/nouveau/nouveau_boa0b5.c new file mode 100644 index 000000000000..55529ee4e823 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nouveau_boa0b5.c @@ -0,0 +1,64 @@ +/* + * Copyright 2007 Dave Airlied + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/* + * Authors: Dave Airlied + * Ben Skeggs + * Jeremy Kolb + */ +#include "nouveau_bo.h" +#include "nouveau_dma.h" +#include "nouveau_mem.h" + +int +nve0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo, + struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) +{ + struct nouveau_mem *mem = nouveau_mem(old_reg); + int ret = RING_SPACE(chan, 10); + if (ret == 0) { + BEGIN_NVC0(chan, NvSubCopy, 0x0400, 8); + OUT_RING (chan, upper_32_bits(mem->vma[0].addr)); + OUT_RING (chan, lower_32_bits(mem->vma[0].addr)); + OUT_RING (chan, upper_32_bits(mem->vma[1].addr)); + OUT_RING (chan, lower_32_bits(mem->vma[1].addr)); + OUT_RING (chan, PAGE_SIZE); + OUT_RING (chan, PAGE_SIZE); + OUT_RING (chan, PAGE_SIZE); + OUT_RING (chan, new_reg->num_pages); + BEGIN_IMC0(chan, NvSubCopy, 0x0300, 0x0386); + } + return ret; +} + +int +nve0_bo_move_init(struct nouveau_channel *chan, u32 handle) +{ + int ret = RING_SPACE(chan, 2); + if (ret == 0) { + BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1); + OUT_RING (chan, handle & 0x0000ffff); + FIRE_RING (chan); + } + return ret; +} From 01c43a66eb7aac48b3a978158cfb45674b18a48e Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 22 Jun 2020 15:54:52 +1000 Subject: [PATCH 081/145] drm/nouveau/bo: convert move init() to new push macros Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/nouveau_bo0039.c | 19 +++++++++++-------- drivers/gpu/drm/nouveau/nouveau_bo5039.c | 23 +++++++++++++---------- drivers/gpu/drm/nouveau/nouveau_bo9039.c | 17 +++++++++++------ drivers/gpu/drm/nouveau/nouveau_boa0b5.c | 18 +++++++++++------- 4 files changed, 46 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nouveau_bo0039.c b/drivers/gpu/drm/nouveau/nouveau_bo0039.c index d5e9a200a64c..ddf2f5ee1140 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo0039.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo0039.c @@ -30,6 +30,8 @@ #include "nouveau_dma.h" #include "nouveau_drv.h" +#include + static inline uint32_t nouveau_bo_mem_ctxdma(struct ttm_buffer_object *bo, struct nouveau_channel *chan, struct ttm_mem_reg *reg) @@ -88,13 +90,14 @@ nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, int nv04_bo_move_init(struct nouveau_channel *chan, u32 handle) { - int ret = RING_SPACE(chan, 4); - if (ret == 0) { - BEGIN_NV04(chan, NvSubCopy, 0x0000, 1); - OUT_RING (chan, handle); - BEGIN_NV04(chan, NvSubCopy, 0x0180, 1); - OUT_RING (chan, chan->drm->ntfy.handle); - } + struct nvif_push *push = chan->chan.push; + int ret; - return ret; + ret = PUSH_WAIT(push, 4); + if (ret) + return ret; + + PUSH_NVSQ(push, NV039, 0x0000, handle); + PUSH_NVSQ(push, NV039, 0x0180, chan->drm->ntfy.handle); + return 0; } diff --git a/drivers/gpu/drm/nouveau/nouveau_bo5039.c b/drivers/gpu/drm/nouveau/nouveau_bo5039.c index a047f7943e6d..9a667dc93dd3 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo5039.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo5039.c @@ -31,6 +31,8 @@ #include "nouveau_drv.h" #include "nouveau_mem.h" +#include + int nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) @@ -107,15 +109,16 @@ nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, int nv50_bo_move_init(struct nouveau_channel *chan, u32 handle) { - int ret = RING_SPACE(chan, 6); - if (ret == 0) { - BEGIN_NV04(chan, NvSubCopy, 0x0000, 1); - OUT_RING (chan, handle); - BEGIN_NV04(chan, NvSubCopy, 0x0180, 3); - OUT_RING (chan, chan->drm->ntfy.handle); - OUT_RING (chan, chan->vram.handle); - OUT_RING (chan, chan->vram.handle); - } + struct nvif_push *push = chan->chan.push; + int ret; - return ret; + ret = PUSH_WAIT(push, 6); + if (ret) + return ret; + + PUSH_NVSQ(push, NV5039, 0x0000, handle); + PUSH_NVSQ(push, NV5039, 0x0180, chan->drm->ntfy.handle, + 0x0184, chan->vram.handle, + 0x0188, chan->vram.handle); + return 0; } diff --git a/drivers/gpu/drm/nouveau/nouveau_bo9039.c b/drivers/gpu/drm/nouveau/nouveau_bo9039.c index 14424f6c3f59..f9ba04faf1a2 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo9039.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo9039.c @@ -30,6 +30,8 @@ #include "nouveau_dma.h" #include "nouveau_mem.h" +#include + int nvc0_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) @@ -72,10 +74,13 @@ nvc0_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, int nvc0_bo_move_init(struct nouveau_channel *chan, u32 handle) { - int ret = RING_SPACE(chan, 2); - if (ret == 0) { - BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1); - OUT_RING (chan, handle); - } - return ret; + struct nvif_push *push = chan->chan.push; + int ret; + + ret = PUSH_WAIT(push, 2); + if (ret) + return ret; + + PUSH_NVSQ(push, NV9039, 0x0000, handle); + return 0; } diff --git a/drivers/gpu/drm/nouveau/nouveau_boa0b5.c b/drivers/gpu/drm/nouveau/nouveau_boa0b5.c index 55529ee4e823..9c09691623d0 100644 --- a/drivers/gpu/drm/nouveau/nouveau_boa0b5.c +++ b/drivers/gpu/drm/nouveau/nouveau_boa0b5.c @@ -30,6 +30,8 @@ #include "nouveau_dma.h" #include "nouveau_mem.h" +#include + int nve0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo, struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) @@ -54,11 +56,13 @@ nve0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo, int nve0_bo_move_init(struct nouveau_channel *chan, u32 handle) { - int ret = RING_SPACE(chan, 2); - if (ret == 0) { - BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1); - OUT_RING (chan, handle & 0x0000ffff); - FIRE_RING (chan); - } - return ret; + struct nvif_push *push = chan->chan.push; + int ret; + + ret = PUSH_WAIT(push, 2); + if (ret) + return ret; + + PUSH_NVSQ(push, NVA0B5, 0x0000, handle & 0x0000ffff); + return 0; } From fe4249afd6a94363e2ef7334d5257171da474bb6 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 22 Jun 2020 16:20:32 +1000 Subject: [PATCH 082/145] drm/nouveau/bo: convert move move() to new push macros Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/nouveau_bo0039.c | 31 +++++------ drivers/gpu/drm/nouveau/nouveau_bo5039.c | 71 +++++++++++------------- drivers/gpu/drm/nouveau/nouveau_bo74c1.c | 27 +++++---- drivers/gpu/drm/nouveau/nouveau_bo85b5.c | 25 +++++---- drivers/gpu/drm/nouveau/nouveau_bo9039.c | 24 ++++---- drivers/gpu/drm/nouveau/nouveau_bo90b5.c | 25 +++++---- drivers/gpu/drm/nouveau/nouveau_boa0b5.c | 31 ++++++----- drivers/gpu/drm/nouveau/nouveau_dma.h | 17 ------ 8 files changed, 117 insertions(+), 134 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nouveau_bo0039.c b/drivers/gpu/drm/nouveau/nouveau_bo0039.c index ddf2f5ee1140..e00ec7cfce5f 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo0039.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo0039.c @@ -45,39 +45,36 @@ int nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) { + struct nvif_push *push = chan->chan.push; u32 src_offset = old_reg->start << PAGE_SHIFT; u32 dst_offset = new_reg->start << PAGE_SHIFT; u32 page_count = new_reg->num_pages; int ret; - ret = RING_SPACE(chan, 3); + ret = PUSH_WAIT(push, 3); if (ret) return ret; - BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE, 2); - OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, old_reg)); - OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, new_reg)); + PUSH_NVSQ(push, NV039, 0x0184, nouveau_bo_mem_ctxdma(bo, chan, old_reg), + 0x0188, nouveau_bo_mem_ctxdma(bo, chan, new_reg)); page_count = new_reg->num_pages; while (page_count) { int line_count = (page_count > 2047) ? 2047 : page_count; - ret = RING_SPACE(chan, 11); + ret = PUSH_WAIT(push, 11); if (ret) return ret; - BEGIN_NV04(chan, NvSubCopy, - NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8); - OUT_RING (chan, src_offset); - OUT_RING (chan, dst_offset); - OUT_RING (chan, PAGE_SIZE); /* src_pitch */ - OUT_RING (chan, PAGE_SIZE); /* dst_pitch */ - OUT_RING (chan, PAGE_SIZE); /* line_length */ - OUT_RING (chan, line_count); - OUT_RING (chan, 0x00000101); - OUT_RING (chan, 0x00000000); - BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1); - OUT_RING (chan, 0); + PUSH_NVSQ(push, NV039, 0x030c, src_offset, + 0x0310, dst_offset, + 0x0314, PAGE_SIZE, /* src_pitch */ + 0x0318, PAGE_SIZE, /* dst_pitch */ + 0x031c, PAGE_SIZE, /* line_length */ + 0x0320, line_count, + 0x0324, 0x00000101, + 0x0328, 0x00000000); + PUSH_NVSQ(push, NV039, 0x0100, 0x00000000); page_count -= line_count; src_offset += (PAGE_SIZE * line_count); diff --git a/drivers/gpu/drm/nouveau/nouveau_bo5039.c b/drivers/gpu/drm/nouveau/nouveau_bo5039.c index 9a667dc93dd3..19fb36b35ff9 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo5039.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo5039.c @@ -38,6 +38,7 @@ nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) { struct nouveau_mem *mem = nouveau_mem(old_reg); + struct nvif_push *push = chan->chan.push; u64 length = (new_reg->num_pages << PAGE_SHIFT); u64 src_offset = mem->vma[0].addr; u64 dst_offset = mem->vma[1].addr; @@ -48,7 +49,7 @@ nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, while (length) { u32 amount, stride, height; - ret = RING_SPACE(chan, 18 + 6 * (src_tiled + dst_tiled)); + ret = PUSH_WAIT(push, 18 + 6 * (src_tiled + dst_tiled)); if (ret) return ret; @@ -57,46 +58,40 @@ nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, height = amount / stride; if (src_tiled) { - BEGIN_NV04(chan, NvSubCopy, 0x0200, 7); - OUT_RING (chan, 0); - OUT_RING (chan, 0); - OUT_RING (chan, stride); - OUT_RING (chan, height); - OUT_RING (chan, 1); - OUT_RING (chan, 0); - OUT_RING (chan, 0); + PUSH_NVSQ(push, NV5039, 0x0200, 0, + 0x0204, 0, + 0x0208, stride, + 0x020c, height, + 0x0210, 1, + 0x0214, 0, + 0x0218, 0); } else { - BEGIN_NV04(chan, NvSubCopy, 0x0200, 1); - OUT_RING (chan, 1); - } - if (dst_tiled) { - BEGIN_NV04(chan, NvSubCopy, 0x021c, 7); - OUT_RING (chan, 0); - OUT_RING (chan, 0); - OUT_RING (chan, stride); - OUT_RING (chan, height); - OUT_RING (chan, 1); - OUT_RING (chan, 0); - OUT_RING (chan, 0); - } else { - BEGIN_NV04(chan, NvSubCopy, 0x021c, 1); - OUT_RING (chan, 1); + PUSH_NVSQ(push, NV5039, 0x0200, 1); } - BEGIN_NV04(chan, NvSubCopy, 0x0238, 2); - OUT_RING (chan, upper_32_bits(src_offset)); - OUT_RING (chan, upper_32_bits(dst_offset)); - BEGIN_NV04(chan, NvSubCopy, 0x030c, 8); - OUT_RING (chan, lower_32_bits(src_offset)); - OUT_RING (chan, lower_32_bits(dst_offset)); - OUT_RING (chan, stride); - OUT_RING (chan, stride); - OUT_RING (chan, stride); - OUT_RING (chan, height); - OUT_RING (chan, 0x00000101); - OUT_RING (chan, 0x00000000); - BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1); - OUT_RING (chan, 0); + if (dst_tiled) { + PUSH_NVSQ(push, NV5039, 0x021c, 0, + 0x0220, 0, + 0x0224, stride, + 0x0228, height, + 0x022c, 1, + 0x0230, 0, + 0x0234, 0); + } else { + PUSH_NVSQ(push, NV5039, 0x021c, 1); + } + + PUSH_NVSQ(push, NV5039, 0x0238, upper_32_bits(src_offset), + 0x023c, upper_32_bits(dst_offset)); + PUSH_NVSQ(push, NV5039, 0x030c, lower_32_bits(src_offset), + 0x0310, lower_32_bits(dst_offset), + 0x0314, stride, + 0x0318, stride, + 0x031c, stride, + 0x0320, height, + 0x0324, 0x00000101, + 0x0328, 0x00000000); + PUSH_NVSQ(push, NV5039, 0x0100, 0x00000000); length -= amount; src_offset += amount; diff --git a/drivers/gpu/drm/nouveau/nouveau_bo74c1.c b/drivers/gpu/drm/nouveau/nouveau_bo74c1.c index 7528a03229b2..1b5fd78ddcba 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo74c1.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo74c1.c @@ -30,20 +30,25 @@ #include "nouveau_dma.h" #include "nouveau_mem.h" +#include + int nv84_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo, struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) { struct nouveau_mem *mem = nouveau_mem(old_reg); - int ret = RING_SPACE(chan, 7); - if (ret == 0) { - BEGIN_NV04(chan, NvSubCopy, 0x0304, 6); - OUT_RING (chan, new_reg->num_pages << PAGE_SHIFT); - OUT_RING (chan, upper_32_bits(mem->vma[0].addr)); - OUT_RING (chan, lower_32_bits(mem->vma[0].addr)); - OUT_RING (chan, upper_32_bits(mem->vma[1].addr)); - OUT_RING (chan, lower_32_bits(mem->vma[1].addr)); - OUT_RING (chan, 0x00000000 /* MODE_COPY, QUERY_NONE */); - } - return ret; + struct nvif_push *push = chan->chan.push; + int ret; + + ret = PUSH_WAIT(push, 7); + if (ret) + return ret; + + PUSH_NVSQ(push, NV74C1, 0x0304, new_reg->num_pages << PAGE_SHIFT, + 0x0308, upper_32_bits(mem->vma[0].addr), + 0x030c, lower_32_bits(mem->vma[0].addr), + 0x0310, upper_32_bits(mem->vma[1].addr), + 0x0314, lower_32_bits(mem->vma[1].addr), + 0x0318, 0x00000000 /* MODE_COPY, QUERY_NONE */); + return 0; } diff --git a/drivers/gpu/drm/nouveau/nouveau_bo85b5.c b/drivers/gpu/drm/nouveau/nouveau_bo85b5.c index c658c5e5fe04..f0df172b029e 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo85b5.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo85b5.c @@ -30,6 +30,8 @@ #include "nouveau_dma.h" #include "nouveau_mem.h" +#include + /*XXX: Fixup class to be compatible with NVIDIA's, which will allow sharing * code with KeplerDmaCopyA. */ @@ -39,6 +41,7 @@ nva3_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo, struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) { struct nouveau_mem *mem = nouveau_mem(old_reg); + struct nvif_push *push = chan->chan.push; u64 src_offset = mem->vma[0].addr; u64 dst_offset = mem->vma[1].addr; u32 page_count = new_reg->num_pages; @@ -48,21 +51,19 @@ nva3_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo, while (page_count) { int line_count = (page_count > 8191) ? 8191 : page_count; - ret = RING_SPACE(chan, 11); + ret = PUSH_WAIT(push, 11); if (ret) return ret; - BEGIN_NV04(chan, NvSubCopy, 0x030c, 8); - OUT_RING (chan, upper_32_bits(src_offset)); - OUT_RING (chan, lower_32_bits(src_offset)); - OUT_RING (chan, upper_32_bits(dst_offset)); - OUT_RING (chan, lower_32_bits(dst_offset)); - OUT_RING (chan, PAGE_SIZE); - OUT_RING (chan, PAGE_SIZE); - OUT_RING (chan, PAGE_SIZE); - OUT_RING (chan, line_count); - BEGIN_NV04(chan, NvSubCopy, 0x0300, 1); - OUT_RING (chan, 0x00000110); + PUSH_NVSQ(push, NV85B5, 0x030c, upper_32_bits(src_offset), + 0x0310, lower_32_bits(src_offset), + 0x0314, upper_32_bits(dst_offset), + 0x0318, lower_32_bits(dst_offset), + 0x031c, PAGE_SIZE, + 0x0320, PAGE_SIZE, + 0x0324, PAGE_SIZE, + 0x0328, line_count); + PUSH_NVSQ(push, NV85B5, 0x0300, 0x00000110); page_count -= line_count; src_offset += (PAGE_SIZE * line_count); diff --git a/drivers/gpu/drm/nouveau/nouveau_bo9039.c b/drivers/gpu/drm/nouveau/nouveau_bo9039.c index f9ba04faf1a2..995ebe7ffe00 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo9039.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo9039.c @@ -36,6 +36,7 @@ int nvc0_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) { + struct nvif_push *push = chan->chan.push; struct nouveau_mem *mem = nouveau_mem(old_reg); u64 src_offset = mem->vma[0].addr; u64 dst_offset = mem->vma[1].addr; @@ -46,22 +47,19 @@ nvc0_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, while (page_count) { int line_count = (page_count > 2047) ? 2047 : page_count; - ret = RING_SPACE(chan, 12); + ret = PUSH_WAIT(push, 12); if (ret) return ret; - BEGIN_NVC0(chan, NvSubCopy, 0x0238, 2); - OUT_RING (chan, upper_32_bits(dst_offset)); - OUT_RING (chan, lower_32_bits(dst_offset)); - BEGIN_NVC0(chan, NvSubCopy, 0x030c, 6); - OUT_RING (chan, upper_32_bits(src_offset)); - OUT_RING (chan, lower_32_bits(src_offset)); - OUT_RING (chan, PAGE_SIZE); /* src_pitch */ - OUT_RING (chan, PAGE_SIZE); /* dst_pitch */ - OUT_RING (chan, PAGE_SIZE); /* line_length */ - OUT_RING (chan, line_count); - BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1); - OUT_RING (chan, 0x00100110); + PUSH_NVSQ(push, NV9039, 0x0238, upper_32_bits(dst_offset), + 0x023c, lower_32_bits(dst_offset)); + PUSH_NVSQ(push, NV9039, 0x030c, upper_32_bits(src_offset), + 0x0310, lower_32_bits(src_offset), + 0x0314, PAGE_SIZE, /* src_pitch */ + 0x0318, PAGE_SIZE, /* dst_pitch */ + 0x031c, PAGE_SIZE, /* line_length */ + 0x0320, line_count); + PUSH_NVSQ(push, NV9039, 0x0300, 0x00100110); page_count -= line_count; src_offset += (PAGE_SIZE * line_count); diff --git a/drivers/gpu/drm/nouveau/nouveau_bo90b5.c b/drivers/gpu/drm/nouveau/nouveau_bo90b5.c index 4c014f9a641f..34b79d561c7f 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo90b5.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo90b5.c @@ -23,6 +23,8 @@ #include "nouveau_dma.h" #include "nouveau_mem.h" +#include + /*XXX: Fixup class to be compatible with NVIDIA's, which will allow sharing * code with KeplerDmaCopyA. */ @@ -32,6 +34,7 @@ nvc0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo, struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) { struct nouveau_mem *mem = nouveau_mem(old_reg); + struct nvif_push *push = chan->chan.push; u64 src_offset = mem->vma[0].addr; u64 dst_offset = mem->vma[1].addr; u32 page_count = new_reg->num_pages; @@ -41,21 +44,19 @@ nvc0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo, while (page_count) { int line_count = (page_count > 8191) ? 8191 : page_count; - ret = RING_SPACE(chan, 11); + ret = PUSH_WAIT(push, 10); if (ret) return ret; - BEGIN_NVC0(chan, NvSubCopy, 0x030c, 8); - OUT_RING (chan, upper_32_bits(src_offset)); - OUT_RING (chan, lower_32_bits(src_offset)); - OUT_RING (chan, upper_32_bits(dst_offset)); - OUT_RING (chan, lower_32_bits(dst_offset)); - OUT_RING (chan, PAGE_SIZE); - OUT_RING (chan, PAGE_SIZE); - OUT_RING (chan, PAGE_SIZE); - OUT_RING (chan, line_count); - BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1); - OUT_RING (chan, 0x00000110); + PUSH_NVSQ(push, NV90B5, 0x030c, upper_32_bits(src_offset), + 0x0310, lower_32_bits(src_offset), + 0x0314, upper_32_bits(dst_offset), + 0x0318, lower_32_bits(dst_offset), + 0x031c, PAGE_SIZE, + 0x0320, PAGE_SIZE, + 0x0324, PAGE_SIZE, + 0x0328, line_count); + PUSH_NVIM(push, NV90B5, 0x0300, 0x0110); page_count -= line_count; src_offset += (PAGE_SIZE * line_count); diff --git a/drivers/gpu/drm/nouveau/nouveau_boa0b5.c b/drivers/gpu/drm/nouveau/nouveau_boa0b5.c index 9c09691623d0..b1afb2724fb7 100644 --- a/drivers/gpu/drm/nouveau/nouveau_boa0b5.c +++ b/drivers/gpu/drm/nouveau/nouveau_boa0b5.c @@ -37,20 +37,23 @@ nve0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo, struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) { struct nouveau_mem *mem = nouveau_mem(old_reg); - int ret = RING_SPACE(chan, 10); - if (ret == 0) { - BEGIN_NVC0(chan, NvSubCopy, 0x0400, 8); - OUT_RING (chan, upper_32_bits(mem->vma[0].addr)); - OUT_RING (chan, lower_32_bits(mem->vma[0].addr)); - OUT_RING (chan, upper_32_bits(mem->vma[1].addr)); - OUT_RING (chan, lower_32_bits(mem->vma[1].addr)); - OUT_RING (chan, PAGE_SIZE); - OUT_RING (chan, PAGE_SIZE); - OUT_RING (chan, PAGE_SIZE); - OUT_RING (chan, new_reg->num_pages); - BEGIN_IMC0(chan, NvSubCopy, 0x0300, 0x0386); - } - return ret; + struct nvif_push *push = chan->chan.push; + int ret; + + ret = PUSH_WAIT(push, 10); + if (ret) + return ret; + + PUSH_NVSQ(push, NVA0B5, 0x0400, upper_32_bits(mem->vma[0].addr), + 0x0404, lower_32_bits(mem->vma[0].addr), + 0x0408, upper_32_bits(mem->vma[1].addr), + 0x040c, lower_32_bits(mem->vma[1].addr), + 0x0410, PAGE_SIZE, + 0x0414, PAGE_SIZE, + 0x0418, PAGE_SIZE, + 0x041c, new_reg->num_pages); + PUSH_NVIM(push, NVA0B5, 0x0300, 0x0386); + return 0; } int diff --git a/drivers/gpu/drm/nouveau/nouveau_dma.h b/drivers/gpu/drm/nouveau/nouveau_dma.h index 72de20437542..8778fd6002c0 100644 --- a/drivers/gpu/drm/nouveau/nouveau_dma.h +++ b/drivers/gpu/drm/nouveau/nouveau_dma.h @@ -63,23 +63,6 @@ enum { NvEvoSema1 = 0x80000011, }; -#define NV_MEMORY_TO_MEMORY_FORMAT 0x00000039 -#define NV_MEMORY_TO_MEMORY_FORMAT_NAME 0x00000000 -#define NV_MEMORY_TO_MEMORY_FORMAT_SET_REF 0x00000050 -#define NV_MEMORY_TO_MEMORY_FORMAT_NOP 0x00000100 -#define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY 0x00000104 -#define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY_STYLE_WRITE 0x00000000 -#define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY_STYLE_WRITE_LE_AWAKEN 0x00000001 -#define NV_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY 0x00000180 -#define NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE 0x00000184 -#define NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN 0x0000030c - -#define NV50_MEMORY_TO_MEMORY_FORMAT 0x00005039 -#define NV50_MEMORY_TO_MEMORY_FORMAT_UNK200 0x00000200 -#define NV50_MEMORY_TO_MEMORY_FORMAT_UNK21C 0x0000021c -#define NV50_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN_HIGH 0x00000238 -#define NV50_MEMORY_TO_MEMORY_FORMAT_OFFSET_OUT_HIGH 0x0000023c - static __must_check inline int RING_SPACE(struct nouveau_channel *chan, int size) { From 71e741ad124d07b15d7f1cd481f98d69867ca0a2 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 22 Jun 2020 19:04:43 +1000 Subject: [PATCH 083/145] drm/nouveau/svm: convert migrate_copy to new push macros Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/nouveau_dmem.c | 33 +++++++++++++------------- 1 file changed, 16 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nouveau_dmem.c b/drivers/gpu/drm/nouveau/nouveau_dmem.c index 462ee0493651..a70dce4469f2 100644 --- a/drivers/gpu/drm/nouveau/nouveau_dmem.c +++ b/drivers/gpu/drm/nouveau/nouveau_dmem.c @@ -29,6 +29,7 @@ #include #include +#include #include #include #include @@ -385,7 +386,7 @@ nvc0b5_migrate_copy(struct nouveau_drm *drm, u64 npages, enum nouveau_aper dst_aper, u64 dst_addr, enum nouveau_aper src_aper, u64 src_addr) { - struct nouveau_channel *chan = drm->dmem->migrate.chan; + struct nvif_push *push = drm->dmem->migrate.chan->chan.push; u32 launch_dma = (1 << 9) /* MULTI_LINE_ENABLE. */ | (1 << 8) /* DST_MEMORY_LAYOUT_PITCH. */ | (1 << 7) /* SRC_MEMORY_LAYOUT_PITCH. */ | @@ -393,17 +394,17 @@ nvc0b5_migrate_copy(struct nouveau_drm *drm, u64 npages, (2 << 0) /* DATA_TRANSFER_TYPE_NON_PIPELINED. */; int ret; - ret = RING_SPACE(chan, 13); + ret = PUSH_WAIT(push, 13); if (ret) return ret; if (src_aper != NOUVEAU_APER_VIRT) { switch (src_aper) { case NOUVEAU_APER_VRAM: - BEGIN_IMC0(chan, NvSubCopy, 0x0260, 0); + PUSH_NVIM(push, NVA0B5, 0x0260, 0); break; case NOUVEAU_APER_HOST: - BEGIN_IMC0(chan, NvSubCopy, 0x0260, 1); + PUSH_NVIM(push, NVA0B5, 0x0260, 1); break; default: return -EINVAL; @@ -414,10 +415,10 @@ nvc0b5_migrate_copy(struct nouveau_drm *drm, u64 npages, if (dst_aper != NOUVEAU_APER_VIRT) { switch (dst_aper) { case NOUVEAU_APER_VRAM: - BEGIN_IMC0(chan, NvSubCopy, 0x0264, 0); + PUSH_NVIM(push, NVA0B5, 0x0264, 0); break; case NOUVEAU_APER_HOST: - BEGIN_IMC0(chan, NvSubCopy, 0x0264, 1); + PUSH_NVIM(push, NVA0B5, 0x0264, 1); break; default: return -EINVAL; @@ -425,17 +426,15 @@ nvc0b5_migrate_copy(struct nouveau_drm *drm, u64 npages, launch_dma |= 0x00002000; /* DST_TYPE_PHYSICAL. */ } - BEGIN_NVC0(chan, NvSubCopy, 0x0400, 8); - OUT_RING (chan, upper_32_bits(src_addr)); - OUT_RING (chan, lower_32_bits(src_addr)); - OUT_RING (chan, upper_32_bits(dst_addr)); - OUT_RING (chan, lower_32_bits(dst_addr)); - OUT_RING (chan, PAGE_SIZE); - OUT_RING (chan, PAGE_SIZE); - OUT_RING (chan, PAGE_SIZE); - OUT_RING (chan, npages); - BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1); - OUT_RING (chan, launch_dma); + PUSH_NVSQ(push, NVA0B5, 0x0400, upper_32_bits(src_addr), + 0x0404, lower_32_bits(src_addr), + 0x0408, upper_32_bits(dst_addr), + 0x040c, lower_32_bits(dst_addr), + 0x0410, PAGE_SIZE, + 0x0414, PAGE_SIZE, + 0x0418, PAGE_SIZE, + 0x041c, npages); + PUSH_NVSQ(push, NVA0B5, 0x0300, launch_dma); return 0; } From 44517aa8d787243dad59c0b55131ae4b6dc100f7 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 22 Jun 2020 19:04:55 +1000 Subject: [PATCH 084/145] drm/nouveau/svm: convert migrate_clear to new push macros Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/nouveau_dma.h | 8 -------- drivers/gpu/drm/nouveau/nouveau_dmem.c | 28 +++++++++++--------------- 2 files changed, 12 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nouveau_dma.h b/drivers/gpu/drm/nouveau/nouveau_dma.h index 8778fd6002c0..32a1f03ec488 100644 --- a/drivers/gpu/drm/nouveau/nouveau_dma.h +++ b/drivers/gpu/drm/nouveau/nouveau_dma.h @@ -49,8 +49,6 @@ void nv50_dma_push(struct nouveau_channel *, u64 addr, int length); enum { NvSubSw = 1, NvSubImageBlit = 2, - - NvSubCopy = 4, /* DO NOT CHANGE - hardcoded for kepler gr fifo */ }; /* Object handles - for stuff that's doesn't use handle == oclass. */ @@ -94,12 +92,6 @@ BEGIN_NVC0(struct nouveau_channel *chan, int subc, int mthd, int size) OUT_RING(chan, 0x20000000 | (size << 16) | (subc << 13) | (mthd >> 2)); } -static inline void -BEGIN_IMC0(struct nouveau_channel *chan, int subc, int mthd, u16 data) -{ - OUT_RING(chan, 0x80000000 | (data << 16) | (subc << 13) | (mthd >> 2)); -} - #define WRITE_PUT(val) do { \ mb(); \ nouveau_bo_rd32(chan->push.buffer, 0); \ diff --git a/drivers/gpu/drm/nouveau/nouveau_dmem.c b/drivers/gpu/drm/nouveau/nouveau_dmem.c index a70dce4469f2..6528e60e567e 100644 --- a/drivers/gpu/drm/nouveau/nouveau_dmem.c +++ b/drivers/gpu/drm/nouveau/nouveau_dmem.c @@ -442,7 +442,7 @@ static int nvc0b5_migrate_clear(struct nouveau_drm *drm, u32 length, enum nouveau_aper dst_aper, u64 dst_addr) { - struct nouveau_channel *chan = drm->dmem->migrate.chan; + struct nvif_push *push = drm->dmem->migrate.chan->chan.push; u32 launch_dma = (1 << 10) /* REMAP_ENABLE_TRUE */ | (1 << 8) /* DST_MEMORY_LAYOUT_PITCH. */ | (1 << 7) /* SRC_MEMORY_LAYOUT_PITCH. */ | @@ -454,33 +454,29 @@ nvc0b5_migrate_clear(struct nouveau_drm *drm, u32 length, (1 << 24) /* NUM_DST_COMPONENTS_TWO */; int ret; - ret = RING_SPACE(chan, 12); + ret = PUSH_WAIT(push, 12); if (ret) return ret; switch (dst_aper) { case NOUVEAU_APER_VRAM: - BEGIN_IMC0(chan, NvSubCopy, 0x0264, 0); - break; + PUSH_NVIM(push, NVA0B5, 0x0264, 0); + break; case NOUVEAU_APER_HOST: - BEGIN_IMC0(chan, NvSubCopy, 0x0264, 1); + PUSH_NVIM(push, NVA0B5, 0x0264, 1); break; default: return -EINVAL; } launch_dma |= 0x00002000; /* DST_TYPE_PHYSICAL. */ - BEGIN_NVC0(chan, NvSubCopy, 0x0700, 3); - OUT_RING(chan, 0); - OUT_RING(chan, 0); - OUT_RING(chan, remap); - BEGIN_NVC0(chan, NvSubCopy, 0x0408, 2); - OUT_RING(chan, upper_32_bits(dst_addr)); - OUT_RING(chan, lower_32_bits(dst_addr)); - BEGIN_NVC0(chan, NvSubCopy, 0x0418, 1); - OUT_RING(chan, length >> 3); - BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1); - OUT_RING(chan, launch_dma); + PUSH_NVSQ(push, NVA0B5, 0x0700, 0, + 0x0704, 0, + 0x0708, remap); + PUSH_NVSQ(push, NVA0B5, 0x0408, upper_32_bits(dst_addr), + 0x040c, lower_32_bits(dst_addr)); + PUSH_NVSQ(push, NVA0B5, 0x0418, length >> 3); + PUSH_NVSQ(push, NVA0B5, 0x0300, launch_dma); return 0; } From 105f756c503846442537016dedeab0e433820041 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 22 Jun 2020 19:36:18 +1000 Subject: [PATCH 085/145] drm/nouveau/kms/nv04: convert page_flip_emit() to new push macros Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv04/crtc.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv04/crtc.c b/drivers/gpu/drm/nouveau/dispnv04/crtc.c index 3d3348478549..94782ba4a1f3 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/crtc.c +++ b/drivers/gpu/drm/nouveau/dispnv04/crtc.c @@ -44,6 +44,8 @@ #include #include +#include + #include #include @@ -1105,6 +1107,7 @@ nv04_page_flip_emit(struct nouveau_channel *chan, struct nouveau_fence_chan *fctx = chan->fence; struct nouveau_drm *drm = chan->drm; struct drm_device *dev = drm->dev; + struct nvif_push *push = chan->chan.push; unsigned long flags; int ret; @@ -1119,13 +1122,12 @@ nv04_page_flip_emit(struct nouveau_channel *chan, goto fail; /* Emit the pageflip */ - ret = RING_SPACE(chan, 2); + ret = PUSH_WAIT(push, 2); if (ret) goto fail; - BEGIN_NV04(chan, NvSubSw, NV_SW_PAGE_FLIP, 1); - OUT_RING (chan, 0x00000000); - FIRE_RING (chan); + PUSH_NVSQ(push, NV_SW, NV_SW_PAGE_FLIP, 0x00000000); + PUSH_KICK(push); ret = nouveau_fence_new(chan, false, pfence); if (ret) From c548b25cab50883082cc10dcb2f81dfdc4aef3be Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 22 Jun 2020 19:39:36 +1000 Subject: [PATCH 086/145] drm/nouveau/kms/nv04: convert page_flip() to new push macros Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv04/crtc.c | 16 +++++++--------- drivers/gpu/drm/nouveau/nouveau_dma.h | 1 - 2 files changed, 7 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv04/crtc.c b/drivers/gpu/drm/nouveau/dispnv04/crtc.c index 94782ba4a1f3..6416b6907aeb 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/crtc.c +++ b/drivers/gpu/drm/nouveau/dispnv04/crtc.c @@ -1157,6 +1157,7 @@ nv04_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, struct nouveau_cli *cli; struct nouveau_fence *fence; struct nv04_display *dispnv04 = nv04_display(dev); + struct nvif_push *push; int head = nouveau_crtc(crtc)->index; int ret; @@ -1164,6 +1165,7 @@ nv04_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, if (!chan) return -ENODEV; cli = (void *)chan->user.client; + push = chan->chan.push; s = kzalloc(sizeof(*s), GFP_KERNEL); if (!s) @@ -1205,18 +1207,14 @@ nv04_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, /* Emit a page flip */ if (swap_interval) { - ret = RING_SPACE(chan, 8); + ret = PUSH_WAIT(push, 8); if (ret) goto fail_unreserve; - BEGIN_NV04(chan, NvSubImageBlit, 0x012c, 1); - OUT_RING (chan, 0); - BEGIN_NV04(chan, NvSubImageBlit, 0x0134, 1); - OUT_RING (chan, head); - BEGIN_NV04(chan, NvSubImageBlit, 0x0100, 1); - OUT_RING (chan, 0); - BEGIN_NV04(chan, NvSubImageBlit, 0x0130, 1); - OUT_RING (chan, 0); + PUSH_NVSQ(push, NV05F, 0x012c, 0); + PUSH_NVSQ(push, NV05F, 0x0134, head); + PUSH_NVSQ(push, NV05F, 0x0100, 0); + PUSH_NVSQ(push, NV05F, 0x0130, 0); } nouveau_bo_ref(new_bo, &dispnv04->image[head]); diff --git a/drivers/gpu/drm/nouveau/nouveau_dma.h b/drivers/gpu/drm/nouveau/nouveau_dma.h index 32a1f03ec488..35318739f7f5 100644 --- a/drivers/gpu/drm/nouveau/nouveau_dma.h +++ b/drivers/gpu/drm/nouveau/nouveau_dma.h @@ -48,7 +48,6 @@ void nv50_dma_push(struct nouveau_channel *, u64 addr, int length); /* Hardcoded object assignments to subchannels (subchannel id). */ enum { NvSubSw = 1, - NvSubImageBlit = 2, }; /* Object handles - for stuff that's doesn't use handle == oclass. */ From 2bf00037c47f3252b75de3cc15da247c61d16fce Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 22 Jun 2020 19:48:59 +1000 Subject: [PATCH 087/145] drm/nouveau/kms/nv04-: no need for multiple nvsw objects Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv04/disp.c | 5 +++-- drivers/gpu/drm/nouveau/nouveau_drm.c | 7 +++---- drivers/gpu/drm/nouveau/nouveau_drv.h | 1 - 3 files changed, 6 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv04/disp.c b/drivers/gpu/drm/nouveau/dispnv04/disp.c index 075fe017915d..900ab69df7e8 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/disp.c +++ b/drivers/gpu/drm/nouveau/dispnv04/disp.c @@ -31,6 +31,7 @@ #include "nouveau_connector.h" #include "nouveau_bo.h" #include "nouveau_gem.h" +#include "nouveau_chan.h" #include @@ -214,8 +215,8 @@ nv04_display_create(struct drm_device *dev) dev->driver_features &= ~DRIVER_ATOMIC; /* Request page flip completion event. */ - if (drm->nvsw.client) { - nvif_notify_ctor(&drm->nvsw, "kmsFlip", nv04_flip_complete, + if (drm->channel) { + nvif_notify_ctor(&drm->channel->nvsw, "kmsFlip", nv04_flip_complete, false, NV04_NVSW_NTFY_UEVENT, NULL, 0, 0, &disp->flip); } diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c index c1b22746a710..3879919050a9 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drm.c +++ b/drivers/gpu/drm/nouveau/nouveau_drm.c @@ -331,7 +331,6 @@ nouveau_accel_gr_fini(struct nouveau_drm *drm) nouveau_channel_idle(drm->channel); nvif_object_dtor(&drm->ntfy); nvkm_gpuobj_del(&drm->notify); - nvif_object_dtor(&drm->nvsw); nouveau_channel_del(&drm->channel); } @@ -363,15 +362,15 @@ nouveau_accel_gr_init(struct nouveau_drm *drm) * synchronisation of page flips, as well as to implement fences * on TNT/TNT2 HW that lacks any kind of support in host. */ - if (device->info.family < NV_DEVICE_INFO_V0_TESLA) { + if (!drm->channel->nvsw.client && device->info.family < NV_DEVICE_INFO_V0_TESLA) { ret = nvif_object_ctor(&drm->channel->user, "drmNvsw", NVDRM_NVSW, nouveau_abi16_swclass(drm), - NULL, 0, &drm->nvsw); + NULL, 0, &drm->channel->nvsw); if (ret == 0) { ret = RING_SPACE(drm->channel, 2); if (ret == 0) { BEGIN_NV04(drm->channel, NvSubSw, 0, 1); - OUT_RING (drm->channel, drm->nvsw.handle); + OUT_RING (drm->channel, drm->channel->nvsw.handle); } } diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h index 30c0bb5b4dc9..ae76a5865a5a 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drv.h +++ b/drivers/gpu/drm/nouveau/nouveau_drv.h @@ -186,7 +186,6 @@ struct nouveau_drm { struct nouveau_channel *channel; struct nvkm_gpuobj *notify; struct nouveau_fbdev *fbcon; - struct nvif_object nvsw; struct nvif_object ntfy; /* nv10-nv40 tiling regions */ From 0d2bdf2b0a73170cf7bc814aa44852a1d37387da Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 22 Jun 2020 19:51:21 +1000 Subject: [PATCH 088/145] drm/nouveau: convert nvsw init to new push macros Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/nouveau_drm.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c index 3879919050a9..22d246acc5e5 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drm.c +++ b/drivers/gpu/drm/nouveau/nouveau_drm.c @@ -41,6 +41,7 @@ #include #include +#include #include #include @@ -367,11 +368,10 @@ nouveau_accel_gr_init(struct nouveau_drm *drm) NVDRM_NVSW, nouveau_abi16_swclass(drm), NULL, 0, &drm->channel->nvsw); if (ret == 0) { - ret = RING_SPACE(drm->channel, 2); - if (ret == 0) { - BEGIN_NV04(drm->channel, NvSubSw, 0, 1); - OUT_RING (drm->channel, drm->channel->nvsw.handle); - } + struct nvif_push *push = drm->channel->chan.push; + ret = PUSH_WAIT(push, 2); + if (ret == 0) + PUSH_NVSQ(push, NV_SW, 0x0000, drm->channel->nvsw.handle); } if (ret) { From cd346a89d249a045f23aac28b9cc61db5f4d34d9 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 22 Jun 2020 19:54:50 +1000 Subject: [PATCH 089/145] drm/nouveau/chan: convert nvsw init to new push macros Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/nouveau_chan.c | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nouveau_chan.c b/drivers/gpu/drm/nouveau/nouveau_chan.c index 27092a6933ee..b80e4ebf14a6 100644 --- a/drivers/gpu/drm/nouveau/nouveau_chan.c +++ b/drivers/gpu/drm/nouveau/nouveau_chan.c @@ -21,8 +21,8 @@ * * Authors: Ben Skeggs */ +#include -#include #include #include #include @@ -32,9 +32,6 @@ #include #include -/*XXX*/ -#include - #include "nouveau_drv.h" #include "nouveau_dma.h" #include "nouveau_bo.h" @@ -482,12 +479,12 @@ nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart) chan->dma.cur = chan->dma.put; chan->dma.free = chan->dma.max - chan->dma.cur; - ret = RING_SPACE(chan, NOUVEAU_DMA_SKIPS); + ret = PUSH_WAIT(chan->chan.push, NOUVEAU_DMA_SKIPS); if (ret) return ret; for (i = 0; i < NOUVEAU_DMA_SKIPS; i++) - OUT_RING(chan, 0x00000000); + PUSH_DATA(chan->chan.push, 0x00000000); /* allocate software object class (used for fences on <= nv05) */ if (device->info.family < NV_DEVICE_INFO_V0_CELSIUS) { @@ -497,13 +494,12 @@ nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart) if (ret) return ret; - ret = RING_SPACE(chan, 2); + ret = PUSH_WAIT(chan->chan.push, 2); if (ret) return ret; - BEGIN_NV04(chan, NvSubSw, 0x0000, 1); - OUT_RING (chan, chan->nvsw.handle); - FIRE_RING (chan); + PUSH_NVSQ(chan->chan.push, NV_SW, 0x0000, chan->nvsw.handle); + PUSH_KICK(chan->chan.push); } /* initialise synchronisation */ From 183b70bbdf61c89afa4aa5945a5cda85d005a2ed Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 22 Jun 2020 20:01:38 +1000 Subject: [PATCH 090/145] drm/nouveau/gem: convert indirect pushbufs to new push macros Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/nouveau_gem.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.c b/drivers/gpu/drm/nouveau/nouveau_gem.c index 133ab6fb7798..81f111ad3f4f 100644 --- a/drivers/gpu/drm/nouveau/nouveau_gem.c +++ b/drivers/gpu/drm/nouveau/nouveau_gem.c @@ -35,6 +35,7 @@ #include "nouveau_vmm.h" #include +#include void nouveau_gem_object_del(struct drm_gem_object *gem) @@ -799,7 +800,7 @@ nouveau_gem_ioctl_pushbuf(struct drm_device *dev, void *data, } } else if (drm->client.device.info.chipset >= 0x25) { - ret = RING_SPACE(chan, req->nr_push * 2); + ret = PUSH_WAIT(chan->chan.push, req->nr_push * 2); if (ret) { NV_PRINTK(err, cli, "cal_space: %d\n", ret); goto out; @@ -809,11 +810,11 @@ nouveau_gem_ioctl_pushbuf(struct drm_device *dev, void *data, struct nouveau_bo *nvbo = (void *)(unsigned long) bo[push[i].bo_index].user_priv; - OUT_RING(chan, (nvbo->offset + push[i].offset) | 2); - OUT_RING(chan, 0); + PUSH_CALL(chan->chan.push, nvbo->offset + push[i].offset); + PUSH_DATA(chan->chan.push, 0); } } else { - ret = RING_SPACE(chan, req->nr_push * (2 + NOUVEAU_DMA_SKIPS)); + ret = PUSH_WAIT(chan->chan.push, req->nr_push * (2 + NOUVEAU_DMA_SKIPS)); if (ret) { NV_PRINTK(err, cli, "jmp_space: %d\n", ret); goto out; @@ -843,11 +844,10 @@ nouveau_gem_ioctl_pushbuf(struct drm_device *dev, void *data, push[i].length - 8) / 4, cmd); } - OUT_RING(chan, 0x20000000 | - (nvbo->offset + push[i].offset)); - OUT_RING(chan, 0); + PUSH_JUMP(chan->chan.push, nvbo->offset + push[i].offset); + PUSH_DATA(chan->chan.push, 0); for (j = 0; j < NOUVEAU_DMA_SKIPS; j++) - OUT_RING(chan, 0); + PUSH_DATA(chan->chan.push, 0); } } From 7aa638cfdb285946f989ac1e132e9c3378f26db6 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 22 Jun 2020 20:18:06 +1000 Subject: [PATCH 091/145] drm/nouveau/fence: convert emit() to new push macros Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/nouveau_dma.h | 5 ----- drivers/gpu/drm/nouveau/nv04_fence.c | 11 +++++------ drivers/gpu/drm/nouveau/nv10_fence.c | 12 ++++++------ drivers/gpu/drm/nouveau/nv84_fence.c | 24 +++++++++++++----------- drivers/gpu/drm/nouveau/nvc0_fence.c | 21 ++++++++++++--------- 5 files changed, 36 insertions(+), 37 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nouveau_dma.h b/drivers/gpu/drm/nouveau/nouveau_dma.h index 35318739f7f5..3e6c39d7ea01 100644 --- a/drivers/gpu/drm/nouveau/nouveau_dma.h +++ b/drivers/gpu/drm/nouveau/nouveau_dma.h @@ -45,11 +45,6 @@ void nv50_dma_push(struct nouveau_channel *, u64 addr, int length); */ #define NOUVEAU_DMA_SKIPS (128 / 4) -/* Hardcoded object assignments to subchannels (subchannel id). */ -enum { - NvSubSw = 1, -}; - /* Object handles - for stuff that's doesn't use handle == oclass. */ enum { NvDmaFB = 0x80000002, diff --git a/drivers/gpu/drm/nouveau/nv04_fence.c b/drivers/gpu/drm/nouveau/nv04_fence.c index c41e82be4893..5b71a5a5cd85 100644 --- a/drivers/gpu/drm/nouveau/nv04_fence.c +++ b/drivers/gpu/drm/nouveau/nv04_fence.c @@ -21,12 +21,12 @@ * * Authors: Ben Skeggs */ - #include "nouveau_drv.h" #include "nouveau_dma.h" #include "nouveau_fence.h" #include +#include struct nv04_fence_chan { struct nouveau_fence_chan base; @@ -39,12 +39,11 @@ struct nv04_fence_priv { static int nv04_fence_emit(struct nouveau_fence *fence) { - struct nouveau_channel *chan = fence->channel; - int ret = RING_SPACE(chan, 2); + struct nvif_push *push = fence->channel->chan.push; + int ret = PUSH_WAIT(push, 2); if (ret == 0) { - BEGIN_NV04(chan, NvSubSw, 0x0150, 1); - OUT_RING (chan, fence->base.seqno); - FIRE_RING (chan); + PUSH_NVSQ(push, NV_SW, 0x0150, fence->base.seqno); + PUSH_KICK(push); } return ret; } diff --git a/drivers/gpu/drm/nouveau/nv10_fence.c b/drivers/gpu/drm/nouveau/nv10_fence.c index 32d07f02b24c..b5117b0c71c1 100644 --- a/drivers/gpu/drm/nouveau/nv10_fence.c +++ b/drivers/gpu/drm/nouveau/nv10_fence.c @@ -21,20 +21,20 @@ * * Authors: Ben Skeggs */ - #include "nouveau_drv.h" #include "nouveau_dma.h" #include "nv10_fence.h" +#include + int nv10_fence_emit(struct nouveau_fence *fence) { - struct nouveau_channel *chan = fence->channel; - int ret = RING_SPACE(chan, 2); + struct nvif_push *push = fence->channel->chan.push; + int ret = PUSH_WAIT(push, 2); if (ret == 0) { - BEGIN_NV04(chan, 0, NV10_SUBCHAN_REF_CNT, 1); - OUT_RING (chan, fence->base.seqno); - FIRE_RING (chan); + PUSH_NVSQ(push, NV06E, NV10_SUBCHAN_REF_CNT, fence->base.seqno); + PUSH_KICK(push); } return ret; } diff --git a/drivers/gpu/drm/nouveau/nv84_fence.c b/drivers/gpu/drm/nouveau/nv84_fence.c index f07da00f285f..0c4b740abea8 100644 --- a/drivers/gpu/drm/nouveau/nv84_fence.c +++ b/drivers/gpu/drm/nouveau/nv84_fence.c @@ -21,7 +21,6 @@ * * Authors: Ben Skeggs */ - #include "nouveau_drv.h" #include "nouveau_dma.h" #include "nouveau_fence.h" @@ -29,20 +28,23 @@ #include "nv50_display.h" +#include + static int nv84_fence_emit32(struct nouveau_channel *chan, u64 virtual, u32 sequence) { - int ret = RING_SPACE(chan, 8); + struct nvif_push *push = chan->chan.push; + int ret = PUSH_WAIT(push, 8); if (ret == 0) { - BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1); - OUT_RING (chan, chan->vram.handle); - BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 5); - OUT_RING (chan, upper_32_bits(virtual)); - OUT_RING (chan, lower_32_bits(virtual)); - OUT_RING (chan, sequence); - OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG); - OUT_RING (chan, 0x00000000); - FIRE_RING (chan); + PUSH_NVSQ(push, NV826F, NV11_SUBCHAN_DMA_SEMAPHORE, chan->vram.handle); + PUSH_NVSQ(push, NV826F, + NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, upper_32_bits(virtual), + NV84_SUBCHAN_SEMAPHORE_ADDRESS_LOW, lower_32_bits(virtual), + NV84_SUBCHAN_SEMAPHORE_SEQUENCE, sequence, + NV84_SUBCHAN_SEMAPHORE_TRIGGER, + NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG, + NV84_SUBCHAN_UEVENT, 0x00000000); + PUSH_KICK(push); } return ret; } diff --git a/drivers/gpu/drm/nouveau/nvc0_fence.c b/drivers/gpu/drm/nouveau/nvc0_fence.c index b79775788bbd..e4b2efaee254 100644 --- a/drivers/gpu/drm/nouveau/nvc0_fence.c +++ b/drivers/gpu/drm/nouveau/nvc0_fence.c @@ -21,25 +21,28 @@ * * Authors: Ben Skeggs */ - #include "nouveau_drv.h" #include "nouveau_dma.h" #include "nouveau_fence.h" #include "nv50_display.h" +#include + static int nvc0_fence_emit32(struct nouveau_channel *chan, u64 virtual, u32 sequence) { - int ret = RING_SPACE(chan, 6); + struct nvif_push *push = chan->chan.push; + int ret = PUSH_WAIT(push, 6); if (ret == 0) { - BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 5); - OUT_RING (chan, upper_32_bits(virtual)); - OUT_RING (chan, lower_32_bits(virtual)); - OUT_RING (chan, sequence); - OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG); - OUT_RING (chan, 0x00000000); - FIRE_RING (chan); + PUSH_NVSQ(push, NV906F, + NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, upper_32_bits(virtual), + NV84_SUBCHAN_SEMAPHORE_ADDRESS_LOW, lower_32_bits(virtual), + NV84_SUBCHAN_SEMAPHORE_SEQUENCE, sequence, + NV84_SUBCHAN_SEMAPHORE_TRIGGER, + NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG, + NV84_SUBCHAN_UEVENT, 0x00000000); + PUSH_KICK(push); } return ret; } From 2f5bfd1c0aad53d7033950f0c8b7a142ddeb0827 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 22 Jun 2020 20:26:07 +1000 Subject: [PATCH 092/145] drm/nouveau/fence: convert sync() to new push macros Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/nouveau_dma.h | 12 --------- drivers/gpu/drm/nouveau/nv17_fence.c | 38 +++++++++++++-------------- drivers/gpu/drm/nouveau/nv84_fence.c | 19 +++++++------- drivers/gpu/drm/nouveau/nvc0_fence.c | 18 +++++++------ 4 files changed, 39 insertions(+), 48 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nouveau_dma.h b/drivers/gpu/drm/nouveau/nouveau_dma.h index 3e6c39d7ea01..3f86cdff927f 100644 --- a/drivers/gpu/drm/nouveau/nouveau_dma.h +++ b/drivers/gpu/drm/nouveau/nouveau_dma.h @@ -74,18 +74,6 @@ OUT_RING(struct nouveau_channel *chan, int data) nouveau_bo_wr32(chan->push.buffer, chan->dma.cur++, data); } -static inline void -BEGIN_NV04(struct nouveau_channel *chan, int subc, int mthd, int size) -{ - OUT_RING(chan, 0x00000000 | (subc << 13) | (size << 18) | mthd); -} - -static inline void -BEGIN_NVC0(struct nouveau_channel *chan, int subc, int mthd, int size) -{ - OUT_RING(chan, 0x20000000 | (size << 16) | (subc << 13) | (mthd >> 2)); -} - #define WRITE_PUT(val) do { \ mb(); \ nouveau_bo_rd32(chan->push.buffer, 0); \ diff --git a/drivers/gpu/drm/nouveau/nv17_fence.c b/drivers/gpu/drm/nouveau/nv17_fence.c index c27d225699a5..8d7b4f2479cc 100644 --- a/drivers/gpu/drm/nouveau/nv17_fence.c +++ b/drivers/gpu/drm/nouveau/nv17_fence.c @@ -21,15 +21,15 @@ * * Authors: Ben Skeggs */ - -#include -#include -#include - #include "nouveau_drv.h" #include "nouveau_dma.h" #include "nv10_fence.h" +#include + +#include +#include + int nv17_fence_sync(struct nouveau_fence *fence, struct nouveau_channel *prev, struct nouveau_channel *chan) @@ -37,6 +37,8 @@ nv17_fence_sync(struct nouveau_fence *fence, struct nouveau_cli *cli = (void *)prev->user.client; struct nv10_fence_priv *priv = chan->drm->fence; struct nv10_fence_chan *fctx = chan->fence; + struct nvif_push *ppush = prev->chan.push; + struct nvif_push *npush = chan->chan.push; u32 value; int ret; @@ -48,23 +50,21 @@ nv17_fence_sync(struct nouveau_fence *fence, priv->sequence += 2; spin_unlock(&priv->lock); - ret = RING_SPACE(prev, 5); + ret = PUSH_WAIT(ppush, 5); if (!ret) { - BEGIN_NV04(prev, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 4); - OUT_RING (prev, fctx->sema.handle); - OUT_RING (prev, 0); - OUT_RING (prev, value + 0); - OUT_RING (prev, value + 1); - FIRE_RING (prev); + PUSH_NVSQ(ppush, NV176E, NV11_SUBCHAN_DMA_SEMAPHORE, fctx->sema.handle, + NV11_SUBCHAN_SEMAPHORE_OFFSET, 0, + NV11_SUBCHAN_SEMAPHORE_ACQUIRE, value + 0, + NV11_SUBCHAN_SEMAPHORE_RELEASE, value + 1); + PUSH_KICK(ppush); } - if (!ret && !(ret = RING_SPACE(chan, 5))) { - BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 4); - OUT_RING (chan, fctx->sema.handle); - OUT_RING (chan, 0); - OUT_RING (chan, value + 1); - OUT_RING (chan, value + 2); - FIRE_RING (chan); + if (!ret && !(ret = PUSH_WAIT(npush, 5))) { + PUSH_NVSQ(npush, NV176E, NV11_SUBCHAN_DMA_SEMAPHORE, fctx->sema.handle, + NV11_SUBCHAN_SEMAPHORE_OFFSET, 0, + NV11_SUBCHAN_SEMAPHORE_ACQUIRE, value + 1, + NV11_SUBCHAN_SEMAPHORE_RELEASE, value + 2); + PUSH_KICK(npush); } mutex_unlock(&cli->mutex); diff --git a/drivers/gpu/drm/nouveau/nv84_fence.c b/drivers/gpu/drm/nouveau/nv84_fence.c index 0c4b740abea8..bc09e64fe6b8 100644 --- a/drivers/gpu/drm/nouveau/nv84_fence.c +++ b/drivers/gpu/drm/nouveau/nv84_fence.c @@ -52,16 +52,17 @@ nv84_fence_emit32(struct nouveau_channel *chan, u64 virtual, u32 sequence) static int nv84_fence_sync32(struct nouveau_channel *chan, u64 virtual, u32 sequence) { - int ret = RING_SPACE(chan, 7); + struct nvif_push *push = chan->chan.push; + int ret = PUSH_WAIT(push, 7); if (ret == 0) { - BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1); - OUT_RING (chan, chan->vram.handle); - BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4); - OUT_RING (chan, upper_32_bits(virtual)); - OUT_RING (chan, lower_32_bits(virtual)); - OUT_RING (chan, sequence); - OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL); - FIRE_RING (chan); + PUSH_NVSQ(push, NV826F, NV11_SUBCHAN_DMA_SEMAPHORE, chan->vram.handle); + PUSH_NVSQ(push, NV826F, + NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, upper_32_bits(virtual), + NV84_SUBCHAN_SEMAPHORE_ADDRESS_LOW, lower_32_bits(virtual), + NV84_SUBCHAN_SEMAPHORE_SEQUENCE, sequence, + NV84_SUBCHAN_SEMAPHORE_TRIGGER, + NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL); + PUSH_KICK(push); } return ret; } diff --git a/drivers/gpu/drm/nouveau/nvc0_fence.c b/drivers/gpu/drm/nouveau/nvc0_fence.c index e4b2efaee254..13b1345081d9 100644 --- a/drivers/gpu/drm/nouveau/nvc0_fence.c +++ b/drivers/gpu/drm/nouveau/nvc0_fence.c @@ -50,15 +50,17 @@ nvc0_fence_emit32(struct nouveau_channel *chan, u64 virtual, u32 sequence) static int nvc0_fence_sync32(struct nouveau_channel *chan, u64 virtual, u32 sequence) { - int ret = RING_SPACE(chan, 5); + struct nvif_push *push = chan->chan.push; + int ret = PUSH_WAIT(push, 5); if (ret == 0) { - BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4); - OUT_RING (chan, upper_32_bits(virtual)); - OUT_RING (chan, lower_32_bits(virtual)); - OUT_RING (chan, sequence); - OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL | - NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD); - FIRE_RING (chan); + PUSH_NVSQ(push, NV906F, + NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, upper_32_bits(virtual), + NV84_SUBCHAN_SEMAPHORE_ADDRESS_LOW, lower_32_bits(virtual), + NV84_SUBCHAN_SEMAPHORE_SEQUENCE, sequence, + NV84_SUBCHAN_SEMAPHORE_TRIGGER, + NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL | + NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD); + PUSH_KICK(push); } return ret; } From 2a0d40bbd6880f680c7f879a40bdc6d99fc8d70a Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 22 Jun 2020 09:18:57 +1000 Subject: [PATCH 093/145] drm/nouveau/kms/nv50-: use NVIDIA's headers for wimm space() Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/curs507a.c | 5 ++- .../drm/nouveau/include/nvhw/class/cl507a.h | 36 +++++++++++++++++++ 2 files changed, 40 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/nouveau/include/nvhw/class/cl507a.h diff --git a/drivers/gpu/drm/nouveau/dispnv50/curs507a.c b/drivers/gpu/drm/nouveau/dispnv50/curs507a.c index 47f6f01b52a0..070328aca16d 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/curs507a.c +++ b/drivers/gpu/drm/nouveau/dispnv50/curs507a.c @@ -26,6 +26,8 @@ #include #include +#include + #include #include @@ -33,9 +35,10 @@ bool curs507a_space(struct nv50_wndw *wndw) { nvif_msec(&nouveau_drm(wndw->plane.dev)->client.device, 100, - if (nvif_rd32(&wndw->wimm.base.user, 0x0008) >= 4) + if (NVIF_TV32(&wndw->wimm.base.user, NV507A, FREE, COUNT, >=, 4)) return true; ); + WARN_ON(1); return false; } diff --git a/drivers/gpu/drm/nouveau/include/nvhw/class/cl507a.h b/drivers/gpu/drm/nouveau/include/nvhw/class/cl507a.h new file mode 100644 index 000000000000..a97bcec1ab9a --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvhw/class/cl507a.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl507a_h_ +#define _cl507a_h_ + +#define NV507A_FREE (0x00000008) +#define NV507A_FREE_COUNT 5:0 +#define NV507A_UPDATE (0x00000080) +#define NV507A_UPDATE_INTERLOCK_WITH_CORE 0:0 +#define NV507A_UPDATE_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NV507A_UPDATE_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NV507A_SET_CURSOR_HOT_SPOT_POINT_OUT (0x00000084) +#define NV507A_SET_CURSOR_HOT_SPOT_POINT_OUT_X 15:0 +#define NV507A_SET_CURSOR_HOT_SPOT_POINT_OUT_Y 31:16 +#endif // _cl507a_h From 937014086af8a09caf0f61353aba8884dfa54699 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sun, 21 Jun 2020 10:25:58 +1000 Subject: [PATCH 094/145] drm/nouveau/kms/nv50-: use NVIDIA's headers for wimm point() Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/curs507a.c | 6 ++-- drivers/gpu/drm/nouveau/dispnv50/cursc37a.c | 8 +++-- drivers/gpu/drm/nouveau/dispnv50/wimmc37b.c | 6 +++- .../drm/nouveau/include/nvhw/class/clc37a.h | 31 +++++++++++++++++++ 4 files changed, 46 insertions(+), 5 deletions(-) create mode 100644 drivers/gpu/drm/nouveau/include/nvhw/class/clc37a.h diff --git a/drivers/gpu/drm/nouveau/dispnv50/curs507a.c b/drivers/gpu/drm/nouveau/dispnv50/curs507a.c index 070328aca16d..5e03b94848b4 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/curs507a.c +++ b/drivers/gpu/drm/nouveau/dispnv50/curs507a.c @@ -55,10 +55,12 @@ curs507a_update(struct nv50_wndw *wndw, u32 *interlock) static int curs507a_point(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) { + struct nvif_object *user = &wndw->wimm.base.user; int ret = nvif_chan_wait(&wndw->wimm, 1); if (ret == 0) { - nvif_wr32(&wndw->wimm.base.user, 0x0084, asyw->point.y << 16 | - asyw->point.x); + NVIF_WR32(user, NV507A, SET_CURSOR_HOT_SPOT_POINT_OUT, + NVVAL(NV507A, SET_CURSOR_HOT_SPOT_POINT_OUT, X, asyw->point.x) | + NVVAL(NV507A, SET_CURSOR_HOT_SPOT_POINT_OUT, Y, asyw->point.y)); } return ret; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/cursc37a.c b/drivers/gpu/drm/nouveau/dispnv50/cursc37a.c index 9d96a246b39a..5bfb6f67c8c3 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/cursc37a.c +++ b/drivers/gpu/drm/nouveau/dispnv50/cursc37a.c @@ -22,6 +22,8 @@ #include "curs.h" #include "atom.h" +#include + static int cursc37a_update(struct nv50_wndw *wndw, u32 *interlock) { @@ -34,10 +36,12 @@ cursc37a_update(struct nv50_wndw *wndw, u32 *interlock) static int cursc37a_point(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) { + struct nvif_object *user = &wndw->wimm.base.user; int ret = nvif_chan_wait(&wndw->wimm, 1); if (ret == 0) { - nvif_wr32(&wndw->wimm.base.user, 0x0208, asyw->point.y << 16 | - asyw->point.x); + NVIF_WR32(user, NVC37A, SET_CURSOR_HOT_SPOT_POINT_OUT(0), + NVVAL(NVC37A, SET_CURSOR_HOT_SPOT_POINT_OUT, X, asyw->point.x) | + NVVAL(NVC37A, SET_CURSOR_HOT_SPOT_POINT_OUT, Y, asyw->point.y)); } return ret; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/wimmc37b.c b/drivers/gpu/drm/nouveau/dispnv50/wimmc37b.c index c2009d477736..d013f89cc371 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wimmc37b.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wimmc37b.c @@ -26,6 +26,8 @@ #include #include +#include + static int wimmc37b_update(struct nv50_wndw *wndw, u32 *interlock) { @@ -50,7 +52,9 @@ wimmc37b_point(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) if ((ret = PUSH_WAIT(push, 2))) return ret; - PUSH_NVSQ(push, NVC37B, 0x0208, asyw->point.y << 16 | asyw->point.x); + PUSH_MTHD(push, NVC37B, SET_POINT_OUT(0), + NVVAL(NVC37B, SET_POINT_OUT, X, asyw->point.x) | + NVVAL(NVC37B, SET_POINT_OUT, Y, asyw->point.y)); return 0; } diff --git a/drivers/gpu/drm/nouveau/include/nvhw/class/clc37a.h b/drivers/gpu/drm/nouveau/include/nvhw/class/clc37a.h new file mode 100644 index 000000000000..ded616f93388 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvhw/class/clc37a.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 1993-2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _clc37a__h_ +#define _clc37a__h_ + +#define NVC37A_UPDATE (0x00000200) +#define NVC37A_SET_CURSOR_HOT_SPOT_POINT_OUT(b) (0x00000208 + (b)*0x00000004) +#define NVC37A_SET_CURSOR_HOT_SPOT_POINT_OUT_X 15:0 +#define NVC37A_SET_CURSOR_HOT_SPOT_POINT_OUT_Y 31:16 +#endif // _clc37a_h From 852dfbde915cb68e577e6e2cac9b3db08a4f81c7 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sun, 21 Jun 2020 10:36:33 +1000 Subject: [PATCH 095/145] drm/nouveau/kms/nv50-: use NVIDIA's headers for wimm update() Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/curs507a.c | 7 +++++-- drivers/gpu/drm/nouveau/dispnv50/cursc37a.c | 3 ++- drivers/gpu/drm/nouveau/dispnv50/wimmc37b.c | 6 +++--- 3 files changed, 10 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/curs507a.c b/drivers/gpu/drm/nouveau/dispnv50/curs507a.c index 5e03b94848b4..54fbd6fe751d 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/curs507a.c +++ b/drivers/gpu/drm/nouveau/dispnv50/curs507a.c @@ -46,9 +46,12 @@ curs507a_space(struct nv50_wndw *wndw) static int curs507a_update(struct nv50_wndw *wndw, u32 *interlock) { + struct nvif_object *user = &wndw->wimm.base.user; int ret = nvif_chan_wait(&wndw->wimm, 1); - if (ret == 0) - nvif_wr32(&wndw->wimm.base.user, 0x0080, 0x00000000); + if (ret == 0) { + NVIF_WR32(user, NV507A, UPDATE, + NVDEF(NV507A, UPDATE, INTERLOCK_WITH_CORE, DISABLE)); + } return ret; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/cursc37a.c b/drivers/gpu/drm/nouveau/dispnv50/cursc37a.c index 5bfb6f67c8c3..e39d08698c63 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/cursc37a.c +++ b/drivers/gpu/drm/nouveau/dispnv50/cursc37a.c @@ -27,9 +27,10 @@ static int cursc37a_update(struct nv50_wndw *wndw, u32 *interlock) { + struct nvif_object *user = &wndw->wimm.base.user; int ret = nvif_chan_wait(&wndw->wimm, 1); if (ret == 0) - nvif_wr32(&wndw->wimm.base.user, 0x0200, 0x00000001); + NVIF_WR32(user, NVC37A, UPDATE, 0x00000001); return ret; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/wimmc37b.c b/drivers/gpu/drm/nouveau/dispnv50/wimmc37b.c index d013f89cc371..685b70871324 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wimmc37b.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wimmc37b.c @@ -37,9 +37,9 @@ wimmc37b_update(struct nv50_wndw *wndw, u32 *interlock) if ((ret = PUSH_WAIT(push, 2))) return ret; - PUSH_NVSQ(push, NVC37B, 0x0200, ((interlock[NV50_DISP_INTERLOCK_WNDW] & - wndw->interlock.data) ? 0x00000002 : 0x00000000) | - 0x00000001); + PUSH_MTHD(push, NVC37B, UPDATE, 0x00000001 | + NVVAL(NVC37B, UPDATE, INTERLOCK_WITH_WINDOW, + !!(interlock[NV50_DISP_INTERLOCK_WNDW] & wndw->interlock.data))); return PUSH_KICK(push); } From fccc858003f3f3e7a8fa272f118eb71d218a2b32 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sat, 20 Jun 2020 10:24:41 +1000 Subject: [PATCH 096/145] drm/nouveau/kms/nv50-: use NVIDIA's headers for wndw sema_set() Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/base507c.c | 10 +- drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c | 10 +- .../drm/nouveau/include/nvhw/class/clc37e.h | 394 ++++++++++++++++++ 3 files changed, 406 insertions(+), 8 deletions(-) create mode 100644 drivers/gpu/drm/nouveau/include/nvhw/class/clc37e.h diff --git a/drivers/gpu/drm/nouveau/dispnv50/base507c.c b/drivers/gpu/drm/nouveau/dispnv50/base507c.c index e5f189859bde..c6b1f8d70ae2 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/base507c.c +++ b/drivers/gpu/drm/nouveau/dispnv50/base507c.c @@ -26,6 +26,8 @@ #include #include +#include + #include #include #include @@ -185,10 +187,10 @@ base507c_sema_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) if ((ret = PUSH_WAIT(push, 5))) return ret; - PUSH_NVSQ(push, NV507C, 0x0088, asyw->sema.offset, - 0x008c, asyw->sema.acquire, - 0x0090, asyw->sema.release, - 0x0094, asyw->sema.handle); + PUSH_MTHD(push, NV507C, SET_SEMAPHORE_CONTROL, asyw->sema.offset, + SET_SEMAPHORE_ACQUIRE, asyw->sema.acquire, + SET_SEMAPHORE_RELEASE, asyw->sema.release, + SET_CONTEXT_DMA_SEMAPHORE, asyw->sema.handle); return 0; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c index b000b3a86371..a69ddf94ef1f 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c @@ -29,6 +29,8 @@ #include #include +#include + static int wndwc37e_csc_clr(struct nv50_wndw *wndw) { @@ -208,10 +210,10 @@ wndwc37e_sema_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) if ((ret = PUSH_WAIT(push, 5))) return ret; - PUSH_NVSQ(push, NVC37E, 0x020c, asyw->sema.offset, - 0x0210, asyw->sema.acquire, - 0x0214, asyw->sema.release, - 0x0218, asyw->sema.handle); + PUSH_MTHD(push, NVC37E, SET_SEMAPHORE_CONTROL, asyw->sema.offset, + SET_SEMAPHORE_ACQUIRE, asyw->sema.acquire, + SET_SEMAPHORE_RELEASE, asyw->sema.release, + SET_CONTEXT_DMA_SEMAPHORE, asyw->sema.handle); return 0; } diff --git a/drivers/gpu/drm/nouveau/include/nvhw/class/clc37e.h b/drivers/gpu/drm/nouveau/include/nvhw/class/clc37e.h new file mode 100644 index 000000000000..99e5a737b0d1 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvhw/class/clc37e.h @@ -0,0 +1,394 @@ +/* + * Copyright (c) 1993-2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _clC37e_h_ +#define _clC37e_h_ + +// class methods +#define NVC37E_UPDATE (0x00000200) +#define NVC37E_UPDATE_INTERLOCK_WITH_WIN_IMM 12:12 +#define NVC37E_UPDATE_INTERLOCK_WITH_WIN_IMM_DISABLE (0x00000000) +#define NVC37E_UPDATE_INTERLOCK_WITH_WIN_IMM_ENABLE (0x00000001) +#define NVC37E_SET_SEMAPHORE_CONTROL (0x0000020C) +#define NVC37E_SET_SEMAPHORE_CONTROL_OFFSET 7:0 +#define NVC37E_SET_SEMAPHORE_ACQUIRE (0x00000210) +#define NVC37E_SET_SEMAPHORE_ACQUIRE_VALUE 31:0 +#define NVC37E_SET_SEMAPHORE_RELEASE (0x00000214) +#define NVC37E_SET_SEMAPHORE_RELEASE_VALUE 31:0 +#define NVC37E_SET_CONTEXT_DMA_SEMAPHORE (0x00000218) +#define NVC37E_SET_CONTEXT_DMA_SEMAPHORE_HANDLE 31:0 +#define NVC37E_SET_CONTEXT_DMA_NOTIFIER (0x0000021C) +#define NVC37E_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0 +#define NVC37E_SET_NOTIFIER_CONTROL (0x00000220) +#define NVC37E_SET_NOTIFIER_CONTROL_MODE 0:0 +#define NVC37E_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000) +#define NVC37E_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001) +#define NVC37E_SET_NOTIFIER_CONTROL_OFFSET 11:4 +#define NVC37E_SET_SIZE (0x00000224) +#define NVC37E_SET_SIZE_WIDTH 15:0 +#define NVC37E_SET_SIZE_HEIGHT 31:16 +#define NVC37E_SET_STORAGE (0x00000228) +#define NVC37E_SET_STORAGE_BLOCK_HEIGHT 3:0 +#define NVC37E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_ONE_GOB (0x00000000) +#define NVC37E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_TWO_GOBS (0x00000001) +#define NVC37E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC37E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC37E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC37E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC37E_SET_STORAGE_MEMORY_LAYOUT 4:4 +#define NVC37E_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVC37E_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVC37E_SET_PARAMS (0x0000022C) +#define NVC37E_SET_PARAMS_FORMAT 7:0 +#define NVC37E_SET_PARAMS_FORMAT_I8 (0x0000001E) +#define NVC37E_SET_PARAMS_FORMAT_R4G4B4A4 (0x0000002F) +#define NVC37E_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8) +#define NVC37E_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9) +#define NVC37E_SET_PARAMS_FORMAT_R5G5B5A1 (0x0000002E) +#define NVC37E_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF) +#define NVC37E_SET_PARAMS_FORMAT_X8R8G8B8 (0x000000E6) +#define NVC37E_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5) +#define NVC37E_SET_PARAMS_FORMAT_X8B8G8R8 (0x000000F9) +#define NVC37E_SET_PARAMS_FORMAT_A2R10G10B10 (0x000000DF) +#define NVC37E_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1) +#define NVC37E_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS (0x00000022) +#define NVC37E_SET_PARAMS_FORMAT_X2BL10GL10RL10_XVYCC (0x00000024) +#define NVC37E_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS (0x00000023) +#define NVC37E_SET_PARAMS_FORMAT_R16_G16_B16_A16 (0x000000C6) +#define NVC37E_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA) +#define NVC37E_SET_PARAMS_FORMAT_Y8_U8__Y8_V8_N422 (0x00000028) +#define NVC37E_SET_PARAMS_FORMAT_U8_Y8__V8_Y8_N422 (0x00000029) +#define NVC37E_SET_PARAMS_FORMAT_Y8___U8V8_N444 (0x00000035) +#define NVC37E_SET_PARAMS_FORMAT_Y8___U8V8_N422 (0x00000036) +#define NVC37E_SET_PARAMS_FORMAT_Y8___U8V8_N422R (0x00000037) +#define NVC37E_SET_PARAMS_FORMAT_Y8___V8U8_N420 (0x00000038) +#define NVC37E_SET_PARAMS_FORMAT_Y8___U8___V8_N444 (0x0000003A) +#define NVC37E_SET_PARAMS_FORMAT_Y8___U8___V8_N420 (0x0000003B) +#define NVC37E_SET_PARAMS_FORMAT_Y10___U10V10_N444 (0x00000055) +#define NVC37E_SET_PARAMS_FORMAT_Y10___U10V10_N422 (0x00000056) +#define NVC37E_SET_PARAMS_FORMAT_Y10___U10V10_N422R (0x00000057) +#define NVC37E_SET_PARAMS_FORMAT_Y10___V10U10_N420 (0x00000058) +#define NVC37E_SET_PARAMS_FORMAT_Y10___U10___V10_N444 (0x0000005A) +#define NVC37E_SET_PARAMS_FORMAT_Y10___U10___V10_N420 (0x0000005B) +#define NVC37E_SET_PARAMS_FORMAT_Y12___U12V12_N444 (0x00000075) +#define NVC37E_SET_PARAMS_FORMAT_Y12___U12V12_N422 (0x00000076) +#define NVC37E_SET_PARAMS_FORMAT_Y12___U12V12_N422R (0x00000077) +#define NVC37E_SET_PARAMS_FORMAT_Y12___V12U12_N420 (0x00000078) +#define NVC37E_SET_PARAMS_FORMAT_Y12___U12___V12_N444 (0x0000007A) +#define NVC37E_SET_PARAMS_FORMAT_Y12___U12___V12_N420 (0x0000007B) +#define NVC37E_SET_PARAMS_COLOR_SPACE 9:8 +#define NVC37E_SET_PARAMS_COLOR_SPACE_RGB (0x00000000) +#define NVC37E_SET_PARAMS_COLOR_SPACE_YUV_601 (0x00000001) +#define NVC37E_SET_PARAMS_COLOR_SPACE_YUV_709 (0x00000002) +#define NVC37E_SET_PARAMS_COLOR_SPACE_YUV_2020 (0x00000003) +#define NVC37E_SET_PARAMS_INPUT_RANGE 13:12 +#define NVC37E_SET_PARAMS_INPUT_RANGE_BYPASS (0x00000000) +#define NVC37E_SET_PARAMS_INPUT_RANGE_LIMITED (0x00000001) +#define NVC37E_SET_PARAMS_INPUT_RANGE_FULL (0x00000002) +#define NVC37E_SET_PARAMS_UNDERREPLICATE 16:16 +#define NVC37E_SET_PARAMS_UNDERREPLICATE_DISABLE (0x00000000) +#define NVC37E_SET_PARAMS_UNDERREPLICATE_ENABLE (0x00000001) +#define NVC37E_SET_PARAMS_DE_GAMMA 21:20 +#define NVC37E_SET_PARAMS_DE_GAMMA_NONE (0x00000000) +#define NVC37E_SET_PARAMS_DE_GAMMA_SRGB (0x00000001) +#define NVC37E_SET_PARAMS_DE_GAMMA_YUV8_10 (0x00000002) +#define NVC37E_SET_PARAMS_DE_GAMMA_YUV12 (0x00000003) +#define NVC37E_SET_PARAMS_CSC 17:17 +#define NVC37E_SET_PARAMS_CSC_DISABLE (0x00000000) +#define NVC37E_SET_PARAMS_CSC_ENABLE (0x00000001) +#define NVC37E_SET_PARAMS_CLAMP_BEFORE_BLEND 18:18 +#define NVC37E_SET_PARAMS_CLAMP_BEFORE_BLEND_DISABLE (0x00000000) +#define NVC37E_SET_PARAMS_CLAMP_BEFORE_BLEND_ENABLE (0x00000001) +#define NVC37E_SET_PARAMS_SWAP_UV 19:19 +#define NVC37E_SET_PARAMS_SWAP_UV_DISABLE (0x00000000) +#define NVC37E_SET_PARAMS_SWAP_UV_ENABLE (0x00000001) +#define NVC37E_SET_PLANAR_STORAGE(b) (0x00000230 + (b)*0x00000004) +#define NVC37E_SET_PLANAR_STORAGE_PITCH 12:0 +#define NVC37E_SET_CONTEXT_DMA_ISO(b) (0x00000240 + (b)*0x00000004) +#define NVC37E_SET_CONTEXT_DMA_ISO_HANDLE 31:0 +#define NVC37E_SET_OFFSET(b) (0x00000260 + (b)*0x00000004) +#define NVC37E_SET_OFFSET_ORIGIN 31:0 +#define NVC37E_SET_POINT_IN(b) (0x00000290 + (b)*0x00000004) +#define NVC37E_SET_POINT_IN_X 15:0 +#define NVC37E_SET_POINT_IN_Y 31:16 +#define NVC37E_SET_SIZE_IN (0x00000298) +#define NVC37E_SET_SIZE_IN_WIDTH 14:0 +#define NVC37E_SET_SIZE_IN_HEIGHT 30:16 +#define NVC37E_SET_SIZE_OUT (0x000002A4) +#define NVC37E_SET_SIZE_OUT_WIDTH 14:0 +#define NVC37E_SET_SIZE_OUT_HEIGHT 30:16 +#define NVC37E_SET_CONTROL_INPUT_LUT (0x000002B0) +#define NVC37E_SET_CONTROL_INPUT_LUT_SIZE 1:0 +#define NVC37E_SET_CONTROL_INPUT_LUT_SIZE_SIZE_257 (0x00000000) +#define NVC37E_SET_CONTROL_INPUT_LUT_SIZE_SIZE_1025 (0x00000002) +#define NVC37E_SET_CONTROL_INPUT_LUT_RANGE 5:4 +#define NVC37E_SET_CONTROL_INPUT_LUT_RANGE_UNITY (0x00000000) +#define NVC37E_SET_CONTROL_INPUT_LUT_RANGE_XRBIAS (0x00000001) +#define NVC37E_SET_CONTROL_INPUT_LUT_RANGE_XVYCC (0x00000002) +#define NVC37E_SET_CONTROL_INPUT_LUT_OUTPUT_MODE 9:8 +#define NVC37E_SET_CONTROL_INPUT_LUT_OUTPUT_MODE_INDEX (0x00000000) +#define NVC37E_SET_CONTROL_INPUT_LUT_OUTPUT_MODE_INTERPOLATE (0x00000001) +#define NVC37E_SET_OFFSET_INPUT_LUT (0x000002B4) +#define NVC37E_SET_OFFSET_INPUT_LUT_ORIGIN 31:0 +#define NVC37E_SET_CONTEXT_DMA_INPUT_LUT (0x000002B8) +#define NVC37E_SET_CONTEXT_DMA_INPUT_LUT_HANDLE 31:0 +#define NVC37E_SET_CSC_RED2RED (0x000002BC) +#define NVC37E_SET_CSC_RED2RED_COEFF 18:0 +#define NVC37E_SET_CSC_GREEN2RED (0x000002C0) +#define NVC37E_SET_CSC_GREEN2RED_COEFF 18:0 +#define NVC37E_SET_CSC_BLUE2RED (0x000002C4) +#define NVC37E_SET_CSC_BLUE2RED_COEFF 18:0 +#define NVC37E_SET_CSC_CONSTANT2RED (0x000002C8) +#define NVC37E_SET_CSC_CONSTANT2RED_COEFF 18:0 +#define NVC37E_SET_CSC_RED2GREEN (0x000002CC) +#define NVC37E_SET_CSC_RED2GREEN_COEFF 18:0 +#define NVC37E_SET_CSC_GREEN2GREEN (0x000002D0) +#define NVC37E_SET_CSC_GREEN2GREEN_COEFF 18:0 +#define NVC37E_SET_CSC_BLUE2GREEN (0x000002D4) +#define NVC37E_SET_CSC_BLUE2GREEN_COEFF 18:0 +#define NVC37E_SET_CSC_CONSTANT2GREEN (0x000002D8) +#define NVC37E_SET_CSC_CONSTANT2GREEN_COEFF 18:0 +#define NVC37E_SET_CSC_RED2BLUE (0x000002DC) +#define NVC37E_SET_CSC_RED2BLUE_COEFF 18:0 +#define NVC37E_SET_CSC_GREEN2BLUE (0x000002E0) +#define NVC37E_SET_CSC_GREEN2BLUE_COEFF 18:0 +#define NVC37E_SET_CSC_BLUE2BLUE (0x000002E4) +#define NVC37E_SET_CSC_BLUE2BLUE_COEFF 18:0 +#define NVC37E_SET_CSC_CONSTANT2BLUE (0x000002E8) +#define NVC37E_SET_CSC_CONSTANT2BLUE_COEFF 18:0 +#define NVC37E_SET_COMPOSITION_CONTROL (0x000002EC) +#define NVC37E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT 1:0 +#define NVC37E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT_DISABLE (0x00000000) +#define NVC37E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT_SRC (0x00000001) +#define NVC37E_SET_COMPOSITION_CONTROL_COLOR_KEY_SELECT_DST (0x00000002) +#define NVC37E_SET_COMPOSITION_CONTROL_DEPTH 11:4 +#define NVC37E_SET_COMPOSITION_CONSTANT_ALPHA (0x000002F0) +#define NVC37E_SET_COMPOSITION_CONSTANT_ALPHA_K1 7:0 +#define NVC37E_SET_COMPOSITION_CONSTANT_ALPHA_K2 15:8 +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT (0x000002F4) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT 3:0 +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_ZERO (0x00000000) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_ONE (0x00000001) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1 (0x00000002) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_SRC (0x00000005) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_DST (0x00000006) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT 7:4 +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_ONE (0x00000001) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1 (0x00000002) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_SRC (0x00000005) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_DST (0x00000006) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT 11:8 +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_ZERO (0x00000000) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_ONE (0x00000001) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K1 (0x00000002) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K2 (0x00000003) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1 (0x00000004) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_DST (0x00000006) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT 15:12 +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_ONE (0x00000001) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K1 (0x00000002) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K2 (0x00000003) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1 (0x00000004) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_K1_TIMES_DST (0x00000006) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT 19:16 +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_ZERO (0x00000000) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_K1 (0x00000002) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_K2 (0x00000003) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT 23:20 +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_K1 (0x00000002) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_K2 (0x00000003) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_ALPHA_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_DST (0x00000008) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT 27:24 +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_ZERO (0x00000000) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_ONE (0x00000001) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_K2 (0x00000003) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT 31:28 +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_ZERO (0x00000000) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_ONE (0x00000001) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_K2 (0x00000003) +#define NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_ALPHA_FACTOR_NO_MATCH_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVC37E_SET_KEY_ALPHA (0x000002F8) +#define NVC37E_SET_KEY_ALPHA_MIN 15:0 +#define NVC37E_SET_KEY_ALPHA_MAX 31:16 +#define NVC37E_SET_KEY_RED_CR (0x000002FC) +#define NVC37E_SET_KEY_RED_CR_MIN 15:0 +#define NVC37E_SET_KEY_RED_CR_MAX 31:16 +#define NVC37E_SET_KEY_GREEN_Y (0x00000300) +#define NVC37E_SET_KEY_GREEN_Y_MIN 15:0 +#define NVC37E_SET_KEY_GREEN_Y_MAX 31:16 +#define NVC37E_SET_KEY_BLUE_CB (0x00000304) +#define NVC37E_SET_KEY_BLUE_CB_MIN 15:0 +#define NVC37E_SET_KEY_BLUE_CB_MAX 31:16 +#define NVC37E_SET_PRESENT_CONTROL (0x00000308) +#define NVC37E_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 3:0 +#define NVC37E_SET_PRESENT_CONTROL_BEGIN_MODE 6:4 +#define NVC37E_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING (0x00000000) +#define NVC37E_SET_PRESENT_CONTROL_BEGIN_MODE_IMMEDIATE (0x00000001) +#define NVC37E_SET_PRESENT_CONTROL_TIMESTAMP_MODE 8:8 +#define NVC37E_SET_PRESENT_CONTROL_TIMESTAMP_MODE_DISABLE (0x00000000) +#define NVC37E_SET_PRESENT_CONTROL_TIMESTAMP_MODE_ENABLE (0x00000001) +#define NVC37E_SET_INTERLOCK_FLAGS (0x00000370) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE 0:0 +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR(i) ((i)+1):((i)+1) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR__SIZE_1 8 +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_DISABLE (0x00000000) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_ENABLE (0x00000001) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0 1:1 +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1 2:2 +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2 3:3 +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3 4:4 +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4 5:5 +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_DISABLE (0x00000000) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_ENABLE (0x00000001) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5 6:6 +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_DISABLE (0x00000000) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_ENABLE (0x00000001) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6 7:7 +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_DISABLE (0x00000000) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_ENABLE (0x00000001) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7 8:8 +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_DISABLE (0x00000000) +#define NVC37E_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS (0x00000374) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW(i) ((i)+0):((i)+0) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW__SIZE_1 32 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0 0:0 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1 1:1 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2 2:2 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3 3:3 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4 4:4 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5 5:5 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6 6:6 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7 7:7 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8 8:8 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9 9:9 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10 10:10 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11 11:11 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12 12:12 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13 13:13 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14 14:14 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15 15:15 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16 16:16 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17 17:17 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18 18:18 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19 19:19 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20 20:20 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21 21:21 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22 22:22 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23 23:23 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24 24:24 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25 25:25 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26 26:26 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27 27:27 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28 28:28 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29 29:29 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30 30:30 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_ENABLE (0x00000001) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31 31:31 +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_DISABLE (0x00000000) +#define NVC37E_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_ENABLE (0x00000001) +#endif // _clC37e_h From 941522b7fe641c276b3dcc430f34908a26b64789 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sat, 20 Jun 2020 11:17:59 +1000 Subject: [PATCH 097/145] drm/nouveau/kms/nv50-: use NVIDIA's headers for wndw sema_clr() Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/base507c.c | 2 +- drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/base507c.c b/drivers/gpu/drm/nouveau/dispnv50/base507c.c index c6b1f8d70ae2..7dc2b6db1190 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/base507c.c +++ b/drivers/gpu/drm/nouveau/dispnv50/base507c.c @@ -174,7 +174,7 @@ base507c_sema_clr(struct nv50_wndw *wndw) if ((ret = PUSH_WAIT(push, 2))) return ret; - PUSH_NVSQ(push, NV507C, 0x0094, 0x00000000); + PUSH_MTHD(push, NV507C, SET_CONTEXT_DMA_SEMAPHORE, 0x00000000); return 0; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c index a69ddf94ef1f..fdc5d30f4cd4 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c @@ -197,7 +197,7 @@ wndwc37e_sema_clr(struct nv50_wndw *wndw) if ((ret = PUSH_WAIT(push, 2))) return ret; - PUSH_NVSQ(push, NVC37E, 0x0218, 0x00000000); + PUSH_MTHD(push, NVC37E, SET_CONTEXT_DMA_SEMAPHORE, 0x00000000); return 0; } From 0ecaefc14423b86f1fe7b5eda1cc1da001da982b Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sun, 21 Jun 2020 17:04:16 +1000 Subject: [PATCH 098/145] drm/nouveau/kms/nv50-: use NVIDIA's headers for wndw ntfy_reset() Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/base507c.c | 3 +- drivers/gpu/drm/nouveau/dispnv50/ovly827e.c | 11 ++- .../drm/nouveau/include/nvhw/class/cl827e.h | 88 +++++++++++++++++++ drivers/gpu/drm/nouveau/nouveau_bo.h | 12 +++ 4 files changed, 109 insertions(+), 5 deletions(-) create mode 100644 drivers/gpu/drm/nouveau/include/nvhw/class/cl827e.h diff --git a/drivers/gpu/drm/nouveau/dispnv50/base507c.c b/drivers/gpu/drm/nouveau/dispnv50/base507c.c index 7dc2b6db1190..3d31b4c9bc59 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/base507c.c +++ b/drivers/gpu/drm/nouveau/dispnv50/base507c.c @@ -162,7 +162,8 @@ base507c_ntfy_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) void base507c_ntfy_reset(struct nouveau_bo *bo, u32 offset) { - nouveau_bo_wr32(bo, offset / 4, 0x00000000); + NVBO_WR32(bo, offset, NV_DISP_BASE_NOTIFIER_1, _0, + NVDEF(NV_DISP_BASE_NOTIFIER_1, _0, STATUS, NOT_BEGUN)); } int diff --git a/drivers/gpu/drm/nouveau/dispnv50/ovly827e.c b/drivers/gpu/drm/nouveau/dispnv50/ovly827e.c index 40b89f8648c4..199f6ddfccd7 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/ovly827e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/ovly827e.c @@ -27,6 +27,8 @@ #include #include +#include + static int ovly827e_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) { @@ -66,10 +68,11 @@ ovly827e_ntfy_wait_begun(struct nouveau_bo *bo, u32 offset, void ovly827e_ntfy_reset(struct nouveau_bo *bo, u32 offset) { - nouveau_bo_wr32(bo, offset / 4 + 0, 0x00000000); - nouveau_bo_wr32(bo, offset / 4 + 1, 0x00000000); - nouveau_bo_wr32(bo, offset / 4 + 2, 0x00000000); - nouveau_bo_wr32(bo, offset / 4 + 3, 0x80000000); + NVBO_WR32(bo, offset, NV_DISP_NOTIFICATION_1, TIME_STAMP_0, 0); + NVBO_WR32(bo, offset, NV_DISP_NOTIFICATION_1, TIME_STAMP_1, 0); + NVBO_WR32(bo, offset, NV_DISP_NOTIFICATION_1, _2, 0); + NVBO_WR32(bo, offset, NV_DISP_NOTIFICATION_1, _3, + NVDEF(NV_DISP_NOTIFICATION_1, _3, STATUS, NOT_BEGUN)); } static const struct nv50_wndw_func diff --git a/drivers/gpu/drm/nouveau/include/nvhw/class/cl827e.h b/drivers/gpu/drm/nouveau/include/nvhw/class/cl827e.h new file mode 100644 index 000000000000..8cae7a53d14d --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvhw/class/cl827e.h @@ -0,0 +1,88 @@ +/* + * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl827e_h_ +#define _cl827e_h_ + +#define NV_DISP_NOTIFICATION_1 0x00000000 +#define NV_DISP_NOTIFICATION_1_SIZEOF 0x00000010 +#define NV_DISP_NOTIFICATION_1_TIME_STAMP_0 0x00000000 +#define NV_DISP_NOTIFICATION_1_TIME_STAMP_0_NANOSECONDS0 31:0 +#define NV_DISP_NOTIFICATION_1_TIME_STAMP_1 0x00000001 +#define NV_DISP_NOTIFICATION_1_TIME_STAMP_1_NANOSECONDS1 31:0 +#define NV_DISP_NOTIFICATION_1__2 0x00000002 +#define NV_DISP_NOTIFICATION_1__2_AUDIT_TIMESTAMP 31:0 +#define NV_DISP_NOTIFICATION_1__3 0x00000003 +#define NV_DISP_NOTIFICATION_1__3_PRESENT_COUNT 7:0 +#define NV_DISP_NOTIFICATION_1__3_R0 15:8 +#define NV_DISP_NOTIFICATION_1__3_STATUS 31:16 +#define NV_DISP_NOTIFICATION_1__3_STATUS_NOT_BEGUN 0x00008000 +#define NV_DISP_NOTIFICATION_1__3_STATUS_BEGUN 0x0000FFFF +#define NV_DISP_NOTIFICATION_1__3_STATUS_FINISHED 0x00000000 + + +// class methods +#define NV827E_SET_PRESENT_CONTROL (0x00000084) +#define NV827E_SET_PRESENT_CONTROL_BEGIN_MODE 1:0 +#define NV827E_SET_PRESENT_CONTROL_BEGIN_MODE_ASAP (0x00000000) +#define NV827E_SET_PRESENT_CONTROL_BEGIN_MODE_TIMESTAMP (0x00000003) +#define NV827E_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 7:4 +#define NV827E_SET_CONTEXT_DMA_ISO (0x000000C0) +#define NV827E_SET_CONTEXT_DMA_ISO_HANDLE 31:0 +#define NV827E_SET_COMPOSITION_CONTROL (0x00000100) +#define NV827E_SET_COMPOSITION_CONTROL_MODE 3:0 +#define NV827E_SET_COMPOSITION_CONTROL_MODE_SOURCE_COLOR_VALUE_KEYING (0x00000000) +#define NV827E_SET_COMPOSITION_CONTROL_MODE_DESTINATION_COLOR_VALUE_KEYING (0x00000001) +#define NV827E_SET_COMPOSITION_CONTROL_MODE_OPAQUE_SUSPEND_BASE (0x00000002) + +#define NV827E_SURFACE_SET_OFFSET (0x00000800) +#define NV827E_SURFACE_SET_OFFSET_ORIGIN 31:0 +#define NV827E_SURFACE_SET_SIZE (0x00000808) +#define NV827E_SURFACE_SET_SIZE_WIDTH 14:0 +#define NV827E_SURFACE_SET_SIZE_HEIGHT 30:16 +#define NV827E_SURFACE_SET_STORAGE (0x0000080C) +#define NV827E_SURFACE_SET_STORAGE_BLOCK_HEIGHT 3:0 +#define NV827E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB (0x00000000) +#define NV827E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS (0x00000001) +#define NV827E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS (0x00000002) +#define NV827E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003) +#define NV827E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NV827E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NV827E_SURFACE_SET_STORAGE_PITCH 17:8 +#define NV827E_SURFACE_SET_STORAGE_MEMORY_LAYOUT 20:20 +#define NV827E_SURFACE_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NV827E_SURFACE_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001) +#define NV827E_SURFACE_SET_PARAMS (0x00000810) +#define NV827E_SURFACE_SET_PARAMS_FORMAT 15:8 +#define NV827E_SURFACE_SET_PARAMS_FORMAT_VE8YO8UE8YE8 (0x00000028) +#define NV827E_SURFACE_SET_PARAMS_FORMAT_YO8VE8YE8UE8 (0x00000029) +#define NV827E_SURFACE_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1) +#define NV827E_SURFACE_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF) +#define NV827E_SURFACE_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9) +#define NV827E_SURFACE_SET_PARAMS_COLOR_SPACE 1:0 +#define NV827E_SURFACE_SET_PARAMS_COLOR_SPACE_RGB (0x00000000) +#define NV827E_SURFACE_SET_PARAMS_COLOR_SPACE_YUV_601 (0x00000001) +#define NV827E_SURFACE_SET_PARAMS_COLOR_SPACE_YUV_709 (0x00000002) +#define NV827E_SURFACE_SET_PARAMS_RESERVED0 22:16 +#define NV827E_SURFACE_SET_PARAMS_RESERVED1 24:24 +#endif // _cl827e_h diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.h b/drivers/gpu/drm/nouveau/nouveau_bo.h index 951ef6fa76d8..52489ce7d029 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo.h +++ b/drivers/gpu/drm/nouveau/nouveau_bo.h @@ -162,4 +162,16 @@ int nve0_bo_move_init(struct nouveau_channel *, u32); int nve0_bo_move_copy(struct nouveau_channel *, struct ttm_buffer_object *, struct ttm_mem_reg *, struct ttm_mem_reg *); +#define NVBO_WR32_(b,o,dr,f) nouveau_bo_wr32((b), (o)/4 + (dr), (f)) +#define NVBO_RD32_(b,o,dr) nouveau_bo_rd32((b), (o)/4 + (dr)) +#define NVBO_RD32(A...) DRF_RD(NVBO_RD32_, ##A) +#define NVBO_RV32(A...) DRF_RV(NVBO_RD32_, ##A) +#define NVBO_TV32(A...) DRF_TV(NVBO_RD32_, ##A) +#define NVBO_TD32(A...) DRF_TD(NVBO_RD32_, ##A) +#define NVBO_WR32(A...) DRF_WR( NVBO_WR32_, ##A) +#define NVBO_WV32(A...) DRF_WV( NVBO_WR32_, ##A) +#define NVBO_WD32(A...) DRF_WD( NVBO_WR32_, ##A) +#define NVBO_MR32(A...) DRF_MR(NVBO_RD32_, NVBO_WR32_, u32, ##A) +#define NVBO_MV32(A...) DRF_MV(NVBO_RD32_, NVBO_WR32_, u32, ##A) +#define NVBO_MD32(A...) DRF_MD(NVBO_RD32_, NVBO_WR32_, u32, ##A) #endif From d4793bc39f03b7016667779d35a591b4850c9914 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sat, 20 Jun 2020 11:25:25 +1000 Subject: [PATCH 099/145] drm/nouveau/kms/nv50-: use NVIDIA's headers for wndw ntfy_set() Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/base507c.c | 8 +++++--- drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c | 8 +++++--- 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/base507c.c b/drivers/gpu/drm/nouveau/dispnv50/base507c.c index 3d31b4c9bc59..0c03835a658a 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/base507c.c +++ b/drivers/gpu/drm/nouveau/dispnv50/base507c.c @@ -153,9 +153,11 @@ base507c_ntfy_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) if ((ret = PUSH_WAIT(push, 3))) return ret; - PUSH_NVSQ(push, NV507C, 0x00a0, asyw->ntfy.awaken << 30 | - asyw->ntfy.offset, - 0x00a4, asyw->ntfy.handle); + PUSH_MTHD(push, NV507C, SET_NOTIFIER_CONTROL, + NVVAL(NV507C, SET_NOTIFIER_CONTROL, MODE, asyw->ntfy.awaken) | + NVVAL(NV507C, SET_NOTIFIER_CONTROL, OFFSET, asyw->ntfy.offset >> 2), + + SET_CONTEXT_DMA_NOTIFIER, asyw->ntfy.handle); return 0; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c index fdc5d30f4cd4..2325c6420b6b 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c @@ -182,9 +182,11 @@ wndwc37e_ntfy_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) if ((ret = PUSH_WAIT(push, 3))) return ret; - PUSH_NVSQ(push, NVC37E, 0x021c, asyw->ntfy.handle, - 0x0220, asyw->ntfy.offset | - asyw->ntfy.awaken); + PUSH_MTHD(push, NVC37E, SET_CONTEXT_DMA_NOTIFIER, asyw->ntfy.handle, + + SET_NOTIFIER_CONTROL, + NVVAL(NVC37E, SET_NOTIFIER_CONTROL, MODE, asyw->ntfy.awaken) | + NVVAL(NVC37E, SET_NOTIFIER_CONTROL, OFFSET, asyw->ntfy.offset >> 4)); return 0; } From 9562e564abbf3670c5e7dc9b1fcf8d853fb9d850 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sat, 20 Jun 2020 11:26:49 +1000 Subject: [PATCH 100/145] drm/nouveau/kms/nv50-: use NVIDIA's headers for wndw ntfy_clr() Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/base507c.c | 2 +- drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/base507c.c b/drivers/gpu/drm/nouveau/dispnv50/base507c.c index 0c03835a658a..a468fae7da6a 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/base507c.c +++ b/drivers/gpu/drm/nouveau/dispnv50/base507c.c @@ -140,7 +140,7 @@ base507c_ntfy_clr(struct nv50_wndw *wndw) if ((ret = PUSH_WAIT(push, 2))) return ret; - PUSH_NVSQ(push, NV507C, 0x00a4, 0x00000000); + PUSH_MTHD(push, NV507C, SET_CONTEXT_DMA_NOTIFIER, 0x00000000); return 0; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c index 2325c6420b6b..ea6ad60403d7 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c @@ -169,7 +169,7 @@ wndwc37e_ntfy_clr(struct nv50_wndw *wndw) if ((ret = PUSH_WAIT(push, 2))) return ret; - PUSH_NVSQ(push, NVC37E, 0x021c, 0x00000000); + PUSH_MTHD(push, NVC37E, SET_CONTEXT_DMA_NOTIFIER, 0x00000000); return 0; } From 75bd8304e61c01d2bc5df46fcf9c2e9838b3a246 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sun, 21 Jun 2020 17:12:19 +1000 Subject: [PATCH 101/145] drm/nouveau/kms/nv50-: use NVIDIA's headers for wndw ntfy_wait_begun() Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/base507c.c | 3 +-- drivers/gpu/drm/nouveau/dispnv50/ovly827e.c | 3 +-- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/base507c.c b/drivers/gpu/drm/nouveau/dispnv50/base507c.c index a468fae7da6a..412270e4783c 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/base507c.c +++ b/drivers/gpu/drm/nouveau/dispnv50/base507c.c @@ -123,8 +123,7 @@ base507c_ntfy_wait_begun(struct nouveau_bo *bo, u32 offset, struct nvif_device *device) { s64 time = nvif_msec(device, 2000ULL, - u32 data = nouveau_bo_rd32(bo, offset / 4); - if ((data & 0xc0000000) == 0x40000000) + if (NVBO_TD32(bo, offset, NV_DISP_BASE_NOTIFIER_1, _0, STATUS, ==, BEGUN)) break; usleep_range(1, 2); ); diff --git a/drivers/gpu/drm/nouveau/dispnv50/ovly827e.c b/drivers/gpu/drm/nouveau/dispnv50/ovly827e.c index 199f6ddfccd7..63b0047eb34f 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/ovly827e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/ovly827e.c @@ -57,8 +57,7 @@ ovly827e_ntfy_wait_begun(struct nouveau_bo *bo, u32 offset, struct nvif_device *device) { s64 time = nvif_msec(device, 2000ULL, - u32 data = nouveau_bo_rd32(bo, offset / 4 + 3); - if ((data & 0xffff0000) == 0xffff0000) + if (NVBO_TD32(bo, offset, NV_DISP_NOTIFICATION_1, _3, STATUS, ==, BEGUN)) break; usleep_range(1, 2); ); From 84e1d06b06777d76a420d4e5eff5ab1c178bd77a Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sat, 20 Jun 2020 11:35:28 +1000 Subject: [PATCH 102/145] drm/nouveau/kms/nv50-: use NVIDIA's headers for wndw csc_set() Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/base907c.c | 9 +- drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c | 2 +- drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c | 4 +- .../drm/nouveau/include/nvhw/class/cl907c.h | 143 ++++++++++++++++++ .../drm/nouveau/include/nvhw/class/clc57e.h | 142 +++++++++++++++++ 5 files changed, 296 insertions(+), 4 deletions(-) create mode 100644 drivers/gpu/drm/nouveau/include/nvhw/class/cl907c.h create mode 100644 drivers/gpu/drm/nouveau/include/nvhw/class/clc57e.h diff --git a/drivers/gpu/drm/nouveau/dispnv50/base907c.c b/drivers/gpu/drm/nouveau/dispnv50/base907c.c index c88a924d7d09..0c490291d014 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/base907c.c +++ b/drivers/gpu/drm/nouveau/dispnv50/base907c.c @@ -23,6 +23,8 @@ #include +#include + static int base907c_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) { @@ -150,8 +152,11 @@ base907c_csc_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) if ((ret = PUSH_WAIT(push, 13))) return ret; - PUSH_NVSQ(push, NV907C, 0x0140, asyw->csc.matrix[0] | 0x80000000, - 0x0144, &asyw->csc.matrix[1], 11); + PUSH_MTHD(push, NV907C, SET_CSC_RED2RED, + NVDEF(NV907C, SET_CSC_RED2RED, OWNER, BASE) | + NVVAL(NV907C, SET_CSC_RED2RED, COEFF, asyw->csc.matrix[0]), + + SET_CSC_GRN2RED, &asyw->csc.matrix[1], 11); return 0; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c index ea6ad60403d7..b72170dab87a 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c @@ -46,7 +46,7 @@ wndwc37e_csc_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) if ((ret = PUSH_WAIT(push, 13))) return ret; - PUSH_NVSQ(push, NVC37E, 0x02bc, asyw->csc.matrix, 12); + PUSH_MTHD(push, NVC37E, SET_CSC_RED2RED, asyw->csc.matrix, 12); return 0; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c b/drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c index 687cb7378c69..d2efbccbaf3f 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c @@ -29,6 +29,8 @@ #include #include +#include + static int wndwc57e_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) { @@ -85,7 +87,7 @@ wndwc57e_csc_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) if ((ret = PUSH_WAIT(push, 13))) return ret; - PUSH_NVSQ(push, NVC57E, 0x0400, asyw->csc.matrix, 12); + PUSH_MTHD(push, NVC57E, SET_FMT_COEFFICIENT_C00, asyw->csc.matrix, 12); return 0; } diff --git a/drivers/gpu/drm/nouveau/include/nvhw/class/cl907c.h b/drivers/gpu/drm/nouveau/include/nvhw/class/cl907c.h new file mode 100644 index 000000000000..77366a2c89ac --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvhw/class/cl907c.h @@ -0,0 +1,143 @@ +/* + * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl907c_h_ +#define _cl907c_h_ + +// class methods +#define NV907C_SET_PRESENT_CONTROL (0x00000084) +#define NV907C_SET_PRESENT_CONTROL_BEGIN_MODE 9:8 +#define NV907C_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING (0x00000000) +#define NV907C_SET_PRESENT_CONTROL_BEGIN_MODE_IMMEDIATE (0x00000001) +#define NV907C_SET_PRESENT_CONTROL_BEGIN_MODE_ON_LINE (0x00000002) +#define NV907C_SET_PRESENT_CONTROL_BEGIN_MODE_AT_FRAME (0x00000003) +#define NV907C_SET_PRESENT_CONTROL_TIMESTAMP_MODE 2:2 +#define NV907C_SET_PRESENT_CONTROL_TIMESTAMP_MODE_DISABLE (0x00000000) +#define NV907C_SET_PRESENT_CONTROL_TIMESTAMP_MODE_ENABLE (0x00000001) +#define NV907C_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 7:4 +#define NV907C_SET_PRESENT_CONTROL_BEGIN_LINE 30:16 +#define NV907C_SET_PRESENT_CONTROL_ON_LINE_MARGIN 15:10 +#define NV907C_SET_CONTEXT_DMAS_ISO(b) (0x000000C0 + (b)*0x00000004) +#define NV907C_SET_CONTEXT_DMAS_ISO_HANDLE 31:0 +#define NV907C_SET_BASE_LUT_LO (0x000000E0) +#define NV907C_SET_BASE_LUT_LO_ENABLE 31:30 +#define NV907C_SET_BASE_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV907C_SET_BASE_LUT_LO_ENABLE_USE_CORE_LUT (0x00000001) +#define NV907C_SET_BASE_LUT_LO_ENABLE_ENABLE (0x00000002) +#define NV907C_SET_BASE_LUT_LO_MODE 27:24 +#define NV907C_SET_BASE_LUT_LO_MODE_LORES (0x00000000) +#define NV907C_SET_BASE_LUT_LO_MODE_HIRES (0x00000001) +#define NV907C_SET_BASE_LUT_LO_MODE_INDEX_1025_UNITY_RANGE (0x00000003) +#define NV907C_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE (0x00000004) +#define NV907C_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE (0x00000005) +#define NV907C_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE (0x00000006) +#define NV907C_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE (0x00000007) +#define NV907C_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE (0x00000008) +#define NV907C_SET_BASE_LUT_HI (0x000000E4) +#define NV907C_SET_BASE_LUT_HI_ORIGIN 31:0 +#define NV907C_SET_OUTPUT_LUT_LO (0x000000E8) +#define NV907C_SET_OUTPUT_LUT_LO_ENABLE 31:30 +#define NV907C_SET_OUTPUT_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV907C_SET_OUTPUT_LUT_LO_ENABLE_USE_CORE_LUT (0x00000001) +#define NV907C_SET_OUTPUT_LUT_LO_ENABLE_ENABLE (0x00000002) +#define NV907C_SET_OUTPUT_LUT_LO_MODE 27:24 +#define NV907C_SET_OUTPUT_LUT_LO_MODE_LORES (0x00000000) +#define NV907C_SET_OUTPUT_LUT_LO_MODE_HIRES (0x00000001) +#define NV907C_SET_OUTPUT_LUT_LO_MODE_INDEX_1025_UNITY_RANGE (0x00000003) +#define NV907C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE (0x00000004) +#define NV907C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE (0x00000005) +#define NV907C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE (0x00000006) +#define NV907C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE (0x00000007) +#define NV907C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE (0x00000008) +#define NV907C_SET_CONTEXT_DMA_LUT (0x000000FC) +#define NV907C_SET_CONTEXT_DMA_LUT_HANDLE 31:0 +#define NV907C_SET_CSC_RED2RED (0x00000140) +#define NV907C_SET_CSC_RED2RED_OWNER 31:31 +#define NV907C_SET_CSC_RED2RED_OWNER_CORE (0x00000000) +#define NV907C_SET_CSC_RED2RED_OWNER_BASE (0x00000001) +#define NV907C_SET_CSC_RED2RED_COEFF 18:0 +#define NV907C_SET_CSC_GRN2RED (0x00000144) +#define NV907C_SET_CSC_GRN2RED_COEFF 18:0 +#define NV907C_SET_CSC_BLU2RED (0x00000148) +#define NV907C_SET_CSC_BLU2RED_COEFF 18:0 +#define NV907C_SET_CSC_CONSTANT2RED (0x0000014C) +#define NV907C_SET_CSC_CONSTANT2RED_COEFF 18:0 +#define NV907C_SET_CSC_RED2GRN (0x00000150) +#define NV907C_SET_CSC_RED2GRN_COEFF 18:0 +#define NV907C_SET_CSC_GRN2GRN (0x00000154) +#define NV907C_SET_CSC_GRN2GRN_COEFF 18:0 +#define NV907C_SET_CSC_BLU2GRN (0x00000158) +#define NV907C_SET_CSC_BLU2GRN_COEFF 18:0 +#define NV907C_SET_CSC_CONSTANT2GRN (0x0000015C) +#define NV907C_SET_CSC_CONSTANT2GRN_COEFF 18:0 +#define NV907C_SET_CSC_RED2BLU (0x00000160) +#define NV907C_SET_CSC_RED2BLU_COEFF 18:0 +#define NV907C_SET_CSC_GRN2BLU (0x00000164) +#define NV907C_SET_CSC_GRN2BLU_COEFF 18:0 +#define NV907C_SET_CSC_BLU2BLU (0x00000168) +#define NV907C_SET_CSC_BLU2BLU_COEFF 18:0 +#define NV907C_SET_CSC_CONSTANT2BLU (0x0000016C) +#define NV907C_SET_CSC_CONSTANT2BLU_COEFF 18:0 + +#define NV907C_SURFACE_SET_OFFSET(a,b) (0x00000400 + (a)*0x00000020 + (b)*0x00000004) +#define NV907C_SURFACE_SET_OFFSET_ORIGIN 31:0 +#define NV907C_SURFACE_SET_SIZE(a) (0x00000408 + (a)*0x00000020) +#define NV907C_SURFACE_SET_SIZE_WIDTH 15:0 +#define NV907C_SURFACE_SET_SIZE_HEIGHT 31:16 +#define NV907C_SURFACE_SET_STORAGE(a) (0x0000040C + (a)*0x00000020) +#define NV907C_SURFACE_SET_STORAGE_BLOCK_HEIGHT 3:0 +#define NV907C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB (0x00000000) +#define NV907C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS (0x00000001) +#define NV907C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS (0x00000002) +#define NV907C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003) +#define NV907C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NV907C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NV907C_SURFACE_SET_STORAGE_PITCH 20:8 +#define NV907C_SURFACE_SET_STORAGE_MEMORY_LAYOUT 24:24 +#define NV907C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NV907C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001) +#define NV907C_SURFACE_SET_PARAMS(a) (0x00000410 + (a)*0x00000020) +#define NV907C_SURFACE_SET_PARAMS_FORMAT 15:8 +#define NV907C_SURFACE_SET_PARAMS_FORMAT_I8 (0x0000001E) +#define NV907C_SURFACE_SET_PARAMS_FORMAT_VOID16 (0x0000001F) +#define NV907C_SURFACE_SET_PARAMS_FORMAT_VOID32 (0x0000002E) +#define NV907C_SURFACE_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA) +#define NV907C_SURFACE_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF) +#define NV907C_SURFACE_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1) +#define NV907C_SURFACE_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS (0x00000022) +#define NV907C_SURFACE_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5) +#define NV907C_SURFACE_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8) +#define NV907C_SURFACE_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9) +#define NV907C_SURFACE_SET_PARAMS_FORMAT_R16_G16_B16_A16 (0x000000C6) +#define NV907C_SURFACE_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS (0x00000023) +#define NV907C_SURFACE_SET_PARAMS_SUPER_SAMPLE 1:0 +#define NV907C_SURFACE_SET_PARAMS_SUPER_SAMPLE_X1_AA (0x00000000) +#define NV907C_SURFACE_SET_PARAMS_SUPER_SAMPLE_X4_AA (0x00000002) +#define NV907C_SURFACE_SET_PARAMS_GAMMA 2:2 +#define NV907C_SURFACE_SET_PARAMS_GAMMA_LINEAR (0x00000000) +#define NV907C_SURFACE_SET_PARAMS_GAMMA_SRGB (0x00000001) +#define NV907C_SURFACE_SET_PARAMS_LAYOUT 5:4 +#define NV907C_SURFACE_SET_PARAMS_LAYOUT_FRM (0x00000000) +#define NV907C_SURFACE_SET_PARAMS_LAYOUT_FLD1 (0x00000001) +#define NV907C_SURFACE_SET_PARAMS_LAYOUT_FLD2 (0x00000002) +#endif // _cl907c_h diff --git a/drivers/gpu/drm/nouveau/include/nvhw/class/clc57e.h b/drivers/gpu/drm/nouveau/include/nvhw/class/clc57e.h new file mode 100644 index 000000000000..850d16fe438d --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvhw/class/clc57e.h @@ -0,0 +1,142 @@ +/* + * Copyright (c) 1993-2020, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clC57e_h_ +#define _clC57e_h_ + +// class methods +#define NVC57E_SET_SIZE (0x00000224) +#define NVC57E_SET_SIZE_WIDTH 15:0 +#define NVC57E_SET_SIZE_HEIGHT 31:16 +#define NVC57E_SET_STORAGE (0x00000228) +#define NVC57E_SET_STORAGE_BLOCK_HEIGHT 3:0 +#define NVC57E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_ONE_GOB (0x00000000) +#define NVC57E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_TWO_GOBS (0x00000001) +#define NVC57E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_FOUR_GOBS (0x00000002) +#define NVC57E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003) +#define NVC57E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NVC57E_SET_STORAGE_BLOCK_HEIGHT_NVD_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NVC57E_SET_STORAGE_MEMORY_LAYOUT 4:4 +#define NVC57E_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVC57E_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVC57E_SET_PARAMS (0x0000022C) +#define NVC57E_SET_PARAMS_FORMAT 7:0 +#define NVC57E_SET_PARAMS_FORMAT_I8 (0x0000001E) +#define NVC57E_SET_PARAMS_FORMAT_R4G4B4A4 (0x0000002F) +#define NVC57E_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8) +#define NVC57E_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9) +#define NVC57E_SET_PARAMS_FORMAT_R5G5B5A1 (0x0000002E) +#define NVC57E_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF) +#define NVC57E_SET_PARAMS_FORMAT_X8R8G8B8 (0x000000E6) +#define NVC57E_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5) +#define NVC57E_SET_PARAMS_FORMAT_X8B8G8R8 (0x000000F9) +#define NVC57E_SET_PARAMS_FORMAT_A2R10G10B10 (0x000000DF) +#define NVC57E_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1) +#define NVC57E_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS (0x00000022) +#define NVC57E_SET_PARAMS_FORMAT_X2BL10GL10RL10_XVYCC (0x00000024) +#define NVC57E_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS (0x00000023) +#define NVC57E_SET_PARAMS_FORMAT_R16_G16_B16_A16 (0x000000C6) +#define NVC57E_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA) +#define NVC57E_SET_PARAMS_FORMAT_Y8_U8__Y8_V8_N422 (0x00000028) +#define NVC57E_SET_PARAMS_FORMAT_U8_Y8__V8_Y8_N422 (0x00000029) +#define NVC57E_SET_PARAMS_FORMAT_Y8___U8V8_N444 (0x00000035) +#define NVC57E_SET_PARAMS_FORMAT_Y8___U8V8_N422 (0x00000036) +#define NVC57E_SET_PARAMS_FORMAT_Y8___V8U8_N420 (0x00000038) +#define NVC57E_SET_PARAMS_FORMAT_Y10___U10V10_N444 (0x00000055) +#define NVC57E_SET_PARAMS_FORMAT_Y10___U10V10_N422 (0x00000056) +#define NVC57E_SET_PARAMS_FORMAT_Y10___V10U10_N420 (0x00000058) +#define NVC57E_SET_PARAMS_FORMAT_Y12___U12V12_N444 (0x00000075) +#define NVC57E_SET_PARAMS_FORMAT_Y12___U12V12_N422 (0x00000076) +#define NVC57E_SET_PARAMS_FORMAT_Y12___V12U12_N420 (0x00000078) +#define NVC57E_SET_PARAMS_CLAMP_BEFORE_BLEND 18:18 +#define NVC57E_SET_PARAMS_CLAMP_BEFORE_BLEND_DISABLE (0x00000000) +#define NVC57E_SET_PARAMS_CLAMP_BEFORE_BLEND_ENABLE (0x00000001) +#define NVC57E_SET_PARAMS_SWAP_UV 19:19 +#define NVC57E_SET_PARAMS_SWAP_UV_DISABLE (0x00000000) +#define NVC57E_SET_PARAMS_SWAP_UV_ENABLE (0x00000001) +#define NVC57E_SET_PARAMS_FMT_ROUNDING_MODE 22:22 +#define NVC57E_SET_PARAMS_FMT_ROUNDING_MODE_ROUND_TO_NEAREST (0x00000000) +#define NVC57E_SET_PARAMS_FMT_ROUNDING_MODE_ROUND_DOWN (0x00000001) +#define NVC57E_SET_PLANAR_STORAGE(b) (0x00000230 + (b)*0x00000004) +#define NVC57E_SET_PLANAR_STORAGE_PITCH 12:0 +#define NVC57E_SET_CONTEXT_DMA_ISO(b) (0x00000240 + (b)*0x00000004) +#define NVC57E_SET_CONTEXT_DMA_ISO_HANDLE 31:0 +#define NVC57E_SET_OFFSET(b) (0x00000260 + (b)*0x00000004) +#define NVC57E_SET_OFFSET_ORIGIN 31:0 +#define NVC57E_SET_POINT_IN(b) (0x00000290 + (b)*0x00000004) +#define NVC57E_SET_POINT_IN_X 15:0 +#define NVC57E_SET_POINT_IN_Y 31:16 +#define NVC57E_SET_SIZE_IN (0x00000298) +#define NVC57E_SET_SIZE_IN_WIDTH 15:0 +#define NVC57E_SET_SIZE_IN_HEIGHT 31:16 +#define NVC57E_SET_SIZE_OUT (0x000002A4) +#define NVC57E_SET_SIZE_OUT_WIDTH 15:0 +#define NVC57E_SET_SIZE_OUT_HEIGHT 31:16 +#define NVC57E_SET_PRESENT_CONTROL (0x00000308) +#define NVC57E_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 3:0 +#define NVC57E_SET_PRESENT_CONTROL_BEGIN_MODE 6:4 +#define NVC57E_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING (0x00000000) +#define NVC57E_SET_PRESENT_CONTROL_BEGIN_MODE_IMMEDIATE (0x00000001) +#define NVC57E_SET_PRESENT_CONTROL_TIMESTAMP_MODE 8:8 +#define NVC57E_SET_PRESENT_CONTROL_TIMESTAMP_MODE_DISABLE (0x00000000) +#define NVC57E_SET_PRESENT_CONTROL_TIMESTAMP_MODE_ENABLE (0x00000001) +#define NVC57E_SET_FMT_COEFFICIENT_C00 (0x00000400) +#define NVC57E_SET_FMT_COEFFICIENT_C00_VALUE 20:0 +#define NVC57E_SET_FMT_COEFFICIENT_C01 (0x00000404) +#define NVC57E_SET_FMT_COEFFICIENT_C01_VALUE 20:0 +#define NVC57E_SET_FMT_COEFFICIENT_C02 (0x00000408) +#define NVC57E_SET_FMT_COEFFICIENT_C02_VALUE 20:0 +#define NVC57E_SET_FMT_COEFFICIENT_C03 (0x0000040C) +#define NVC57E_SET_FMT_COEFFICIENT_C03_VALUE 20:0 +#define NVC57E_SET_FMT_COEFFICIENT_C10 (0x00000410) +#define NVC57E_SET_FMT_COEFFICIENT_C10_VALUE 20:0 +#define NVC57E_SET_FMT_COEFFICIENT_C11 (0x00000414) +#define NVC57E_SET_FMT_COEFFICIENT_C11_VALUE 20:0 +#define NVC57E_SET_FMT_COEFFICIENT_C12 (0x00000418) +#define NVC57E_SET_FMT_COEFFICIENT_C12_VALUE 20:0 +#define NVC57E_SET_FMT_COEFFICIENT_C13 (0x0000041C) +#define NVC57E_SET_FMT_COEFFICIENT_C13_VALUE 20:0 +#define NVC57E_SET_FMT_COEFFICIENT_C20 (0x00000420) +#define NVC57E_SET_FMT_COEFFICIENT_C20_VALUE 20:0 +#define NVC57E_SET_FMT_COEFFICIENT_C21 (0x00000424) +#define NVC57E_SET_FMT_COEFFICIENT_C21_VALUE 20:0 +#define NVC57E_SET_FMT_COEFFICIENT_C22 (0x00000428) +#define NVC57E_SET_FMT_COEFFICIENT_C22_VALUE 20:0 +#define NVC57E_SET_FMT_COEFFICIENT_C23 (0x0000042C) +#define NVC57E_SET_FMT_COEFFICIENT_C23_VALUE 20:0 +#define NVC57E_SET_ILUT_CONTROL (0x00000440) +#define NVC57E_SET_ILUT_CONTROL_INTERPOLATE 0:0 +#define NVC57E_SET_ILUT_CONTROL_INTERPOLATE_DISABLE (0x00000000) +#define NVC57E_SET_ILUT_CONTROL_INTERPOLATE_ENABLE (0x00000001) +#define NVC57E_SET_ILUT_CONTROL_MIRROR 1:1 +#define NVC57E_SET_ILUT_CONTROL_MIRROR_DISABLE (0x00000000) +#define NVC57E_SET_ILUT_CONTROL_MIRROR_ENABLE (0x00000001) +#define NVC57E_SET_ILUT_CONTROL_MODE 3:2 +#define NVC57E_SET_ILUT_CONTROL_MODE_SEGMENTED (0x00000000) +#define NVC57E_SET_ILUT_CONTROL_MODE_DIRECT8 (0x00000001) +#define NVC57E_SET_ILUT_CONTROL_MODE_DIRECT10 (0x00000002) +#define NVC57E_SET_ILUT_CONTROL_SIZE 18:8 +#define NVC57E_SET_CONTEXT_DMA_ILUT (0x00000444) +#define NVC57E_SET_CONTEXT_DMA_ILUT_HANDLE 31:0 +#define NVC57E_SET_OFFSET_ILUT (0x00000448) +#define NVC57E_SET_OFFSET_ILUT_ORIGIN 31:0 +#endif // _clC57e_h From 2740edb3c640e7a13fdfe752bb17154fd824f28d Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sat, 20 Jun 2020 11:36:58 +1000 Subject: [PATCH 103/145] drm/nouveau/kms/nv50-: use NVIDIA's headers for wndw csc_clr() Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/base907c.c | 3 ++- drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/base907c.c b/drivers/gpu/drm/nouveau/dispnv50/base907c.c index 0c490291d014..e962234f62d6 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/base907c.c +++ b/drivers/gpu/drm/nouveau/dispnv50/base907c.c @@ -139,7 +139,8 @@ base907c_csc_clr(struct nv50_wndw *wndw) if ((ret = PUSH_WAIT(push, 2))) return ret; - PUSH_NVSQ(push, NV907C, 0x0140, 0x00000000); + PUSH_MTHD(push, NV907C, SET_CSC_RED2RED, + NVDEF(NV907C, SET_CSC_RED2RED, OWNER, CORE)); return 0; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c b/drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c index d2efbccbaf3f..1da5ffbae4eb 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c @@ -74,7 +74,7 @@ wndwc57e_csc_clr(struct nv50_wndw *wndw) if ((ret = PUSH_WAIT(push, 1 + ARRAY_SIZE(identity)))) return ret; - PUSH_NVSQ(push, NVC57E, 0x0400, identity, ARRAY_SIZE(identity)); + PUSH_MTHD(push, NVC57E, SET_FMT_COEFFICIENT_C00, identity, ARRAY_SIZE(identity)); return 0; } From 6833d2a0c778252929805fabfdc89e4e181fcb82 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sat, 20 Jun 2020 11:52:44 +1000 Subject: [PATCH 104/145] drm/nouveau/kms/nv50-: use NVIDIA's headers for wndw xlut_set() Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/base507c.c | 3 ++- drivers/gpu/drm/nouveau/dispnv50/base907c.c | 23 ++++++++++++++------ drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c | 20 +++++++++-------- drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c | 24 +++++++++++---------- 4 files changed, 42 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/base507c.c b/drivers/gpu/drm/nouveau/dispnv50/base507c.c index 412270e4783c..d497bd0b84d3 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/base507c.c +++ b/drivers/gpu/drm/nouveau/dispnv50/base507c.c @@ -114,7 +114,8 @@ base507c_xlut_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) if ((ret = PUSH_WAIT(push, 2))) return ret; - PUSH_NVSQ(push, NV507C, 0x00e0, 0x40000000); + PUSH_MTHD(push, NV507C, SET_BASE_LUT_LO, + NVDEF(NV507C, SET_BASE_LUT_LO, ENABLE, USE_CORE_LUT)); return 0; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/base907c.c b/drivers/gpu/drm/nouveau/dispnv50/base907c.c index e962234f62d6..2fb033c623e9 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/base907c.c +++ b/drivers/gpu/drm/nouveau/dispnv50/base907c.c @@ -72,11 +72,16 @@ base907c_xlut_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) if ((ret = PUSH_WAIT(push, 6))) return ret; - PUSH_NVSQ(push, NV907C, 0x00e0, asyw->xlut.i.enable << 30 | - asyw->xlut.i.mode << 24, - 0x00e4, asyw->xlut.i.offset >> 8, - 0x00e8, 0x40000000); - PUSH_NVSQ(push, NV907C, 0x00fc, asyw->xlut.handle); + PUSH_MTHD(push, NV907C, SET_BASE_LUT_LO, + NVVAL(NV907C, SET_BASE_LUT_LO, ENABLE, asyw->xlut.i.enable) | + NVVAL(NV907C, SET_BASE_LUT_LO, MODE, asyw->xlut.i.mode), + + SET_BASE_LUT_HI, asyw->xlut.i.offset >> 8, + + SET_OUTPUT_LUT_LO, + NVDEF(NV907C, SET_OUTPUT_LUT_LO, ENABLE, USE_CORE_LUT)); + + PUSH_MTHD(push, NV907C, SET_CONTEXT_DMA_LUT, asyw->xlut.handle); return 0; } @@ -86,8 +91,12 @@ base907c_ilut(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw, int size) if (size != 256 && size != 1024) return false; - asyw->xlut.i.mode = size == 1024 ? 4 : 7; - asyw->xlut.i.enable = 2; + if (size == 1024) + asyw->xlut.i.mode = NV907C_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE; + else + asyw->xlut.i.mode = NV907C_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE; + + asyw->xlut.i.enable = NV907C_SET_BASE_LUT_LO_ENABLE_ENABLE; asyw->xlut.i.load = head907d_olut_load; return true; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c index b72170dab87a..942b68ee4c75 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c @@ -72,11 +72,13 @@ wndwc37e_ilut_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) if ((ret = PUSH_WAIT(push, 4))) return ret; - PUSH_NVSQ(push, NVC37E, 0x02b0, asyw->xlut.i.output_mode << 8 | - asyw->xlut.i.range << 4 | - asyw->xlut.i.size, - 0x02b4, asyw->xlut.i.offset >> 8, - 0x02b8, asyw->xlut.handle); + PUSH_MTHD(push, NVC37E, SET_CONTROL_INPUT_LUT, + NVVAL(NVC37E, SET_CONTROL_INPUT_LUT, OUTPUT_MODE, asyw->xlut.i.output_mode) | + NVVAL(NVC37E, SET_CONTROL_INPUT_LUT, RANGE, asyw->xlut.i.range) | + NVVAL(NVC37E, SET_CONTROL_INPUT_LUT, SIZE, asyw->xlut.i.size), + + SET_OFFSET_INPUT_LUT, asyw->xlut.i.offset >> 8, + SET_CONTEXT_DMA_INPUT_LUT, asyw->xlut.handle); return 0; } @@ -86,10 +88,10 @@ wndwc37e_ilut(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw, int size) if (size != 256 && size != 1024) return false; - asyw->xlut.i.mode = 2; - asyw->xlut.i.size = size == 1024 ? 2 : 0; - asyw->xlut.i.range = 0; - asyw->xlut.i.output_mode = 1; + asyw->xlut.i.size = size == 1024 ? NVC37E_SET_CONTROL_INPUT_LUT_SIZE_SIZE_1025 : + NVC37E_SET_CONTROL_INPUT_LUT_SIZE_SIZE_257; + asyw->xlut.i.range = NVC37E_SET_CONTROL_INPUT_LUT_RANGE_UNITY; + asyw->xlut.i.output_mode = NVC37E_SET_CONTROL_INPUT_LUT_OUTPUT_MODE_INTERPOLATE; asyw->xlut.i.load = head907d_olut_load; return true; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c b/drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c index 1da5ffbae4eb..86c50ed224cc 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c @@ -113,11 +113,13 @@ wndwc57e_ilut_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) if ((ret = PUSH_WAIT(push, 4))) return ret; - PUSH_NVSQ(push, NVC57E, 0x0440, asyw->xlut.i.size << 8 | - asyw->xlut.i.mode << 2 | - asyw->xlut.i.output_mode, - 0x0444, asyw->xlut.handle, - 0x0448, asyw->xlut.i.offset >> 8); + PUSH_MTHD(push, NVC57E, SET_ILUT_CONTROL, + NVVAL(NVC57E, SET_ILUT_CONTROL, SIZE, asyw->xlut.i.size) | + NVVAL(NVC57E, SET_ILUT_CONTROL, MODE, asyw->xlut.i.mode) | + NVVAL(NVC57E, SET_ILUT_CONTROL, INTERPOLATE, asyw->xlut.i.output_mode), + + SET_CONTEXT_DMA_ILUT, asyw->xlut.handle, + SET_OFFSET_ILUT, asyw->xlut.i.offset >> 8); return 0; } @@ -163,13 +165,13 @@ wndwc57e_ilut(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw, int size) if (size = size ? size : 1024, size != 256 && size != 1024) return false; - if (size == 256) { - asyw->xlut.i.mode = 1; /* DIRECT8. */ - } else { - asyw->xlut.i.mode = 2; /* DIRECT10. */ - } + if (size == 256) + asyw->xlut.i.mode = NVC57E_SET_ILUT_CONTROL_MODE_DIRECT8; + else + asyw->xlut.i.mode = NVC57E_SET_ILUT_CONTROL_MODE_DIRECT10; + asyw->xlut.i.size = 4 /* VSS header. */ + size + 1 /* Entries. */; - asyw->xlut.i.output_mode = 0; /* INTERPOLATE_DISABLE. */ + asyw->xlut.i.output_mode = NVC57E_SET_ILUT_CONTROL_INTERPOLATE_DISABLE; asyw->xlut.i.load = wndwc57e_ilut_load; return true; } From 66f7b7bddfe60a708c7711e47c95d20db05e2110 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sat, 20 Jun 2020 11:58:58 +1000 Subject: [PATCH 105/145] drm/nouveau/kms/nv50-: use NVIDIA's headers for wndw xlut_clr() Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/base507c.c | 3 ++- drivers/gpu/drm/nouveau/dispnv50/base907c.c | 10 +++++++--- drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c | 2 +- drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c | 2 +- 4 files changed, 11 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/base507c.c b/drivers/gpu/drm/nouveau/dispnv50/base507c.c index d497bd0b84d3..3f98f7f2f504 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/base507c.c +++ b/drivers/gpu/drm/nouveau/dispnv50/base507c.c @@ -101,7 +101,8 @@ base507c_xlut_clr(struct nv50_wndw *wndw) if ((ret = PUSH_WAIT(push, 2))) return ret; - PUSH_NVSQ(push, NV507C, 0x00e0, 0x00000000); + PUSH_MTHD(push, NV507C, SET_BASE_LUT_LO, + NVDEF(NV507C, SET_BASE_LUT_LO, ENABLE, DISABLE)); return 0; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/base907c.c b/drivers/gpu/drm/nouveau/dispnv50/base907c.c index 2fb033c623e9..789d7b7e9667 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/base907c.c +++ b/drivers/gpu/drm/nouveau/dispnv50/base907c.c @@ -57,9 +57,13 @@ base907c_xlut_clr(struct nv50_wndw *wndw) if ((ret = PUSH_WAIT(push, 6))) return ret; - PUSH_NVSQ(push, NV907C, 0x00e0, 0x00000000); - PUSH_NVSQ(push, NV907C, 0x00e8, 0x00000000); - PUSH_NVSQ(push, NV907C, 0x00fc, 0x00000000); + PUSH_MTHD(push, NV907C, SET_BASE_LUT_LO, + NVDEF(NV907C, SET_BASE_LUT_LO, ENABLE, DISABLE)); + + PUSH_MTHD(push, NV907C, SET_OUTPUT_LUT_LO, + NVDEF(NV907C, SET_OUTPUT_LUT_LO, ENABLE, DISABLE)); + + PUSH_MTHD(push, NV907C, SET_CONTEXT_DMA_LUT, 0x00000000); return 0; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c index 942b68ee4c75..d59a3a59e36d 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c @@ -59,7 +59,7 @@ wndwc37e_ilut_clr(struct nv50_wndw *wndw) if ((ret = PUSH_WAIT(push, 2))) return ret; - PUSH_NVSQ(push, NVC37E, 0x02b8, 0x00000000); + PUSH_MTHD(push, NVC37E, SET_CONTEXT_DMA_INPUT_LUT, 0x00000000); return 0; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c b/drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c index 86c50ed224cc..ffe5519f0163 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c @@ -100,7 +100,7 @@ wndwc57e_ilut_clr(struct nv50_wndw *wndw) if ((ret = PUSH_WAIT(push, 2))) return ret; - PUSH_NVSQ(push, NVC57E, 0x0444, 0x00000000); + PUSH_MTHD(push, NVC57E, SET_CONTEXT_DMA_ILUT, 0x00000000); return 0; } From f844eb485eb056ad3b67e49f95cbc6c685a73db4 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sat, 20 Jun 2020 13:08:47 +1000 Subject: [PATCH 106/145] drm/nouveau/kms/nv50-: use NVIDIA's headers for wndw image_set() Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/base507c.c | 52 +++++++---- drivers/gpu/drm/nouveau/dispnv50/base827c.c | 52 +++++++---- drivers/gpu/drm/nouveau/dispnv50/base907c.c | 36 ++++--- drivers/gpu/drm/nouveau/dispnv50/ovly507e.c | 40 +++++--- drivers/gpu/drm/nouveau/dispnv50/ovly827e.c | 35 ++++--- drivers/gpu/drm/nouveau/dispnv50/ovly907e.c | 37 +++++--- drivers/gpu/drm/nouveau/dispnv50/wndw.c | 75 ++++++++++----- drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c | 59 ++++++++---- drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c | 54 +++++++---- .../drm/nouveau/include/nvhw/class/cl507e.h | 93 +++++++++++++++++++ .../drm/nouveau/include/nvhw/class/cl827c.h | 86 +++++++++++++++++ .../drm/nouveau/include/nvhw/class/cl907e.h | 73 +++++++++++++++ 12 files changed, 557 insertions(+), 135 deletions(-) create mode 100644 drivers/gpu/drm/nouveau/include/nvhw/class/cl507e.h create mode 100644 drivers/gpu/drm/nouveau/include/nvhw/class/cl827c.h create mode 100644 drivers/gpu/drm/nouveau/include/nvhw/class/cl907e.h diff --git a/drivers/gpu/drm/nouveau/dispnv50/base507c.c b/drivers/gpu/drm/nouveau/dispnv50/base507c.c index 3f98f7f2f504..fac830cb9eaa 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/base507c.c +++ b/drivers/gpu/drm/nouveau/dispnv50/base507c.c @@ -70,25 +70,43 @@ base507c_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) if ((ret = PUSH_WAIT(push, 13))) return ret; - PUSH_NVSQ(push, NV507C, 0x0084, asyw->image.mode << 8 | - asyw->image.interval << 4); - PUSH_NVSQ(push, NV507C, 0x00c0, asyw->image.handle[0]); - if (asyw->image.format == 0xca) { - PUSH_NVSQ(push, NV507C, 0x0110, 1, - 0x0114, 0x6400); + PUSH_MTHD(push, NV507C, SET_PRESENT_CONTROL, + NVVAL(NV507C, SET_PRESENT_CONTROL, BEGIN_MODE, asyw->image.mode) | + NVVAL(NV507C, SET_PRESENT_CONTROL, MIN_PRESENT_INTERVAL, asyw->image.interval)); + + PUSH_MTHD(push, NV507C, SET_CONTEXT_DMA_ISO, asyw->image.handle[0]); + + if (asyw->image.format == NV507C_SURFACE_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16) { + PUSH_MTHD(push, NV507C, SET_PROCESSING, + NVDEF(NV507C, SET_PROCESSING, USE_GAIN_OFS, ENABLE), + + SET_CONVERSION, + NVVAL(NV507C, SET_CONVERSION, GAIN, 0) | + NVVAL(NV507C, SET_CONVERSION, OFS, 0x64)); } else { - PUSH_NVSQ(push, NV507C, 0x0110, 0, - 0x0114, 0); + PUSH_MTHD(push, NV507C, SET_PROCESSING, + NVDEF(NV507C, SET_PROCESSING, USE_GAIN_OFS, DISABLE)); } - PUSH_NVSQ(push, NV507C, 0x0800, asyw->image.offset[0] >> 8, - 0x0804, 0x00000000, - 0x0808, asyw->image.h << 16 | asyw->image.w, - 0x080c, asyw->image.layout << 20 | - (asyw->image.pitch[0] >> 8) << 8 | - asyw->image.blocks[0] << 8 | - asyw->image.blockh, - 0x0810, asyw->image.kind << 16 | - asyw->image.format << 8); + + PUSH_MTHD(push, NV507C, SURFACE_SET_OFFSET(0, 0), asyw->image.offset[0] >> 8); + + PUSH_MTHD(push, NV507C, SURFACE_SET_SIZE(0), + NVVAL(NV507C, SURFACE_SET_SIZE, WIDTH, asyw->image.w) | + NVVAL(NV507C, SURFACE_SET_SIZE, HEIGHT, asyw->image.h), + + SURFACE_SET_STORAGE(0), + NVVAL(NV507C, SURFACE_SET_STORAGE, MEMORY_LAYOUT, asyw->image.layout) | + NVVAL(NV507C, SURFACE_SET_STORAGE, PITCH, asyw->image.pitch[0] >> 8) | + NVVAL(NV507C, SURFACE_SET_STORAGE, PITCH, asyw->image.blocks[0]) | + NVVAL(NV507C, SURFACE_SET_STORAGE, BLOCK_HEIGHT, asyw->image.blockh), + + SURFACE_SET_PARAMS(0), + NVVAL(NV507C, SURFACE_SET_PARAMS, FORMAT, asyw->image.format) | + NVDEF(NV507C, SURFACE_SET_PARAMS, SUPER_SAMPLE, X1_AA) | + NVDEF(NV507C, SURFACE_SET_PARAMS, GAMMA, LINEAR) | + NVDEF(NV507C, SURFACE_SET_PARAMS, LAYOUT, FRM) | + NVVAL(NV507C, SURFACE_SET_PARAMS, KIND, asyw->image.kind) | + NVDEF(NV507C, SURFACE_SET_PARAMS, PART_STRIDE, PARTSTRIDE_256)); return 0; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/base827c.c b/drivers/gpu/drm/nouveau/dispnv50/base827c.c index c1995194aa7b..18d34096f125 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/base827c.c +++ b/drivers/gpu/drm/nouveau/dispnv50/base827c.c @@ -23,6 +23,8 @@ #include +#include + static int base827c_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) { @@ -32,24 +34,42 @@ base827c_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) if ((ret = PUSH_WAIT(push, 13))) return ret; - PUSH_NVSQ(push, NV827C, 0x0084, asyw->image.mode << 8 | - asyw->image.interval << 4); - PUSH_NVSQ(push, NV827C, 0x00c0, asyw->image.handle[0]); - if (asyw->image.format == 0xca) { - PUSH_NVSQ(push, NV827C, 0x0110, 1, - 0x0114, 0x6400); + PUSH_MTHD(push, NV827C, SET_PRESENT_CONTROL, + NVVAL(NV827C, SET_PRESENT_CONTROL, BEGIN_MODE, asyw->image.mode) | + NVVAL(NV827C, SET_PRESENT_CONTROL, MIN_PRESENT_INTERVAL, asyw->image.interval)); + + PUSH_MTHD(push, NV827C, SET_CONTEXT_DMAS_ISO(0), asyw->image.handle, 1); + + if (asyw->image.format == NV827C_SURFACE_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16) { + PUSH_MTHD(push, NV827C, SET_PROCESSING, + NVDEF(NV827C, SET_PROCESSING, USE_GAIN_OFS, ENABLE), + + SET_CONVERSION, + NVVAL(NV827C, SET_CONVERSION, GAIN, 0) | + NVVAL(NV827C, SET_CONVERSION, OFS, 0x64)); } else { - PUSH_NVSQ(push, NV827C, 0x0110, 0, - 0x0114, 0); + PUSH_MTHD(push, NV827C, SET_PROCESSING, + NVDEF(NV827C, SET_PROCESSING, USE_GAIN_OFS, DISABLE)); } - PUSH_NVSQ(push, NV827C, 0x0800, asyw->image.offset[0] >> 8, - 0x0804, 0x00000000, - 0x0808, asyw->image.h << 16 | asyw->image.w, - 0x080c, asyw->image.layout << 20 | - (asyw->image.pitch[0] >> 8) << 8 | - asyw->image.blocks[0] << 8 | - asyw->image.blockh, - 0x0810, asyw->image.format << 8); + + PUSH_MTHD(push, NV827C, SURFACE_SET_OFFSET(0, 0), asyw->image.offset[0] >> 8, + SURFACE_SET_OFFSET(0, 1), 0x00000000, + + SURFACE_SET_SIZE(0), + NVVAL(NV827C, SURFACE_SET_SIZE, WIDTH, asyw->image.w) | + NVVAL(NV827C, SURFACE_SET_SIZE, HEIGHT, asyw->image.h), + + SURFACE_SET_STORAGE(0), + NVVAL(NV827C, SURFACE_SET_STORAGE, BLOCK_HEIGHT, asyw->image.blockh) | + NVVAL(NV827C, SURFACE_SET_STORAGE, PITCH, asyw->image.pitch[0] >> 8) | + NVVAL(NV827C, SURFACE_SET_STORAGE, PITCH, asyw->image.blocks[0]) | + NVVAL(NV827C, SURFACE_SET_STORAGE, MEMORY_LAYOUT, asyw->image.layout), + + SURFACE_SET_PARAMS(0), + NVVAL(NV827C, SURFACE_SET_PARAMS, FORMAT, asyw->image.format) | + NVDEF(NV827C, SURFACE_SET_PARAMS, SUPER_SAMPLE, X1_AA) | + NVDEF(NV827C, SURFACE_SET_PARAMS, GAMMA, LINEAR) | + NVDEF(NV827C, SURFACE_SET_PARAMS, LAYOUT, FRM)); return 0; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/base907c.c b/drivers/gpu/drm/nouveau/dispnv50/base907c.c index 789d7b7e9667..5396e3707cc4 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/base907c.c +++ b/drivers/gpu/drm/nouveau/dispnv50/base907c.c @@ -34,17 +34,31 @@ base907c_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) if ((ret = PUSH_WAIT(push, 10))) return ret; - PUSH_NVSQ(push, NV907C, 0x0084, asyw->image.mode << 8 | - asyw->image.interval << 4); - PUSH_NVSQ(push, NV907C, 0x00c0, asyw->image.handle[0]); - PUSH_NVSQ(push, NV907C, 0x0400, asyw->image.offset[0] >> 8, - 0x0404, 0x00000000, - 0x0408, asyw->image.h << 16 | asyw->image.w, - 0x040c, asyw->image.layout << 24 | - (asyw->image.pitch[0] >> 8) << 8 | - asyw->image.blocks[0] << 8 | - asyw->image.blockh, - 0x0410, asyw->image.format << 8); + PUSH_MTHD(push, NV907C, SET_PRESENT_CONTROL, + NVVAL(NV907C, SET_PRESENT_CONTROL, BEGIN_MODE, asyw->image.mode) | + NVDEF(NV907C, SET_PRESENT_CONTROL, TIMESTAMP_MODE, DISABLE) | + NVVAL(NV907C, SET_PRESENT_CONTROL, MIN_PRESENT_INTERVAL, asyw->image.interval)); + + PUSH_MTHD(push, NV907C, SET_CONTEXT_DMAS_ISO(0), asyw->image.handle, 1); + + PUSH_MTHD(push, NV907C, SURFACE_SET_OFFSET(0, 0), asyw->image.offset[0] >> 8, + SURFACE_SET_OFFSET(0, 1), 0x00000000, + + SURFACE_SET_SIZE(0), + NVVAL(NV907C, SURFACE_SET_SIZE, WIDTH, asyw->image.w) | + NVVAL(NV907C, SURFACE_SET_SIZE, HEIGHT, asyw->image.h), + + SURFACE_SET_STORAGE(0), + NVVAL(NV907C, SURFACE_SET_STORAGE, BLOCK_HEIGHT, asyw->image.blockh) | + NVVAL(NV907C, SURFACE_SET_STORAGE, PITCH, asyw->image.pitch[0] >> 8) | + NVVAL(NV907C, SURFACE_SET_STORAGE, PITCH, asyw->image.blocks[0]) | + NVVAL(NV907C, SURFACE_SET_STORAGE, MEMORY_LAYOUT, asyw->image.layout), + + SURFACE_SET_PARAMS(0), + NVVAL(NV907C, SURFACE_SET_PARAMS, FORMAT, asyw->image.format) | + NVDEF(NV907C, SURFACE_SET_PARAMS, SUPER_SAMPLE, X1_AA) | + NVDEF(NV907C, SURFACE_SET_PARAMS, GAMMA, LINEAR) | + NVDEF(NV907C, SURFACE_SET_PARAMS, LAYOUT, FRM)); return 0; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/ovly507e.c b/drivers/gpu/drm/nouveau/dispnv50/ovly507e.c index b46c95e71e49..5369080d97f3 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/ovly507e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/ovly507e.c @@ -30,6 +30,8 @@ #include #include +#include + int ovly507e_scale_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) { @@ -54,18 +56,32 @@ ovly507e_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) if ((ret = PUSH_WAIT(push, 12))) return ret; - PUSH_NVSQ(push, NV507E, 0x0084, asyw->image.interval << 4); - PUSH_NVSQ(push, NV507E, 0x00c0, asyw->image.handle[0]); - PUSH_NVSQ(push, NV507E, 0x0100, 0x00000002); - PUSH_NVSQ(push, NV507E, 0x0800, asyw->image.offset[0] >> 8); - PUSH_NVSQ(push, NV507E, 0x0808, asyw->image.h << 16 | asyw->image.w, - 0x080c, asyw->image.layout << 20 | - (asyw->image.pitch[0] >> 8) << 8 | - asyw->image.blocks[0] << 8 | - asyw->image.blockh, - 0x0810, asyw->image.kind << 16 | - asyw->image.format << 8 | - asyw->image.colorspace); + PUSH_MTHD(push, NV507E, SET_PRESENT_CONTROL, + NVDEF(NV507E, SET_PRESENT_CONTROL, BEGIN_MODE, ASAP) | + NVVAL(NV507E, SET_PRESENT_CONTROL, MIN_PRESENT_INTERVAL, asyw->image.interval)); + + PUSH_MTHD(push, NV507E, SET_CONTEXT_DMA_ISO, asyw->image.handle[0]); + + PUSH_MTHD(push, NV507E, SET_COMPOSITION_CONTROL, + NVDEF(NV507E, SET_COMPOSITION_CONTROL, MODE, OPAQUE_SUSPEND_BASE)); + + PUSH_MTHD(push, NV507E, SURFACE_SET_OFFSET, asyw->image.offset[0] >> 8); + + PUSH_MTHD(push, NV507E, SURFACE_SET_SIZE, + NVVAL(NV507E, SURFACE_SET_SIZE, WIDTH, asyw->image.w) | + NVVAL(NV507E, SURFACE_SET_SIZE, HEIGHT, asyw->image.h), + + SURFACE_SET_STORAGE, + NVVAL(NV507E, SURFACE_SET_STORAGE, BLOCK_HEIGHT, asyw->image.blockh) | + NVVAL(NV507E, SURFACE_SET_STORAGE, PITCH, (asyw->image.pitch[0] >> 8)) | + NVVAL(NV507E, SURFACE_SET_STORAGE, PITCH, asyw->image.blocks[0]) | + NVVAL(NV507E, SURFACE_SET_STORAGE, MEMORY_LAYOUT, asyw->image.layout), + + SURFACE_SET_PARAMS, + NVVAL(NV507E, SURFACE_SET_PARAMS, FORMAT, asyw->image.format) | + NVVAL(NV507E, SURFACE_SET_PARAMS, COLOR_SPACE, asyw->image.colorspace) | + NVVAL(NV507E, SURFACE_SET_PARAMS, KIND, asyw->image.kind) | + NVDEF(NV507E, SURFACE_SET_PARAMS, PART_STRIDE, PARTSTRIDE_256)); return 0; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/ovly827e.c b/drivers/gpu/drm/nouveau/dispnv50/ovly827e.c index 63b0047eb34f..02dc02d9260f 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/ovly827e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/ovly827e.c @@ -38,17 +38,30 @@ ovly827e_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) if ((ret = PUSH_WAIT(push, 12))) return ret; - PUSH_NVSQ(push, NV827E, 0x0084, asyw->image.interval << 4); - PUSH_NVSQ(push, NV827E, 0x00c0, asyw->image.handle[0]); - PUSH_NVSQ(push, NV827E, 0x0100, 0x00000002); - PUSH_NVSQ(push, NV827E, 0x0800, asyw->image.offset[0] >> 8); - PUSH_NVSQ(push, NV827E, 0x0808, asyw->image.h << 16 | asyw->image.w, - 0x080c, asyw->image.layout << 20 | - (asyw->image.pitch[0] >> 8) << 8 | - asyw->image.blocks[0] << 8 | - asyw->image.blockh, - 0x0810, asyw->image.format << 8 | - asyw->image.colorspace); + PUSH_MTHD(push, NV827E, SET_PRESENT_CONTROL, + NVDEF(NV827E, SET_PRESENT_CONTROL, BEGIN_MODE, ASAP) | + NVVAL(NV827E, SET_PRESENT_CONTROL, MIN_PRESENT_INTERVAL, asyw->image.interval)); + + PUSH_MTHD(push, NV827E, SET_CONTEXT_DMA_ISO, asyw->image.handle[0]); + + PUSH_MTHD(push, NV827E, SET_COMPOSITION_CONTROL, + NVDEF(NV827E, SET_COMPOSITION_CONTROL, MODE, OPAQUE_SUSPEND_BASE)); + + PUSH_MTHD(push, NV827E, SURFACE_SET_OFFSET, asyw->image.offset[0] >> 8); + + PUSH_MTHD(push, NV827E, SURFACE_SET_SIZE, + NVVAL(NV827E, SURFACE_SET_SIZE, WIDTH, asyw->image.w) | + NVVAL(NV827E, SURFACE_SET_SIZE, HEIGHT, asyw->image.h), + + SURFACE_SET_STORAGE, + NVVAL(NV827E, SURFACE_SET_STORAGE, BLOCK_HEIGHT, asyw->image.blockh) | + NVVAL(NV827E, SURFACE_SET_STORAGE, PITCH, (asyw->image.pitch[0] >> 8)) | + NVVAL(NV827E, SURFACE_SET_STORAGE, PITCH, asyw->image.blocks[0]) | + NVVAL(NV827E, SURFACE_SET_STORAGE, MEMORY_LAYOUT, asyw->image.layout), + + SURFACE_SET_PARAMS, + NVVAL(NV827E, SURFACE_SET_PARAMS, FORMAT, asyw->image.format) | + NVVAL(NV827E, SURFACE_SET_PARAMS, COLOR_SPACE, asyw->image.colorspace)); return 0; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/ovly907e.c b/drivers/gpu/drm/nouveau/dispnv50/ovly907e.c index b2780f5f6e64..645130d18a99 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/ovly907e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/ovly907e.c @@ -24,6 +24,8 @@ #include +#include + static int ovly907e_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) { @@ -33,17 +35,30 @@ ovly907e_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) if ((ret = PUSH_WAIT(push, 12))) return ret; - PUSH_NVSQ(push, NV907E, 0x0084, asyw->image.interval << 4); - PUSH_NVSQ(push, NV907E, 0x00c0, asyw->image.handle[0]); - PUSH_NVSQ(push, NV907E, 0x0100, 0x00000002); - PUSH_NVSQ(push, NV907E, 0x0400, asyw->image.offset[0] >> 8); - PUSH_NVSQ(push, NV907E, 0x0408, asyw->image.h << 16 | asyw->image.w, - 0x040c, asyw->image.layout << 24 | - (asyw->image.pitch[0] >> 8) << 8 | - asyw->image.blocks[0] << 8 | - asyw->image.blockh, - 0x0410, asyw->image.format << 8 | - asyw->image.colorspace); + PUSH_MTHD(push, NV907E, SET_PRESENT_CONTROL, + NVDEF(NV907E, SET_PRESENT_CONTROL, BEGIN_MODE, ASAP) | + NVVAL(NV907E, SET_PRESENT_CONTROL, MIN_PRESENT_INTERVAL, asyw->image.interval)); + + PUSH_MTHD(push, NV907E, SET_CONTEXT_DMA_ISO, asyw->image.handle[0]); + + PUSH_MTHD(push, NV907E, SET_COMPOSITION_CONTROL, + NVDEF(NV907E, SET_COMPOSITION_CONTROL, MODE, OPAQUE)); + + PUSH_MTHD(push, NV907E, SURFACE_SET_OFFSET, asyw->image.offset[0] >> 8); + + PUSH_MTHD(push, NV907E, SURFACE_SET_SIZE, + NVVAL(NV907E, SURFACE_SET_SIZE, WIDTH, asyw->image.w) | + NVVAL(NV907E, SURFACE_SET_SIZE, HEIGHT, asyw->image.h), + + SURFACE_SET_STORAGE, + NVVAL(NV907E, SURFACE_SET_STORAGE, BLOCK_HEIGHT, asyw->image.blockh) | + NVVAL(NV907E, SURFACE_SET_STORAGE, PITCH, (asyw->image.pitch[0] >> 8)) | + NVVAL(NV907E, SURFACE_SET_STORAGE, PITCH, asyw->image.blocks[0]) | + NVVAL(NV907E, SURFACE_SET_STORAGE, MEMORY_LAYOUT, asyw->image.layout), + + SURFACE_SET_PARAMS, + NVVAL(NV907E, SURFACE_SET_PARAMS, FORMAT, asyw->image.format) | + NVVAL(NV907E, SURFACE_SET_PARAMS, COLOR_SPACE, asyw->image.colorspace)); return 0; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndw.c b/drivers/gpu/drm/nouveau/dispnv50/wndw.c index baf693e5641c..8f6717267df1 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndw.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndw.c @@ -26,6 +26,10 @@ #include #include +#include +#include +#include + #include #include @@ -137,7 +141,7 @@ nv50_wndw_flush_set(struct nv50_wndw *wndw, u32 *interlock, struct nv50_wndw_atom *asyw) { if (interlock[NV50_DISP_INTERLOCK_CORE]) { - asyw->image.mode = 0; + asyw->image.mode = NV507C_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING; asyw->image.interval = 1; } @@ -201,13 +205,18 @@ static int nv50_wndw_atomic_check_acquire_yuv(struct nv50_wndw_atom *asyw) { switch (asyw->state.fb->format->format) { - case DRM_FORMAT_YUYV: asyw->image.format = 0x28; break; - case DRM_FORMAT_UYVY: asyw->image.format = 0x29; break; + case DRM_FORMAT_YUYV: + asyw->image.format = NV507E_SURFACE_SET_PARAMS_FORMAT_VE8YO8UE8YE8; + break; + case DRM_FORMAT_UYVY: + asyw->image.format = NV507E_SURFACE_SET_PARAMS_FORMAT_YO8VE8YE8UE8; + break; default: WARN_ON(1); return -EINVAL; } - asyw->image.colorspace = 1; + + asyw->image.colorspace = NV507E_SURFACE_SET_PARAMS_COLOR_SPACE_YUV_601; return 0; } @@ -215,24 +224,41 @@ static int nv50_wndw_atomic_check_acquire_rgb(struct nv50_wndw_atom *asyw) { switch (asyw->state.fb->format->format) { - case DRM_FORMAT_C8 : asyw->image.format = 0x1e; break; - case DRM_FORMAT_XRGB8888 : - case DRM_FORMAT_ARGB8888 : asyw->image.format = 0xcf; break; - case DRM_FORMAT_RGB565 : asyw->image.format = 0xe8; break; - case DRM_FORMAT_XRGB1555 : - case DRM_FORMAT_ARGB1555 : asyw->image.format = 0xe9; break; - case DRM_FORMAT_XBGR2101010 : - case DRM_FORMAT_ABGR2101010 : asyw->image.format = 0xd1; break; - case DRM_FORMAT_XBGR8888 : - case DRM_FORMAT_ABGR8888 : asyw->image.format = 0xd5; break; - case DRM_FORMAT_XRGB2101010 : - case DRM_FORMAT_ARGB2101010 : asyw->image.format = 0xdf; break; + case DRM_FORMAT_C8: + asyw->image.format = NV507C_SURFACE_SET_PARAMS_FORMAT_I8; + break; + case DRM_FORMAT_XRGB8888: + case DRM_FORMAT_ARGB8888: + asyw->image.format = NV507C_SURFACE_SET_PARAMS_FORMAT_A8R8G8B8; + break; + case DRM_FORMAT_RGB565: + asyw->image.format = NV507C_SURFACE_SET_PARAMS_FORMAT_R5G6B5; + break; + case DRM_FORMAT_XRGB1555: + case DRM_FORMAT_ARGB1555: + asyw->image.format = NV507C_SURFACE_SET_PARAMS_FORMAT_A1R5G5B5; + break; + case DRM_FORMAT_XBGR2101010: + case DRM_FORMAT_ABGR2101010: + asyw->image.format = NV507C_SURFACE_SET_PARAMS_FORMAT_A2B10G10R10; + break; + case DRM_FORMAT_XBGR8888: + case DRM_FORMAT_ABGR8888: + asyw->image.format = NV507C_SURFACE_SET_PARAMS_FORMAT_A8B8G8R8; + break; + case DRM_FORMAT_XRGB2101010: + case DRM_FORMAT_ARGB2101010: + asyw->image.format = NVC37E_SET_PARAMS_FORMAT_A2R10G10B10; + break; case DRM_FORMAT_XBGR16161616F: - case DRM_FORMAT_ABGR16161616F: asyw->image.format = 0xca; break; + case DRM_FORMAT_ABGR16161616F: + asyw->image.format = NV507C_SURFACE_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16; + break; default: return -EINVAL; } - asyw->image.colorspace = 0; + + asyw->image.colorspace = NV507E_SURFACE_SET_PARAMS_COLOR_SPACE_RGB; return 0; } @@ -265,7 +291,7 @@ nv50_wndw_atomic_check_acquire(struct nv50_wndw *wndw, bool modeset, } if (asyw->image.kind) { - asyw->image.layout = 0; + asyw->image.layout = NV507C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR; if (drm->client.device.info.chipset >= 0xc0) asyw->image.blockh = tile_mode >> 4; else @@ -273,8 +299,8 @@ nv50_wndw_atomic_check_acquire(struct nv50_wndw *wndw, bool modeset, asyw->image.blocks[0] = fb->pitches[0] / 64; asyw->image.pitch[0] = 0; } else { - asyw->image.layout = 1; - asyw->image.blockh = 0; + asyw->image.layout = NV507C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_PITCH; + asyw->image.blockh = NV507C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB; asyw->image.blocks[0] = 0; asyw->image.pitch[0] = fb->pitches[0]; } @@ -283,7 +309,12 @@ nv50_wndw_atomic_check_acquire(struct nv50_wndw *wndw, bool modeset, asyw->image.interval = 1; else asyw->image.interval = 0; - asyw->image.mode = asyw->image.interval ? 0 : 1; + + if (asyw->image.interval) + asyw->image.mode = NV507C_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING; + else + asyw->image.mode = NV507C_SET_PRESENT_CONTROL_BEGIN_MODE_IMMEDIATE; + asyw->set.image = wndw->func->image_set != NULL; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c index d59a3a59e36d..a3ab22608f8b 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c @@ -141,24 +141,47 @@ wndwc37e_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) if ((ret = PUSH_WAIT(push, 17))) return ret; - PUSH_NVSQ(push, NVC37E, 0x0308, asyw->image.mode << 4 | - asyw->image.interval); - PUSH_NVSQ(push, NVC37E, 0x0224, asyw->image.h << 16 | asyw->image.w, - 0x0228, asyw->image.layout << 4 | - asyw->image.blockh, - 0x022c, asyw->csc.valid << 17 | - asyw->image.colorspace << 8 | - asyw->image.format, - 0x0230, asyw->image.blocks[0] | - (asyw->image.pitch[0] >> 6)); - PUSH_NVSQ(push, NVC37E, 0x0240, asyw->image.handle[0]); - PUSH_NVSQ(push, NVC37E, 0x0260, asyw->image.offset[0] >> 8); - PUSH_NVSQ(push, NVC37E, 0x0290,(asyw->state.src_y >> 16) << 16 | - (asyw->state.src_x >> 16)); - PUSH_NVSQ(push, NVC37E, 0x0298,(asyw->state.src_h >> 16) << 16 | - (asyw->state.src_w >> 16)); - PUSH_NVSQ(push, NVC37E, 0x02a4, asyw->state.crtc_h << 16 | - asyw->state.crtc_w); + PUSH_MTHD(push, NVC37E, SET_PRESENT_CONTROL, + NVVAL(NVC37E, SET_PRESENT_CONTROL, MIN_PRESENT_INTERVAL, asyw->image.interval) | + NVVAL(NVC37E, SET_PRESENT_CONTROL, BEGIN_MODE, asyw->image.mode) | + NVDEF(NVC37E, SET_PRESENT_CONTROL, TIMESTAMP_MODE, DISABLE)); + + PUSH_MTHD(push, NVC37E, SET_SIZE, + NVVAL(NVC37E, SET_SIZE, WIDTH, asyw->image.w) | + NVVAL(NVC37E, SET_SIZE, HEIGHT, asyw->image.h), + + SET_STORAGE, + NVVAL(NVC37E, SET_STORAGE, BLOCK_HEIGHT, asyw->image.blockh) | + NVVAL(NVC37E, SET_STORAGE, MEMORY_LAYOUT, asyw->image.layout), + + SET_PARAMS, + NVVAL(NVC37E, SET_PARAMS, FORMAT, asyw->image.format) | + NVVAL(NVC37E, SET_PARAMS, COLOR_SPACE, asyw->image.colorspace) | + NVDEF(NVC37E, SET_PARAMS, INPUT_RANGE, BYPASS) | + NVDEF(NVC37E, SET_PARAMS, UNDERREPLICATE, DISABLE) | + NVDEF(NVC37E, SET_PARAMS, DE_GAMMA, NONE) | + NVVAL(NVC37E, SET_PARAMS, CSC, asyw->csc.valid) | + NVDEF(NVC37E, SET_PARAMS, CLAMP_BEFORE_BLEND, DISABLE) | + NVDEF(NVC37E, SET_PARAMS, SWAP_UV, DISABLE), + + SET_PLANAR_STORAGE(0), + NVVAL(NVC37E, SET_PLANAR_STORAGE, PITCH, asyw->image.blocks[0]) | + NVVAL(NVC37E, SET_PLANAR_STORAGE, PITCH, asyw->image.pitch[0] >> 6)); + + PUSH_MTHD(push, NVC37E, SET_CONTEXT_DMA_ISO(0), asyw->image.handle, 1); + PUSH_MTHD(push, NVC37E, SET_OFFSET(0), asyw->image.offset[0] >> 8); + + PUSH_MTHD(push, NVC37E, SET_POINT_IN(0), + NVVAL(NVC37E, SET_POINT_IN, X, asyw->state.src_x >> 16) | + NVVAL(NVC37E, SET_POINT_IN, Y, asyw->state.src_y >> 16)); + + PUSH_MTHD(push, NVC37E, SET_SIZE_IN, + NVVAL(NVC37E, SET_SIZE_IN, WIDTH, asyw->state.src_w >> 16) | + NVVAL(NVC37E, SET_SIZE_IN, HEIGHT, asyw->state.src_h >> 16)); + + PUSH_MTHD(push, NVC37E, SET_SIZE_OUT, + NVVAL(NVC37E, SET_SIZE_OUT, WIDTH, asyw->state.crtc_w) | + NVVAL(NVC37E, SET_SIZE_OUT, HEIGHT, asyw->state.crtc_h)); return 0; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c b/drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c index ffe5519f0163..429be0bb0222 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c @@ -40,23 +40,43 @@ wndwc57e_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) if ((ret = PUSH_WAIT(push, 17))) return ret; - PUSH_NVSQ(push, NVC57E, 0x0308, asyw->image.mode << 4 | - asyw->image.interval); - PUSH_NVSQ(push, NVC57E, 0x0224, asyw->image.h << 16 | asyw->image.w, - 0x0228, asyw->image.layout << 4 | - asyw->image.blockh, - 0x022c, asyw->image.colorspace << 8 | - asyw->image.format, - 0x0230, asyw->image.blocks[0] | - (asyw->image.pitch[0] >> 6)); - PUSH_NVSQ(push, NVC57E, 0x0240, asyw->image.handle[0]); - PUSH_NVSQ(push, NVC57E, 0x0260, asyw->image.offset[0] >> 8); - PUSH_NVSQ(push, NVC57E, 0x0290,(asyw->state.src_y >> 16) << 16 | - (asyw->state.src_x >> 16)); - PUSH_NVSQ(push, NVC57E, 0x0298,(asyw->state.src_h >> 16) << 16 | - (asyw->state.src_w >> 16)); - PUSH_NVSQ(push, NVC57E, 0x02a4, asyw->state.crtc_h << 16 | - asyw->state.crtc_w); + PUSH_MTHD(push, NVC57E, SET_PRESENT_CONTROL, + NVVAL(NVC57E, SET_PRESENT_CONTROL, MIN_PRESENT_INTERVAL, asyw->image.interval) | + NVVAL(NVC57E, SET_PRESENT_CONTROL, BEGIN_MODE, asyw->image.mode) | + NVDEF(NVC57E, SET_PRESENT_CONTROL, TIMESTAMP_MODE, DISABLE)); + + PUSH_MTHD(push, NVC57E, SET_SIZE, + NVVAL(NVC57E, SET_SIZE, WIDTH, asyw->image.w) | + NVVAL(NVC57E, SET_SIZE, HEIGHT, asyw->image.h), + + SET_STORAGE, + NVVAL(NVC57E, SET_STORAGE, BLOCK_HEIGHT, asyw->image.blockh) | + NVVAL(NVC57E, SET_STORAGE, MEMORY_LAYOUT, asyw->image.layout), + + SET_PARAMS, + NVVAL(NVC57E, SET_PARAMS, FORMAT, asyw->image.format) | + NVDEF(NVC57E, SET_PARAMS, CLAMP_BEFORE_BLEND, DISABLE) | + NVDEF(NVC57E, SET_PARAMS, SWAP_UV, DISABLE) | + NVDEF(NVC57E, SET_PARAMS, FMT_ROUNDING_MODE, ROUND_TO_NEAREST), + + SET_PLANAR_STORAGE(0), + NVVAL(NVC57E, SET_PLANAR_STORAGE, PITCH, asyw->image.blocks[0]) | + NVVAL(NVC57E, SET_PLANAR_STORAGE, PITCH, asyw->image.pitch[0] >> 6)); + + PUSH_MTHD(push, NVC57E, SET_CONTEXT_DMA_ISO(0), asyw->image.handle, 1); + PUSH_MTHD(push, NVC57E, SET_OFFSET(0), asyw->image.offset[0] >> 8); + + PUSH_MTHD(push, NVC57E, SET_POINT_IN(0), + NVVAL(NVC57E, SET_POINT_IN, X, asyw->state.src_x >> 16) | + NVVAL(NVC57E, SET_POINT_IN, Y, asyw->state.src_y >> 16)); + + PUSH_MTHD(push, NVC57E, SET_SIZE_IN, + NVVAL(NVC57E, SET_SIZE_IN, WIDTH, asyw->state.src_w >> 16) | + NVVAL(NVC57E, SET_SIZE_IN, HEIGHT, asyw->state.src_h >> 16)); + + PUSH_MTHD(push, NVC57E, SET_SIZE_OUT, + NVVAL(NVC57E, SET_SIZE_OUT, WIDTH, asyw->state.crtc_w) | + NVVAL(NVC57E, SET_SIZE_OUT, HEIGHT, asyw->state.crtc_h)); return 0; } diff --git a/drivers/gpu/drm/nouveau/include/nvhw/class/cl507e.h b/drivers/gpu/drm/nouveau/include/nvhw/class/cl507e.h new file mode 100644 index 000000000000..1f432b43cbb9 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvhw/class/cl507e.h @@ -0,0 +1,93 @@ +/* + * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl507e_h_ +#define _cl507e_h_ + +// class methods +#define NV507E_SET_PRESENT_CONTROL (0x00000084) +#define NV507E_SET_PRESENT_CONTROL_BEGIN_MODE 1:0 +#define NV507E_SET_PRESENT_CONTROL_BEGIN_MODE_ASAP (0x00000000) +#define NV507E_SET_PRESENT_CONTROL_BEGIN_MODE_TIMESTAMP (0x00000003) +#define NV507E_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 7:4 +#define NV507E_SET_CONTEXT_DMA_ISO (0x000000C0) +#define NV507E_SET_CONTEXT_DMA_ISO_HANDLE 31:0 +#define NV507E_SET_POINT_IN (0x000000E0) +#define NV507E_SET_POINT_IN_X 14:0 +#define NV507E_SET_POINT_IN_Y 30:16 +#define NV507E_SET_SIZE_IN (0x000000E4) +#define NV507E_SET_SIZE_IN_WIDTH 14:0 +#define NV507E_SET_SIZE_IN_HEIGHT 30:16 +#define NV507E_SET_SIZE_OUT (0x000000E8) +#define NV507E_SET_SIZE_OUT_WIDTH 14:0 +#define NV507E_SET_COMPOSITION_CONTROL (0x00000100) +#define NV507E_SET_COMPOSITION_CONTROL_MODE 3:0 +#define NV507E_SET_COMPOSITION_CONTROL_MODE_SOURCE_COLOR_VALUE_KEYING (0x00000000) +#define NV507E_SET_COMPOSITION_CONTROL_MODE_DESTINATION_COLOR_VALUE_KEYING (0x00000001) +#define NV507E_SET_COMPOSITION_CONTROL_MODE_OPAQUE_SUSPEND_BASE (0x00000002) + +#define NV507E_SURFACE_SET_OFFSET (0x00000800) +#define NV507E_SURFACE_SET_OFFSET_ORIGIN 31:0 +#define NV507E_SURFACE_SET_SIZE (0x00000808) +#define NV507E_SURFACE_SET_SIZE_WIDTH 14:0 +#define NV507E_SURFACE_SET_SIZE_HEIGHT 30:16 +#define NV507E_SURFACE_SET_STORAGE (0x0000080C) +#define NV507E_SURFACE_SET_STORAGE_BLOCK_HEIGHT 3:0 +#define NV507E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB (0x00000000) +#define NV507E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS (0x00000001) +#define NV507E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS (0x00000002) +#define NV507E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003) +#define NV507E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NV507E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NV507E_SURFACE_SET_STORAGE_PITCH 17:8 +#define NV507E_SURFACE_SET_STORAGE_MEMORY_LAYOUT 20:20 +#define NV507E_SURFACE_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NV507E_SURFACE_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001) +#define NV507E_SURFACE_SET_PARAMS (0x00000810) +#define NV507E_SURFACE_SET_PARAMS_FORMAT 15:8 +#define NV507E_SURFACE_SET_PARAMS_FORMAT_VE8YO8UE8YE8 (0x00000028) +#define NV507E_SURFACE_SET_PARAMS_FORMAT_YO8VE8YE8UE8 (0x00000029) +#define NV507E_SURFACE_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF) +#define NV507E_SURFACE_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9) +#define NV507E_SURFACE_SET_PARAMS_COLOR_SPACE 1:0 +#define NV507E_SURFACE_SET_PARAMS_COLOR_SPACE_RGB (0x00000000) +#define NV507E_SURFACE_SET_PARAMS_COLOR_SPACE_YUV_601 (0x00000001) +#define NV507E_SURFACE_SET_PARAMS_COLOR_SPACE_YUV_709 (0x00000002) +#define NV507E_SURFACE_SET_PARAMS_KIND 22:16 +#define NV507E_SURFACE_SET_PARAMS_KIND_KIND_PITCH (0x00000000) +#define NV507E_SURFACE_SET_PARAMS_KIND_KIND_GENERIC_8BX2 (0x00000070) +#define NV507E_SURFACE_SET_PARAMS_KIND_KIND_GENERIC_8BX2_BANKSWIZ (0x00000072) +#define NV507E_SURFACE_SET_PARAMS_KIND_KIND_GENERIC_16BX1 (0x00000074) +#define NV507E_SURFACE_SET_PARAMS_KIND_KIND_GENERIC_16BX1_BANKSWIZ (0x00000076) +#define NV507E_SURFACE_SET_PARAMS_KIND_KIND_C32_MS4 (0x00000078) +#define NV507E_SURFACE_SET_PARAMS_KIND_KIND_C32_MS8 (0x00000079) +#define NV507E_SURFACE_SET_PARAMS_KIND_KIND_C32_MS4_BANKSWIZ (0x0000007A) +#define NV507E_SURFACE_SET_PARAMS_KIND_KIND_C32_MS8_BANKSWIZ (0x0000007B) +#define NV507E_SURFACE_SET_PARAMS_KIND_KIND_C64_MS4 (0x0000007C) +#define NV507E_SURFACE_SET_PARAMS_KIND_KIND_C64_MS8 (0x0000007D) +#define NV507E_SURFACE_SET_PARAMS_KIND_KIND_C128_MS4 (0x0000007E) +#define NV507E_SURFACE_SET_PARAMS_KIND_FROM_PTE (0x0000007F) +#define NV507E_SURFACE_SET_PARAMS_PART_STRIDE 24:24 +#define NV507E_SURFACE_SET_PARAMS_PART_STRIDE_PARTSTRIDE_256 (0x00000000) +#define NV507E_SURFACE_SET_PARAMS_PART_STRIDE_PARTSTRIDE_1024 (0x00000001) +#endif // _cl507e_h diff --git a/drivers/gpu/drm/nouveau/include/nvhw/class/cl827c.h b/drivers/gpu/drm/nouveau/include/nvhw/class/cl827c.h new file mode 100644 index 000000000000..4b8938ee34a4 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvhw/class/cl827c.h @@ -0,0 +1,86 @@ +/* + * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl827c_h_ +#define _cl827c_h_ + +// class methods +#define NV827C_SET_PRESENT_CONTROL (0x00000084) +#define NV827C_SET_PRESENT_CONTROL_BEGIN_MODE 9:8 +#define NV827C_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING (0x00000000) +#define NV827C_SET_PRESENT_CONTROL_BEGIN_MODE_IMMEDIATE (0x00000001) +#define NV827C_SET_PRESENT_CONTROL_BEGIN_MODE_ON_LINE (0x00000002) +#define NV827C_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 7:4 +#define NV827C_SET_PRESENT_CONTROL_BEGIN_LINE 30:16 +#define NV827C_SET_PRESENT_CONTROL_ON_LINE_MARGIN 15:10 +#define NV827C_SET_CONTEXT_DMAS_ISO(b) (0x000000C0 + (b)*0x00000004) +#define NV827C_SET_CONTEXT_DMAS_ISO_HANDLE 31:0 +#define NV827C_SET_PROCESSING (0x00000110) +#define NV827C_SET_PROCESSING_USE_GAIN_OFS 0:0 +#define NV827C_SET_PROCESSING_USE_GAIN_OFS_DISABLE (0x00000000) +#define NV827C_SET_PROCESSING_USE_GAIN_OFS_ENABLE (0x00000001) +#define NV827C_SET_CONVERSION (0x00000114) +#define NV827C_SET_CONVERSION_GAIN 15:0 +#define NV827C_SET_CONVERSION_OFS 31:16 + +#define NV827C_SURFACE_SET_OFFSET(a,b) (0x00000800 + (a)*0x00000020 + (b)*0x00000004) +#define NV827C_SURFACE_SET_OFFSET_ORIGIN 31:0 +#define NV827C_SURFACE_SET_SIZE(a) (0x00000808 + (a)*0x00000020) +#define NV827C_SURFACE_SET_SIZE_WIDTH 14:0 +#define NV827C_SURFACE_SET_SIZE_HEIGHT 30:16 +#define NV827C_SURFACE_SET_STORAGE(a) (0x0000080C + (a)*0x00000020) +#define NV827C_SURFACE_SET_STORAGE_BLOCK_HEIGHT 3:0 +#define NV827C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB (0x00000000) +#define NV827C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS (0x00000001) +#define NV827C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS (0x00000002) +#define NV827C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003) +#define NV827C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NV827C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NV827C_SURFACE_SET_STORAGE_PITCH 17:8 +#define NV827C_SURFACE_SET_STORAGE_MEMORY_LAYOUT 20:20 +#define NV827C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NV827C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001) +#define NV827C_SURFACE_SET_PARAMS(a) (0x00000810 + (a)*0x00000020) +#define NV827C_SURFACE_SET_PARAMS_FORMAT 15:8 +#define NV827C_SURFACE_SET_PARAMS_FORMAT_I8 (0x0000001E) +#define NV827C_SURFACE_SET_PARAMS_FORMAT_VOID16 (0x0000001F) +#define NV827C_SURFACE_SET_PARAMS_FORMAT_VOID32 (0x0000002E) +#define NV827C_SURFACE_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA) +#define NV827C_SURFACE_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF) +#define NV827C_SURFACE_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1) +#define NV827C_SURFACE_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5) +#define NV827C_SURFACE_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8) +#define NV827C_SURFACE_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9) +#define NV827C_SURFACE_SET_PARAMS_SUPER_SAMPLE 1:0 +#define NV827C_SURFACE_SET_PARAMS_SUPER_SAMPLE_X1_AA (0x00000000) +#define NV827C_SURFACE_SET_PARAMS_SUPER_SAMPLE_X4_AA (0x00000002) +#define NV827C_SURFACE_SET_PARAMS_GAMMA 2:2 +#define NV827C_SURFACE_SET_PARAMS_GAMMA_LINEAR (0x00000000) +#define NV827C_SURFACE_SET_PARAMS_GAMMA_SRGB (0x00000001) +#define NV827C_SURFACE_SET_PARAMS_LAYOUT 5:4 +#define NV827C_SURFACE_SET_PARAMS_LAYOUT_FRM (0x00000000) +#define NV827C_SURFACE_SET_PARAMS_LAYOUT_FLD1 (0x00000001) +#define NV827C_SURFACE_SET_PARAMS_LAYOUT_FLD2 (0x00000002) +#define NV827C_SURFACE_SET_PARAMS_RESERVED0 22:16 +#define NV827C_SURFACE_SET_PARAMS_RESERVED1 24:24 +#endif // _cl827c_h diff --git a/drivers/gpu/drm/nouveau/include/nvhw/class/cl907e.h b/drivers/gpu/drm/nouveau/include/nvhw/class/cl907e.h new file mode 100644 index 000000000000..64ef0c578153 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvhw/class/cl907e.h @@ -0,0 +1,73 @@ +/* + * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl907e_h_ +#define _cl907e_h_ + +// class methods +#define NV907E_SET_PRESENT_CONTROL (0x00000084) +#define NV907E_SET_PRESENT_CONTROL_BEGIN_MODE 1:0 +#define NV907E_SET_PRESENT_CONTROL_BEGIN_MODE_ASAP (0x00000000) +#define NV907E_SET_PRESENT_CONTROL_BEGIN_MODE_TIMESTAMP (0x00000003) +#define NV907E_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 7:4 +#define NV907E_SET_CONTEXT_DMA_ISO (0x000000C0) +#define NV907E_SET_CONTEXT_DMA_ISO_HANDLE 31:0 +#define NV907E_SET_COMPOSITION_CONTROL (0x00000100) +#define NV907E_SET_COMPOSITION_CONTROL_MODE 3:0 +#define NV907E_SET_COMPOSITION_CONTROL_MODE_SOURCE_COLOR_VALUE_KEYING (0x00000000) +#define NV907E_SET_COMPOSITION_CONTROL_MODE_DESTINATION_COLOR_VALUE_KEYING (0x00000001) +#define NV907E_SET_COMPOSITION_CONTROL_MODE_OPAQUE (0x00000002) + +#define NV907E_SURFACE_SET_OFFSET (0x00000400) +#define NV907E_SURFACE_SET_OFFSET_ORIGIN 31:0 +#define NV907E_SURFACE_SET_SIZE (0x00000408) +#define NV907E_SURFACE_SET_SIZE_WIDTH 15:0 +#define NV907E_SURFACE_SET_SIZE_HEIGHT 31:16 +#define NV907E_SURFACE_SET_STORAGE (0x0000040C) +#define NV907E_SURFACE_SET_STORAGE_BLOCK_HEIGHT 3:0 +#define NV907E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB (0x00000000) +#define NV907E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS (0x00000001) +#define NV907E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS (0x00000002) +#define NV907E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003) +#define NV907E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NV907E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NV907E_SURFACE_SET_STORAGE_PITCH 20:8 +#define NV907E_SURFACE_SET_STORAGE_MEMORY_LAYOUT 24:24 +#define NV907E_SURFACE_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NV907E_SURFACE_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001) +#define NV907E_SURFACE_SET_PARAMS (0x00000410) +#define NV907E_SURFACE_SET_PARAMS_FORMAT 15:8 +#define NV907E_SURFACE_SET_PARAMS_FORMAT_VE8YO8UE8YE8 (0x00000028) +#define NV907E_SURFACE_SET_PARAMS_FORMAT_YO8VE8YE8UE8 (0x00000029) +#define NV907E_SURFACE_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1) +#define NV907E_SURFACE_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS (0x00000022) +#define NV907E_SURFACE_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF) +#define NV907E_SURFACE_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9) +#define NV907E_SURFACE_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA) +#define NV907E_SURFACE_SET_PARAMS_FORMAT_R16_G16_B16_A16 (0x000000C6) +#define NV907E_SURFACE_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS (0x00000023) +#define NV907E_SURFACE_SET_PARAMS_COLOR_SPACE 1:0 +#define NV907E_SURFACE_SET_PARAMS_COLOR_SPACE_RGB (0x00000000) +#define NV907E_SURFACE_SET_PARAMS_COLOR_SPACE_YUV_601 (0x00000001) +#define NV907E_SURFACE_SET_PARAMS_COLOR_SPACE_YUV_709 (0x00000002) +#endif // _cl907e_h From 1070832b1eab7309c59d9564ed26f84932fed817 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sat, 20 Jun 2020 14:21:59 +1000 Subject: [PATCH 107/145] drm/nouveau/kms/nv50-: use NVIDIA's headers for wndw image_clr() Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/base507c.c | 7 +++++-- drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c | 7 +++++-- 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/base507c.c b/drivers/gpu/drm/nouveau/dispnv50/base507c.c index fac830cb9eaa..db811751800a 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/base507c.c +++ b/drivers/gpu/drm/nouveau/dispnv50/base507c.c @@ -56,8 +56,11 @@ base507c_image_clr(struct nv50_wndw *wndw) if ((ret = PUSH_WAIT(push, 4))) return ret; - PUSH_NVSQ(push, NV507C, 0x0084, 0x00000000); - PUSH_NVSQ(push, NV507C, 0x00c0, 0x00000000); + PUSH_MTHD(push, NV507C, SET_PRESENT_CONTROL, + NVDEF(NV507C, SET_PRESENT_CONTROL, BEGIN_MODE, NON_TEARING) | + NVVAL(NV507C, SET_PRESENT_CONTROL, MIN_PRESENT_INTERVAL, 0)); + + PUSH_MTHD(push, NV507C, SET_CONTEXT_DMA_ISO, 0x00000000); return 0; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c index a3ab22608f8b..b071cca8dfbf 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c @@ -127,8 +127,11 @@ wndwc37e_image_clr(struct nv50_wndw *wndw) if ((ret = PUSH_WAIT(push, 4))) return ret; - PUSH_NVSQ(push, NVC37E, 0x0308, 0x00000000); - PUSH_NVSQ(push, NVC37E, 0x0240, 0x00000000); + PUSH_MTHD(push, NVC37E, SET_PRESENT_CONTROL, + NVVAL(NVC37E, SET_PRESENT_CONTROL, MIN_PRESENT_INTERVAL, 0) | + NVDEF(NVC37E, SET_PRESENT_CONTROL, BEGIN_MODE, NON_TEARING)); + + PUSH_MTHD(push, NVC37E, SET_CONTEXT_DMA_ISO(0), 0x00000000); return 0; } From 5329dbd4a3bf97a96c54fe46cba9c604d932bb14 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sat, 20 Jun 2020 14:24:57 +1000 Subject: [PATCH 108/145] drm/nouveau/kms/nv50-: use NVIDIA's headers for wndw scale_set() Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/ovly507e.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/ovly507e.c b/drivers/gpu/drm/nouveau/dispnv50/ovly507e.c index 5369080d97f3..afd6c7271de1 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/ovly507e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/ovly507e.c @@ -41,9 +41,16 @@ ovly507e_scale_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) if ((ret = PUSH_WAIT(push, 4))) return ret; - PUSH_NVSQ(push, NV507E, 0x00e0, asyw->scale.sy << 16 | asyw->scale.sx, - 0x00e4, asyw->scale.sh << 16 | asyw->scale.sw, - 0x00e8, asyw->scale.dw); + PUSH_MTHD(push, NV507E, SET_POINT_IN, + NVVAL(NV507E, SET_POINT_IN, X, asyw->scale.sx) | + NVVAL(NV507E, SET_POINT_IN, Y, asyw->scale.sy), + + SET_SIZE_IN, + NVVAL(NV507E, SET_SIZE_IN, WIDTH, asyw->scale.sw) | + NVVAL(NV507E, SET_SIZE_IN, HEIGHT, asyw->scale.sh), + + SET_SIZE_OUT, + NVVAL(NV507E, SET_SIZE_OUT, WIDTH, asyw->scale.dw)); return 0; } From fbc318bdbb43a151b4f60ff3b86d577daeb63791 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sat, 20 Jun 2020 15:46:52 +1000 Subject: [PATCH 109/145] drm/nouveau/kms/nv50-: use NVIDIA's headers for wndw blend_set() Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/wndw.c | 12 +++--- drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c | 43 ++++++++++++++++----- 2 files changed, 39 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndw.c b/drivers/gpu/drm/nouveau/dispnv50/wndw.c index 8f6717267df1..447ecc9fec42 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndw.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndw.c @@ -334,17 +334,17 @@ nv50_wndw_atomic_check_acquire(struct nv50_wndw *wndw, bool modeset, asyw->blend.k1 = asyw->state.alpha >> 8; switch (asyw->state.pixel_blend_mode) { case DRM_MODE_BLEND_PREMULTI: - asyw->blend.src_color = 2; /* K1 */ - asyw->blend.dst_color = 7; /* NEG_K1_TIMES_SRC */ + asyw->blend.src_color = NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1; + asyw->blend.dst_color = NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_SRC; break; case DRM_MODE_BLEND_COVERAGE: - asyw->blend.src_color = 5; /* K1_TIMES_SRC */ - asyw->blend.dst_color = 7; /* NEG_K1_TIMES_SRC */ + asyw->blend.src_color = NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1_TIMES_SRC; + asyw->blend.dst_color = NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1_TIMES_SRC; break; case DRM_MODE_BLEND_PIXEL_NONE: default: - asyw->blend.src_color = 2; /* K1 */ - asyw->blend.dst_color = 4; /* NEG_K1 */ + asyw->blend.src_color = NVC37E_SET_COMPOSITION_FACTOR_SELECT_SRC_COLOR_FACTOR_MATCH_SELECT_K1; + asyw->blend.dst_color = NVC37E_SET_COMPOSITION_FACTOR_SELECT_DST_COLOR_FACTOR_MATCH_SELECT_NEG_K1; break; } if (memcmp(&armw->blend, &asyw->blend, sizeof(asyw->blend))) diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c index b071cca8dfbf..8dd1e89f4725 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c @@ -105,16 +105,39 @@ wndwc37e_blend_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) if ((ret = PUSH_WAIT(push, 8))) return ret; - PUSH_NVSQ(push, NVC37E, 0x02ec, asyw->blend.depth << 4, - 0x02f0, asyw->blend.k1, - 0x02f4, asyw->blend.dst_color << 12 | - asyw->blend.dst_color << 8 | - asyw->blend.src_color << 4 | - asyw->blend.src_color, - 0x02f8, 0xffff0000, - 0x02fc, 0xffff0000, - 0x0300, 0xffff0000, - 0x0304, 0xffff0000); + PUSH_MTHD(push, NVC37E, SET_COMPOSITION_CONTROL, + NVDEF(NVC37E, SET_COMPOSITION_CONTROL, COLOR_KEY_SELECT, DISABLE) | + NVVAL(NVC37E, SET_COMPOSITION_CONTROL, DEPTH, asyw->blend.depth), + + SET_COMPOSITION_CONSTANT_ALPHA, + NVVAL(NVC37E, SET_COMPOSITION_CONSTANT_ALPHA, K1, asyw->blend.k1) | + NVVAL(NVC37E, SET_COMPOSITION_CONSTANT_ALPHA, K2, 0), + + SET_COMPOSITION_FACTOR_SELECT, + NVVAL(NVC37E, SET_COMPOSITION_FACTOR_SELECT, SRC_COLOR_FACTOR_MATCH_SELECT, + asyw->blend.src_color) | + NVVAL(NVC37E, SET_COMPOSITION_FACTOR_SELECT, SRC_COLOR_FACTOR_NO_MATCH_SELECT, + asyw->blend.src_color) | + NVVAL(NVC37E, SET_COMPOSITION_FACTOR_SELECT, DST_COLOR_FACTOR_MATCH_SELECT, + asyw->blend.dst_color) | + NVVAL(NVC37E, SET_COMPOSITION_FACTOR_SELECT, DST_COLOR_FACTOR_NO_MATCH_SELECT, + asyw->blend.dst_color), + + SET_KEY_ALPHA, + NVVAL(NVC37E, SET_KEY_ALPHA, MIN, 0x0000) | + NVVAL(NVC37E, SET_KEY_ALPHA, MAX, 0xffff), + + SET_KEY_RED_CR, + NVVAL(NVC37E, SET_KEY_RED_CR, MIN, 0x0000) | + NVVAL(NVC37E, SET_KEY_RED_CR, MAX, 0xffff), + + SET_KEY_GREEN_Y, + NVVAL(NVC37E, SET_KEY_GREEN_Y, MIN, 0x0000) | + NVVAL(NVC37E, SET_KEY_GREEN_Y, MAX, 0xffff), + + SET_KEY_BLUE_CB, + NVVAL(NVC37E, SET_KEY_BLUE_CB, MIN, 0x0000) | + NVVAL(NVC37E, SET_KEY_BLUE_CB, MAX, 0xffff)); return 0; } From 9f7ffb49ee6b80a339191a8c282fdf1c89fc01f7 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sat, 20 Jun 2020 15:53:59 +1000 Subject: [PATCH 110/145] drm/nouveau/kms/nv50-: use NVIDIA's headers for wndw update() Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/base507c.c | 2 +- drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c | 14 ++++++++------ 2 files changed, 9 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/base507c.c b/drivers/gpu/drm/nouveau/dispnv50/base507c.c index db811751800a..302d4e6fc52f 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/base507c.c +++ b/drivers/gpu/drm/nouveau/dispnv50/base507c.c @@ -43,7 +43,7 @@ base507c_update(struct nv50_wndw *wndw, u32 *interlock) if ((ret = PUSH_WAIT(push, 2))) return ret; - PUSH_NVSQ(push, NV507C, 0x0080, interlock[NV50_DISP_INTERLOCK_CORE]); + PUSH_MTHD(push, NV507C, UPDATE, interlock[NV50_DISP_INTERLOCK_CORE]); return PUSH_KICK(push); } diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c index 8dd1e89f4725..57df997c5ff3 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c @@ -279,12 +279,14 @@ wndwc37e_update(struct nv50_wndw *wndw, u32 *interlock) if ((ret = PUSH_WAIT(push, 5))) return ret; - PUSH_NVSQ(push, NVC37E, 0x0370, interlock[NV50_DISP_INTERLOCK_CURS] << 1 | - interlock[NV50_DISP_INTERLOCK_CORE], - 0x0374, interlock[NV50_DISP_INTERLOCK_WNDW]); - PUSH_NVSQ(push, NVC37E, 0x0200,((interlock[NV50_DISP_INTERLOCK_WIMM] & - wndw->interlock.data) ? 0x00001000 : 0x00000000) | - 0x00000001); + PUSH_MTHD(push, NVC37E, SET_INTERLOCK_FLAGS, interlock[NV50_DISP_INTERLOCK_CURS] << 1 | + interlock[NV50_DISP_INTERLOCK_CORE], + SET_WINDOW_INTERLOCK_FLAGS, interlock[NV50_DISP_INTERLOCK_WNDW]); + + PUSH_MTHD(push, NVC37E, UPDATE, 0x00000001 | + NVVAL(NVC37E, UPDATE, INTERLOCK_WITH_WIN_IMM, + !!(interlock[NV50_DISP_INTERLOCK_WIMM] & wndw->interlock.data))); + return PUSH_KICK(push); } From b11d8ca151d08e9ce8f0d8fa3cac561a7e76cf63 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sat, 20 Jun 2020 17:51:49 +1000 Subject: [PATCH 111/145] drm/nouveau/kms/nv50-: use NVIDIA's headers for core init() Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/core507d.c | 4 +- drivers/gpu/drm/nouveau/dispnv50/corec37d.c | 21 +- drivers/gpu/drm/nouveau/dispnv50/corec57d.c | 20 +- .../drm/nouveau/include/nvhw/class/cl507d.h | 372 ++++++++++++ .../drm/nouveau/include/nvhw/class/clc37d.h | 567 ++++++++++++++++++ .../drm/nouveau/include/nvhw/class/clc57d.h | 286 +++++++++ 6 files changed, 1261 insertions(+), 9 deletions(-) create mode 100644 drivers/gpu/drm/nouveau/include/nvhw/class/cl507d.h create mode 100644 drivers/gpu/drm/nouveau/include/nvhw/class/clc37d.h create mode 100644 drivers/gpu/drm/nouveau/include/nvhw/class/clc57d.h diff --git a/drivers/gpu/drm/nouveau/dispnv50/core507d.c b/drivers/gpu/drm/nouveau/dispnv50/core507d.c index 4938e4b751a4..a0f470be3140 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/core507d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/core507d.c @@ -26,6 +26,8 @@ #include #include +#include + #include "nouveau_bo.h" int @@ -86,7 +88,7 @@ core507d_init(struct nv50_core *core) if ((ret = PUSH_WAIT(push, 2))) return ret; - PUSH_NVSQ(push, NV507D, 0x0088, core->chan.sync.handle); + PUSH_MTHD(push, NV507D, SET_CONTEXT_DMA_NOTIFIER, core->chan.sync.handle); return PUSH_KICK(push); } diff --git a/drivers/gpu/drm/nouveau/dispnv50/corec37d.c b/drivers/gpu/drm/nouveau/dispnv50/corec37d.c index 1b3d5896640e..008327ee4b58 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/corec37d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/corec37d.c @@ -26,6 +26,8 @@ #include #include +#include + #include int @@ -123,12 +125,23 @@ corec37d_init(struct nv50_core *core) if ((ret = PUSH_WAIT(push, 2 + windows * 5))) return ret; - PUSH_NVSQ(push, NVC37D, 0x0208, core->chan.sync.handle); + PUSH_MTHD(push, NVC37D, SET_CONTEXT_DMA_NOTIFIER, core->chan.sync.handle); for (i = 0; i < windows; i++) { - PUSH_NVSQ(push, NVC37D, 0x1004 + (i * 0x080), 0x0000001f, - 0x1008 + (i * 0x080), 0x00000000); - PUSH_NVSQ(push, NVC37D, 0x1010 + (i * 0x080), 0x00127fff); + PUSH_MTHD(push, NVC37D, WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS(i), + NVDEF(NVC37D, WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS, RGB_PACKED1BPP, TRUE) | + NVDEF(NVC37D, WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS, RGB_PACKED2BPP, TRUE) | + NVDEF(NVC37D, WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS, RGB_PACKED4BPP, TRUE) | + NVDEF(NVC37D, WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS, RGB_PACKED8BPP, TRUE) | + NVDEF(NVC37D, WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS, YUV_PACKED422, TRUE), + + WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS(i), 0x00000000); + + PUSH_MTHD(push, NVC37D, WINDOW_SET_WINDOW_USAGE_BOUNDS(i), + NVVAL(NVC37D, WINDOW_SET_WINDOW_USAGE_BOUNDS, MAX_PIXELS_FETCHED_PER_LINE, 0x7fff) | + NVDEF(NVC37D, WINDOW_SET_WINDOW_USAGE_BOUNDS, INPUT_LUT, USAGE_1025) | + NVDEF(NVC37D, WINDOW_SET_WINDOW_USAGE_BOUNDS, INPUT_SCALER_TAPS, TAPS_2) | + NVDEF(NVC37D, WINDOW_SET_WINDOW_USAGE_BOUNDS, UPSCALING_ALLOWED, FALSE)); } core->assign_windows = true; diff --git a/drivers/gpu/drm/nouveau/dispnv50/corec57d.c b/drivers/gpu/drm/nouveau/dispnv50/corec57d.c index afc703a05fea..75876546eac1 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/corec57d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/corec57d.c @@ -24,6 +24,8 @@ #include +#include + static int corec57d_init(struct nv50_core *core) { @@ -34,12 +36,22 @@ corec57d_init(struct nv50_core *core) if ((ret = PUSH_WAIT(push, 2 + windows * 5))) return ret; - PUSH_NVSQ(push, NVC57D, 0x0208, core->chan.sync.handle); + PUSH_MTHD(push, NVC57D, SET_CONTEXT_DMA_NOTIFIER, core->chan.sync.handle); for (i = 0; i < windows; i++) { - PUSH_NVSQ(push, NVC57D, 0x1004 + (i * 0x080), 0x0000000f, - 0x1008 + (i * 0x080), 0x00000000); - PUSH_NVSQ(push, NVC57D, 0x1010 + (i * 0x080), 0x00117fff); + PUSH_MTHD(push, NVC57D, WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS(i), + NVDEF(NVC57D, WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS, RGB_PACKED1BPP, TRUE) | + NVDEF(NVC57D, WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS, RGB_PACKED2BPP, TRUE) | + NVDEF(NVC57D, WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS, RGB_PACKED4BPP, TRUE) | + NVDEF(NVC57D, WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS, RGB_PACKED8BPP, TRUE), + + WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS(i), 0x00000000); + + PUSH_MTHD(push, NVC57D, WINDOW_SET_WINDOW_USAGE_BOUNDS(i), + NVVAL(NVC57D, WINDOW_SET_WINDOW_USAGE_BOUNDS, MAX_PIXELS_FETCHED_PER_LINE, 0x7fff) | + NVDEF(NVC57D, WINDOW_SET_WINDOW_USAGE_BOUNDS, ILUT_ALLOWED, TRUE) | + NVDEF(NVC57D, WINDOW_SET_WINDOW_USAGE_BOUNDS, INPUT_SCALER_TAPS, TAPS_2) | + NVDEF(NVC57D, WINDOW_SET_WINDOW_USAGE_BOUNDS, UPSCALING_ALLOWED, FALSE)); } core->assign_windows = true; diff --git a/drivers/gpu/drm/nouveau/include/nvhw/class/cl507d.h b/drivers/gpu/drm/nouveau/include/nvhw/class/cl507d.h new file mode 100644 index 000000000000..2e444bac701d --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvhw/class/cl507d.h @@ -0,0 +1,372 @@ +/* + * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl507d_h_ +#define _cl507d_h_ + +#define NV_DISP_CORE_NOTIFIER_1 0x00000000 +#define NV_DISP_CORE_NOTIFIER_1_SIZEOF 0x00000054 +#define NV_DISP_CORE_NOTIFIER_1_COMPLETION_0 0x00000000 +#define NV_DISP_CORE_NOTIFIER_1_COMPLETION_0_DONE 0:0 +#define NV_DISP_CORE_NOTIFIER_1_COMPLETION_0_DONE_FALSE 0x00000000 +#define NV_DISP_CORE_NOTIFIER_1_COMPLETION_0_DONE_TRUE 0x00000001 +#define NV_DISP_CORE_NOTIFIER_1_COMPLETION_0_R0 15:1 +#define NV_DISP_CORE_NOTIFIER_1_COMPLETION_0_TIMESTAMP 29:16 + + +// class methods +#define NV507D_UPDATE (0x00000080) +#define NV507D_UPDATE_INTERLOCK_WITH_CURSOR0 0:0 +#define NV507D_UPDATE_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000) +#define NV507D_UPDATE_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001) +#define NV507D_UPDATE_INTERLOCK_WITH_CURSOR1 8:8 +#define NV507D_UPDATE_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000) +#define NV507D_UPDATE_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001) +#define NV507D_UPDATE_INTERLOCK_WITH_BASE0 1:1 +#define NV507D_UPDATE_INTERLOCK_WITH_BASE0_DISABLE (0x00000000) +#define NV507D_UPDATE_INTERLOCK_WITH_BASE0_ENABLE (0x00000001) +#define NV507D_UPDATE_INTERLOCK_WITH_BASE1 9:9 +#define NV507D_UPDATE_INTERLOCK_WITH_BASE1_DISABLE (0x00000000) +#define NV507D_UPDATE_INTERLOCK_WITH_BASE1_ENABLE (0x00000001) +#define NV507D_UPDATE_INTERLOCK_WITH_OVERLAY0 2:2 +#define NV507D_UPDATE_INTERLOCK_WITH_OVERLAY0_DISABLE (0x00000000) +#define NV507D_UPDATE_INTERLOCK_WITH_OVERLAY0_ENABLE (0x00000001) +#define NV507D_UPDATE_INTERLOCK_WITH_OVERLAY1 10:10 +#define NV507D_UPDATE_INTERLOCK_WITH_OVERLAY1_DISABLE (0x00000000) +#define NV507D_UPDATE_INTERLOCK_WITH_OVERLAY1_ENABLE (0x00000001) +#define NV507D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0 3:3 +#define NV507D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_DISABLE (0x00000000) +#define NV507D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_ENABLE (0x00000001) +#define NV507D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1 11:11 +#define NV507D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_DISABLE (0x00000000) +#define NV507D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_ENABLE (0x00000001) +#define NV507D_UPDATE_NOT_DRIVER_FRIENDLY 31:31 +#define NV507D_UPDATE_NOT_DRIVER_FRIENDLY_FALSE (0x00000000) +#define NV507D_UPDATE_NOT_DRIVER_FRIENDLY_TRUE (0x00000001) +#define NV507D_UPDATE_NOT_DRIVER_UNFRIENDLY 30:30 +#define NV507D_UPDATE_NOT_DRIVER_UNFRIENDLY_FALSE (0x00000000) +#define NV507D_UPDATE_NOT_DRIVER_UNFRIENDLY_TRUE (0x00000001) +#define NV507D_UPDATE_INHIBIT_INTERRUPTS 29:29 +#define NV507D_UPDATE_INHIBIT_INTERRUPTS_FALSE (0x00000000) +#define NV507D_UPDATE_INHIBIT_INTERRUPTS_TRUE (0x00000001) +#define NV507D_SET_NOTIFIER_CONTROL (0x00000084) +#define NV507D_SET_NOTIFIER_CONTROL_MODE 30:30 +#define NV507D_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000) +#define NV507D_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001) +#define NV507D_SET_NOTIFIER_CONTROL_OFFSET 11:2 +#define NV507D_SET_NOTIFIER_CONTROL_NOTIFY 31:31 +#define NV507D_SET_NOTIFIER_CONTROL_NOTIFY_DISABLE (0x00000000) +#define NV507D_SET_NOTIFIER_CONTROL_NOTIFY_ENABLE (0x00000001) +#define NV507D_SET_CONTEXT_DMA_NOTIFIER (0x00000088) +#define NV507D_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0 +#define NV507D_GET_CAPABILITIES (0x0000008C) +#define NV507D_GET_CAPABILITIES_DUMMY 31:0 + +#define NV507D_DAC_SET_CONTROL(a) (0x00000400 + (a)*0x00000080) +#define NV507D_DAC_SET_CONTROL_OWNER 3:0 +#define NV507D_DAC_SET_CONTROL_OWNER_NONE (0x00000000) +#define NV507D_DAC_SET_CONTROL_OWNER_HEAD0 (0x00000001) +#define NV507D_DAC_SET_CONTROL_OWNER_HEAD1 (0x00000002) +#define NV507D_DAC_SET_CONTROL_SUB_OWNER 5:4 +#define NV507D_DAC_SET_CONTROL_SUB_OWNER_NONE (0x00000000) +#define NV507D_DAC_SET_CONTROL_SUB_OWNER_SUBHEAD0 (0x00000001) +#define NV507D_DAC_SET_CONTROL_SUB_OWNER_SUBHEAD1 (0x00000002) +#define NV507D_DAC_SET_CONTROL_SUB_OWNER_BOTH (0x00000003) +#define NV507D_DAC_SET_CONTROL_PROTOCOL 13:8 +#define NV507D_DAC_SET_CONTROL_PROTOCOL_RGB_CRT (0x00000000) +#define NV507D_DAC_SET_CONTROL_PROTOCOL_CPST_NTSC_M (0x00000001) +#define NV507D_DAC_SET_CONTROL_PROTOCOL_CPST_NTSC_J (0x00000002) +#define NV507D_DAC_SET_CONTROL_PROTOCOL_CPST_PAL_BDGHI (0x00000003) +#define NV507D_DAC_SET_CONTROL_PROTOCOL_CPST_PAL_M (0x00000004) +#define NV507D_DAC_SET_CONTROL_PROTOCOL_CPST_PAL_N (0x00000005) +#define NV507D_DAC_SET_CONTROL_PROTOCOL_CPST_PAL_CN (0x00000006) +#define NV507D_DAC_SET_CONTROL_PROTOCOL_COMP_NTSC_M (0x00000007) +#define NV507D_DAC_SET_CONTROL_PROTOCOL_COMP_NTSC_J (0x00000008) +#define NV507D_DAC_SET_CONTROL_PROTOCOL_COMP_PAL_BDGHI (0x00000009) +#define NV507D_DAC_SET_CONTROL_PROTOCOL_COMP_PAL_M (0x0000000A) +#define NV507D_DAC_SET_CONTROL_PROTOCOL_COMP_PAL_N (0x0000000B) +#define NV507D_DAC_SET_CONTROL_PROTOCOL_COMP_PAL_CN (0x0000000C) +#define NV507D_DAC_SET_CONTROL_PROTOCOL_COMP_480P_60 (0x0000000D) +#define NV507D_DAC_SET_CONTROL_PROTOCOL_COMP_576P_50 (0x0000000E) +#define NV507D_DAC_SET_CONTROL_PROTOCOL_COMP_720P_50 (0x0000000F) +#define NV507D_DAC_SET_CONTROL_PROTOCOL_COMP_720P_60 (0x00000010) +#define NV507D_DAC_SET_CONTROL_PROTOCOL_COMP_1080I_50 (0x00000011) +#define NV507D_DAC_SET_CONTROL_PROTOCOL_COMP_1080I_60 (0x00000012) +#define NV507D_DAC_SET_CONTROL_PROTOCOL_CUSTOM (0x0000003F) +#define NV507D_DAC_SET_CONTROL_INVALIDATE_FIRST_FIELD 14:14 +#define NV507D_DAC_SET_CONTROL_INVALIDATE_FIRST_FIELD_FALSE (0x00000000) +#define NV507D_DAC_SET_CONTROL_INVALIDATE_FIRST_FIELD_TRUE (0x00000001) +#define NV507D_DAC_SET_POLARITY(a) (0x00000404 + (a)*0x00000080) +#define NV507D_DAC_SET_POLARITY_HSYNC 0:0 +#define NV507D_DAC_SET_POLARITY_HSYNC_POSITIVE_TRUE (0x00000000) +#define NV507D_DAC_SET_POLARITY_HSYNC_NEGATIVE_TRUE (0x00000001) +#define NV507D_DAC_SET_POLARITY_VSYNC 1:1 +#define NV507D_DAC_SET_POLARITY_VSYNC_POSITIVE_TRUE (0x00000000) +#define NV507D_DAC_SET_POLARITY_VSYNC_NEGATIVE_TRUE (0x00000001) +#define NV507D_DAC_SET_POLARITY_RESERVED 31:2 + +#define NV507D_SOR_SET_CONTROL(a) (0x00000600 + (a)*0x00000040) +#define NV507D_SOR_SET_CONTROL_OWNER 3:0 +#define NV507D_SOR_SET_CONTROL_OWNER_NONE (0x00000000) +#define NV507D_SOR_SET_CONTROL_OWNER_HEAD0 (0x00000001) +#define NV507D_SOR_SET_CONTROL_OWNER_HEAD1 (0x00000002) +#define NV507D_SOR_SET_CONTROL_SUB_OWNER 5:4 +#define NV507D_SOR_SET_CONTROL_SUB_OWNER_NONE (0x00000000) +#define NV507D_SOR_SET_CONTROL_SUB_OWNER_SUBHEAD0 (0x00000001) +#define NV507D_SOR_SET_CONTROL_SUB_OWNER_SUBHEAD1 (0x00000002) +#define NV507D_SOR_SET_CONTROL_SUB_OWNER_BOTH (0x00000003) +#define NV507D_SOR_SET_CONTROL_PROTOCOL 11:8 +#define NV507D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM (0x00000000) +#define NV507D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A (0x00000001) +#define NV507D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B (0x00000002) +#define NV507D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_AB (0x00000003) +#define NV507D_SOR_SET_CONTROL_PROTOCOL_DUAL_SINGLE_TMDS (0x00000004) +#define NV507D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS (0x00000005) +#define NV507D_SOR_SET_CONTROL_PROTOCOL_DDI_OUT (0x00000007) +#define NV507D_SOR_SET_CONTROL_PROTOCOL_CUSTOM (0x0000000F) +#define NV507D_SOR_SET_CONTROL_HSYNC_POLARITY 12:12 +#define NV507D_SOR_SET_CONTROL_HSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV507D_SOR_SET_CONTROL_HSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV507D_SOR_SET_CONTROL_VSYNC_POLARITY 13:13 +#define NV507D_SOR_SET_CONTROL_VSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV507D_SOR_SET_CONTROL_VSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV507D_SOR_SET_CONTROL_DE_SYNC_POLARITY 14:14 +#define NV507D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV507D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001) + +#define NV507D_PIOR_SET_CONTROL(a) (0x00000700 + (a)*0x00000040) +#define NV507D_PIOR_SET_CONTROL_OWNER 3:0 +#define NV507D_PIOR_SET_CONTROL_OWNER_NONE (0x00000000) +#define NV507D_PIOR_SET_CONTROL_OWNER_HEAD0 (0x00000001) +#define NV507D_PIOR_SET_CONTROL_OWNER_HEAD1 (0x00000002) +#define NV507D_PIOR_SET_CONTROL_SUB_OWNER 5:4 +#define NV507D_PIOR_SET_CONTROL_SUB_OWNER_NONE (0x00000000) +#define NV507D_PIOR_SET_CONTROL_SUB_OWNER_SUBHEAD0 (0x00000001) +#define NV507D_PIOR_SET_CONTROL_SUB_OWNER_SUBHEAD1 (0x00000002) +#define NV507D_PIOR_SET_CONTROL_SUB_OWNER_BOTH (0x00000003) +#define NV507D_PIOR_SET_CONTROL_PROTOCOL 11:8 +#define NV507D_PIOR_SET_CONTROL_PROTOCOL_EXT_TMDS_ENC (0x00000000) +#define NV507D_PIOR_SET_CONTROL_PROTOCOL_EXT_TV_ENC (0x00000001) +#define NV507D_PIOR_SET_CONTROL_HSYNC_POLARITY 12:12 +#define NV507D_PIOR_SET_CONTROL_HSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV507D_PIOR_SET_CONTROL_HSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV507D_PIOR_SET_CONTROL_VSYNC_POLARITY 13:13 +#define NV507D_PIOR_SET_CONTROL_VSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV507D_PIOR_SET_CONTROL_VSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV507D_PIOR_SET_CONTROL_DE_SYNC_POLARITY 14:14 +#define NV507D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV507D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001) + +#define NV507D_HEAD_SET_PIXEL_CLOCK(a) (0x00000804 + (a)*0x00000400) +#define NV507D_HEAD_SET_PIXEL_CLOCK_FREQUENCY 21:0 +#define NV507D_HEAD_SET_PIXEL_CLOCK_MODE 23:22 +#define NV507D_HEAD_SET_PIXEL_CLOCK_MODE_CLK_25 (0x00000000) +#define NV507D_HEAD_SET_PIXEL_CLOCK_MODE_CLK_28 (0x00000001) +#define NV507D_HEAD_SET_PIXEL_CLOCK_MODE_CLK_CUSTOM (0x00000002) +#define NV507D_HEAD_SET_PIXEL_CLOCK_ADJ1000DIV1001 24:24 +#define NV507D_HEAD_SET_PIXEL_CLOCK_ADJ1000DIV1001_FALSE (0x00000000) +#define NV507D_HEAD_SET_PIXEL_CLOCK_ADJ1000DIV1001_TRUE (0x00000001) +#define NV507D_HEAD_SET_PIXEL_CLOCK_NOT_DRIVER 25:25 +#define NV507D_HEAD_SET_PIXEL_CLOCK_NOT_DRIVER_FALSE (0x00000000) +#define NV507D_HEAD_SET_PIXEL_CLOCK_NOT_DRIVER_TRUE (0x00000001) +#define NV507D_HEAD_SET_CONTROL(a) (0x00000808 + (a)*0x00000400) +#define NV507D_HEAD_SET_CONTROL_STRUCTURE 2:1 +#define NV507D_HEAD_SET_CONTROL_STRUCTURE_PROGRESSIVE (0x00000000) +#define NV507D_HEAD_SET_CONTROL_STRUCTURE_INTERLACED (0x00000001) +#define NV507D_HEAD_SET_OVERSCAN_COLOR(a) (0x00000810 + (a)*0x00000400) +#define NV507D_HEAD_SET_OVERSCAN_COLOR_RED 9:0 +#define NV507D_HEAD_SET_OVERSCAN_COLOR_GRN 19:10 +#define NV507D_HEAD_SET_OVERSCAN_COLOR_BLU 29:20 +#define NV507D_HEAD_SET_RASTER_SIZE(a) (0x00000814 + (a)*0x00000400) +#define NV507D_HEAD_SET_RASTER_SIZE_WIDTH 14:0 +#define NV507D_HEAD_SET_RASTER_SIZE_HEIGHT 30:16 +#define NV507D_HEAD_SET_RASTER_SYNC_END(a) (0x00000818 + (a)*0x00000400) +#define NV507D_HEAD_SET_RASTER_SYNC_END_X 14:0 +#define NV507D_HEAD_SET_RASTER_SYNC_END_Y 30:16 +#define NV507D_HEAD_SET_RASTER_BLANK_END(a) (0x0000081C + (a)*0x00000400) +#define NV507D_HEAD_SET_RASTER_BLANK_END_X 14:0 +#define NV507D_HEAD_SET_RASTER_BLANK_END_Y 30:16 +#define NV507D_HEAD_SET_RASTER_BLANK_START(a) (0x00000820 + (a)*0x00000400) +#define NV507D_HEAD_SET_RASTER_BLANK_START_X 14:0 +#define NV507D_HEAD_SET_RASTER_BLANK_START_Y 30:16 +#define NV507D_HEAD_SET_RASTER_VERT_BLANK2(a) (0x00000824 + (a)*0x00000400) +#define NV507D_HEAD_SET_RASTER_VERT_BLANK2_YSTART 14:0 +#define NV507D_HEAD_SET_RASTER_VERT_BLANK2_YEND 30:16 +#define NV507D_HEAD_SET_RASTER_VERT_BLANK_DMI(a) (0x00000828 + (a)*0x00000400) +#define NV507D_HEAD_SET_RASTER_VERT_BLANK_DMI_DURATION 11:0 +#define NV507D_HEAD_SET_DEFAULT_BASE_COLOR(a) (0x0000082C + (a)*0x00000400) +#define NV507D_HEAD_SET_DEFAULT_BASE_COLOR_RED 9:0 +#define NV507D_HEAD_SET_DEFAULT_BASE_COLOR_GREEN 19:10 +#define NV507D_HEAD_SET_DEFAULT_BASE_COLOR_BLUE 29:20 +#define NV507D_HEAD_SET_BASE_LUT_LO(a) (0x00000840 + (a)*0x00000400) +#define NV507D_HEAD_SET_BASE_LUT_LO_ENABLE 31:31 +#define NV507D_HEAD_SET_BASE_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV507D_HEAD_SET_BASE_LUT_LO_ENABLE_ENABLE (0x00000001) +#define NV507D_HEAD_SET_BASE_LUT_LO_MODE 30:30 +#define NV507D_HEAD_SET_BASE_LUT_LO_MODE_LORES (0x00000000) +#define NV507D_HEAD_SET_BASE_LUT_LO_MODE_HIRES (0x00000001) +#define NV507D_HEAD_SET_BASE_LUT_LO_ORIGIN 7:2 +#define NV507D_HEAD_SET_BASE_LUT_HI(a) (0x00000844 + (a)*0x00000400) +#define NV507D_HEAD_SET_BASE_LUT_HI_ORIGIN 31:0 +#define NV507D_HEAD_SET_OFFSET(a,b) (0x00000860 + (a)*0x00000400 + (b)*0x00000004) +#define NV507D_HEAD_SET_OFFSET_ORIGIN 31:0 +#define NV507D_HEAD_SET_SIZE(a) (0x00000868 + (a)*0x00000400) +#define NV507D_HEAD_SET_SIZE_WIDTH 14:0 +#define NV507D_HEAD_SET_SIZE_HEIGHT 30:16 +#define NV507D_HEAD_SET_STORAGE(a) (0x0000086C + (a)*0x00000400) +#define NV507D_HEAD_SET_STORAGE_BLOCK_HEIGHT 3:0 +#define NV507D_HEAD_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB (0x00000000) +#define NV507D_HEAD_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS (0x00000001) +#define NV507D_HEAD_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS (0x00000002) +#define NV507D_HEAD_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003) +#define NV507D_HEAD_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NV507D_HEAD_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NV507D_HEAD_SET_STORAGE_PITCH 17:8 +#define NV507D_HEAD_SET_STORAGE_MEMORY_LAYOUT 20:20 +#define NV507D_HEAD_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NV507D_HEAD_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001) +#define NV507D_HEAD_SET_PARAMS(a) (0x00000870 + (a)*0x00000400) +#define NV507D_HEAD_SET_PARAMS_FORMAT 15:8 +#define NV507D_HEAD_SET_PARAMS_FORMAT_I8 (0x0000001E) +#define NV507D_HEAD_SET_PARAMS_FORMAT_VOID16 (0x0000001F) +#define NV507D_HEAD_SET_PARAMS_FORMAT_VOID32 (0x0000002E) +#define NV507D_HEAD_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA) +#define NV507D_HEAD_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF) +#define NV507D_HEAD_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1) +#define NV507D_HEAD_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5) +#define NV507D_HEAD_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8) +#define NV507D_HEAD_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9) +#define NV507D_HEAD_SET_PARAMS_KIND 22:16 +#define NV507D_HEAD_SET_PARAMS_KIND_KIND_PITCH (0x00000000) +#define NV507D_HEAD_SET_PARAMS_KIND_KIND_GENERIC_8BX2 (0x00000070) +#define NV507D_HEAD_SET_PARAMS_KIND_KIND_GENERIC_8BX2_BANKSWIZ (0x00000072) +#define NV507D_HEAD_SET_PARAMS_KIND_KIND_GENERIC_16BX1 (0x00000074) +#define NV507D_HEAD_SET_PARAMS_KIND_KIND_GENERIC_16BX1_BANKSWIZ (0x00000076) +#define NV507D_HEAD_SET_PARAMS_KIND_KIND_C32_MS4 (0x00000078) +#define NV507D_HEAD_SET_PARAMS_KIND_KIND_C32_MS8 (0x00000079) +#define NV507D_HEAD_SET_PARAMS_KIND_KIND_C32_MS4_BANKSWIZ (0x0000007A) +#define NV507D_HEAD_SET_PARAMS_KIND_KIND_C32_MS8_BANKSWIZ (0x0000007B) +#define NV507D_HEAD_SET_PARAMS_KIND_KIND_C64_MS4 (0x0000007C) +#define NV507D_HEAD_SET_PARAMS_KIND_KIND_C64_MS8 (0x0000007D) +#define NV507D_HEAD_SET_PARAMS_KIND_KIND_C128_MS4 (0x0000007E) +#define NV507D_HEAD_SET_PARAMS_KIND_FROM_PTE (0x0000007F) +#define NV507D_HEAD_SET_PARAMS_PART_STRIDE 24:24 +#define NV507D_HEAD_SET_PARAMS_PART_STRIDE_PARTSTRIDE_256 (0x00000000) +#define NV507D_HEAD_SET_PARAMS_PART_STRIDE_PARTSTRIDE_1024 (0x00000001) +#define NV507D_HEAD_SET_CONTEXT_DMA_ISO(a) (0x00000874 + (a)*0x00000400) +#define NV507D_HEAD_SET_CONTEXT_DMA_ISO_HANDLE 31:0 +#define NV507D_HEAD_SET_CONTROL_CURSOR(a) (0x00000880 + (a)*0x00000400) +#define NV507D_HEAD_SET_CONTROL_CURSOR_ENABLE 31:31 +#define NV507D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE (0x00000000) +#define NV507D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE (0x00000001) +#define NV507D_HEAD_SET_CONTROL_CURSOR_FORMAT 25:24 +#define NV507D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5 (0x00000000) +#define NV507D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8 (0x00000001) +#define NV507D_HEAD_SET_CONTROL_CURSOR_SIZE 26:26 +#define NV507D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32 (0x00000000) +#define NV507D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64 (0x00000001) +#define NV507D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X 13:8 +#define NV507D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y 21:16 +#define NV507D_HEAD_SET_CONTROL_CURSOR_COMPOSITION 29:28 +#define NV507D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_ALPHA_BLEND (0x00000000) +#define NV507D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_PREMULT_ALPHA_BLEND (0x00000001) +#define NV507D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_XOR (0x00000002) +#define NV507D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER 5:4 +#define NV507D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_NONE (0x00000000) +#define NV507D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_SUBHEAD0 (0x00000001) +#define NV507D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_SUBHEAD1 (0x00000002) +#define NV507D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_BOTH (0x00000003) +#define NV507D_HEAD_SET_OFFSET_CURSOR(a) (0x00000884 + (a)*0x00000400) +#define NV507D_HEAD_SET_OFFSET_CURSOR_ORIGIN 31:0 +#define NV507D_HEAD_SET_DITHER_CONTROL(a) (0x000008A0 + (a)*0x00000400) +#define NV507D_HEAD_SET_DITHER_CONTROL_ENABLE 0:0 +#define NV507D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE (0x00000000) +#define NV507D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE (0x00000001) +#define NV507D_HEAD_SET_DITHER_CONTROL_BITS 2:1 +#define NV507D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_6_BITS (0x00000000) +#define NV507D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_8_BITS (0x00000001) +#define NV507D_HEAD_SET_DITHER_CONTROL_MODE 6:3 +#define NV507D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC (0x00000000) +#define NV507D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC (0x00000001) +#define NV507D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2 (0x00000002) +#define NV507D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2 (0x00000003) +#define NV507D_HEAD_SET_DITHER_CONTROL_PHASE 8:7 +#define NV507D_HEAD_SET_CONTROL_OUTPUT_SCALER(a) (0x000008A4 + (a)*0x00000400) +#define NV507D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS 2:0 +#define NV507D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_1 (0x00000000) +#define NV507D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_2 (0x00000001) +#define NV507D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3 (0x00000002) +#define NV507D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3_ADAPTIVE (0x00000003) +#define NV507D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_5 (0x00000004) +#define NV507D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS 4:3 +#define NV507D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_1 (0x00000000) +#define NV507D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_2 (0x00000001) +#define NV507D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_8 (0x00000002) +#define NV507D_HEAD_SET_CONTROL_OUTPUT_SCALER_HRESPONSE_BIAS 23:16 +#define NV507D_HEAD_SET_CONTROL_OUTPUT_SCALER_VRESPONSE_BIAS 31:24 +#define NV507D_HEAD_SET_PROCAMP(a) (0x000008A8 + (a)*0x00000400) +#define NV507D_HEAD_SET_PROCAMP_COLOR_SPACE 1:0 +#define NV507D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB (0x00000000) +#define NV507D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601 (0x00000001) +#define NV507D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709 (0x00000002) +#define NV507D_HEAD_SET_PROCAMP_CHROMA_LPF 2:2 +#define NV507D_HEAD_SET_PROCAMP_CHROMA_LPF_AUTO (0x00000000) +#define NV507D_HEAD_SET_PROCAMP_CHROMA_LPF_ON (0x00000001) +#define NV507D_HEAD_SET_PROCAMP_SAT_COS 19:8 +#define NV507D_HEAD_SET_PROCAMP_SAT_SINE 31:20 +#define NV507D_HEAD_SET_PROCAMP_TRANSITION 4:3 +#define NV507D_HEAD_SET_PROCAMP_TRANSITION_HARD (0x00000000) +#define NV507D_HEAD_SET_PROCAMP_TRANSITION_NTSC (0x00000001) +#define NV507D_HEAD_SET_PROCAMP_TRANSITION_PAL (0x00000002) +#define NV507D_HEAD_SET_VIEWPORT_POINT_IN(a,b) (0x000008C0 + (a)*0x00000400 + (b)*0x00000004) +#define NV507D_HEAD_SET_VIEWPORT_POINT_IN_X 14:0 +#define NV507D_HEAD_SET_VIEWPORT_POINT_IN_Y 30:16 +#define NV507D_HEAD_SET_VIEWPORT_SIZE_IN(a) (0x000008C8 + (a)*0x00000400) +#define NV507D_HEAD_SET_VIEWPORT_SIZE_IN_WIDTH 14:0 +#define NV507D_HEAD_SET_VIEWPORT_SIZE_IN_HEIGHT 30:16 +#define NV507D_HEAD_SET_VIEWPORT_SIZE_OUT(a) (0x000008D8 + (a)*0x00000400) +#define NV507D_HEAD_SET_VIEWPORT_SIZE_OUT_WIDTH 14:0 +#define NV507D_HEAD_SET_VIEWPORT_SIZE_OUT_HEIGHT 30:16 +#define NV507D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN(a) (0x000008DC + (a)*0x00000400) +#define NV507D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_WIDTH 14:0 +#define NV507D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_HEIGHT 30:16 +#define NV507D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(a) (0x00000900 + (a)*0x00000400) +#define NV507D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE 0:0 +#define NV507D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_FALSE (0x00000000) +#define NV507D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_TRUE (0x00000001) +#define NV507D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH 11:8 +#define NV507D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_8 (0x00000000) +#define NV507D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16 (0x00000001) +#define NV507D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32 (0x00000003) +#define NV507D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64 (0x00000005) +#define NV507D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE 13:12 +#define NV507D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X1_AA (0x00000000) +#define NV507D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X4_AA (0x00000002) +#define NV507D_HEAD_SET_OVERLAY_USAGE_BOUNDS(a) (0x00000904 + (a)*0x00000400) +#define NV507D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE 0:0 +#define NV507D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_FALSE (0x00000000) +#define NV507D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_TRUE (0x00000001) +#define NV507D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH 11:8 +#define NV507D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16 (0x00000001) +#define NV507D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32 (0x00000003) +#endif // _cl507d_h diff --git a/drivers/gpu/drm/nouveau/include/nvhw/class/clc37d.h b/drivers/gpu/drm/nouveau/include/nvhw/class/clc37d.h new file mode 100644 index 000000000000..2b8c314c9ed9 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvhw/class/clc37d.h @@ -0,0 +1,567 @@ +/* + * Copyright (c) 1993-2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _clC37d_h_ +#define _clC37d_h_ + +#define NV_DISP_NOTIFIER 0x00000000 +#define NV_DISP_NOTIFIER_SIZEOF 0x00000010 +#define NV_DISP_NOTIFIER__0 0x00000000 +#define NV_DISP_NOTIFIER__0_PRESENT_COUNT 7:0 +#define NV_DISP_NOTIFIER__0_FIELD 8:8 +#define NV_DISP_NOTIFIER__0_FLIP_TYPE 9:9 +#define NV_DISP_NOTIFIER__0_FLIP_TYPE_NON_TEARING 0x00000000 +#define NV_DISP_NOTIFIER__0_FLIP_TYPE_IMMEDIATE 0x00000001 +#define NV_DISP_NOTIFIER__0_R1 15:10 +#define NV_DISP_NOTIFIER__0_R2 23:16 +#define NV_DISP_NOTIFIER__0_R3 29:24 +#define NV_DISP_NOTIFIER__0_STATUS 31:30 +#define NV_DISP_NOTIFIER__0_STATUS_NOT_BEGUN 0x00000000 +#define NV_DISP_NOTIFIER__0_STATUS_BEGUN 0x00000001 +#define NV_DISP_NOTIFIER__0_STATUS_FINISHED 0x00000002 +#define NV_DISP_NOTIFIER__1 0x00000001 +#define NV_DISP_NOTIFIER__1_R4 31:0 +#define NV_DISP_NOTIFIER__2 0x00000002 +#define NV_DISP_NOTIFIER__2_TIMESTAMP_LO 31:0 +#define NV_DISP_NOTIFIER__3 0x00000003 +#define NV_DISP_NOTIFIER__3_TIMESTAMP_HI 31:0 + + +// class methods +#define NVC37D_UPDATE (0x00000200) +#define NVC37D_UPDATE_SPECIAL_HANDLING 21:20 +#define NVC37D_UPDATE_SPECIAL_HANDLING_NONE (0x00000000) +#define NVC37D_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM (0x00000001) +#define NVC37D_UPDATE_SPECIAL_HANDLING_MODE_SWITCH (0x00000002) +#define NVC37D_UPDATE_SPECIAL_HANDLING_REASON 19:12 +#define NVC37D_UPDATE_INHIBIT_INTERRUPTS 24:24 +#define NVC37D_UPDATE_INHIBIT_INTERRUPTS_FALSE (0x00000000) +#define NVC37D_UPDATE_INHIBIT_INTERRUPTS_TRUE (0x00000001) +#define NVC37D_SET_CONTEXT_DMA_NOTIFIER (0x00000208) +#define NVC37D_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0 +#define NVC37D_SET_NOTIFIER_CONTROL (0x0000020C) +#define NVC37D_SET_NOTIFIER_CONTROL_MODE 0:0 +#define NVC37D_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000) +#define NVC37D_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001) +#define NVC37D_SET_NOTIFIER_CONTROL_OFFSET 11:4 +#define NVC37D_SET_NOTIFIER_CONTROL_NOTIFY 12:12 +#define NVC37D_SET_NOTIFIER_CONTROL_NOTIFY_DISABLE (0x00000000) +#define NVC37D_SET_NOTIFIER_CONTROL_NOTIFY_ENABLE (0x00000001) +#define NVC37D_SET_INTERLOCK_FLAGS (0x00000218) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR(i) ((i)+0):((i)+0) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR__SIZE_1 8 +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_DISABLE (0x00000000) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR_ENABLE (0x00000001) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0 0:0 +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1 1:1 +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2 2:2 +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3 3:3 +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4 4:4 +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_DISABLE (0x00000000) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR4_ENABLE (0x00000001) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5 5:5 +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_DISABLE (0x00000000) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR5_ENABLE (0x00000001) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6 6:6 +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_DISABLE (0x00000000) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR6_ENABLE (0x00000001) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7 7:7 +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_DISABLE (0x00000000) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CURSOR7_ENABLE (0x00000001) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE 16:16 +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NVC37D_SET_INTERLOCK_FLAGS_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS (0x0000021C) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW(i) ((i)+0):((i)+0) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW__SIZE_1 32 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0 0:0 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW0_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1 1:1 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW1_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2 2:2 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW2_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3 3:3 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW3_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4 4:4 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW4_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5 5:5 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW5_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6 6:6 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW6_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7 7:7 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW7_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8 8:8 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW8_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9 9:9 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW9_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10 10:10 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW10_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11 11:11 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW11_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12 12:12 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW12_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13 13:13 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW13_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14 14:14 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW14_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15 15:15 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW15_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16 16:16 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW16_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17 17:17 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW17_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18 18:18 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW18_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19 19:19 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW19_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20 20:20 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW20_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21 21:21 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW21_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22 22:22 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW22_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23 23:23 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW23_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24 24:24 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW24_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25 25:25 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW25_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26 26:26 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW26_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27 27:27 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW27_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28 28:28 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW28_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29 29:29 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW29_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30 30:30 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW30_ENABLE (0x00000001) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31 31:31 +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_DISABLE (0x00000000) +#define NVC37D_SET_WINDOW_INTERLOCK_FLAGS_INTERLOCK_WITH_WINDOW31_ENABLE (0x00000001) + +#define NVC37D_SOR_SET_CONTROL(a) (0x00000300 + (a)*0x00000020) +#define NVC37D_SOR_SET_CONTROL_OWNER_MASK 7:0 +#define NVC37D_SOR_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NVC37D_SOR_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NVC37D_SOR_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NVC37D_SOR_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NVC37D_SOR_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NVC37D_SOR_SET_CONTROL_OWNER_MASK_HEAD4 (0x00000010) +#define NVC37D_SOR_SET_CONTROL_OWNER_MASK_HEAD5 (0x00000020) +#define NVC37D_SOR_SET_CONTROL_OWNER_MASK_HEAD6 (0x00000040) +#define NVC37D_SOR_SET_CONTROL_OWNER_MASK_HEAD7 (0x00000080) +#define NVC37D_SOR_SET_CONTROL_PROTOCOL 11:8 +#define NVC37D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM (0x00000000) +#define NVC37D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A (0x00000001) +#define NVC37D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B (0x00000002) +#define NVC37D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS (0x00000005) +#define NVC37D_SOR_SET_CONTROL_PROTOCOL_DP_A (0x00000008) +#define NVC37D_SOR_SET_CONTROL_PROTOCOL_DP_B (0x00000009) +#define NVC37D_SOR_SET_CONTROL_PROTOCOL_DSI (0x0000000A) +#define NVC37D_SOR_SET_CONTROL_PROTOCOL_CUSTOM (0x0000000F) +#define NVC37D_SOR_SET_CONTROL_DE_SYNC_POLARITY 16:16 +#define NVC37D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NVC37D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NVC37D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE 21:20 +#define NVC37D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_OFF (0x00000000) +#define NVC37D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X2 (0x00000001) +#define NVC37D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X4 (0x00000002) + +#define NVC37D_WINDOW_SET_CONTROL(a) (0x00001000 + (a)*0x00000080) +#define NVC37D_WINDOW_SET_CONTROL_OWNER 3:0 +#define NVC37D_WINDOW_SET_CONTROL_OWNER_HEAD(i) (0x00000000 +(i)) +#define NVC37D_WINDOW_SET_CONTROL_OWNER_HEAD__SIZE_1 8 +#define NVC37D_WINDOW_SET_CONTROL_OWNER_HEAD0 (0x00000000) +#define NVC37D_WINDOW_SET_CONTROL_OWNER_HEAD1 (0x00000001) +#define NVC37D_WINDOW_SET_CONTROL_OWNER_HEAD2 (0x00000002) +#define NVC37D_WINDOW_SET_CONTROL_OWNER_HEAD3 (0x00000003) +#define NVC37D_WINDOW_SET_CONTROL_OWNER_HEAD4 (0x00000004) +#define NVC37D_WINDOW_SET_CONTROL_OWNER_HEAD5 (0x00000005) +#define NVC37D_WINDOW_SET_CONTROL_OWNER_HEAD6 (0x00000006) +#define NVC37D_WINDOW_SET_CONTROL_OWNER_HEAD7 (0x00000007) +#define NVC37D_WINDOW_SET_CONTROL_OWNER_NONE (0x0000000F) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS(a) (0x00001004 + (a)*0x00000080) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP 0:0 +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP 1:1 +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP 2:2 +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP 3:3 +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PACKED422 4:4 +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PACKED422_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PACKED422_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR420 5:5 +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR444 6:6 +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420 7:7 +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422 8:8 +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R 9:9 +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444 10:10 +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420 11:11 +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444 12:12 +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420 13:13 +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422 14:14 +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R 15:15 +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444 16:16 +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS(a) (0x00001008 + (a)*0x00000080) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP 0:0 +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP 1:1 +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP 2:2 +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP 3:3 +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PACKED422 4:4 +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PACKED422_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PACKED422_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR420 5:5 +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR444 6:6 +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420 7:7 +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422 8:8 +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R 9:9 +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444 10:10 +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420 11:11 +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444 12:12 +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420 13:13 +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422 14:14 +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R 15:15 +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444 16:16 +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_TRUE (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS(a) (0x00001010 + (a)*0x00000080) +#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_MAX_PIXELS_FETCHED_PER_LINE 14:0 +#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_LUT 17:16 +#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_LUT_USAGE_NONE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_LUT_USAGE_257 (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_LUT_USAGE_1025 (0x00000002) +#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_SCALER_TAPS 22:20 +#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_SCALER_TAPS_TAPS_2 (0x00000001) +#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_SCALER_TAPS_TAPS_5 (0x00000004) +#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_UPSCALING_ALLOWED 24:24 +#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_UPSCALING_ALLOWED_FALSE (0x00000000) +#define NVC37D_WINDOW_SET_WINDOW_USAGE_BOUNDS_UPSCALING_ALLOWED_TRUE (0x00000001) + +#define NVC37D_HEAD_SET_PROCAMP(a) (0x00002000 + (a)*0x00000400) +#define NVC37D_HEAD_SET_PROCAMP_COLOR_SPACE 1:0 +#define NVC37D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB (0x00000000) +#define NVC37D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601 (0x00000001) +#define NVC37D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709 (0x00000002) +#define NVC37D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_2020 (0x00000003) +#define NVC37D_HEAD_SET_PROCAMP_CHROMA_LPF 3:3 +#define NVC37D_HEAD_SET_PROCAMP_CHROMA_LPF_DISABLE (0x00000000) +#define NVC37D_HEAD_SET_PROCAMP_CHROMA_LPF_ENABLE (0x00000001) +#define NVC37D_HEAD_SET_PROCAMP_SAT_COS 15:4 +#define NVC37D_HEAD_SET_PROCAMP_SAT_SINE 27:16 +#define NVC37D_HEAD_SET_PROCAMP_DYNAMIC_RANGE 28:28 +#define NVC37D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_VESA (0x00000000) +#define NVC37D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_CEA (0x00000001) +#define NVC37D_HEAD_SET_PROCAMP_RANGE_COMPRESSION 29:29 +#define NVC37D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_DISABLE (0x00000000) +#define NVC37D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_ENABLE (0x00000001) +#define NVC37D_HEAD_SET_PROCAMP_BLACK_LEVEL 31:30 +#define NVC37D_HEAD_SET_PROCAMP_BLACK_LEVEL_AUTO (0x00000000) +#define NVC37D_HEAD_SET_PROCAMP_BLACK_LEVEL_VIDEO (0x00000001) +#define NVC37D_HEAD_SET_PROCAMP_BLACK_LEVEL_GRAPHICS (0x00000002) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE(a) (0x00002004 + (a)*0x00000400) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE 1:0 +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_ACTIVE_RASTER (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_COMPLETE_RASTER (0x00000001) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_NON_ACTIVE_RASTER (0x00000002) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY 2:2 +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY 3:3 +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH 7:4 +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_422 (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444 (0x00000001) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_20_422 (0x00000002) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_422 (0x00000003) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444 (0x00000004) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_30_444 (0x00000005) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_32_422 (0x00000006) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_36_444 (0x00000007) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_48_444 (0x00000008) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE 24:24 +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_DISABLE (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_ENABLE (0x00000001) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_FLAG 23:12 +#define NVC37D_HEAD_SET_PIXEL_CLOCK_FREQUENCY(a) (0x0000200C + (a)*0x00000400) +#define NVC37D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HERTZ 30:0 +#define NVC37D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001 31:31 +#define NVC37D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_FALSE (0x00000000) +#define NVC37D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_TRUE (0x00000001) +#define NVC37D_HEAD_SET_DITHER_CONTROL(a) (0x00002018 + (a)*0x00000400) +#define NVC37D_HEAD_SET_DITHER_CONTROL_ENABLE 0:0 +#define NVC37D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE (0x00000000) +#define NVC37D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE (0x00000001) +#define NVC37D_HEAD_SET_DITHER_CONTROL_BITS 5:4 +#define NVC37D_HEAD_SET_DITHER_CONTROL_BITS_TO_6_BITS (0x00000000) +#define NVC37D_HEAD_SET_DITHER_CONTROL_BITS_TO_8_BITS (0x00000001) +#define NVC37D_HEAD_SET_DITHER_CONTROL_BITS_TO_10_BITS (0x00000002) +#define NVC37D_HEAD_SET_DITHER_CONTROL_BITS_TO_12_BITS (0x00000003) +#define NVC37D_HEAD_SET_DITHER_CONTROL_OFFSET_ENABLE 2:2 +#define NVC37D_HEAD_SET_DITHER_CONTROL_OFFSET_ENABLE_DISABLE (0x00000000) +#define NVC37D_HEAD_SET_DITHER_CONTROL_OFFSET_ENABLE_ENABLE (0x00000001) +#define NVC37D_HEAD_SET_DITHER_CONTROL_MODE 10:8 +#define NVC37D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC (0x00000000) +#define NVC37D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC (0x00000001) +#define NVC37D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2 (0x00000002) +#define NVC37D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2 (0x00000003) +#define NVC37D_HEAD_SET_DITHER_CONTROL_MODE_TEMPORAL (0x00000004) +#define NVC37D_HEAD_SET_DITHER_CONTROL_PHASE 13:12 +#define NVC37D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(a) (0x00002028 + (a)*0x00000400) +#define NVC37D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_HERTZ 30:0 +#define NVC37D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001 31:31 +#define NVC37D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_FALSE (0x00000000) +#define NVC37D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_TRUE (0x00000001) +#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS(a) (0x00002030 + (a)*0x00000400) +#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR 2:0 +#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_NONE (0x00000000) +#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W32_H32 (0x00000001) +#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W64_H64 (0x00000002) +#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W128_H128 (0x00000003) +#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W256_H256 (0x00000004) +#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_LUT 5:4 +#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_LUT_USAGE_NONE (0x00000000) +#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_LUT_USAGE_257 (0x00000001) +#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_LUT_USAGE_1025 (0x00000002) +#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_UPSCALING_ALLOWED 8:8 +#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_UPSCALING_ALLOWED_FALSE (0x00000000) +#define NVC37D_HEAD_SET_HEAD_USAGE_BOUNDS_UPSCALING_ALLOWED_TRUE (0x00000001) +#define NVC37D_HEAD_SET_VIEWPORT_SIZE_IN(a) (0x0000204C + (a)*0x00000400) +#define NVC37D_HEAD_SET_VIEWPORT_SIZE_IN_WIDTH 14:0 +#define NVC37D_HEAD_SET_VIEWPORT_SIZE_IN_HEIGHT 30:16 +#define NVC37D_HEAD_SET_VIEWPORT_SIZE_OUT(a) (0x00002058 + (a)*0x00000400) +#define NVC37D_HEAD_SET_VIEWPORT_SIZE_OUT_WIDTH 14:0 +#define NVC37D_HEAD_SET_VIEWPORT_SIZE_OUT_HEIGHT 30:16 +#define NVC37D_HEAD_SET_RASTER_SIZE(a) (0x00002064 + (a)*0x00000400) +#define NVC37D_HEAD_SET_RASTER_SIZE_WIDTH 14:0 +#define NVC37D_HEAD_SET_RASTER_SIZE_HEIGHT 30:16 +#define NVC37D_HEAD_SET_RASTER_SYNC_END(a) (0x00002068 + (a)*0x00000400) +#define NVC37D_HEAD_SET_RASTER_SYNC_END_X 14:0 +#define NVC37D_HEAD_SET_RASTER_SYNC_END_Y 30:16 +#define NVC37D_HEAD_SET_RASTER_BLANK_END(a) (0x0000206C + (a)*0x00000400) +#define NVC37D_HEAD_SET_RASTER_BLANK_END_X 14:0 +#define NVC37D_HEAD_SET_RASTER_BLANK_END_Y 30:16 +#define NVC37D_HEAD_SET_RASTER_BLANK_START(a) (0x00002070 + (a)*0x00000400) +#define NVC37D_HEAD_SET_RASTER_BLANK_START_X 14:0 +#define NVC37D_HEAD_SET_RASTER_BLANK_START_Y 30:16 +#define NVC37D_HEAD_SET_CONTEXT_DMA_CURSOR(a,b) (0x00002088 + (a)*0x00000400 + (b)*0x00000004) +#define NVC37D_HEAD_SET_CONTEXT_DMA_CURSOR_HANDLE 31:0 +#define NVC37D_HEAD_SET_OFFSET_CURSOR(a,b) (0x00002090 + (a)*0x00000400 + (b)*0x00000004) +#define NVC37D_HEAD_SET_OFFSET_CURSOR_ORIGIN 31:0 +#define NVC37D_HEAD_SET_CONTROL_CURSOR(a) (0x0000209C + (a)*0x00000400) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_ENABLE 31:31 +#define NVC37D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE (0x00000001) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_FORMAT 7:0 +#define NVC37D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5 (0x000000E9) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8 (0x000000CF) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_SIZE 9:8 +#define NVC37D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32 (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64 (0x00000001) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_SIZE_W128_H128 (0x00000002) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_SIZE_W256_H256 (0x00000003) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X 19:12 +#define NVC37D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y 27:20 +#define NVC37D_HEAD_SET_CONTROL_CURSOR_DE_GAMMA 29:28 +#define NVC37D_HEAD_SET_CONTROL_CURSOR_DE_GAMMA_NONE (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_DE_GAMMA_SRGB (0x00000001) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_DE_GAMMA_YUV8_10 (0x00000002) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_DE_GAMMA_YUV12 (0x00000003) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION(a) (0x000020A0 + (a)*0x00000400) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_K1 7:0 +#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_CURSOR_COLOR_FACTOR_SELECT 11:8 +#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_CURSOR_COLOR_FACTOR_SELECT_K1 (0x00000002) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_CURSOR_COLOR_FACTOR_SELECT_K1_TIMES_SRC (0x00000005) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT 15:12 +#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT_ZERO (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT_K1 (0x00000002) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_VIEWPORT_COLOR_FACTOR_SELECT_NEG_K1_TIMES_SRC (0x00000007) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_MODE 16:16 +#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_MODE_BLEND (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_MODE_XOR (0x00000001) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT(a) (0x000020A4 + (a)*0x00000400) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_SIZE 1:0 +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_SIZE_SIZE_257 (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_SIZE_SIZE_1025 (0x00000002) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_RANGE 5:4 +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_RANGE_UNITY (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_RANGE_XRBIAS (0x00000001) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_RANGE_XVYCC (0x00000002) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_OUTPUT_MODE 9:8 +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_OUTPUT_MODE_INDEX (0x00000000) +#define NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_OUTPUT_MODE_INTERPOLATE (0x00000001) +#define NVC37D_HEAD_SET_OFFSET_OUTPUT_LUT(a) (0x000020A8 + (a)*0x00000400) +#define NVC37D_HEAD_SET_OFFSET_OUTPUT_LUT_ORIGIN 31:0 +#define NVC37D_HEAD_SET_CONTEXT_DMA_OUTPUT_LUT(a) (0x000020AC + (a)*0x00000400) +#define NVC37D_HEAD_SET_CONTEXT_DMA_OUTPUT_LUT_HANDLE 31:0 +#define NVC37D_HEAD_SET_CONTEXT_DMA_CRC(a) (0x00002180 + (a)*0x00000400) +#define NVC37D_HEAD_SET_CONTEXT_DMA_CRC_HANDLE 31:0 +#define NVC37D_HEAD_SET_CRC_CONTROL(a) (0x00002184 + (a)*0x00000400) +#define NVC37D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL 4:0 +#define NVC37D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE 8:8 +#define NVC37D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE_FALSE (0x00000000) +#define NVC37D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE_TRUE (0x00000001) +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC 19:12 +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_NONE (0x00000000) +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SF (0x00000030) +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR(i) (0x00000050 +(i)) +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR__SIZE_1 8 +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR0 (0x00000050) +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR1 (0x00000051) +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR2 (0x00000052) +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR3 (0x00000053) +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR4 (0x00000054) +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR5 (0x00000055) +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR6 (0x00000056) +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_SOR7 (0x00000057) +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_PIOR(i) (0x00000060 +(i)) +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_PIOR__SIZE_1 4 +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_PIOR0 (0x00000060) +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_PIOR1 (0x00000061) +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_PIOR2 (0x00000062) +#define NVC37D_HEAD_SET_CRC_CONTROL_PRIMARY_CRC_PIOR3 (0x00000063) +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC 27:20 +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_NONE (0x00000000) +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SF (0x00000030) +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR(i) (0x00000050 +(i)) +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR__SIZE_1 8 +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR0 (0x00000050) +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR1 (0x00000051) +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR2 (0x00000052) +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR3 (0x00000053) +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR4 (0x00000054) +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR5 (0x00000055) +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR6 (0x00000056) +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_SOR7 (0x00000057) +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_PIOR(i) (0x00000060 +(i)) +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_PIOR__SIZE_1 4 +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_PIOR0 (0x00000060) +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_PIOR1 (0x00000061) +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_PIOR2 (0x00000062) +#define NVC37D_HEAD_SET_CRC_CONTROL_SECONDARY_CRC_PIOR3 (0x00000063) +#define NVC37D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE 9:9 +#define NVC37D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE_DISABLE (0x00000000) +#define NVC37D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE_ENABLE (0x00000001) +#endif // _clC37d_h diff --git a/drivers/gpu/drm/nouveau/include/nvhw/class/clc57d.h b/drivers/gpu/drm/nouveau/include/nvhw/class/clc57d.h new file mode 100644 index 000000000000..d83ac815e06c --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvhw/class/clc57d.h @@ -0,0 +1,286 @@ +/* + * Copyright (c) 1993-2020, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _clC57d_h_ +#define _clC57d_h_ + +// class methods +#define NVC57D_SET_CONTEXT_DMA_NOTIFIER (0x00000208) +#define NVC57D_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0 + +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS(a) (0x00001004 + (a)*0x00000080) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP 0:0 +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP 1:1 +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP 2:2 +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP 3:3 +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PACKED422 4:4 +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PACKED422_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PACKED422_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR420 5:5 +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR444 6:6 +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420 7:7 +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422 8:8 +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R 9:9 +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444 10:10 +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420 11:11 +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444 12:12 +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420 13:13 +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422 14:14 +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R 15:15 +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444 16:16 +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS(a) (0x00001008 + (a)*0x00000080) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP 0:0 +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP 1:1 +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP 2:2 +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP 3:3 +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_RGB_PACKED8BPP_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PACKED422 4:4 +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PACKED422_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PACKED422_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR420 5:5 +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR420_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR444 6:6 +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_PLANAR444_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420 7:7 +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR420_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422 8:8 +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R 9:9 +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR422R_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444 10:10 +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_YUV_SEMI_PLANAR444_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420 11:11 +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR420_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444 12:12 +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_PLANAR444_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420 13:13 +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR420_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422 14:14 +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R 15:15 +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR422R_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444 16:16 +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_ROTATED_FORMAT_USAGE_BOUNDS_EXT_YUV_SEMI_PLANAR444_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_USAGE_BOUNDS(a) (0x00001010 + (a)*0x00000080) +#define NVC57D_WINDOW_SET_WINDOW_USAGE_BOUNDS_MAX_PIXELS_FETCHED_PER_LINE 14:0 +#define NVC57D_WINDOW_SET_WINDOW_USAGE_BOUNDS_ILUT_ALLOWED 16:16 +#define NVC57D_WINDOW_SET_WINDOW_USAGE_BOUNDS_ILUT_ALLOWED_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_USAGE_BOUNDS_ILUT_ALLOWED_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_USAGE_BOUNDS_TMO_LUT_ALLOWED 28:28 +#define NVC57D_WINDOW_SET_WINDOW_USAGE_BOUNDS_TMO_LUT_ALLOWED_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_USAGE_BOUNDS_TMO_LUT_ALLOWED_TRUE (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_SCALER_TAPS 22:20 +#define NVC57D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_SCALER_TAPS_TAPS_2 (0x00000001) +#define NVC57D_WINDOW_SET_WINDOW_USAGE_BOUNDS_INPUT_SCALER_TAPS_TAPS_5 (0x00000004) +#define NVC57D_WINDOW_SET_WINDOW_USAGE_BOUNDS_UPSCALING_ALLOWED 24:24 +#define NVC57D_WINDOW_SET_WINDOW_USAGE_BOUNDS_UPSCALING_ALLOWED_FALSE (0x00000000) +#define NVC57D_WINDOW_SET_WINDOW_USAGE_BOUNDS_UPSCALING_ALLOWED_TRUE (0x00000001) + +#define NVC57D_HEAD_SET_PROCAMP(a) (0x00002000 + (a)*0x00000400) +#define NVC57D_HEAD_SET_PROCAMP_COLOR_SPACE 1:0 +#define NVC57D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB (0x00000000) +#define NVC57D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601 (0x00000001) +#define NVC57D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709 (0x00000002) +#define NVC57D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_2020 (0x00000003) +#define NVC57D_HEAD_SET_PROCAMP_CHROMA_LPF 3:3 +#define NVC57D_HEAD_SET_PROCAMP_CHROMA_LPF_DISABLE (0x00000000) +#define NVC57D_HEAD_SET_PROCAMP_CHROMA_LPF_ENABLE (0x00000001) +#define NVC57D_HEAD_SET_PROCAMP_DYNAMIC_RANGE 28:28 +#define NVC57D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_VESA (0x00000000) +#define NVC57D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_CEA (0x00000001) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE(a) (0x00002004 + (a)*0x00000400) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE 1:0 +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_ACTIVE_RASTER (0x00000000) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_COMPLETE_RASTER (0x00000001) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_NON_ACTIVE_RASTER (0x00000002) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY 2:2 +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY 3:3 +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH 7:4 +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_422 (0x00000000) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444 (0x00000001) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_20_422 (0x00000002) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_422 (0x00000003) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444 (0x00000004) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_30_444 (0x00000005) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_32_422 (0x00000006) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_36_444 (0x00000007) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_48_444 (0x00000008) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE 24:24 +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_DISABLE (0x00000000) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_ENABLE (0x00000001) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_FLAG 23:12 +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN 31:26 +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN0 (0x00000000) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN1 (0x00000001) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN2 (0x00000002) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN3 (0x00000003) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN4 (0x00000004) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN5 (0x00000005) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN6 (0x00000006) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN7 (0x00000007) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN8 (0x00000008) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN9 (0x00000009) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN10 (0x0000000A) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN11 (0x0000000B) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN12 (0x0000000C) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN13 (0x0000000D) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN14 (0x0000000E) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN15 (0x0000000F) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN16 (0x00000010) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN17 (0x00000011) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN18 (0x00000012) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN19 (0x00000013) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN20 (0x00000014) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN21 (0x00000015) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN22 (0x00000016) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN23 (0x00000017) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN24 (0x00000018) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN25 (0x00000019) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN26 (0x0000001A) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN27 (0x0000001B) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN28 (0x0000001C) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN29 (0x0000001D) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN30 (0x0000001E) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_WIN31 (0x0000001F) +#define NVC57D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_EXT_PACKET_WIN_NONE (0x0000003F) +#define NVC57D_HEAD_SET_PIXEL_CLOCK_FREQUENCY(a) (0x0000200C + (a)*0x00000400) +#define NVC57D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HERTZ 30:0 +#define NVC57D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001 31:31 +#define NVC57D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_FALSE (0x00000000) +#define NVC57D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_TRUE (0x00000001) +#define NVC57D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION(a) (0x0000201C + (a)*0x00000400) +#define NVC57D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER 0:0 +#define NVC57D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_FALSE (0x00000000) +#define NVC57D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_TRUE (0x00000001) +#define NVC57D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING 4:4 +#define NVC57D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_DISABLE (0x00000000) +#define NVC57D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_ENABLE (0x00000001) +#define NVC57D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE 9:8 +#define NVC57D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_VBLANK (0x00000000) +#define NVC57D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_HBLANK (0x00000001) +#define NVC57D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(a) (0x00002028 + (a)*0x00000400) +#define NVC57D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_HERTZ 30:0 +#define NVC57D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001 31:31 +#define NVC57D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_FALSE (0x00000000) +#define NVC57D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_TRUE (0x00000001) +#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS(a) (0x00002030 + (a)*0x00000400) +#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR 2:0 +#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_NONE (0x00000000) +#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W32_H32 (0x00000001) +#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W64_H64 (0x00000002) +#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W128_H128 (0x00000003) +#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_CURSOR_USAGE_W256_H256 (0x00000004) +#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_OLUT_ALLOWED 4:4 +#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_OLUT_ALLOWED_FALSE (0x00000000) +#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_OLUT_ALLOWED_TRUE (0x00000001) +#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_SCALER_TAPS 14:12 +#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_SCALER_TAPS_TAPS_2 (0x00000001) +#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_OUTPUT_SCALER_TAPS_TAPS_5 (0x00000004) +#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_UPSCALING_ALLOWED 8:8 +#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_UPSCALING_ALLOWED_FALSE (0x00000000) +#define NVC57D_HEAD_SET_HEAD_USAGE_BOUNDS_UPSCALING_ALLOWED_TRUE (0x00000001) +#define NVC57D_HEAD_SET_RASTER_SIZE(a) (0x00002064 + (a)*0x00000400) +#define NVC57D_HEAD_SET_RASTER_SIZE_WIDTH 14:0 +#define NVC57D_HEAD_SET_RASTER_SIZE_HEIGHT 30:16 +#define NVC57D_HEAD_SET_RASTER_SYNC_END(a) (0x00002068 + (a)*0x00000400) +#define NVC57D_HEAD_SET_RASTER_SYNC_END_X 14:0 +#define NVC57D_HEAD_SET_RASTER_SYNC_END_Y 30:16 +#define NVC57D_HEAD_SET_RASTER_BLANK_END(a) (0x0000206C + (a)*0x00000400) +#define NVC57D_HEAD_SET_RASTER_BLANK_END_X 14:0 +#define NVC57D_HEAD_SET_RASTER_BLANK_END_Y 30:16 +#define NVC57D_HEAD_SET_RASTER_BLANK_START(a) (0x00002070 + (a)*0x00000400) +#define NVC57D_HEAD_SET_RASTER_BLANK_START_X 14:0 +#define NVC57D_HEAD_SET_RASTER_BLANK_START_Y 30:16 +#define NVC57D_HEAD_SET_OLUT_CONTROL(a) (0x00002280 + (a)*0x00000400) +#define NVC57D_HEAD_SET_OLUT_CONTROL_INTERPOLATE 0:0 +#define NVC57D_HEAD_SET_OLUT_CONTROL_INTERPOLATE_DISABLE (0x00000000) +#define NVC57D_HEAD_SET_OLUT_CONTROL_INTERPOLATE_ENABLE (0x00000001) +#define NVC57D_HEAD_SET_OLUT_CONTROL_MIRROR 1:1 +#define NVC57D_HEAD_SET_OLUT_CONTROL_MIRROR_DISABLE (0x00000000) +#define NVC57D_HEAD_SET_OLUT_CONTROL_MIRROR_ENABLE (0x00000001) +#define NVC57D_HEAD_SET_OLUT_CONTROL_MODE 3:2 +#define NVC57D_HEAD_SET_OLUT_CONTROL_MODE_SEGMENTED (0x00000000) +#define NVC57D_HEAD_SET_OLUT_CONTROL_MODE_DIRECT8 (0x00000001) +#define NVC57D_HEAD_SET_OLUT_CONTROL_MODE_DIRECT10 (0x00000002) +#define NVC57D_HEAD_SET_OLUT_CONTROL_SIZE 18:8 +#define NVC57D_HEAD_SET_OLUT_FP_NORM_SCALE(a) (0x00002284 + (a)*0x00000400) +#define NVC57D_HEAD_SET_OLUT_FP_NORM_SCALE_VALUE 31:0 +#define NVC57D_HEAD_SET_CONTEXT_DMA_OLUT(a) (0x00002288 + (a)*0x00000400) +#define NVC57D_HEAD_SET_CONTEXT_DMA_OLUT_HANDLE 31:0 +#define NVC57D_HEAD_SET_OFFSET_OLUT(a) (0x0000228C + (a)*0x00000400) +#define NVC57D_HEAD_SET_OFFSET_OLUT_ORIGIN 31:0 +#endif // _clC57d_h From 38a323b0076c4c0fa330c92751967ef51936588d Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sun, 21 Jun 2020 17:21:16 +1000 Subject: [PATCH 112/145] drm/nouveau/kms/nv50-: use NVIDIA's headers for core ntfy_init() Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/core507d.c | 3 ++- drivers/gpu/drm/nouveau/dispnv50/corec37d.c | 9 +++++---- 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/core507d.c b/drivers/gpu/drm/nouveau/dispnv50/core507d.c index a0f470be3140..f28b91cae2db 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/core507d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/core507d.c @@ -63,7 +63,8 @@ core507d_ntfy_wait_done(struct nouveau_bo *bo, u32 offset, void core507d_ntfy_init(struct nouveau_bo *bo, u32 offset) { - nouveau_bo_wr32(bo, offset / 4, 0x00000000); + NVBO_WR32(bo, offset, NV_DISP_CORE_NOTIFIER_1, COMPLETION_0, + NVDEF(NV_DISP_CORE_NOTIFIER_1, COMPLETION_0, DONE, FALSE)); } int diff --git a/drivers/gpu/drm/nouveau/dispnv50/corec37d.c b/drivers/gpu/drm/nouveau/dispnv50/corec37d.c index 008327ee4b58..b7a929d8109f 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/corec37d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/corec37d.c @@ -85,10 +85,11 @@ corec37d_ntfy_wait_done(struct nouveau_bo *bo, u32 offset, void corec37d_ntfy_init(struct nouveau_bo *bo, u32 offset) { - nouveau_bo_wr32(bo, offset / 4 + 0, 0x00000000); - nouveau_bo_wr32(bo, offset / 4 + 1, 0x00000000); - nouveau_bo_wr32(bo, offset / 4 + 2, 0x00000000); - nouveau_bo_wr32(bo, offset / 4 + 3, 0x00000000); + NVBO_WR32(bo, offset, NV_DISP_NOTIFIER, _0, + NVDEF(NV_DISP_NOTIFIER, _0, STATUS, NOT_BEGUN)); + NVBO_WR32(bo, offset, NV_DISP_NOTIFIER, _1, 0); + NVBO_WR32(bo, offset, NV_DISP_NOTIFIER, _2, 0); + NVBO_WR32(bo, offset, NV_DISP_NOTIFIER, _3, 0); } int corec37d_caps_init(struct nouveau_drm *drm, struct nv50_disp *disp) From d8b24526ef68059b91b4c2ea6c4ff8a0e39eb926 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sat, 20 Jun 2020 17:55:22 +1000 Subject: [PATCH 113/145] drm/nouveau/kms/nv50-: use NVIDIA's headers for core caps_init() Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/core507d.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/core507d.c b/drivers/gpu/drm/nouveau/dispnv50/core507d.c index f28b91cae2db..626f83904434 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/core507d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/core507d.c @@ -76,7 +76,7 @@ core507d_caps_init(struct nouveau_drm *drm, struct nv50_disp *disp) if ((ret = PUSH_WAIT(push, 2))) return ret; - PUSH_NVSQ(push, NV507D, 0x008c, 0x00000000); + PUSH_MTHD(push, NV507D, GET_CAPABILITIES, 0x00000000); return PUSH_KICK(push); } From 4daef27cb802d3425dee3ef712cb4c0f013e2b71 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sun, 21 Jun 2020 17:24:27 +1000 Subject: [PATCH 114/145] drm/nouveau/kms/nv50-: use NVIDIA's headers for core ntfy_wait_done() Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/core507d.c | 2 +- drivers/gpu/drm/nouveau/dispnv50/corec37d.c | 4 +--- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/core507d.c b/drivers/gpu/drm/nouveau/dispnv50/core507d.c index 626f83904434..aa742bc71b84 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/core507d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/core507d.c @@ -53,7 +53,7 @@ core507d_ntfy_wait_done(struct nouveau_bo *bo, u32 offset, struct nvif_device *device) { s64 time = nvif_msec(device, 2000ULL, - if (nouveau_bo_rd32(bo, offset / 4)) + if (NVBO_TD32(bo, offset, NV_DISP_CORE_NOTIFIER_1, COMPLETION_0, DONE, ==, TRUE)) break; usleep_range(1, 2); ); diff --git a/drivers/gpu/drm/nouveau/dispnv50/corec37d.c b/drivers/gpu/drm/nouveau/dispnv50/corec37d.c index b7a929d8109f..37d125987b1a 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/corec37d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/corec37d.c @@ -72,10 +72,8 @@ int corec37d_ntfy_wait_done(struct nouveau_bo *bo, u32 offset, struct nvif_device *device) { - u32 data; s64 time = nvif_msec(device, 2000ULL, - data = nouveau_bo_rd32(bo, offset / 4 + 0); - if ((data & 0xc0000000) == 0x80000000) + if (NVBO_TD32(bo, offset, NV_DISP_NOTIFIER, _0, STATUS, ==, FINISHED)) break; usleep_range(1, 2); ); From 2806280a0cd7b9b2fb97fa5fbd5ae69a8f4d46a1 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sat, 20 Jun 2020 17:39:00 +1000 Subject: [PATCH 115/145] drm/nouveau/kms/nv50-: use NVIDIA's headers for core update() Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/core507d.c | 17 +++++++++++----- drivers/gpu/drm/nouveau/dispnv50/corec37d.c | 22 ++++++++++++++------- 2 files changed, 27 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/core507d.c b/drivers/gpu/drm/nouveau/dispnv50/core507d.c index aa742bc71b84..ad1f09a143aa 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/core507d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/core507d.c @@ -39,12 +39,19 @@ core507d_update(struct nv50_core *core, u32 *interlock, bool ntfy) if ((ret = PUSH_WAIT(push, 5))) return ret; - if (ntfy) - PUSH_NVSQ(push, NV507D, 0x0084, 0x80000000 | NV50_DISP_CORE_NTFY); + if (ntfy) { + PUSH_MTHD(push, NV507D, SET_NOTIFIER_CONTROL, + NVDEF(NV507D, SET_NOTIFIER_CONTROL, MODE, WRITE) | + NVVAL(NV507D, SET_NOTIFIER_CONTROL, OFFSET, NV50_DISP_CORE_NTFY >> 2) | + NVDEF(NV507D, SET_NOTIFIER_CONTROL, NOTIFY, ENABLE)); + } + + PUSH_MTHD(push, NV507D, UPDATE, interlock[NV50_DISP_INTERLOCK_BASE] | + interlock[NV50_DISP_INTERLOCK_OVLY] | + NVDEF(NV507D, UPDATE, NOT_DRIVER_FRIENDLY, FALSE) | + NVDEF(NV507D, UPDATE, NOT_DRIVER_UNFRIENDLY, FALSE) | + NVDEF(NV507D, UPDATE, INHIBIT_INTERRUPTS, FALSE)); - PUSH_NVSQ(push, NV507D, 0x0080, interlock[NV50_DISP_INTERLOCK_BASE] | - interlock[NV50_DISP_INTERLOCK_OVLY], - 0x0084, 0x00000000); return PUSH_KICK(push); } diff --git a/drivers/gpu/drm/nouveau/dispnv50/corec37d.c b/drivers/gpu/drm/nouveau/dispnv50/corec37d.c index 37d125987b1a..796e847ca874 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/corec37d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/corec37d.c @@ -55,15 +55,23 @@ corec37d_update(struct nv50_core *core, u32 *interlock, bool ntfy) if ((ret = PUSH_WAIT(push, 9))) return ret; - if (ntfy) - PUSH_NVSQ(push, NVC37D, 0x020c, 0x00001000 | NV50_DISP_CORE_NTFY); + if (ntfy) { + PUSH_MTHD(push, NVC37D, SET_NOTIFIER_CONTROL, + NVDEF(NVC37D, SET_NOTIFIER_CONTROL, MODE, WRITE) | + NVVAL(NVC37D, SET_NOTIFIER_CONTROL, OFFSET, NV50_DISP_CORE_NTFY >> 4) | + NVDEF(NVC37D, SET_NOTIFIER_CONTROL, NOTIFY, ENABLE)); + } - PUSH_NVSQ(push, NVC37D, 0x0218, interlock[NV50_DISP_INTERLOCK_CURS], - 0x021c, interlock[NV50_DISP_INTERLOCK_WNDW]); - PUSH_NVSQ(push, NVC37D, 0x0200, 0x00000001); + PUSH_MTHD(push, NVC37D, SET_INTERLOCK_FLAGS, interlock[NV50_DISP_INTERLOCK_CURS], + SET_WINDOW_INTERLOCK_FLAGS, interlock[NV50_DISP_INTERLOCK_WNDW]); + PUSH_MTHD(push, NVC37D, UPDATE, 0x00000001 | + NVDEF(NVC37D, UPDATE, SPECIAL_HANDLING, NONE) | + NVDEF(NVC37D, UPDATE, INHIBIT_INTERRUPTS, FALSE)); - if (ntfy) - PUSH_NVSQ(push, NVC37D, 0x020c, 0x00000000); + if (ntfy) { + PUSH_MTHD(push, NVC37D, SET_NOTIFIER_CONTROL, + NVDEF(NVC37D, SET_NOTIFIER_CONTROL, NOTIFY, DISABLE)); + } return PUSH_KICK(push); } From 8e650ecbcd5d769afa03618cb4c7f4a21498ecd5 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sat, 20 Jun 2020 17:59:39 +1000 Subject: [PATCH 116/145] drm/nouveau/kms/nv50-: use NVIDIA's headers for core wndw_owner() Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/corec37d.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/corec37d.c b/drivers/gpu/drm/nouveau/dispnv50/corec37d.c index 796e847ca874..9035d3ab062c 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/corec37d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/corec37d.c @@ -40,8 +40,10 @@ corec37d_wndw_owner(struct nv50_core *core) if ((ret = PUSH_WAIT(push, windows * 2))) return ret; - for (i = 0; i < windows; i++) - PUSH_NVSQ(push, NVC37D, 0x1000 + (i * 0x080), i >> 1); + for (i = 0; i < windows; i++) { + PUSH_MTHD(push, NVC37D, WINDOW_SET_CONTROL(i), + NVDEF(NVC37D, WINDOW_SET_CONTROL, OWNER, HEAD(i >> 1))); + } return 0; } From 344c2e5a47960a95ef0504d8f0852005d1e199f0 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sat, 20 Jun 2020 18:09:59 +1000 Subject: [PATCH 117/145] drm/nouveau/kms/nv50-: use NVIDIA's headers for core or_ctrl() Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/dac507d.c | 10 +- drivers/gpu/drm/nouveau/dispnv50/dac907d.c | 4 +- drivers/gpu/drm/nouveau/dispnv50/disp.c | 79 ++-- drivers/gpu/drm/nouveau/dispnv50/pior507d.c | 11 +- drivers/gpu/drm/nouveau/dispnv50/sor507d.c | 11 +- drivers/gpu/drm/nouveau/dispnv50/sor907d.c | 4 +- drivers/gpu/drm/nouveau/dispnv50/sorc37d.c | 6 +- .../drm/nouveau/include/nvhw/class/cl837d.h | 101 +++++ .../drm/nouveau/include/nvhw/class/cl887d.h | 68 +++ .../drm/nouveau/include/nvhw/class/cl907d.h | 429 ++++++++++++++++++ .../drm/nouveau/include/nvhw/class/cl917d.h | 104 +++++ 11 files changed, 785 insertions(+), 42 deletions(-) create mode 100644 drivers/gpu/drm/nouveau/include/nvhw/class/cl837d.h create mode 100644 drivers/gpu/drm/nouveau/include/nvhw/class/cl887d.h create mode 100644 drivers/gpu/drm/nouveau/include/nvhw/class/cl907d.h create mode 100644 drivers/gpu/drm/nouveau/include/nvhw/class/cl917d.h diff --git a/drivers/gpu/drm/nouveau/dispnv50/dac507d.c b/drivers/gpu/drm/nouveau/dispnv50/dac507d.c index 4f424c65ebf9..09de78d96679 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/dac507d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/dac507d.c @@ -23,6 +23,8 @@ #include +#include + static int dac507d_ctrl(struct nv50_core *core, int or, u32 ctrl, struct nv50_head_atom *asyh) @@ -32,15 +34,15 @@ dac507d_ctrl(struct nv50_core *core, int or, u32 ctrl, int ret; if (asyh) { - sync |= asyh->or.nvsync << 1; - sync |= asyh->or.nhsync; + sync |= NVVAL(NV507D, DAC_SET_POLARITY, HSYNC, asyh->or.nhsync); + sync |= NVVAL(NV507D, DAC_SET_POLARITY, VSYNC, asyh->or.nvsync); } if ((ret = PUSH_WAIT(push, 3))) return ret; - PUSH_NVSQ(push, NV507D, 0x0400 + (or * 0x080), ctrl, - 0x0404 + (or * 0x080), sync); + PUSH_MTHD(push, NV507D, DAC_SET_CONTROL(or), ctrl, + DAC_SET_POLARITY(or), sync); return 0; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/dac907d.c b/drivers/gpu/drm/nouveau/dispnv50/dac907d.c index f32e470b9358..95efa625b691 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/dac907d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/dac907d.c @@ -23,6 +23,8 @@ #include +#include + static int dac907d_ctrl(struct nv50_core *core, int or, u32 ctrl, struct nv50_head_atom *asyh) @@ -33,7 +35,7 @@ dac907d_ctrl(struct nv50_core *core, int or, u32 ctrl, if ((ret = PUSH_WAIT(push, 2))) return ret; - PUSH_NVSQ(push, NV907D, 0x0180 + (or * 0x020), ctrl); + PUSH_MTHD(push, NV907D, DAC_SET_CONTROL(or), ctrl); return 0; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c b/drivers/gpu/drm/nouveau/dispnv50/disp.c index 0b3751c0d2a4..64bac6718457 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/disp.c +++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c @@ -51,6 +51,11 @@ #include #include +#include +#include +#include +#include +#include #include "nouveau_drv.h" #include "nouveau_dma.h" @@ -414,8 +419,9 @@ nv50_dac_disable(struct drm_encoder *encoder) { struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); struct nv50_core *core = nv50_disp(encoder->dev)->core; + const u32 ctrl = NVDEF(NV507D, DAC_SET_CONTROL, OWNER, NONE); if (nv_encoder->crtc) - core->func->dac->ctrl(core, nv_encoder->or, 0x00000000, NULL); + core->func->dac->ctrl(core, nv_encoder->or, ctrl, NULL); nv_encoder->crtc = NULL; nv50_outp_release(nv_encoder); } @@ -427,10 +433,23 @@ nv50_dac_enable(struct drm_encoder *encoder) struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state); struct nv50_core *core = nv50_disp(encoder->dev)->core; + u32 ctrl = 0; + + switch (nv_crtc->index) { + case 0: ctrl |= NVDEF(NV507D, DAC_SET_CONTROL, OWNER, HEAD0); break; + case 1: ctrl |= NVDEF(NV507D, DAC_SET_CONTROL, OWNER, HEAD1); break; + case 2: ctrl |= NVDEF(NV907D, DAC_SET_CONTROL, OWNER_MASK, HEAD2); break; + case 3: ctrl |= NVDEF(NV907D, DAC_SET_CONTROL, OWNER_MASK, HEAD3); break; + default: + WARN_ON(1); + break; + } + + ctrl |= NVDEF(NV507D, DAC_SET_CONTROL, PROTOCOL, RGB_CRT); nv50_outp_acquire(nv_encoder, false); - core->func->dac->ctrl(core, nv_encoder->or, 1 << nv_crtc->index, asyh); + core->func->dac->ctrl(core, nv_encoder->or, ctrl, asyh); asyh->or.depth = 0; nv_encoder->crtc = encoder->crtc; @@ -980,10 +999,10 @@ static u8 nv50_dp_bpc_to_depth(unsigned int bpc) { switch (bpc) { - case 6: return 0x2; - case 8: return 0x5; + case 6: return NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444; + case 8: return NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444; case 10: - default: return 0x6; + default: return NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444; } } @@ -1022,9 +1041,9 @@ nv50_msto_enable(struct drm_encoder *encoder) nv50_outp_acquire(mstm->outp, false /*XXX: MST audio.*/); if (mstm->outp->link & 1) - proto = 0x8; + proto = NV917D_SOR_SET_CONTROL_PROTOCOL_DP_A; else - proto = 0x9; + proto = NV917D_SOR_SET_CONTROL_PROTOCOL_DP_B; mstm->outp->update(mstm->outp, head->base.index, armh, proto, nv50_dp_bpc_to_depth(armh->or.bpc)); @@ -1553,10 +1572,10 @@ nv50_sor_update(struct nouveau_encoder *nv_encoder, u8 head, if (!asyh) { nv_encoder->ctrl &= ~BIT(head); - if (!(nv_encoder->ctrl & 0x0000000f)) + if (NVDEF_TEST(nv_encoder->ctrl, NV507D, SOR_SET_CONTROL, OWNER, ==, NONE)) nv_encoder->ctrl = 0; } else { - nv_encoder->ctrl |= proto << 8; + nv_encoder->ctrl |= NVVAL(NV507D, SOR_SET_CONTROL, PROTOCOL, proto); nv_encoder->ctrl |= BIT(head); asyh->or.depth = depth; } @@ -1614,8 +1633,8 @@ nv50_sor_enable(struct drm_encoder *encoder) struct nouveau_connector *nv_connector; struct nvbios *bios = &drm->vbios; bool hda = false; - u8 proto = 0xf; - u8 depth = 0x0; + u8 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_CUSTOM; + u8 depth = NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT; nv_connector = nouveau_encoder_connector_get(nv_encoder); nv_encoder->crtc = encoder->crtc; @@ -1629,7 +1648,7 @@ nv50_sor_enable(struct drm_encoder *encoder) switch (nv_encoder->dcb->type) { case DCB_OUTPUT_TMDS: if (nv_encoder->link & 1) { - proto = 0x1; + proto = NV507D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A; /* Only enable dual-link if: * - Need to (i.e. rate > 165MHz) * - DCB says we can @@ -1639,15 +1658,15 @@ nv50_sor_enable(struct drm_encoder *encoder) if (mode->clock >= 165000 && nv_encoder->dcb->duallink_possible && !drm_detect_hdmi_monitor(nv_connector->edid)) - proto |= 0x4; + proto = NV507D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS; } else { - proto = 0x2; + proto = NV507D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B; } nv50_hdmi_enable(&nv_encoder->base.base, mode); break; case DCB_OUTPUT_LVDS: - proto = 0x0; + proto = NV507D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM; if (bios->fp_no_ddc) { if (bios->fp.dual_link) @@ -1681,9 +1700,9 @@ nv50_sor_enable(struct drm_encoder *encoder) depth = nv50_dp_bpc_to_depth(asyh->or.bpc); if (nv_encoder->link & 1) - proto = 0x8; + proto = NV887D_SOR_SET_CONTROL_PROTOCOL_DP_A; else - proto = 0x9; + proto = NV887D_SOR_SET_CONTROL_PROTOCOL_DP_B; nv50_audio_enable(encoder, mode); break; @@ -1818,8 +1837,9 @@ nv50_pior_disable(struct drm_encoder *encoder) { struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); struct nv50_core *core = nv50_disp(encoder->dev)->core; + const u32 ctrl = NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, NONE); if (nv_encoder->crtc) - core->func->pior->ctrl(core, nv_encoder->or, 0x00000000, NULL); + core->func->pior->ctrl(core, nv_encoder->or, ctrl, NULL); nv_encoder->crtc = NULL; nv50_outp_release(nv_encoder); } @@ -1831,29 +1851,36 @@ nv50_pior_enable(struct drm_encoder *encoder) struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state); struct nv50_core *core = nv50_disp(encoder->dev)->core; - u8 owner = 1 << nv_crtc->index; - u8 proto; + u32 ctrl = 0; + + switch (nv_crtc->index) { + case 0: ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, HEAD0); break; + case 1: ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, OWNER, HEAD1); break; + default: + WARN_ON(1); + break; + } nv50_outp_acquire(nv_encoder, false); switch (asyh->or.bpc) { - case 10: asyh->or.depth = 0x6; break; - case 8: asyh->or.depth = 0x5; break; - case 6: asyh->or.depth = 0x2; break; - default: asyh->or.depth = 0x0; break; + case 10: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444; break; + case 8: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444; break; + case 6: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444; break; + default: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT; break; } switch (nv_encoder->dcb->type) { case DCB_OUTPUT_TMDS: case DCB_OUTPUT_DP: - proto = 0x0; + ctrl |= NVDEF(NV507D, PIOR_SET_CONTROL, PROTOCOL, EXT_TMDS_ENC); break; default: BUG(); break; } - core->func->pior->ctrl(core, nv_encoder->or, (proto << 8) | owner, asyh); + core->func->pior->ctrl(core, nv_encoder->or, ctrl, asyh); nv_encoder->crtc = encoder->crtc; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/pior507d.c b/drivers/gpu/drm/nouveau/dispnv50/pior507d.c index 6af30c1617e5..17d230256bdd 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/pior507d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/pior507d.c @@ -23,6 +23,9 @@ #include +#include +#include + static int pior507d_ctrl(struct nv50_core *core, int or, u32 ctrl, struct nv50_head_atom *asyh) @@ -31,15 +34,15 @@ pior507d_ctrl(struct nv50_core *core, int or, u32 ctrl, int ret; if (asyh) { - ctrl |= asyh->or.depth << 16; - ctrl |= asyh->or.nvsync << 13; - ctrl |= asyh->or.nhsync << 12; + ctrl |= NVVAL(NV507D, PIOR_SET_CONTROL, HSYNC_POLARITY, asyh->or.nhsync); + ctrl |= NVVAL(NV507D, PIOR_SET_CONTROL, VSYNC_POLARITY, asyh->or.nvsync); + ctrl |= NVVAL(NV837D, PIOR_SET_CONTROL, PIXEL_DEPTH, asyh->or.depth); } if ((ret = PUSH_WAIT(push, 2))) return ret; - PUSH_NVSQ(push, NV507D, 0x0700 + (or * 0x040), ctrl); + PUSH_MTHD(push, NV507D, PIOR_SET_CONTROL(or), ctrl); return 0; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/sor507d.c b/drivers/gpu/drm/nouveau/dispnv50/sor507d.c index ead66163ff4f..ca73d7710885 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/sor507d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/sor507d.c @@ -23,6 +23,9 @@ #include +#include +#include + static int sor507d_ctrl(struct nv50_core *core, int or, u32 ctrl, struct nv50_head_atom *asyh) @@ -31,15 +34,15 @@ sor507d_ctrl(struct nv50_core *core, int or, u32 ctrl, int ret; if (asyh) { - ctrl |= asyh->or.depth << 16; - ctrl |= asyh->or.nvsync << 13; - ctrl |= asyh->or.nhsync << 12; + ctrl |= NVVAL(NV507D, SOR_SET_CONTROL, HSYNC_POLARITY, asyh->or.nhsync); + ctrl |= NVVAL(NV507D, SOR_SET_CONTROL, VSYNC_POLARITY, asyh->or.nvsync); + ctrl |= NVVAL(NV837D, SOR_SET_CONTROL, PIXEL_DEPTH, asyh->or.depth); } if ((ret = PUSH_WAIT(push, 2))) return ret; - PUSH_NVSQ(push, NV507D, 0x0600 + (or * 0x40), ctrl); + PUSH_MTHD(push, NV507D, SOR_SET_CONTROL(or), ctrl); return 0; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/sor907d.c b/drivers/gpu/drm/nouveau/dispnv50/sor907d.c index ea5da300cc11..db09cc5af5f6 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/sor907d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/sor907d.c @@ -24,6 +24,8 @@ #include #include +#include + #include static int @@ -36,7 +38,7 @@ sor907d_ctrl(struct nv50_core *core, int or, u32 ctrl, if ((ret = PUSH_WAIT(push, 2))) return ret; - PUSH_NVSQ(push, NV907D, 0x0200 + (or * 0x20), ctrl); + PUSH_MTHD(push, NV907D, SOR_SET_CONTROL(or), ctrl); return 0; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/sorc37d.c b/drivers/gpu/drm/nouveau/dispnv50/sorc37d.c index 734944864198..9eaef34816da 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/sorc37d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/sorc37d.c @@ -21,7 +21,9 @@ */ #include "core.h" -#include +#include + +#include static int sorc37d_ctrl(struct nv50_core *core, int or, u32 ctrl, @@ -33,7 +35,7 @@ sorc37d_ctrl(struct nv50_core *core, int or, u32 ctrl, if ((ret = PUSH_WAIT(push, 2))) return ret; - PUSH_NVSQ(push, NVC37D, 0x0300 + (or * 0x20), ctrl); + PUSH_MTHD(push, NVC37D, SOR_SET_CONTROL(or), ctrl); return 0; } diff --git a/drivers/gpu/drm/nouveau/include/nvhw/class/cl837d.h b/drivers/gpu/drm/nouveau/include/nvhw/class/cl837d.h new file mode 100644 index 000000000000..0db9d4e730ec --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvhw/class/cl837d.h @@ -0,0 +1,101 @@ +/* + * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl837d_h_ +#define _cl837d_h_ + +// class methods +#define NV837D_SOR_SET_CONTROL(a) (0x00000600 + (a)*0x00000040) +#define NV837D_SOR_SET_CONTROL_OWNER 3:0 +#define NV837D_SOR_SET_CONTROL_OWNER_NONE (0x00000000) +#define NV837D_SOR_SET_CONTROL_OWNER_HEAD0 (0x00000001) +#define NV837D_SOR_SET_CONTROL_OWNER_HEAD1 (0x00000002) +#define NV837D_SOR_SET_CONTROL_SUB_OWNER 5:4 +#define NV837D_SOR_SET_CONTROL_SUB_OWNER_NONE (0x00000000) +#define NV837D_SOR_SET_CONTROL_SUB_OWNER_SUBHEAD0 (0x00000001) +#define NV837D_SOR_SET_CONTROL_SUB_OWNER_SUBHEAD1 (0x00000002) +#define NV837D_SOR_SET_CONTROL_SUB_OWNER_BOTH (0x00000003) +#define NV837D_SOR_SET_CONTROL_PROTOCOL 11:8 +#define NV837D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM (0x00000000) +#define NV837D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A (0x00000001) +#define NV837D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B (0x00000002) +#define NV837D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_AB (0x00000003) +#define NV837D_SOR_SET_CONTROL_PROTOCOL_DUAL_SINGLE_TMDS (0x00000004) +#define NV837D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS (0x00000005) +#define NV837D_SOR_SET_CONTROL_PROTOCOL_DDI_OUT (0x00000007) +#define NV837D_SOR_SET_CONTROL_PROTOCOL_CUSTOM (0x0000000F) +#define NV837D_SOR_SET_CONTROL_HSYNC_POLARITY 12:12 +#define NV837D_SOR_SET_CONTROL_HSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV837D_SOR_SET_CONTROL_HSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV837D_SOR_SET_CONTROL_VSYNC_POLARITY 13:13 +#define NV837D_SOR_SET_CONTROL_VSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV837D_SOR_SET_CONTROL_VSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV837D_SOR_SET_CONTROL_DE_SYNC_POLARITY 14:14 +#define NV837D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV837D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH 19:16 +#define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT (0x00000000) +#define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_16_422 (0x00000001) +#define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444 (0x00000002) +#define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_20_422 (0x00000003) +#define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_422 (0x00000004) +#define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444 (0x00000005) +#define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444 (0x00000006) +#define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_32_422 (0x00000007) +#define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_36_444 (0x00000008) +#define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_48_444 (0x00000009) + +#define NV837D_PIOR_SET_CONTROL(a) (0x00000700 + (a)*0x00000040) +#define NV837D_PIOR_SET_CONTROL_OWNER 3:0 +#define NV837D_PIOR_SET_CONTROL_OWNER_NONE (0x00000000) +#define NV837D_PIOR_SET_CONTROL_OWNER_HEAD0 (0x00000001) +#define NV837D_PIOR_SET_CONTROL_OWNER_HEAD1 (0x00000002) +#define NV837D_PIOR_SET_CONTROL_SUB_OWNER 5:4 +#define NV837D_PIOR_SET_CONTROL_SUB_OWNER_NONE (0x00000000) +#define NV837D_PIOR_SET_CONTROL_SUB_OWNER_SUBHEAD0 (0x00000001) +#define NV837D_PIOR_SET_CONTROL_SUB_OWNER_SUBHEAD1 (0x00000002) +#define NV837D_PIOR_SET_CONTROL_SUB_OWNER_BOTH (0x00000003) +#define NV837D_PIOR_SET_CONTROL_PROTOCOL 11:8 +#define NV837D_PIOR_SET_CONTROL_PROTOCOL_EXT_TMDS_ENC (0x00000000) +#define NV837D_PIOR_SET_CONTROL_PROTOCOL_EXT_TV_ENC (0x00000001) +#define NV837D_PIOR_SET_CONTROL_HSYNC_POLARITY 12:12 +#define NV837D_PIOR_SET_CONTROL_HSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV837D_PIOR_SET_CONTROL_HSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV837D_PIOR_SET_CONTROL_VSYNC_POLARITY 13:13 +#define NV837D_PIOR_SET_CONTROL_VSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV837D_PIOR_SET_CONTROL_VSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV837D_PIOR_SET_CONTROL_DE_SYNC_POLARITY 14:14 +#define NV837D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV837D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH 19:16 +#define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT (0x00000000) +#define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_16_422 (0x00000001) +#define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444 (0x00000002) +#define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_20_422 (0x00000003) +#define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_422 (0x00000004) +#define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444 (0x00000005) +#define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444 (0x00000006) +#define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_32_422 (0x00000007) +#define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_36_444 (0x00000008) +#define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_48_444 (0x00000009) +#endif // _cl837d_h diff --git a/drivers/gpu/drm/nouveau/include/nvhw/class/cl887d.h b/drivers/gpu/drm/nouveau/include/nvhw/class/cl887d.h new file mode 100644 index 000000000000..c93efc642a92 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvhw/class/cl887d.h @@ -0,0 +1,68 @@ +/* + * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl887d_h_ +#define _cl887d_h_ + +#define NV887D_SOR_SET_CONTROL(a) (0x00000600 + (a)*0x00000040) +#define NV887D_SOR_SET_CONTROL_OWNER 3:0 +#define NV887D_SOR_SET_CONTROL_OWNER_NONE (0x00000000) +#define NV887D_SOR_SET_CONTROL_OWNER_HEAD0 (0x00000001) +#define NV887D_SOR_SET_CONTROL_OWNER_HEAD1 (0x00000002) +#define NV887D_SOR_SET_CONTROL_SUB_OWNER 5:4 +#define NV887D_SOR_SET_CONTROL_SUB_OWNER_NONE (0x00000000) +#define NV887D_SOR_SET_CONTROL_SUB_OWNER_SUBHEAD0 (0x00000001) +#define NV887D_SOR_SET_CONTROL_SUB_OWNER_SUBHEAD1 (0x00000002) +#define NV887D_SOR_SET_CONTROL_SUB_OWNER_BOTH (0x00000003) +#define NV887D_SOR_SET_CONTROL_PROTOCOL 11:8 +#define NV887D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM (0x00000000) +#define NV887D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A (0x00000001) +#define NV887D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B (0x00000002) +#define NV887D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_AB (0x00000003) +#define NV887D_SOR_SET_CONTROL_PROTOCOL_DUAL_SINGLE_TMDS (0x00000004) +#define NV887D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS (0x00000005) +#define NV887D_SOR_SET_CONTROL_PROTOCOL_DDI_OUT (0x00000007) +#define NV887D_SOR_SET_CONTROL_PROTOCOL_DP_A (0x00000008) +#define NV887D_SOR_SET_CONTROL_PROTOCOL_DP_B (0x00000009) +#define NV887D_SOR_SET_CONTROL_PROTOCOL_CUSTOM (0x0000000F) +#define NV887D_SOR_SET_CONTROL_HSYNC_POLARITY 12:12 +#define NV887D_SOR_SET_CONTROL_HSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV887D_SOR_SET_CONTROL_HSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV887D_SOR_SET_CONTROL_VSYNC_POLARITY 13:13 +#define NV887D_SOR_SET_CONTROL_VSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV887D_SOR_SET_CONTROL_VSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV887D_SOR_SET_CONTROL_DE_SYNC_POLARITY 14:14 +#define NV887D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV887D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH 19:16 +#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT (0x00000000) +#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_16_422 (0x00000001) +#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444 (0x00000002) +#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_20_422 (0x00000003) +#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_422 (0x00000004) +#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444 (0x00000005) +#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444 (0x00000006) +#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_32_422 (0x00000007) +#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_36_444 (0x00000008) +#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_48_444 (0x00000009) +#endif // _cl887d_h diff --git a/drivers/gpu/drm/nouveau/include/nvhw/class/cl907d.h b/drivers/gpu/drm/nouveau/include/nvhw/class/cl907d.h new file mode 100644 index 000000000000..34bc3eafac7d --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvhw/class/cl907d.h @@ -0,0 +1,429 @@ +/* + * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl907d_h_ +#define _cl907d_h_ + +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20 0x00000014 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18 0:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24 1:1 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18 2:2 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24 3:3 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R0 7:4 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A 8:8 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B 9:9 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R1 10:10 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS 11:11 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R2 12:12 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R3 15:14 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R4 19:17 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R5 23:20 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A 24:24 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B 25:25 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE 26:26 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R6 31:27 + + +// class methods +#define NV907D_DAC_SET_CONTROL(a) (0x00000180 + (a)*0x00000020) +#define NV907D_DAC_SET_CONTROL_OWNER_MASK 3:0 +#define NV907D_DAC_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NV907D_DAC_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NV907D_DAC_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NV907D_DAC_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NV907D_DAC_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NV907D_DAC_SET_CONTROL_PROTOCOL 12:8 +#define NV907D_DAC_SET_CONTROL_PROTOCOL_RGB_CRT (0x00000000) +#define NV907D_DAC_SET_CONTROL_PROTOCOL_YUV_CRT (0x00000013) + +#define NV907D_SOR_SET_CONTROL(a) (0x00000200 + (a)*0x00000020) +#define NV907D_SOR_SET_CONTROL_OWNER_MASK 3:0 +#define NV907D_SOR_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NV907D_SOR_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NV907D_SOR_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NV907D_SOR_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NV907D_SOR_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NV907D_SOR_SET_CONTROL_PROTOCOL 11:8 +#define NV907D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM (0x00000000) +#define NV907D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A (0x00000001) +#define NV907D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B (0x00000002) +#define NV907D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS (0x00000005) +#define NV907D_SOR_SET_CONTROL_PROTOCOL_DP_A (0x00000008) +#define NV907D_SOR_SET_CONTROL_PROTOCOL_DP_B (0x00000009) +#define NV907D_SOR_SET_CONTROL_PROTOCOL_CUSTOM (0x0000000F) +#define NV907D_SOR_SET_CONTROL_DE_SYNC_POLARITY 14:14 +#define NV907D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV907D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV907D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE 21:20 +#define NV907D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_OFF (0x00000000) +#define NV907D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X2 (0x00000001) +#define NV907D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X4 (0x00000002) + +#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE(a) (0x00000404 + (a)*0x00000300) +#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE 1:0 +#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_ACTIVE_RASTER (0x00000000) +#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_COMPLETE_RASTER (0x00000001) +#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_NON_ACTIVE_RASTER (0x00000002) +#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY 3:3 +#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY 4:4 +#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH 9:6 +#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_DEFAULT (0x00000000) +#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_422 (0x00000001) +#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444 (0x00000002) +#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_20_422 (0x00000003) +#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_422 (0x00000004) +#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444 (0x00000005) +#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_30_444 (0x00000006) +#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_32_422 (0x00000007) +#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_36_444 (0x00000008) +#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_48_444 (0x00000009) +#define NV907D_HEAD_SET_CONTROL(a) (0x00000408 + (a)*0x00000300) +#define NV907D_HEAD_SET_CONTROL_STRUCTURE 0:0 +#define NV907D_HEAD_SET_CONTROL_STRUCTURE_PROGRESSIVE (0x00000000) +#define NV907D_HEAD_SET_CONTROL_STRUCTURE_INTERLACED (0x00000001) +#define NV907D_HEAD_SET_OVERSCAN_COLOR(a) (0x00000410 + (a)*0x00000300) +#define NV907D_HEAD_SET_OVERSCAN_COLOR_RED 9:0 +#define NV907D_HEAD_SET_OVERSCAN_COLOR_GRN 19:10 +#define NV907D_HEAD_SET_OVERSCAN_COLOR_BLU 29:20 +#define NV907D_HEAD_SET_RASTER_SIZE(a) (0x00000414 + (a)*0x00000300) +#define NV907D_HEAD_SET_RASTER_SIZE_WIDTH 14:0 +#define NV907D_HEAD_SET_RASTER_SIZE_HEIGHT 30:16 +#define NV907D_HEAD_SET_RASTER_SYNC_END(a) (0x00000418 + (a)*0x00000300) +#define NV907D_HEAD_SET_RASTER_SYNC_END_X 14:0 +#define NV907D_HEAD_SET_RASTER_SYNC_END_Y 30:16 +#define NV907D_HEAD_SET_RASTER_BLANK_END(a) (0x0000041C + (a)*0x00000300) +#define NV907D_HEAD_SET_RASTER_BLANK_END_X 14:0 +#define NV907D_HEAD_SET_RASTER_BLANK_END_Y 30:16 +#define NV907D_HEAD_SET_RASTER_BLANK_START(a) (0x00000420 + (a)*0x00000300) +#define NV907D_HEAD_SET_RASTER_BLANK_START_X 14:0 +#define NV907D_HEAD_SET_RASTER_BLANK_START_Y 30:16 +#define NV907D_HEAD_SET_RASTER_VERT_BLANK2(a) (0x00000424 + (a)*0x00000300) +#define NV907D_HEAD_SET_RASTER_VERT_BLANK2_YSTART 14:0 +#define NV907D_HEAD_SET_RASTER_VERT_BLANK2_YEND 30:16 +#define NV907D_HEAD_SET_DEFAULT_BASE_COLOR(a) (0x0000042C + (a)*0x00000300) +#define NV907D_HEAD_SET_DEFAULT_BASE_COLOR_RED 9:0 +#define NV907D_HEAD_SET_DEFAULT_BASE_COLOR_GREEN 19:10 +#define NV907D_HEAD_SET_DEFAULT_BASE_COLOR_BLUE 29:20 +#define NV907D_HEAD_SET_CRC_CONTROL(a) (0x00000430 + (a)*0x00000300) +#define NV907D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL 1:0 +#define NV907D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_CORE (0x00000000) +#define NV907D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_BASE (0x00000001) +#define NV907D_HEAD_SET_CRC_CONTROL_CONTROLLING_CHANNEL_OVERLAY (0x00000002) +#define NV907D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE 2:2 +#define NV907D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE_FALSE (0x00000000) +#define NV907D_HEAD_SET_CRC_CONTROL_EXPECT_BUFFER_COLLAPSE_TRUE (0x00000001) +#define NV907D_HEAD_SET_CRC_CONTROL_TIMESTAMP_MODE 3:3 +#define NV907D_HEAD_SET_CRC_CONTROL_TIMESTAMP_MODE_FALSE (0x00000000) +#define NV907D_HEAD_SET_CRC_CONTROL_TIMESTAMP_MODE_TRUE (0x00000001) +#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT 19:8 +#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC(i) (0x00000FF0 +(i)) +#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC__SIZE_1 4 +#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC0 (0x00000FF0) +#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC1 (0x00000FF1) +#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC2 (0x00000FF2) +#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_DAC3 (0x00000FF3) +#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG(i) (0x00000FF8 +(i)) +#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG__SIZE_1 4 +#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG0 (0x00000FF8) +#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG1 (0x00000FF9) +#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG2 (0x00000FFA) +#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_RG3 (0x00000FFB) +#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR(i) (0x00000F0F +(i)*16) +#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR__SIZE_1 8 +#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR0 (0x00000F0F) +#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR1 (0x00000F1F) +#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR2 (0x00000F2F) +#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR3 (0x00000F3F) +#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR4 (0x00000F4F) +#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR5 (0x00000F5F) +#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR6 (0x00000F6F) +#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SOR7 (0x00000F7F) +#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF(i) (0x00000F8F +(i)*16) +#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF__SIZE_1 4 +#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF0 (0x00000F8F) +#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF1 (0x00000F9F) +#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF2 (0x00000FAF) +#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_SF3 (0x00000FBF) +#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR(i) (0x000000FF +(i)*256) +#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR__SIZE_1 8 +#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR0 (0x000000FF) +#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR1 (0x000001FF) +#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR2 (0x000002FF) +#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR3 (0x000003FF) +#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR4 (0x000004FF) +#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR5 (0x000005FF) +#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR6 (0x000006FF) +#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_PIOR7 (0x000007FF) +#define NV907D_HEAD_SET_CRC_CONTROL_PRIMARY_OUTPUT_NONE (0x00000FFF) +#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT 31:20 +#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC(i) (0x00000FF0 +(i)) +#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC__SIZE_1 4 +#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC0 (0x00000FF0) +#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC1 (0x00000FF1) +#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC2 (0x00000FF2) +#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_DAC3 (0x00000FF3) +#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG(i) (0x00000FF8 +(i)) +#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG__SIZE_1 4 +#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG0 (0x00000FF8) +#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG1 (0x00000FF9) +#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG2 (0x00000FFA) +#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_RG3 (0x00000FFB) +#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR(i) (0x00000F0F +(i)*16) +#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR__SIZE_1 8 +#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR0 (0x00000F0F) +#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR1 (0x00000F1F) +#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR2 (0x00000F2F) +#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR3 (0x00000F3F) +#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR4 (0x00000F4F) +#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR5 (0x00000F5F) +#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR6 (0x00000F6F) +#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SOR7 (0x00000F7F) +#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF(i) (0x00000F8F +(i)*16) +#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF__SIZE_1 4 +#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF0 (0x00000F8F) +#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF1 (0x00000F9F) +#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF2 (0x00000FAF) +#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_SF3 (0x00000FBF) +#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR(i) (0x000000FF +(i)*256) +#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR__SIZE_1 8 +#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR0 (0x000000FF) +#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR1 (0x000001FF) +#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR2 (0x000002FF) +#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR3 (0x000003FF) +#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR4 (0x000004FF) +#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR5 (0x000005FF) +#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR6 (0x000006FF) +#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_PIOR7 (0x000007FF) +#define NV907D_HEAD_SET_CRC_CONTROL_SECONDARY_OUTPUT_NONE (0x00000FFF) +#define NV907D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE 5:5 +#define NV907D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE_DISABLE (0x00000000) +#define NV907D_HEAD_SET_CRC_CONTROL_CRC_DURING_SNOOZE_ENABLE (0x00000001) +#define NV907D_HEAD_SET_CONTEXT_DMA_CRC(a) (0x00000438 + (a)*0x00000300) +#define NV907D_HEAD_SET_CONTEXT_DMA_CRC_HANDLE 31:0 +#define NV907D_HEAD_SET_OUTPUT_LUT_LO(a) (0x00000448 + (a)*0x00000300) +#define NV907D_HEAD_SET_OUTPUT_LUT_LO_ENABLE 31:31 +#define NV907D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV907D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_ENABLE (0x00000001) +#define NV907D_HEAD_SET_OUTPUT_LUT_LO_MODE 27:24 +#define NV907D_HEAD_SET_OUTPUT_LUT_LO_MODE_LORES (0x00000000) +#define NV907D_HEAD_SET_OUTPUT_LUT_LO_MODE_HIRES (0x00000001) +#define NV907D_HEAD_SET_OUTPUT_LUT_LO_MODE_INDEX_1025_UNITY_RANGE (0x00000003) +#define NV907D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE (0x00000004) +#define NV907D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE (0x00000005) +#define NV907D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE (0x00000006) +#define NV907D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE (0x00000007) +#define NV907D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE (0x00000008) +#define NV907D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE 20:20 +#define NV907D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_DISABLE (0x00000000) +#define NV907D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_ENABLE (0x00000001) +#define NV907D_HEAD_SET_OUTPUT_LUT_HI(a) (0x0000044C + (a)*0x00000300) +#define NV907D_HEAD_SET_OUTPUT_LUT_HI_ORIGIN 31:0 +#define NV907D_HEAD_SET_PIXEL_CLOCK_FREQUENCY(a) (0x00000450 + (a)*0x00000300) +#define NV907D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HERTZ 30:0 +#define NV907D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001 31:31 +#define NV907D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_FALSE (0x00000000) +#define NV907D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_TRUE (0x00000001) +#define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION(a) (0x00000454 + (a)*0x00000300) +#define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE 21:20 +#define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_25 (0x00000000) +#define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_28 (0x00000001) +#define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_CUSTOM (0x00000002) +#define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER 24:24 +#define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_FALSE (0x00000000) +#define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_TRUE (0x00000001) +#define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING 25:25 +#define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING_FALSE (0x00000000) +#define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING_TRUE (0x00000001) +#define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE 26:26 +#define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_VBLANK (0x00000000) +#define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_HBLANK (0x00000001) +#define NV907D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(a) (0x00000458 + (a)*0x00000300) +#define NV907D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_HERTZ 30:0 +#define NV907D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001 31:31 +#define NV907D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_FALSE (0x00000000) +#define NV907D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_TRUE (0x00000001) +#define NV907D_HEAD_SET_CONTEXT_DMA_LUT(a) (0x0000045C + (a)*0x00000300) +#define NV907D_HEAD_SET_CONTEXT_DMA_LUT_HANDLE 31:0 +#define NV907D_HEAD_SET_OFFSET(a) (0x00000460 + (a)*0x00000300) +#define NV907D_HEAD_SET_OFFSET_ORIGIN 31:0 +#define NV907D_HEAD_SET_SIZE(a) (0x00000468 + (a)*0x00000300) +#define NV907D_HEAD_SET_SIZE_WIDTH 15:0 +#define NV907D_HEAD_SET_SIZE_HEIGHT 31:16 +#define NV907D_HEAD_SET_STORAGE(a) (0x0000046C + (a)*0x00000300) +#define NV907D_HEAD_SET_STORAGE_BLOCK_HEIGHT 3:0 +#define NV907D_HEAD_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB (0x00000000) +#define NV907D_HEAD_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS (0x00000001) +#define NV907D_HEAD_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS (0x00000002) +#define NV907D_HEAD_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003) +#define NV907D_HEAD_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NV907D_HEAD_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NV907D_HEAD_SET_STORAGE_PITCH 20:8 +#define NV907D_HEAD_SET_STORAGE_MEMORY_LAYOUT 24:24 +#define NV907D_HEAD_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NV907D_HEAD_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001) +#define NV907D_HEAD_SET_PARAMS(a) (0x00000470 + (a)*0x00000300) +#define NV907D_HEAD_SET_PARAMS_FORMAT 15:8 +#define NV907D_HEAD_SET_PARAMS_FORMAT_I8 (0x0000001E) +#define NV907D_HEAD_SET_PARAMS_FORMAT_VOID16 (0x0000001F) +#define NV907D_HEAD_SET_PARAMS_FORMAT_VOID32 (0x0000002E) +#define NV907D_HEAD_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA) +#define NV907D_HEAD_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF) +#define NV907D_HEAD_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1) +#define NV907D_HEAD_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS (0x00000022) +#define NV907D_HEAD_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5) +#define NV907D_HEAD_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8) +#define NV907D_HEAD_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9) +#define NV907D_HEAD_SET_PARAMS_FORMAT_R16_G16_B16_A16 (0x000000C6) +#define NV907D_HEAD_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS (0x00000023) +#define NV907D_HEAD_SET_PARAMS_SUPER_SAMPLE 1:0 +#define NV907D_HEAD_SET_PARAMS_SUPER_SAMPLE_X1_AA (0x00000000) +#define NV907D_HEAD_SET_PARAMS_SUPER_SAMPLE_X4_AA (0x00000002) +#define NV907D_HEAD_SET_PARAMS_GAMMA 2:2 +#define NV907D_HEAD_SET_PARAMS_GAMMA_LINEAR (0x00000000) +#define NV907D_HEAD_SET_PARAMS_GAMMA_SRGB (0x00000001) +#define NV907D_HEAD_SET_CONTEXT_DMAS_ISO(a) (0x00000474 + (a)*0x00000300) +#define NV907D_HEAD_SET_CONTEXT_DMAS_ISO_HANDLE 31:0 +#define NV907D_HEAD_SET_CONTROL_CURSOR(a) (0x00000480 + (a)*0x00000300) +#define NV907D_HEAD_SET_CONTROL_CURSOR_ENABLE 31:31 +#define NV907D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE (0x00000000) +#define NV907D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE (0x00000001) +#define NV907D_HEAD_SET_CONTROL_CURSOR_FORMAT 25:24 +#define NV907D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5 (0x00000000) +#define NV907D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8 (0x00000001) +#define NV907D_HEAD_SET_CONTROL_CURSOR_SIZE 26:26 +#define NV907D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32 (0x00000000) +#define NV907D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64 (0x00000001) +#define NV907D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X 13:8 +#define NV907D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y 21:16 +#define NV907D_HEAD_SET_CONTROL_CURSOR_COMPOSITION 29:28 +#define NV907D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_ALPHA_BLEND (0x00000000) +#define NV907D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_PREMULT_ALPHA_BLEND (0x00000001) +#define NV907D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_XOR (0x00000002) +#define NV907D_HEAD_SET_OFFSET_CURSOR(a) (0x00000484 + (a)*0x00000300) +#define NV907D_HEAD_SET_OFFSET_CURSOR_ORIGIN 31:0 +#define NV907D_HEAD_SET_CONTEXT_DMA_CURSOR(a) (0x0000048C + (a)*0x00000300) +#define NV907D_HEAD_SET_CONTEXT_DMA_CURSOR_HANDLE 31:0 +#define NV907D_HEAD_SET_DITHER_CONTROL(a) (0x00000490 + (a)*0x00000300) +#define NV907D_HEAD_SET_DITHER_CONTROL_ENABLE 0:0 +#define NV907D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE (0x00000000) +#define NV907D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE (0x00000001) +#define NV907D_HEAD_SET_DITHER_CONTROL_BITS 2:1 +#define NV907D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_6_BITS (0x00000000) +#define NV907D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_8_BITS (0x00000001) +#define NV907D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_10_BITS (0x00000002) +#define NV907D_HEAD_SET_DITHER_CONTROL_MODE 6:3 +#define NV907D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC (0x00000000) +#define NV907D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC (0x00000001) +#define NV907D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2 (0x00000002) +#define NV907D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2 (0x00000003) +#define NV907D_HEAD_SET_DITHER_CONTROL_MODE_TEMPORAL (0x00000004) +#define NV907D_HEAD_SET_DITHER_CONTROL_PHASE 8:7 +#define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER(a) (0x00000494 + (a)*0x00000300) +#define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS 2:0 +#define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_1 (0x00000000) +#define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_2 (0x00000001) +#define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3 (0x00000002) +#define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3_ADAPTIVE (0x00000003) +#define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_5 (0x00000004) +#define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS 4:3 +#define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_1 (0x00000000) +#define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_2 (0x00000001) +#define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_8 (0x00000002) +#define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER_HRESPONSE_BIAS 23:16 +#define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER_VRESPONSE_BIAS 31:24 +#define NV907D_HEAD_SET_PROCAMP(a) (0x00000498 + (a)*0x00000300) +#define NV907D_HEAD_SET_PROCAMP_COLOR_SPACE 1:0 +#define NV907D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB (0x00000000) +#define NV907D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601 (0x00000001) +#define NV907D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709 (0x00000002) +#define NV907D_HEAD_SET_PROCAMP_CHROMA_LPF 2:2 +#define NV907D_HEAD_SET_PROCAMP_CHROMA_LPF_AUTO (0x00000000) +#define NV907D_HEAD_SET_PROCAMP_CHROMA_LPF_ON (0x00000001) +#define NV907D_HEAD_SET_PROCAMP_SAT_COS 19:8 +#define NV907D_HEAD_SET_PROCAMP_SAT_SINE 31:20 +#define NV907D_HEAD_SET_PROCAMP_DYNAMIC_RANGE 5:5 +#define NV907D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_VESA (0x00000000) +#define NV907D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_CEA (0x00000001) +#define NV907D_HEAD_SET_PROCAMP_RANGE_COMPRESSION 6:6 +#define NV907D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_DISABLE (0x00000000) +#define NV907D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_ENABLE (0x00000001) +#define NV907D_HEAD_SET_VIEWPORT_POINT_IN(a) (0x000004B0 + (a)*0x00000300) +#define NV907D_HEAD_SET_VIEWPORT_POINT_IN_X 14:0 +#define NV907D_HEAD_SET_VIEWPORT_POINT_IN_Y 30:16 +#define NV907D_HEAD_SET_VIEWPORT_SIZE_IN(a) (0x000004B8 + (a)*0x00000300) +#define NV907D_HEAD_SET_VIEWPORT_SIZE_IN_WIDTH 14:0 +#define NV907D_HEAD_SET_VIEWPORT_SIZE_IN_HEIGHT 30:16 +#define NV907D_HEAD_SET_VIEWPORT_SIZE_OUT(a) (0x000004C0 + (a)*0x00000300) +#define NV907D_HEAD_SET_VIEWPORT_SIZE_OUT_WIDTH 14:0 +#define NV907D_HEAD_SET_VIEWPORT_SIZE_OUT_HEIGHT 30:16 +#define NV907D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN(a) (0x000004C4 + (a)*0x00000300) +#define NV907D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_WIDTH 14:0 +#define NV907D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_HEIGHT 30:16 +#define NV907D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX(a) (0x000004C8 + (a)*0x00000300) +#define NV907D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX_WIDTH 14:0 +#define NV907D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX_HEIGHT 30:16 +#define NV907D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(a) (0x000004D0 + (a)*0x00000300) +#define NV907D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE 0:0 +#define NV907D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_FALSE (0x00000000) +#define NV907D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_TRUE (0x00000001) +#define NV907D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH 11:8 +#define NV907D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_8 (0x00000000) +#define NV907D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16 (0x00000001) +#define NV907D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32 (0x00000003) +#define NV907D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64 (0x00000005) +#define NV907D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE 13:12 +#define NV907D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X1_AA (0x00000000) +#define NV907D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X4_AA (0x00000002) +#define NV907D_HEAD_SET_OVERLAY_USAGE_BOUNDS(a) (0x000004D4 + (a)*0x00000300) +#define NV907D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE 0:0 +#define NV907D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_FALSE (0x00000000) +#define NV907D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_TRUE (0x00000001) +#define NV907D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH 11:8 +#define NV907D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16 (0x00000001) +#define NV907D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32 (0x00000003) +#define NV907D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64 (0x00000005) +#endif // _cl907d_h diff --git a/drivers/gpu/drm/nouveau/include/nvhw/class/cl917d.h b/drivers/gpu/drm/nouveau/include/nvhw/class/cl917d.h new file mode 100644 index 000000000000..2a2612d6e1e0 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvhw/class/cl917d.h @@ -0,0 +1,104 @@ +/* + * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl917d_h_ +#define _cl917d_h_ + +// class methods +#define NV917D_SOR_SET_CONTROL(a) (0x00000200 + (a)*0x00000020) +#define NV917D_SOR_SET_CONTROL_OWNER_MASK 3:0 +#define NV917D_SOR_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NV917D_SOR_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NV917D_SOR_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NV917D_SOR_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NV917D_SOR_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NV917D_SOR_SET_CONTROL_PROTOCOL 11:8 +#define NV917D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM (0x00000000) +#define NV917D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A (0x00000001) +#define NV917D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B (0x00000002) +#define NV917D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS (0x00000005) +#define NV917D_SOR_SET_CONTROL_PROTOCOL_DP_A (0x00000008) +#define NV917D_SOR_SET_CONTROL_PROTOCOL_DP_B (0x00000009) +#define NV917D_SOR_SET_CONTROL_PROTOCOL_CUSTOM (0x0000000F) +#define NV917D_SOR_SET_CONTROL_DE_SYNC_POLARITY 14:14 +#define NV917D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV917D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV917D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE 21:20 +#define NV917D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_OFF (0x00000000) +#define NV917D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X2 (0x00000001) +#define NV917D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X4 (0x00000002) + +#define NV917D_HEAD_SET_CONTROL_CURSOR(a) (0x00000480 + (a)*0x00000300) +#define NV917D_HEAD_SET_CONTROL_CURSOR_ENABLE 31:31 +#define NV917D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE (0x00000000) +#define NV917D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE (0x00000001) +#define NV917D_HEAD_SET_CONTROL_CURSOR_FORMAT 25:24 +#define NV917D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5 (0x00000000) +#define NV917D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8 (0x00000001) +#define NV917D_HEAD_SET_CONTROL_CURSOR_SIZE 27:26 +#define NV917D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32 (0x00000000) +#define NV917D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64 (0x00000001) +#define NV917D_HEAD_SET_CONTROL_CURSOR_SIZE_W128_H128 (0x00000002) +#define NV917D_HEAD_SET_CONTROL_CURSOR_SIZE_W256_H256 (0x00000003) +#define NV917D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X 15:8 +#define NV917D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y 23:16 +#define NV917D_HEAD_SET_CONTROL_CURSOR_COMPOSITION 29:28 +#define NV917D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_ALPHA_BLEND (0x00000000) +#define NV917D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_PREMULT_ALPHA_BLEND (0x00000001) +#define NV917D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_XOR (0x00000002) +#define NV917D_HEAD_SET_DITHER_CONTROL(a) (0x000004A0 + (a)*0x00000300) +#define NV917D_HEAD_SET_DITHER_CONTROL_ENABLE 0:0 +#define NV917D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE (0x00000000) +#define NV917D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE (0x00000001) +#define NV917D_HEAD_SET_DITHER_CONTROL_BITS 2:1 +#define NV917D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_6_BITS (0x00000000) +#define NV917D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_8_BITS (0x00000001) +#define NV917D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_10_BITS (0x00000002) +#define NV917D_HEAD_SET_DITHER_CONTROL_MODE 6:3 +#define NV917D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC (0x00000000) +#define NV917D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC (0x00000001) +#define NV917D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2 (0x00000002) +#define NV917D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2 (0x00000003) +#define NV917D_HEAD_SET_DITHER_CONTROL_MODE_TEMPORAL (0x00000004) +#define NV917D_HEAD_SET_DITHER_CONTROL_PHASE 8:7 +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(a) (0x000004D0 + (a)*0x00000300) +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE 0:0 +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_FALSE (0x00000000) +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_TRUE (0x00000001) +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH 11:8 +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_8 (0x00000000) +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16 (0x00000001) +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32 (0x00000003) +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64 (0x00000005) +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE 13:12 +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X1_AA (0x00000000) +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X4_AA (0x00000002) +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT 17:16 +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_NONE (0x00000000) +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_257 (0x00000001) +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_1025 (0x00000002) +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT 21:20 +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_NONE (0x00000000) +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_257 (0x00000001) +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_1025 (0x00000002) +#endif // _cl917d_h From ca31b0c01a2759d5ac40695e51287962e08826fe Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sun, 21 Jun 2020 17:40:51 +1000 Subject: [PATCH 118/145] drm/nouveau/kms/nv50-: use NVIDIA's headers for core or_get_caps() Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/sor907d.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/sor907d.c b/drivers/gpu/drm/nouveau/dispnv50/sor907d.c index db09cc5af5f6..c86cd8fa61d6 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/sor907d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/sor907d.c @@ -45,10 +45,10 @@ sor907d_ctrl(struct nv50_core *core, int or, u32 ctrl, static void sor907d_get_caps(struct nv50_disp *disp, struct nouveau_encoder *outp, int or) { + struct nouveau_bo *bo = disp->sync; const int off = or * 2; - u32 tmp = nouveau_bo_rd32(disp->sync, 0x000014 + off); - - outp->caps.dp_interlace = !!(tmp & 0x04000000); + outp->caps.dp_interlace = + NVBO_RV32(bo, off, NV907D_CORE_NOTIFIER_3, CAPABILITIES_CAP_SOR0_20, DP_INTERLACE); } const struct nv50_outp_func From fb3939e232f6120387f20a26510894a17680db3a Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sun, 21 Jun 2020 10:55:21 +1000 Subject: [PATCH 119/145] drm/nouveau/kms/nv50-: use NVIDIA's headers for core head_view() Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/head507d.c | 23 ++++++++++++++--- drivers/gpu/drm/nouveau/dispnv50/head907d.c | 28 +++++++++++++++++---- drivers/gpu/drm/nouveau/dispnv50/headc37d.c | 11 ++++++-- 3 files changed, 51 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/head507d.c b/drivers/gpu/drm/nouveau/dispnv50/head507d.c index 2e72ee410fa7..c4699a92b12b 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head507d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head507d.c @@ -24,6 +24,8 @@ #include +#include + int head507d_procamp(struct nv50_head *head, struct nv50_head_atom *asyh) { @@ -339,10 +341,23 @@ head507d_view(struct nv50_head *head, struct nv50_head_atom *asyh) if ((ret = PUSH_WAIT(push, 7))) return ret; - PUSH_NVSQ(push, NV507D, 0x08a4 + (i * 0x400), 0x00000000); - PUSH_NVSQ(push, NV507D, 0x08c8 + (i * 0x400), asyh->view.iH << 16 | asyh->view.iW); - PUSH_NVSQ(push, NV507D, 0x08d8 + (i * 0x400), asyh->view.oH << 16 | asyh->view.oW, - 0x08dc + (i * 0x400), asyh->view.oH << 16 | asyh->view.oW); + PUSH_MTHD(push, NV507D, HEAD_SET_CONTROL_OUTPUT_SCALER(i), + NVDEF(NV507D, HEAD_SET_CONTROL_OUTPUT_SCALER, VERTICAL_TAPS, TAPS_1) | + NVDEF(NV507D, HEAD_SET_CONTROL_OUTPUT_SCALER, HORIZONTAL_TAPS, TAPS_1) | + NVVAL(NV507D, HEAD_SET_CONTROL_OUTPUT_SCALER, HRESPONSE_BIAS, 0) | + NVVAL(NV507D, HEAD_SET_CONTROL_OUTPUT_SCALER, VRESPONSE_BIAS, 0)); + + PUSH_MTHD(push, NV507D, HEAD_SET_VIEWPORT_SIZE_IN(i), + NVVAL(NV507D, HEAD_SET_VIEWPORT_SIZE_IN, WIDTH, asyh->view.iW) | + NVVAL(NV507D, HEAD_SET_VIEWPORT_SIZE_IN, HEIGHT, asyh->view.iH)); + + PUSH_MTHD(push, NV507D, HEAD_SET_VIEWPORT_SIZE_OUT(i), + NVVAL(NV507D, HEAD_SET_VIEWPORT_SIZE_OUT, WIDTH, asyh->view.oW) | + NVVAL(NV507D, HEAD_SET_VIEWPORT_SIZE_OUT, HEIGHT, asyh->view.oH), + + HEAD_SET_VIEWPORT_SIZE_OUT_MIN(i), + NVVAL(NV507D, HEAD_SET_VIEWPORT_SIZE_OUT_MIN, WIDTH, asyh->view.oW) | + NVVAL(NV507D, HEAD_SET_VIEWPORT_SIZE_OUT_MIN, HEIGHT, asyh->view.oH)); return 0; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/head907d.c b/drivers/gpu/drm/nouveau/dispnv50/head907d.c index 3be63f09dfa6..52240a865915 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head907d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head907d.c @@ -31,6 +31,8 @@ #include +#include + int head907d_or(struct nv50_head *head, struct nv50_head_atom *asyh) { @@ -302,11 +304,27 @@ head907d_view(struct nv50_head *head, struct nv50_head_atom *asyh) if ((ret = PUSH_WAIT(push, 8))) return ret; - PUSH_NVSQ(push, NV907D, 0x0494 + (i * 0x300), 0x00000000); - PUSH_NVSQ(push, NV907D, 0x04b8 + (i * 0x300), asyh->view.iH << 16 | asyh->view.iW); - PUSH_NVSQ(push, NV907D, 0x04c0 + (i * 0x300), asyh->view.oH << 16 | asyh->view.oW, - 0x04c4 + (i * 0x300), asyh->view.oH << 16 | asyh->view.oW, - 0x04c8 + (i * 0x300), asyh->view.oH << 16 | asyh->view.oW); + PUSH_MTHD(push, NV907D, HEAD_SET_CONTROL_OUTPUT_SCALER(i), + NVDEF(NV907D, HEAD_SET_CONTROL_OUTPUT_SCALER, VERTICAL_TAPS, TAPS_1) | + NVDEF(NV907D, HEAD_SET_CONTROL_OUTPUT_SCALER, HORIZONTAL_TAPS, TAPS_1) | + NVVAL(NV907D, HEAD_SET_CONTROL_OUTPUT_SCALER, HRESPONSE_BIAS, 0) | + NVVAL(NV907D, HEAD_SET_CONTROL_OUTPUT_SCALER, VRESPONSE_BIAS, 0)); + + PUSH_MTHD(push, NV907D, HEAD_SET_VIEWPORT_SIZE_IN(i), + NVVAL(NV907D, HEAD_SET_VIEWPORT_SIZE_IN, WIDTH, asyh->view.iW) | + NVVAL(NV907D, HEAD_SET_VIEWPORT_SIZE_IN, HEIGHT, asyh->view.iH)); + + PUSH_MTHD(push, NV907D, HEAD_SET_VIEWPORT_SIZE_OUT(i), + NVVAL(NV907D, HEAD_SET_VIEWPORT_SIZE_OUT, WIDTH, asyh->view.oW) | + NVVAL(NV907D, HEAD_SET_VIEWPORT_SIZE_OUT, HEIGHT, asyh->view.oH), + + HEAD_SET_VIEWPORT_SIZE_OUT_MIN(i), + NVVAL(NV907D, HEAD_SET_VIEWPORT_SIZE_OUT_MIN, WIDTH, asyh->view.oW) | + NVVAL(NV907D, HEAD_SET_VIEWPORT_SIZE_OUT_MIN, HEIGHT, asyh->view.oH), + + HEAD_SET_VIEWPORT_SIZE_OUT_MAX(i), + NVVAL(NV907D, HEAD_SET_VIEWPORT_SIZE_OUT_MAX, WIDTH, asyh->view.oW) | + NVVAL(NV907D, HEAD_SET_VIEWPORT_SIZE_OUT_MAX, HEIGHT, asyh->view.oH)); return 0; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/headc37d.c b/drivers/gpu/drm/nouveau/dispnv50/headc37d.c index bd63245caf6b..7553f1198509 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/headc37d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/headc37d.c @@ -25,6 +25,8 @@ #include +#include + static int headc37d_or(struct nv50_head *head, struct nv50_head_atom *asyh) { @@ -212,8 +214,13 @@ headc37d_view(struct nv50_head *head, struct nv50_head_atom *asyh) if ((ret = PUSH_WAIT(push, 4))) return ret; - PUSH_NVSQ(push, NVC37D, 0x204c + (i * 0x400), asyh->view.iH << 16 | asyh->view.iW); - PUSH_NVSQ(push, NVC37D, 0x2058 + (i * 0x400), asyh->view.oH << 16 | asyh->view.oW); + PUSH_MTHD(push, NVC37D, HEAD_SET_VIEWPORT_SIZE_IN(i), + NVVAL(NVC37D, HEAD_SET_VIEWPORT_SIZE_IN, WIDTH, asyh->view.iW) | + NVVAL(NVC37D, HEAD_SET_VIEWPORT_SIZE_IN, HEIGHT, asyh->view.iH)); + + PUSH_MTHD(push, NVC37D, HEAD_SET_VIEWPORT_SIZE_OUT(i), + NVVAL(NVC37D, HEAD_SET_VIEWPORT_SIZE_OUT, WIDTH, asyh->view.oW) | + NVVAL(NVC37D, HEAD_SET_VIEWPORT_SIZE_OUT, HEIGHT, asyh->view.oH)); return 0; } From c4c751885efb951a65f3a4df123fe08464dddbba Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sun, 21 Jun 2020 11:25:06 +1000 Subject: [PATCH 120/145] drm/nouveau/kms/nv50-: use NVIDIA's headers for core head_mode() Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/head507d.c | 51 ++++++++++++++---- drivers/gpu/drm/nouveau/dispnv50/head907d.c | 60 +++++++++++++++++---- drivers/gpu/drm/nouveau/dispnv50/headc37d.c | 40 ++++++++++---- drivers/gpu/drm/nouveau/dispnv50/headc57d.c | 43 +++++++++++---- 4 files changed, 153 insertions(+), 41 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/head507d.c b/drivers/gpu/drm/nouveau/dispnv50/head507d.c index c4699a92b12b..a4759641931f 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head507d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head507d.c @@ -318,16 +318,47 @@ head507d_mode(struct nv50_head *head, struct nv50_head_atom *asyh) if ((ret = PUSH_WAIT(push, 13))) return ret; - PUSH_NVSQ(push, NV507D, 0x0804 + (i * 0x400), 0x00800000 | m->clock, - 0x0808 + (i * 0x400), m->interlace ? 0x00000002 : 0x00000000); - PUSH_NVSQ(push, NV507D, 0x0810 + (i * 0x400), 0x00000000, - 0x0814 + (i * 0x400), m->v.active << 16 | m->h.active, - 0x0818 + (i * 0x400), m->v.synce << 16 | m->h.synce, - 0x081c + (i * 0x400), m->v.blanke << 16 | m->h.blanke, - 0x0820 + (i * 0x400), m->v.blanks << 16 | m->h.blanks, - 0x0824 + (i * 0x400), m->v.blank2e << 16 | m->v.blank2s, - 0x0828 + (i * 0x400), asyh->mode.v.blankus); - PUSH_NVSQ(push, NV507D, 0x082c + (i * 0x400), 0x00000000); + PUSH_MTHD(push, NV507D, HEAD_SET_PIXEL_CLOCK(i), + NVVAL(NV507D, HEAD_SET_PIXEL_CLOCK, FREQUENCY, m->clock) | + NVDEF(NV507D, HEAD_SET_PIXEL_CLOCK, MODE, CLK_CUSTOM) | + NVDEF(NV507D, HEAD_SET_PIXEL_CLOCK, ADJ1000DIV1001, FALSE) | + NVDEF(NV507D, HEAD_SET_PIXEL_CLOCK, NOT_DRIVER, FALSE), + + HEAD_SET_CONTROL(i), + NVVAL(NV507D, HEAD_SET_CONTROL, STRUCTURE, m->interlace)); + + PUSH_MTHD(push, NV507D, HEAD_SET_OVERSCAN_COLOR(i), + NVVAL(NV507D, HEAD_SET_OVERSCAN_COLOR, RED, 0) | + NVVAL(NV507D, HEAD_SET_OVERSCAN_COLOR, GRN, 0) | + NVVAL(NV507D, HEAD_SET_OVERSCAN_COLOR, BLU, 0), + + HEAD_SET_RASTER_SIZE(i), + NVVAL(NV507D, HEAD_SET_RASTER_SIZE, WIDTH, m->h.active) | + NVVAL(NV507D, HEAD_SET_RASTER_SIZE, HEIGHT, m->v.active), + + HEAD_SET_RASTER_SYNC_END(i), + NVVAL(NV507D, HEAD_SET_RASTER_SYNC_END, X, m->h.synce) | + NVVAL(NV507D, HEAD_SET_RASTER_SYNC_END, Y, m->v.synce), + + HEAD_SET_RASTER_BLANK_END(i), + NVVAL(NV507D, HEAD_SET_RASTER_BLANK_END, X, m->h.blanke) | + NVVAL(NV507D, HEAD_SET_RASTER_BLANK_END, Y, m->v.blanke), + + HEAD_SET_RASTER_BLANK_START(i), + NVVAL(NV507D, HEAD_SET_RASTER_BLANK_START, X, m->h.blanks) | + NVVAL(NV507D, HEAD_SET_RASTER_BLANK_START, Y, m->v.blanks), + + HEAD_SET_RASTER_VERT_BLANK2(i), + NVVAL(NV507D, HEAD_SET_RASTER_VERT_BLANK2, YSTART, m->v.blank2s) | + NVVAL(NV507D, HEAD_SET_RASTER_VERT_BLANK2, YEND, m->v.blank2e), + + HEAD_SET_RASTER_VERT_BLANK_DMI(i), + NVVAL(NV507D, HEAD_SET_RASTER_VERT_BLANK_DMI, DURATION, m->v.blankus)); + + PUSH_MTHD(push, NV507D, HEAD_SET_DEFAULT_BASE_COLOR(i), + NVVAL(NV507D, HEAD_SET_DEFAULT_BASE_COLOR, RED, 0) | + NVVAL(NV507D, HEAD_SET_DEFAULT_BASE_COLOR, GREEN, 0) | + NVVAL(NV507D, HEAD_SET_DEFAULT_BASE_COLOR, BLUE, 0)); return 0; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/head907d.c b/drivers/gpu/drm/nouveau/dispnv50/head907d.c index 52240a865915..9a0a1ceb5432 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head907d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head907d.c @@ -280,17 +280,55 @@ head907d_mode(struct nv50_head *head, struct nv50_head_atom *asyh) if ((ret = PUSH_WAIT(push, 14))) return ret; - PUSH_NVSQ(push, NV907D, 0x0410 + (i * 0x300), 0x00000000, - 0x0414 + (i * 0x300), m->v.active << 16 | m->h.active, - 0x0418 + (i * 0x300), m->v.synce << 16 | m->h.synce, - 0x041c + (i * 0x300), m->v.blanke << 16 | m->h.blanke, - 0x0420 + (i * 0x300), m->v.blanks << 16 | m->h.blanks, - 0x0424 + (i * 0x300), m->v.blank2e << 16 | m->v.blank2s); - PUSH_NVSQ(push, NV907D, 0x042c + (i * 0x300), 0x00000000, - 0x0430 + (i * 0x300), 0xffffff00); - PUSH_NVSQ(push, NV907D, 0x0450 + (i * 0x300), m->clock * 1000, - 0x0454 + (i * 0x300), 0x00200000, - 0x0458 + (i * 0x300), m->clock * 1000); + PUSH_MTHD(push, NV907D, HEAD_SET_OVERSCAN_COLOR(i), + NVVAL(NV907D, HEAD_SET_OVERSCAN_COLOR, RED, 0) | + NVVAL(NV907D, HEAD_SET_OVERSCAN_COLOR, GRN, 0) | + NVVAL(NV907D, HEAD_SET_OVERSCAN_COLOR, BLU, 0), + + HEAD_SET_RASTER_SIZE(i), + NVVAL(NV907D, HEAD_SET_RASTER_SIZE, WIDTH, m->h.active) | + NVVAL(NV907D, HEAD_SET_RASTER_SIZE, HEIGHT, m->v.active), + + HEAD_SET_RASTER_SYNC_END(i), + NVVAL(NV907D, HEAD_SET_RASTER_SYNC_END, X, m->h.synce) | + NVVAL(NV907D, HEAD_SET_RASTER_SYNC_END, Y, m->v.synce), + + HEAD_SET_RASTER_BLANK_END(i), + NVVAL(NV907D, HEAD_SET_RASTER_BLANK_END, X, m->h.blanke) | + NVVAL(NV907D, HEAD_SET_RASTER_BLANK_END, Y, m->v.blanke), + + HEAD_SET_RASTER_BLANK_START(i), + NVVAL(NV907D, HEAD_SET_RASTER_BLANK_START, X, m->h.blanks) | + NVVAL(NV907D, HEAD_SET_RASTER_BLANK_START, Y, m->v.blanks), + + HEAD_SET_RASTER_VERT_BLANK2(i), + NVVAL(NV907D, HEAD_SET_RASTER_VERT_BLANK2, YSTART, m->v.blank2s) | + NVVAL(NV907D, HEAD_SET_RASTER_VERT_BLANK2, YEND, m->v.blank2e)); + + PUSH_MTHD(push, NV907D, HEAD_SET_DEFAULT_BASE_COLOR(i), + NVVAL(NV907D, HEAD_SET_DEFAULT_BASE_COLOR, RED, 0) | + NVVAL(NV907D, HEAD_SET_DEFAULT_BASE_COLOR, GREEN, 0) | + NVVAL(NV907D, HEAD_SET_DEFAULT_BASE_COLOR, BLUE, 0), + + HEAD_SET_CRC_CONTROL(i), + NVDEF(NV907D, HEAD_SET_CRC_CONTROL, CONTROLLING_CHANNEL, CORE) | + NVDEF(NV907D, HEAD_SET_CRC_CONTROL, EXPECT_BUFFER_COLLAPSE, FALSE) | + NVDEF(NV907D, HEAD_SET_CRC_CONTROL, TIMESTAMP_MODE, FALSE) | + NVDEF(NV907D, HEAD_SET_CRC_CONTROL, PRIMARY_OUTPUT, NONE) | + NVDEF(NV907D, HEAD_SET_CRC_CONTROL, SECONDARY_OUTPUT, NONE)); + + PUSH_MTHD(push, NV907D, HEAD_SET_PIXEL_CLOCK_FREQUENCY(i), + NVVAL(NV907D, HEAD_SET_PIXEL_CLOCK_FREQUENCY, HERTZ, m->clock * 1000) | + NVDEF(NV907D, HEAD_SET_PIXEL_CLOCK_FREQUENCY, ADJ1000DIV1001, FALSE), + + HEAD_SET_PIXEL_CLOCK_CONFIGURATION(i), + NVDEF(NV907D, HEAD_SET_PIXEL_CLOCK_CONFIGURATION, MODE, CLK_CUSTOM) | + NVDEF(NV907D, HEAD_SET_PIXEL_CLOCK_CONFIGURATION, NOT_DRIVER, FALSE) | + NVDEF(NV907D, HEAD_SET_PIXEL_CLOCK_CONFIGURATION, ENABLE_HOPPING, FALSE), + + HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(i), + NVVAL(NV907D, HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX, HERTZ, m->clock * 1000) | + NVDEF(NV907D, HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX, ADJ1000DIV1001, FALSE)); return 0; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/headc37d.c b/drivers/gpu/drm/nouveau/dispnv50/headc37d.c index 7553f1198509..e397ababa3e7 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/headc37d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/headc37d.c @@ -187,20 +187,40 @@ headc37d_mode(struct nv50_head *head, struct nv50_head_atom *asyh) const int i = head->base.index; int ret; - if ((ret = PUSH_WAIT(push, 13))) + if ((ret = PUSH_WAIT(push, 15))) return ret; - PUSH_NVSQ(push, NVC37D, 0x2064 + (i * 0x400), m->v.active << 16 | m->h.active, - 0x2068 + (i * 0x400), m->v.synce << 16 | m->h.synce, - 0x206c + (i * 0x400), m->v.blanke << 16 | m->h.blanke, - 0x2070 + (i * 0x400), m->v.blanks << 16 | m->h.blanks, - 0x2074 + (i * 0x400), m->v.blank2e << 16 | m->v.blank2s); - PUSH_NVSQ(push, NVC37D, 0x2008 + (i * 0x400), m->interlace, - 0x200c + (i * 0x400), m->clock * 1000); - PUSH_NVSQ(push, NVC37D, 0x2028 + (i * 0x400), m->clock * 1000); + PUSH_MTHD(push, NVC37D, HEAD_SET_RASTER_SIZE(i), + NVVAL(NVC37D, HEAD_SET_RASTER_SIZE, WIDTH, m->h.active) | + NVVAL(NVC37D, HEAD_SET_RASTER_SIZE, HEIGHT, m->v.active), + + HEAD_SET_RASTER_SYNC_END(i), + NVVAL(NVC37D, HEAD_SET_RASTER_SYNC_END, X, m->h.synce) | + NVVAL(NVC37D, HEAD_SET_RASTER_SYNC_END, Y, m->v.synce), + + HEAD_SET_RASTER_BLANK_END(i), + NVVAL(NVC37D, HEAD_SET_RASTER_BLANK_END, X, m->h.blanke) | + NVVAL(NVC37D, HEAD_SET_RASTER_BLANK_END, Y, m->v.blanke), + + HEAD_SET_RASTER_BLANK_START(i), + NVVAL(NVC37D, HEAD_SET_RASTER_BLANK_START, X, m->h.blanks) | + NVVAL(NVC37D, HEAD_SET_RASTER_BLANK_START, Y, m->v.blanks)); + + //XXX: + PUSH_NVSQ(push, NVC37D, 0x2074 + (i * 0x400), m->v.blank2e << 16 | m->v.blank2s); + PUSH_NVSQ(push, NVC37D, 0x2008 + (i * 0x400), m->interlace); + + PUSH_MTHD(push, NVC37D, HEAD_SET_PIXEL_CLOCK_FREQUENCY(i), + NVVAL(NVC37D, HEAD_SET_PIXEL_CLOCK_FREQUENCY, HERTZ, m->clock * 1000)); + + PUSH_MTHD(push, NVC37D, HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(i), + NVVAL(NVC37D, HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX, HERTZ, m->clock * 1000)); /*XXX: HEAD_USAGE_BOUNDS, doesn't belong here. */ - PUSH_NVSQ(push, NVC37D, 0x2030 + (i * 0x400), 0x00000124); + PUSH_MTHD(push, NVC37D, HEAD_SET_HEAD_USAGE_BOUNDS(i), + NVDEF(NVC37D, HEAD_SET_HEAD_USAGE_BOUNDS, CURSOR, USAGE_W256_H256) | + NVDEF(NVC37D, HEAD_SET_HEAD_USAGE_BOUNDS, OUTPUT_LUT, USAGE_1025) | + NVDEF(NVC37D, HEAD_SET_HEAD_USAGE_BOUNDS, UPSCALING_ALLOWED, TRUE)); return 0; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/headc57d.c b/drivers/gpu/drm/nouveau/dispnv50/headc57d.c index e38087bf7171..9cfaf62341b0 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/headc57d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/headc57d.c @@ -25,6 +25,8 @@ #include +#include + static int headc57d_or(struct nv50_head *head, struct nv50_head_atom *asyh) { @@ -183,20 +185,41 @@ headc57d_mode(struct nv50_head *head, struct nv50_head_atom *asyh) const int i = head->base.index; int ret; - if ((ret = PUSH_WAIT(push, 13))) + if ((ret = PUSH_WAIT(push, 15))) return ret; - PUSH_NVSQ(push, NVC57D, 0x2064 + (i * 0x400), m->v.active << 16 | m->h.active, - 0x2068 + (i * 0x400), m->v.synce << 16 | m->h.synce, - 0x206c + (i * 0x400), m->v.blanke << 16 | m->h.blanke, - 0x2070 + (i * 0x400), m->v.blanks << 16 | m->h.blanks, - 0x2074 + (i * 0x400), m->v.blank2e << 16 | m->v.blank2s); - PUSH_NVSQ(push, NVC57D, 0x2008 + (i * 0x400), m->interlace, - 0x200c + (i * 0x400), m->clock * 1000); - PUSH_NVSQ(push, NVC57D, 0x2028 + (i * 0x400), m->clock * 1000); + PUSH_MTHD(push, NVC57D, HEAD_SET_RASTER_SIZE(i), + NVVAL(NVC57D, HEAD_SET_RASTER_SIZE, WIDTH, m->h.active) | + NVVAL(NVC57D, HEAD_SET_RASTER_SIZE, HEIGHT, m->v.active), + + HEAD_SET_RASTER_SYNC_END(i), + NVVAL(NVC57D, HEAD_SET_RASTER_SYNC_END, X, m->h.synce) | + NVVAL(NVC57D, HEAD_SET_RASTER_SYNC_END, Y, m->v.synce), + + HEAD_SET_RASTER_BLANK_END(i), + NVVAL(NVC57D, HEAD_SET_RASTER_BLANK_END, X, m->h.blanke) | + NVVAL(NVC57D, HEAD_SET_RASTER_BLANK_END, Y, m->v.blanke), + + HEAD_SET_RASTER_BLANK_START(i), + NVVAL(NVC57D, HEAD_SET_RASTER_BLANK_START, X, m->h.blanks) | + NVVAL(NVC57D, HEAD_SET_RASTER_BLANK_START, Y, m->v.blanks)); + + //XXX: + PUSH_NVSQ(push, NVC57D, 0x2074 + (i * 0x400), m->v.blank2e << 16 | m->v.blank2s); + PUSH_NVSQ(push, NVC57D, 0x2008 + (i * 0x400), m->interlace); + + PUSH_MTHD(push, NVC57D, HEAD_SET_PIXEL_CLOCK_FREQUENCY(i), + NVVAL(NVC57D, HEAD_SET_PIXEL_CLOCK_FREQUENCY, HERTZ, m->clock * 1000)); + + PUSH_MTHD(push, NVC57D, HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(i), + NVVAL(NVC57D, HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX, HERTZ, m->clock * 1000)); /*XXX: HEAD_USAGE_BOUNDS, doesn't belong here. */ - PUSH_NVSQ(push, NVC57D, 0x2030 + (i * 0x400), 0x00001114); + PUSH_MTHD(push, NVC57D, HEAD_SET_HEAD_USAGE_BOUNDS(i), + NVDEF(NVC57D, HEAD_SET_HEAD_USAGE_BOUNDS, CURSOR, USAGE_W256_H256) | + NVDEF(NVC57D, HEAD_SET_HEAD_USAGE_BOUNDS, OLUT_ALLOWED, TRUE) | + NVDEF(NVC57D, HEAD_SET_HEAD_USAGE_BOUNDS, OUTPUT_SCALER_TAPS, TAPS_2) | + NVDEF(NVC57D, HEAD_SET_HEAD_USAGE_BOUNDS, UPSCALING_ALLOWED, TRUE)); return 0; } From a41ef363f5e8a1608d5dd970aa706601145a142f Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sun, 21 Jun 2020 11:44:39 +1000 Subject: [PATCH 121/145] drm/nouveau/kms/nv50-: use NVIDIA's headers for core head_olut_set() Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/head507d.c | 13 ++- drivers/gpu/drm/nouveau/dispnv50/head827d.c | 14 ++- drivers/gpu/drm/nouveau/dispnv50/head907d.c | 18 ++- drivers/gpu/drm/nouveau/dispnv50/headc37d.c | 20 ++-- drivers/gpu/drm/nouveau/dispnv50/headc57d.c | 19 ++-- .../drm/nouveau/include/nvhw/class/cl827d.h | 106 ++++++++++++++++++ 6 files changed, 162 insertions(+), 28 deletions(-) create mode 100644 drivers/gpu/drm/nouveau/include/nvhw/class/cl827d.h diff --git a/drivers/gpu/drm/nouveau/dispnv50/head507d.c b/drivers/gpu/drm/nouveau/dispnv50/head507d.c index a4759641931f..f46603cc6f01 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head507d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head507d.c @@ -270,8 +270,13 @@ head507d_olut_set(struct nv50_head *head, struct nv50_head_atom *asyh) if ((ret = PUSH_WAIT(push, 3))) return ret; - PUSH_NVSQ(push, NV507D, 0x0840 + (i * 0x400), 0x80000000 | asyh->olut.mode << 30, - 0x0844 + (i * 0x400), asyh->olut.offset >> 8); + PUSH_MTHD(push, NV507D, HEAD_SET_BASE_LUT_LO(i), + NVDEF(NV507D, HEAD_SET_BASE_LUT_LO, ENABLE, ENABLE) | + NVVAL(NV507D, HEAD_SET_BASE_LUT_LO, MODE, asyh->olut.mode) | + NVVAL(NV507D, HEAD_SET_BASE_LUT_LO, ORIGIN, 0), + + HEAD_SET_BASE_LUT_HI(i), + NVVAL(NV507D, HEAD_SET_BASE_LUT_HI, ORIGIN, asyh->olut.offset >> 8)); return 0; } @@ -299,9 +304,9 @@ head507d_olut(struct nv50_head *head, struct nv50_head_atom *asyh, int size) return false; if (asyh->base.cpp == 1) - asyh->olut.mode = 0; + asyh->olut.mode = NV507D_HEAD_SET_BASE_LUT_LO_MODE_LORES; else - asyh->olut.mode = 1; + asyh->olut.mode = NV507D_HEAD_SET_BASE_LUT_LO_MODE_HIRES; asyh->olut.load = head507d_olut_load; return true; diff --git a/drivers/gpu/drm/nouveau/dispnv50/head827d.c b/drivers/gpu/drm/nouveau/dispnv50/head827d.c index 66bacb4bb712..01a8887f4bbe 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head827d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head827d.c @@ -24,6 +24,8 @@ #include +#include + static int head827d_curs_clr(struct nv50_head *head) { @@ -104,9 +106,15 @@ head827d_olut_set(struct nv50_head *head, struct nv50_head_atom *asyh) if ((ret = PUSH_WAIT(push, 5))) return ret; - PUSH_NVSQ(push, NV827D, 0x0840 + (i * 0x400), 0x80000000 | asyh->olut.mode << 30, - 0x0844 + (i * 0x400), asyh->olut.offset >> 8); - PUSH_NVSQ(push, NV827D, 0x085c + (i * 0x400), asyh->olut.handle); + PUSH_MTHD(push, NV827D, HEAD_SET_BASE_LUT_LO(i), + NVDEF(NV827D, HEAD_SET_BASE_LUT_LO, ENABLE, ENABLE) | + NVVAL(NV827D, HEAD_SET_BASE_LUT_LO, MODE, asyh->olut.mode) | + NVVAL(NV827D, HEAD_SET_BASE_LUT_LO, ORIGIN, 0), + + HEAD_SET_BASE_LUT_HI(i), + NVVAL(NV827D, HEAD_SET_BASE_LUT_HI, ORIGIN, asyh->olut.offset >> 8)); + + PUSH_MTHD(push, NV827D, HEAD_SET_CONTEXT_DMA_LUT(i), asyh->olut.handle); return 0; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/head907d.c b/drivers/gpu/drm/nouveau/dispnv50/head907d.c index 9a0a1ceb5432..69aa24bc7678 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head907d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head907d.c @@ -235,9 +235,15 @@ head907d_olut_set(struct nv50_head *head, struct nv50_head_atom *asyh) if ((ret = PUSH_WAIT(push, 5))) return ret; - PUSH_NVSQ(push, NV907D, 0x0448 + (i * 0x300), 0x80000000 | asyh->olut.mode << 24, - 0x044c + (i * 0x300), asyh->olut.offset >> 8); - PUSH_NVSQ(push, NV907D, 0x045c + (i * 0x300), asyh->olut.handle); + PUSH_MTHD(push, NV907D, HEAD_SET_OUTPUT_LUT_LO(i), + NVDEF(NV907D, HEAD_SET_OUTPUT_LUT_LO, ENABLE, ENABLE) | + NVVAL(NV907D, HEAD_SET_OUTPUT_LUT_LO, MODE, asyh->olut.mode) | + NVDEF(NV907D, HEAD_SET_OUTPUT_LUT_LO, NEVER_YIELD_TO_BASE, DISABLE), + + HEAD_SET_OUTPUT_LUT_HI(i), + NVVAL(NV907D, HEAD_SET_OUTPUT_LUT_HI, ORIGIN, asyh->olut.offset >> 8)); + + PUSH_MTHD(push, NV907D, HEAD_SET_CONTEXT_DMA_LUT(i), asyh->olut.handle); return 0; } @@ -264,7 +270,11 @@ head907d_olut(struct nv50_head *head, struct nv50_head_atom *asyh, int size) if (size != 256 && size != 1024) return false; - asyh->olut.mode = size == 1024 ? 4 : 7; + if (size == 1024) + asyh->olut.mode = NV907D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE; + else + asyh->olut.mode = NV907D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE; + asyh->olut.load = head907d_olut_load; return true; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/headc37d.c b/drivers/gpu/drm/nouveau/dispnv50/headc37d.c index e397ababa3e7..eb81ed1e0707 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/headc37d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/headc37d.c @@ -157,11 +157,13 @@ headc37d_olut_set(struct nv50_head *head, struct nv50_head_atom *asyh) if ((ret = PUSH_WAIT(push, 4))) return ret; - PUSH_NVSQ(push, NVC37D, 0x20a4 + (i * 0x400), asyh->olut.output_mode << 8 | - asyh->olut.range << 4 | - asyh->olut.size, - 0x20a8 + (i * 0x400), asyh->olut.offset >> 8, - 0x20ac + (i * 0x400), asyh->olut.handle); + PUSH_MTHD(push, NVC37D, HEAD_SET_CONTROL_OUTPUT_LUT(i), + NVVAL(NVC37D, HEAD_SET_CONTROL_OUTPUT_LUT, SIZE, asyh->olut.size) | + NVVAL(NVC37D, HEAD_SET_CONTROL_OUTPUT_LUT, RANGE, asyh->olut.range) | + NVVAL(NVC37D, HEAD_SET_CONTROL_OUTPUT_LUT, OUTPUT_MODE, asyh->olut.output_mode), + + HEAD_SET_OFFSET_OUTPUT_LUT(i), asyh->olut.offset >> 8, + HEAD_SET_CONTEXT_DMA_OUTPUT_LUT(i), asyh->olut.handle); return 0; } @@ -171,10 +173,10 @@ headc37d_olut(struct nv50_head *head, struct nv50_head_atom *asyh, int size) if (size != 256 && size != 1024) return false; - asyh->olut.mode = 2; - asyh->olut.size = size == 1024 ? 2 : 0; - asyh->olut.range = 0; - asyh->olut.output_mode = 1; + asyh->olut.size = size == 1024 ? NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_SIZE_SIZE_1025 : + NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_SIZE_SIZE_257; + asyh->olut.range = NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_RANGE_UNITY; + asyh->olut.output_mode = NVC37D_HEAD_SET_CONTROL_OUTPUT_LUT_OUTPUT_MODE_INTERPOLATE; asyh->olut.load = head907d_olut_load; return true; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/headc57d.c b/drivers/gpu/drm/nouveau/dispnv50/headc57d.c index 9cfaf62341b0..9cd4781a52ed 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/headc57d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/headc57d.c @@ -99,12 +99,15 @@ headc57d_olut_set(struct nv50_head *head, struct nv50_head_atom *asyh) if ((ret = PUSH_WAIT(push, 5))) return ret; - PUSH_NVSQ(push, NVC57D, 0x2280 + (i * 0x400), asyh->olut.size << 8 | - asyh->olut.mode << 2 | - asyh->olut.output_mode, - 0x2284 + (i * 0x400), 0xffffffff, - 0x2288 + (i * 0x400), asyh->olut.handle, - 0x228c + (i * 0x400), asyh->olut.offset >> 8); + PUSH_MTHD(push, NVC57D, HEAD_SET_OLUT_CONTROL(i), + NVVAL(NVC57D, HEAD_SET_OLUT_CONTROL, INTERPOLATE, asyh->olut.output_mode) | + NVDEF(NVC57D, HEAD_SET_OLUT_CONTROL, MIRROR, DISABLE) | + NVVAL(NVC57D, HEAD_SET_OLUT_CONTROL, MODE, asyh->olut.mode) | + NVVAL(NVC57D, HEAD_SET_OLUT_CONTROL, SIZE, asyh->olut.size), + + HEAD_SET_OLUT_FP_NORM_SCALE(i), 0xffffffff, + HEAD_SET_CONTEXT_DMA_OLUT(i), asyh->olut.handle, + HEAD_SET_OFFSET_OLUT(i), asyh->olut.offset >> 8); return 0; } @@ -167,9 +170,9 @@ headc57d_olut(struct nv50_head *head, struct nv50_head_atom *asyh, int size) if (size != 0 && size != 256 && size != 1024) return false; - asyh->olut.mode = 2; /* DIRECT10 */ + asyh->olut.mode = NVC57D_HEAD_SET_OLUT_CONTROL_MODE_DIRECT10; asyh->olut.size = 4 /* VSS header. */ + 1024 + 1 /* Entries. */; - asyh->olut.output_mode = 1; /* INTERPOLATE_ENABLE. */ + asyh->olut.output_mode = NVC57D_HEAD_SET_OLUT_CONTROL_INTERPOLATE_ENABLE; if (size == 256) asyh->olut.load = headc57d_olut_load_8; else diff --git a/drivers/gpu/drm/nouveau/include/nvhw/class/cl827d.h b/drivers/gpu/drm/nouveau/include/nvhw/class/cl827d.h new file mode 100644 index 000000000000..5da5d5579dab --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvhw/class/cl827d.h @@ -0,0 +1,106 @@ +/* + * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl827d_h_ +#define _cl827d_h_ + +// class methods +#define NV827D_HEAD_SET_BASE_LUT_LO(a) (0x00000840 + (a)*0x00000400) +#define NV827D_HEAD_SET_BASE_LUT_LO_ENABLE 31:31 +#define NV827D_HEAD_SET_BASE_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV827D_HEAD_SET_BASE_LUT_LO_ENABLE_ENABLE (0x00000001) +#define NV827D_HEAD_SET_BASE_LUT_LO_MODE 30:30 +#define NV827D_HEAD_SET_BASE_LUT_LO_MODE_LORES (0x00000000) +#define NV827D_HEAD_SET_BASE_LUT_LO_MODE_HIRES (0x00000001) +#define NV827D_HEAD_SET_BASE_LUT_LO_ORIGIN 7:2 +#define NV827D_HEAD_SET_BASE_LUT_HI(a) (0x00000844 + (a)*0x00000400) +#define NV827D_HEAD_SET_BASE_LUT_HI_ORIGIN 31:0 +#define NV827D_HEAD_SET_CONTEXT_DMA_LUT(a) (0x0000085C + (a)*0x00000400) +#define NV827D_HEAD_SET_CONTEXT_DMA_LUT_HANDLE 31:0 +#define NV827D_HEAD_SET_OFFSET(a,b) (0x00000860 + (a)*0x00000400 + (b)*0x00000004) +#define NV827D_HEAD_SET_OFFSET_ORIGIN 31:0 +#define NV827D_HEAD_SET_SIZE(a) (0x00000868 + (a)*0x00000400) +#define NV827D_HEAD_SET_SIZE_WIDTH 14:0 +#define NV827D_HEAD_SET_SIZE_HEIGHT 30:16 +#define NV827D_HEAD_SET_STORAGE(a) (0x0000086C + (a)*0x00000400) +#define NV827D_HEAD_SET_STORAGE_BLOCK_HEIGHT 3:0 +#define NV827D_HEAD_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB (0x00000000) +#define NV827D_HEAD_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS (0x00000001) +#define NV827D_HEAD_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS (0x00000002) +#define NV827D_HEAD_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003) +#define NV827D_HEAD_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NV827D_HEAD_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NV827D_HEAD_SET_STORAGE_PITCH 17:8 +#define NV827D_HEAD_SET_STORAGE_MEMORY_LAYOUT 20:20 +#define NV827D_HEAD_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NV827D_HEAD_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001) +#define NV827D_HEAD_SET_PARAMS(a) (0x00000870 + (a)*0x00000400) +#define NV827D_HEAD_SET_PARAMS_FORMAT 15:8 +#define NV827D_HEAD_SET_PARAMS_FORMAT_I8 (0x0000001E) +#define NV827D_HEAD_SET_PARAMS_FORMAT_VOID16 (0x0000001F) +#define NV827D_HEAD_SET_PARAMS_FORMAT_VOID32 (0x0000002E) +#define NV827D_HEAD_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA) +#define NV827D_HEAD_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF) +#define NV827D_HEAD_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1) +#define NV827D_HEAD_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5) +#define NV827D_HEAD_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8) +#define NV827D_HEAD_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9) +#define NV827D_HEAD_SET_PARAMS_SUPER_SAMPLE 1:0 +#define NV827D_HEAD_SET_PARAMS_SUPER_SAMPLE_X1_AA (0x00000000) +#define NV827D_HEAD_SET_PARAMS_SUPER_SAMPLE_X4_AA (0x00000002) +#define NV827D_HEAD_SET_PARAMS_GAMMA 2:2 +#define NV827D_HEAD_SET_PARAMS_GAMMA_LINEAR (0x00000000) +#define NV827D_HEAD_SET_PARAMS_GAMMA_SRGB (0x00000001) +#define NV827D_HEAD_SET_PARAMS_RESERVED0 22:16 +#define NV827D_HEAD_SET_PARAMS_RESERVED1 24:24 +#define NV827D_HEAD_SET_CONTEXT_DMAS_ISO(a,b) (0x00000874 + (a)*0x00000400 + (b)*0x00000004) +#define NV827D_HEAD_SET_CONTEXT_DMAS_ISO_HANDLE 31:0 +#define NV827D_HEAD_SET_CONTROL_CURSOR(a) (0x00000880 + (a)*0x00000400) +#define NV827D_HEAD_SET_CONTROL_CURSOR_ENABLE 31:31 +#define NV827D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE (0x00000000) +#define NV827D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE (0x00000001) +#define NV827D_HEAD_SET_CONTROL_CURSOR_FORMAT 25:24 +#define NV827D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5 (0x00000000) +#define NV827D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8 (0x00000001) +#define NV827D_HEAD_SET_CONTROL_CURSOR_SIZE 26:26 +#define NV827D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32 (0x00000000) +#define NV827D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64 (0x00000001) +#define NV827D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X 13:8 +#define NV827D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y 21:16 +#define NV827D_HEAD_SET_CONTROL_CURSOR_COMPOSITION 29:28 +#define NV827D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_ALPHA_BLEND (0x00000000) +#define NV827D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_PREMULT_ALPHA_BLEND (0x00000001) +#define NV827D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_XOR (0x00000002) +#define NV827D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER 5:4 +#define NV827D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_NONE (0x00000000) +#define NV827D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_SUBHEAD0 (0x00000001) +#define NV827D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_SUBHEAD1 (0x00000002) +#define NV827D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_BOTH (0x00000003) +#define NV827D_HEAD_SET_OFFSET_CURSOR(a) (0x00000884 + (a)*0x00000400) +#define NV827D_HEAD_SET_OFFSET_CURSOR_ORIGIN 31:0 +#define NV827D_HEAD_SET_CONTEXT_DMA_CURSOR(a) (0x0000089C + (a)*0x00000400) +#define NV827D_HEAD_SET_CONTEXT_DMA_CURSOR_HANDLE 31:0 +#define NV827D_HEAD_SET_VIEWPORT_POINT_IN(a,b) (0x000008C0 + (a)*0x00000400 + (b)*0x00000004) +#define NV827D_HEAD_SET_VIEWPORT_POINT_IN_X 14:0 +#define NV827D_HEAD_SET_VIEWPORT_POINT_IN_Y 30:16 +#endif // _cl827d_h From a66a096d784843f6d4c8e4c0b028524baf747f4c Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sun, 21 Jun 2020 11:47:21 +1000 Subject: [PATCH 122/145] drm/nouveau/kms/nv50-: use NVIDIA's headers for core head_olut_clr() Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/head507d.c | 3 ++- drivers/gpu/drm/nouveau/dispnv50/head827d.c | 6 ++++-- drivers/gpu/drm/nouveau/dispnv50/head907d.c | 6 ++++-- drivers/gpu/drm/nouveau/dispnv50/headc37d.c | 2 +- drivers/gpu/drm/nouveau/dispnv50/headc57d.c | 2 +- 5 files changed, 12 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/head507d.c b/drivers/gpu/drm/nouveau/dispnv50/head507d.c index f46603cc6f01..0bdacc9697f1 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head507d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head507d.c @@ -256,7 +256,8 @@ head507d_olut_clr(struct nv50_head *head) if ((ret = PUSH_WAIT(push, 2))) return ret; - PUSH_NVSQ(push, NV507D, 0x0840 + (i * 0x400), 0x00000000); + PUSH_MTHD(push, NV507D, HEAD_SET_BASE_LUT_LO(i), + NVDEF(NV507D, HEAD_SET_BASE_LUT_LO, ENABLE, DISABLE)); return 0; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/head827d.c b/drivers/gpu/drm/nouveau/dispnv50/head827d.c index 01a8887f4bbe..6cae23fb7b44 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head827d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head827d.c @@ -91,8 +91,10 @@ head827d_olut_clr(struct nv50_head *head) if ((ret = PUSH_WAIT(push, 4))) return ret; - PUSH_NVSQ(push, NV827D, 0x0840 + (i * 0x400), 0x00000000); - PUSH_NVSQ(push, NV827D, 0x085c + (i * 0x400), 0x00000000); + PUSH_MTHD(push, NV827D, HEAD_SET_BASE_LUT_LO(i), + NVDEF(NV827D, HEAD_SET_BASE_LUT_LO, ENABLE, DISABLE)); + + PUSH_MTHD(push, NV827D, HEAD_SET_CONTEXT_DMA_LUT(i), 0x00000000); return 0; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/head907d.c b/drivers/gpu/drm/nouveau/dispnv50/head907d.c index 69aa24bc7678..a54ac9e6d8a4 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head907d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head907d.c @@ -220,8 +220,10 @@ head907d_olut_clr(struct nv50_head *head) if ((ret = PUSH_WAIT(push, 4))) return ret; - PUSH_NVSQ(push, NV907D, 0x0448 + (i * 0x300), 0x00000000); - PUSH_NVSQ(push, NV907D, 0x045c + (i * 0x300), 0x00000000); + PUSH_MTHD(push, NV907D, HEAD_SET_OUTPUT_LUT_LO(i), + NVDEF(NV907D, HEAD_SET_OUTPUT_LUT_LO, ENABLE, DISABLE)); + + PUSH_MTHD(push, NV907D, HEAD_SET_CONTEXT_DMA_LUT(i), 0x00000000); return 0; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/headc37d.c b/drivers/gpu/drm/nouveau/dispnv50/headc37d.c index eb81ed1e0707..8898b65d0c41 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/headc37d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/headc37d.c @@ -143,7 +143,7 @@ headc37d_olut_clr(struct nv50_head *head) if ((ret = PUSH_WAIT(push, 2))) return ret; - PUSH_NVSQ(push, NVC37D, 0x20ac + (i * 0x400), 0x00000000); + PUSH_MTHD(push, NVC37D, HEAD_SET_CONTEXT_DMA_OUTPUT_LUT(i), 0x00000000); return 0; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/headc57d.c b/drivers/gpu/drm/nouveau/dispnv50/headc57d.c index 9cd4781a52ed..3c0001cd0a6a 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/headc57d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/headc57d.c @@ -85,7 +85,7 @@ headc57d_olut_clr(struct nv50_head *head) if ((ret = PUSH_WAIT(push, 2))) return ret; - PUSH_NVSQ(push, NVC57D, 0x2288 + (i * 0x400), 0x00000000); + PUSH_MTHD(push, NVC57D, HEAD_SET_CONTEXT_DMA_OLUT(i), 0x00000000); return 0; } From 1302634f793110fc272f9de4568164737c2539cd Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sun, 21 Jun 2020 11:59:09 +1000 Subject: [PATCH 123/145] drm/nouveau/kms/nv50-: use NVIDIA's headers for core head_core_set() Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/head507d.c | 42 ++++++++++++++------- drivers/gpu/drm/nouveau/dispnv50/head827d.c | 33 +++++++++++----- drivers/gpu/drm/nouveau/dispnv50/head907d.c | 33 +++++++++++----- 3 files changed, 76 insertions(+), 32 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/head507d.c b/drivers/gpu/drm/nouveau/dispnv50/head507d.c index 0bdacc9697f1..2cc9918c4540 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head507d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head507d.c @@ -194,16 +194,30 @@ head507d_core_set(struct nv50_head *head, struct nv50_head_atom *asyh) if ((ret = PUSH_WAIT(push, 9))) return ret; - PUSH_NVSQ(push, NV507D, 0x0860 + (i * 0x400), asyh->core.offset >> 8); - PUSH_NVSQ(push, NV507D, 0x0868 + (i * 0x400), asyh->core.h << 16 | asyh->core.w, - 0x086c + (i * 0x400), asyh->core.layout << 20 | - (asyh->core.pitch >> 8) << 8 | - asyh->core.blocks << 8 | - asyh->core.blockh, - 0x0870 + (i * 0x400), asyh->core.kind << 16 | - asyh->core.format << 8, - 0x0874 + (i * 0x400), asyh->core.handle); - PUSH_NVSQ(push, NV507D, 0x08c0 + (i * 0x400), asyh->core.y << 16 | asyh->core.x); + PUSH_MTHD(push, NV507D, HEAD_SET_OFFSET(i, 0), + NVVAL(NV507D, HEAD_SET_OFFSET, ORIGIN, asyh->core.offset >> 8)); + + PUSH_MTHD(push, NV507D, HEAD_SET_SIZE(i), + NVVAL(NV507D, HEAD_SET_SIZE, WIDTH, asyh->core.w) | + NVVAL(NV507D, HEAD_SET_SIZE, HEIGHT, asyh->core.h), + + HEAD_SET_STORAGE(i), + NVVAL(NV507D, HEAD_SET_STORAGE, BLOCK_HEIGHT, asyh->core.blockh) | + NVVAL(NV507D, HEAD_SET_STORAGE, PITCH, asyh->core.pitch >> 8) | + NVVAL(NV507D, HEAD_SET_STORAGE, PITCH, asyh->core.blocks) | + NVVAL(NV507D, HEAD_SET_STORAGE, MEMORY_LAYOUT, asyh->core.layout), + + HEAD_SET_PARAMS(i), + NVVAL(NV507D, HEAD_SET_PARAMS, FORMAT, asyh->core.format) | + NVVAL(NV507D, HEAD_SET_PARAMS, KIND, asyh->core.kind) | + NVDEF(NV507D, HEAD_SET_PARAMS, PART_STRIDE, PARTSTRIDE_256), + + HEAD_SET_CONTEXT_DMA_ISO(i), + NVVAL(NV507D, HEAD_SET_CONTEXT_DMA_ISO, HANDLE, asyh->core.handle)); + + PUSH_MTHD(push, NV507D, HEAD_SET_VIEWPORT_POINT_IN(i, 0), + NVVAL(NV507D, HEAD_SET_VIEWPORT_POINT_IN, X, asyh->core.x) | + NVVAL(NV507D, HEAD_SET_VIEWPORT_POINT_IN, Y, asyh->core.y)); /* EVO will complain with INVALID_STATE if we have an * active cursor and (re)specify HeadSetContextDmaIso @@ -238,10 +252,10 @@ head507d_core_calc(struct nv50_head *head, struct nv50_head_atom *asyh) } asyh->core.handle = disp->core->chan.vram.handle; asyh->core.offset = 0; - asyh->core.format = 0xcf; - asyh->core.kind = 0; - asyh->core.layout = 1; - asyh->core.blockh = 0; + asyh->core.format = NV507D_HEAD_SET_PARAMS_FORMAT_A8R8G8B8; + asyh->core.kind = NV507D_HEAD_SET_PARAMS_KIND_KIND_PITCH; + asyh->core.layout = NV507D_HEAD_SET_STORAGE_MEMORY_LAYOUT_PITCH; + asyh->core.blockh = NV507D_HEAD_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB; asyh->core.blocks = 0; asyh->core.pitch = ALIGN(asyh->core.w, 64) * 4; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/head827d.c b/drivers/gpu/drm/nouveau/dispnv50/head827d.c index 6cae23fb7b44..1b68c9b82f5a 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head827d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head827d.c @@ -69,15 +69,30 @@ head827d_core_set(struct nv50_head *head, struct nv50_head_atom *asyh) if ((ret = PUSH_WAIT(push, 9))) return ret; - PUSH_NVSQ(push, NV827D, 0x0860 + (i * 0x400), asyh->core.offset >> 8); - PUSH_NVSQ(push, NV827D, 0x0868 + (i * 0x400), asyh->core.h << 16 | asyh->core.w, - 0x086c + (i * 0x400), asyh->core.layout << 20 | - (asyh->core.pitch >> 8) << 8 | - asyh->core.blocks << 8 | - asyh->core.blockh, - 0x0870 + (i * 0x400), asyh->core.format << 8, - 0x0874 + (i * 0x400), asyh->core.handle); - PUSH_NVSQ(push, NV827D, 0x08c0 + (i * 0x400), asyh->core.y << 16 | asyh->core.x); + PUSH_MTHD(push, NV827D, HEAD_SET_OFFSET(i, 0), + NVVAL(NV827D, HEAD_SET_OFFSET, ORIGIN, asyh->core.offset >> 8)); + + PUSH_MTHD(push, NV827D, HEAD_SET_SIZE(i), + NVVAL(NV827D, HEAD_SET_SIZE, WIDTH, asyh->core.w) | + NVVAL(NV827D, HEAD_SET_SIZE, HEIGHT, asyh->core.h), + + HEAD_SET_STORAGE(i), + NVVAL(NV827D, HEAD_SET_STORAGE, BLOCK_HEIGHT, asyh->core.blockh) | + NVVAL(NV827D, HEAD_SET_STORAGE, PITCH, asyh->core.pitch >> 8) | + NVVAL(NV827D, HEAD_SET_STORAGE, PITCH, asyh->core.blocks) | + NVVAL(NV827D, HEAD_SET_STORAGE, MEMORY_LAYOUT, asyh->core.layout), + + HEAD_SET_PARAMS(i), + NVVAL(NV827D, HEAD_SET_PARAMS, FORMAT, asyh->core.format) | + NVDEF(NV827D, HEAD_SET_PARAMS, SUPER_SAMPLE, X1_AA) | + NVDEF(NV827D, HEAD_SET_PARAMS, GAMMA, LINEAR), + + HEAD_SET_CONTEXT_DMAS_ISO(i, 0), + NVVAL(NV827D, HEAD_SET_CONTEXT_DMAS_ISO, HANDLE, asyh->core.handle)); + + PUSH_MTHD(push, NV827D, HEAD_SET_VIEWPORT_POINT_IN(i, 0), + NVVAL(NV827D, HEAD_SET_VIEWPORT_POINT_IN, X, asyh->core.x) | + NVVAL(NV827D, HEAD_SET_VIEWPORT_POINT_IN, Y, asyh->core.y)); return 0; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/head907d.c b/drivers/gpu/drm/nouveau/dispnv50/head907d.c index a54ac9e6d8a4..3b3b5af74993 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head907d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head907d.c @@ -198,15 +198,30 @@ head907d_core_set(struct nv50_head *head, struct nv50_head_atom *asyh) if ((ret = PUSH_WAIT(push, 9))) return ret; - PUSH_NVSQ(push, NV907D, 0x0460 + (i * 0x300), asyh->core.offset >> 8); - PUSH_NVSQ(push, NV907D, 0x0468 + (i * 0x300), asyh->core.h << 16 | asyh->core.w, - 0x046c + (i * 0x300), asyh->core.layout << 24 | - (asyh->core.pitch >> 8) << 8 | - asyh->core.blocks << 8 | - asyh->core.blockh, - 0x0470 + (i * 0x300), asyh->core.format << 8, - 0x0474 + (i * 0x300), asyh->core.handle); - PUSH_NVSQ(push, NV907D, 0x04b0 + (i * 0x300), asyh->core.y << 16 | asyh->core.x); + PUSH_MTHD(push, NV907D, HEAD_SET_OFFSET(i), + NVVAL(NV907D, HEAD_SET_OFFSET, ORIGIN, asyh->core.offset >> 8)); + + PUSH_MTHD(push, NV907D, HEAD_SET_SIZE(i), + NVVAL(NV907D, HEAD_SET_SIZE, WIDTH, asyh->core.w) | + NVVAL(NV907D, HEAD_SET_SIZE, HEIGHT, asyh->core.h), + + HEAD_SET_STORAGE(i), + NVVAL(NV907D, HEAD_SET_STORAGE, BLOCK_HEIGHT, asyh->core.blockh) | + NVVAL(NV907D, HEAD_SET_STORAGE, PITCH, asyh->core.pitch >> 8) | + NVVAL(NV907D, HEAD_SET_STORAGE, PITCH, asyh->core.blocks) | + NVVAL(NV907D, HEAD_SET_STORAGE, MEMORY_LAYOUT, asyh->core.layout), + + HEAD_SET_PARAMS(i), + NVVAL(NV907D, HEAD_SET_PARAMS, FORMAT, asyh->core.format) | + NVDEF(NV907D, HEAD_SET_PARAMS, SUPER_SAMPLE, X1_AA) | + NVDEF(NV907D, HEAD_SET_PARAMS, GAMMA, LINEAR), + + HEAD_SET_CONTEXT_DMAS_ISO(i), + NVVAL(NV907D, HEAD_SET_CONTEXT_DMAS_ISO, HANDLE, asyh->core.handle)); + + PUSH_MTHD(push, NV907D, HEAD_SET_VIEWPORT_POINT_IN(i), + NVVAL(NV907D, HEAD_SET_VIEWPORT_POINT_IN, X, asyh->core.x) | + NVVAL(NV907D, HEAD_SET_VIEWPORT_POINT_IN, Y, asyh->core.y)); return 0; } From dbb23f544e9c0dd364fd5e3a027c8aebe9dae75e Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sun, 21 Jun 2020 11:59:54 +1000 Subject: [PATCH 124/145] drm/nouveau/kms/nv50-: use NVIDIA's headers for core head_core_clr() Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/head507d.c | 2 +- drivers/gpu/drm/nouveau/dispnv50/head907d.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/head507d.c b/drivers/gpu/drm/nouveau/dispnv50/head507d.c index 2cc9918c4540..dc50032711b5 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head507d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head507d.c @@ -180,7 +180,7 @@ head507d_core_clr(struct nv50_head *head) if ((ret = PUSH_WAIT(push, 2))) return ret; - PUSH_NVSQ(push, NV507D, 0x0874 + (i * 0x400), 0x00000000); + PUSH_MTHD(push, NV507D, HEAD_SET_CONTEXT_DMA_ISO(i), 0x00000000); return 0; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/head907d.c b/drivers/gpu/drm/nouveau/dispnv50/head907d.c index 3b3b5af74993..f5e669deed62 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head907d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head907d.c @@ -184,7 +184,7 @@ head907d_core_clr(struct nv50_head *head) if ((ret = PUSH_WAIT(push, 2))) return ret; - PUSH_NVSQ(push, NV907D, 0x0474 + (i * 0x300), 0x00000000); + PUSH_MTHD(push, NV907D, HEAD_SET_CONTEXT_DMAS_ISO(i), 0x00000000); return 0; } From ed0b86a90bf91d0c41f6b373befd2ce98658b49e Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sun, 21 Jun 2020 12:10:42 +1000 Subject: [PATCH 125/145] drm/nouveau/kms/nv50-: use NVIDIA's headers for core head_curs_set() Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/head507d.c | 20 +++++++++++------ drivers/gpu/drm/nouveau/dispnv50/head827d.c | 17 ++++++++++----- drivers/gpu/drm/nouveau/dispnv50/head907d.c | 16 +++++++++----- drivers/gpu/drm/nouveau/dispnv50/head917d.c | 10 +++++---- drivers/gpu/drm/nouveau/dispnv50/headc37d.c | 24 +++++++++++++++------ 5 files changed, 60 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/head507d.c b/drivers/gpu/drm/nouveau/dispnv50/head507d.c index dc50032711b5..473119804b5b 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head507d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head507d.c @@ -137,10 +137,16 @@ head507d_curs_set(struct nv50_head *head, struct nv50_head_atom *asyh) if ((ret = PUSH_WAIT(push, 3))) return ret; - PUSH_NVSQ(push, NV507D, 0x0880 + (i * 0x400), 0x80000000 | - asyh->curs.layout << 26 | - asyh->curs.format << 24, - 0x0884 + (i * 0x400), asyh->curs.offset >> 8); + PUSH_MTHD(push, NV507D, HEAD_SET_CONTROL_CURSOR(i), + NVDEF(NV507D, HEAD_SET_CONTROL_CURSOR, ENABLE, ENABLE) | + NVVAL(NV507D, HEAD_SET_CONTROL_CURSOR, FORMAT, asyh->curs.format) | + NVVAL(NV507D, HEAD_SET_CONTROL_CURSOR, SIZE, asyh->curs.layout) | + NVVAL(NV507D, HEAD_SET_CONTROL_CURSOR, HOT_SPOT_X, 0) | + NVVAL(NV507D, HEAD_SET_CONTROL_CURSOR, HOT_SPOT_Y, 0) | + NVDEF(NV507D, HEAD_SET_CONTROL_CURSOR, COMPOSITION, ALPHA_BLEND) | + NVDEF(NV507D, HEAD_SET_CONTROL_CURSOR, SUB_OWNER, NONE), + + HEAD_SET_OFFSET_CURSOR(i), asyh->curs.offset >> 8); return 0; } @@ -149,7 +155,7 @@ head507d_curs_format(struct nv50_head *head, struct nv50_wndw_atom *asyw, struct nv50_head_atom *asyh) { switch (asyw->image.format) { - case 0xcf: asyh->curs.format = 1; break; + case 0xcf: asyh->curs.format = NV507D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8; break; default: WARN_ON(1); return -EINVAL; @@ -162,8 +168,8 @@ head507d_curs_layout(struct nv50_head *head, struct nv50_wndw_atom *asyw, struct nv50_head_atom *asyh) { switch (asyw->image.w) { - case 32: asyh->curs.layout = 0; break; - case 64: asyh->curs.layout = 1; break; + case 32: asyh->curs.layout = NV507D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32; break; + case 64: asyh->curs.layout = NV507D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64; break; default: return -EINVAL; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/head827d.c b/drivers/gpu/drm/nouveau/dispnv50/head827d.c index 1b68c9b82f5a..0dc04774d3d2 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head827d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head827d.c @@ -51,11 +51,18 @@ head827d_curs_set(struct nv50_head *head, struct nv50_head_atom *asyh) if ((ret = PUSH_WAIT(push, 5))) return ret; - PUSH_NVSQ(push, NV827D, 0x0880 + (i * 0x400), 0x80000000 | - asyh->curs.layout << 26 | - asyh->curs.format << 24, - 0x0884 + (i * 0x400), asyh->curs.offset >> 8); - PUSH_NVSQ(push, NV827D, 0x089c + (i * 0x400), asyh->curs.handle); + PUSH_MTHD(push, NV827D, HEAD_SET_CONTROL_CURSOR(i), + NVDEF(NV827D, HEAD_SET_CONTROL_CURSOR, ENABLE, ENABLE) | + NVVAL(NV827D, HEAD_SET_CONTROL_CURSOR, FORMAT, asyh->curs.format) | + NVVAL(NV827D, HEAD_SET_CONTROL_CURSOR, SIZE, asyh->curs.layout) | + NVVAL(NV827D, HEAD_SET_CONTROL_CURSOR, HOT_SPOT_X, 0) | + NVVAL(NV827D, HEAD_SET_CONTROL_CURSOR, HOT_SPOT_Y, 0) | + NVDEF(NV827D, HEAD_SET_CONTROL_CURSOR, COMPOSITION, ALPHA_BLEND) | + NVDEF(NV827D, HEAD_SET_CONTROL_CURSOR, SUB_OWNER, NONE), + + HEAD_SET_OFFSET_CURSOR(i), asyh->curs.offset >> 8); + + PUSH_MTHD(push, NV827D, HEAD_SET_CONTEXT_DMA_CURSOR(i), asyh->curs.handle); return 0; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/head907d.c b/drivers/gpu/drm/nouveau/dispnv50/head907d.c index f5e669deed62..aca4da6c2eea 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head907d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head907d.c @@ -166,11 +166,17 @@ head907d_curs_set(struct nv50_head *head, struct nv50_head_atom *asyh) if ((ret = PUSH_WAIT(push, 5))) return ret; - PUSH_NVSQ(push, NV907D, 0x0480 + (i * 0x300), 0x80000000 | - asyh->curs.layout << 26 | - asyh->curs.format << 24, - 0x0484 + (i * 0x300), asyh->curs.offset >> 8); - PUSH_NVSQ(push, NV907D, 0x048c + (i * 0x300), asyh->curs.handle); + PUSH_MTHD(push, NV907D, HEAD_SET_CONTROL_CURSOR(i), + NVDEF(NV907D, HEAD_SET_CONTROL_CURSOR, ENABLE, ENABLE) | + NVVAL(NV907D, HEAD_SET_CONTROL_CURSOR, FORMAT, asyh->curs.format) | + NVVAL(NV907D, HEAD_SET_CONTROL_CURSOR, SIZE, asyh->curs.layout) | + NVVAL(NV907D, HEAD_SET_CONTROL_CURSOR, HOT_SPOT_X, 0) | + NVVAL(NV907D, HEAD_SET_CONTROL_CURSOR, HOT_SPOT_Y, 0) | + NVDEF(NV907D, HEAD_SET_CONTROL_CURSOR, COMPOSITION, ALPHA_BLEND), + + HEAD_SET_OFFSET_CURSOR(i), asyh->curs.offset >> 8); + + PUSH_MTHD(push, NV907D, HEAD_SET_CONTEXT_DMA_CURSOR(i), asyh->curs.handle); return 0; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/head917d.c b/drivers/gpu/drm/nouveau/dispnv50/head917d.c index 07d12f3ba333..e70628b8d733 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head917d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head917d.c @@ -24,6 +24,8 @@ #include +#include + static int head917d_dither(struct nv50_head *head, struct nv50_head_atom *asyh) { @@ -73,10 +75,10 @@ head917d_curs_layout(struct nv50_head *head, struct nv50_wndw_atom *asyw, struct nv50_head_atom *asyh) { switch (asyw->state.fb->width) { - case 32: asyh->curs.layout = 0; break; - case 64: asyh->curs.layout = 1; break; - case 128: asyh->curs.layout = 2; break; - case 256: asyh->curs.layout = 3; break; + case 32: asyh->curs.layout = NV917D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32; break; + case 64: asyh->curs.layout = NV917D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64; break; + case 128: asyh->curs.layout = NV917D_HEAD_SET_CONTROL_CURSOR_SIZE_W128_H128; break; + case 256: asyh->curs.layout = NV917D_HEAD_SET_CONTROL_CURSOR_SIZE_W256_H256; break; default: return -EINVAL; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/headc37d.c b/drivers/gpu/drm/nouveau/dispnv50/headc37d.c index 8898b65d0c41..a9ede937222d 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/headc37d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/headc37d.c @@ -116,12 +116,24 @@ headc37d_curs_set(struct nv50_head *head, struct nv50_head_atom *asyh) if ((ret = PUSH_WAIT(push, 7))) return ret; - PUSH_NVSQ(push, NVC37D, 0x209c + (i * 0x400), 0x80000000 | - asyh->curs.layout << 8 | - asyh->curs.format << 0, - 0x20a0 + (i * 0x400), 0x000072ff); - PUSH_NVSQ(push, NVC37D, 0x2088 + (i * 0x400), asyh->curs.handle); - PUSH_NVSQ(push, NVC37D, 0x2090 + (i * 0x400), asyh->curs.offset >> 8); + PUSH_MTHD(push, NVC37D, HEAD_SET_CONTROL_CURSOR(i), + NVDEF(NVC37D, HEAD_SET_CONTROL_CURSOR, ENABLE, ENABLE) | + NVVAL(NVC37D, HEAD_SET_CONTROL_CURSOR, FORMAT, asyh->curs.format) | + NVVAL(NVC37D, HEAD_SET_CONTROL_CURSOR, SIZE, asyh->curs.layout) | + NVVAL(NVC37D, HEAD_SET_CONTROL_CURSOR, HOT_SPOT_X, 0) | + NVVAL(NVC37D, HEAD_SET_CONTROL_CURSOR, HOT_SPOT_Y, 0) | + NVDEF(NVC37D, HEAD_SET_CONTROL_CURSOR, DE_GAMMA, NONE), + + HEAD_SET_CONTROL_CURSOR_COMPOSITION(i), + NVVAL(NVC37D, HEAD_SET_CONTROL_CURSOR_COMPOSITION, K1, 0xff) | + NVDEF(NVC37D, HEAD_SET_CONTROL_CURSOR_COMPOSITION, CURSOR_COLOR_FACTOR_SELECT, + K1) | + NVDEF(NVC37D, HEAD_SET_CONTROL_CURSOR_COMPOSITION, VIEWPORT_COLOR_FACTOR_SELECT, + NEG_K1_TIMES_SRC) | + NVDEF(NVC37D, HEAD_SET_CONTROL_CURSOR_COMPOSITION, MODE, BLEND)); + + PUSH_MTHD(push, NVC37D, HEAD_SET_CONTEXT_DMA_CURSOR(i, 0), asyh->curs.handle); + PUSH_MTHD(push, NVC37D, HEAD_SET_OFFSET_CURSOR(i, 0), asyh->curs.offset >> 8); return 0; } From 916722fce5a25a1ffefac616f8f0213de9ce0353 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sun, 21 Jun 2020 12:16:24 +1000 Subject: [PATCH 126/145] drm/nouveau/kms/nv50-: use NVIDIA's headers for core head_curs_clr() Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/head507d.c | 5 ++++- drivers/gpu/drm/nouveau/dispnv50/head827d.c | 8 ++++++-- drivers/gpu/drm/nouveau/dispnv50/head907d.c | 8 ++++++-- drivers/gpu/drm/nouveau/dispnv50/headc37d.c | 7 +++++-- 4 files changed, 21 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/head507d.c b/drivers/gpu/drm/nouveau/dispnv50/head507d.c index 473119804b5b..de6ab797e7fd 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head507d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head507d.c @@ -123,7 +123,10 @@ head507d_curs_clr(struct nv50_head *head) if ((ret = PUSH_WAIT(push, 2))) return ret; - PUSH_NVSQ(push, NV507D, 0x0880 + (i * 0x400), 0x05000000); + PUSH_MTHD(push, NV507D, HEAD_SET_CONTROL_CURSOR(i), + NVDEF(NV507D, HEAD_SET_CONTROL_CURSOR, ENABLE, DISABLE) | + NVDEF(NV507D, HEAD_SET_CONTROL_CURSOR, FORMAT, A8R8G8B8) | + NVDEF(NV507D, HEAD_SET_CONTROL_CURSOR, SIZE, W64_H64)); return 0; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/head827d.c b/drivers/gpu/drm/nouveau/dispnv50/head827d.c index 0dc04774d3d2..194d1771c481 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head827d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head827d.c @@ -36,8 +36,12 @@ head827d_curs_clr(struct nv50_head *head) if ((ret = PUSH_WAIT(push, 4))) return ret; - PUSH_NVSQ(push, NV827D, 0x0880 + (i * 0x400), 0x05000000); - PUSH_NVSQ(push, NV827D, 0x089c + (i * 0x400), 0x00000000); + PUSH_MTHD(push, NV827D, HEAD_SET_CONTROL_CURSOR(i), + NVDEF(NV827D, HEAD_SET_CONTROL_CURSOR, ENABLE, DISABLE) | + NVDEF(NV827D, HEAD_SET_CONTROL_CURSOR, FORMAT, A8R8G8B8) | + NVDEF(NV827D, HEAD_SET_CONTROL_CURSOR, SIZE, W64_H64)); + + PUSH_MTHD(push, NV827D, HEAD_SET_CONTEXT_DMA_CURSOR(i), 0x00000000); return 0; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/head907d.c b/drivers/gpu/drm/nouveau/dispnv50/head907d.c index aca4da6c2eea..3683d940f6cc 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head907d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head907d.c @@ -151,8 +151,12 @@ head907d_curs_clr(struct nv50_head *head) if ((ret = PUSH_WAIT(push, 4))) return ret; - PUSH_NVSQ(push, NV907D, 0x0480 + (i * 0x300), 0x05000000); - PUSH_NVSQ(push, NV907D, 0x048c + (i * 0x300), 0x00000000); + PUSH_MTHD(push, NV907D, HEAD_SET_CONTROL_CURSOR(i), + NVDEF(NV907D, HEAD_SET_CONTROL_CURSOR, ENABLE, DISABLE) | + NVDEF(NV907D, HEAD_SET_CONTROL_CURSOR, FORMAT, A8R8G8B8) | + NVDEF(NV907D, HEAD_SET_CONTROL_CURSOR, SIZE, W64_H64)); + + PUSH_MTHD(push, NV907D, HEAD_SET_CONTEXT_DMA_CURSOR(i), 0x00000000); return 0; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/headc37d.c b/drivers/gpu/drm/nouveau/dispnv50/headc37d.c index a9ede937222d..48b8b4dbd693 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/headc37d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/headc37d.c @@ -101,8 +101,11 @@ headc37d_curs_clr(struct nv50_head *head) if ((ret = PUSH_WAIT(push, 4))) return ret; - PUSH_NVSQ(push, NVC37D, 0x209c + (i * 0x400), 0x000000cf); - PUSH_NVSQ(push, NVC37D, 0x2088 + (i * 0x400), 0x00000000); + PUSH_MTHD(push, NVC37D, HEAD_SET_CONTROL_CURSOR(i), + NVDEF(NVC37D, HEAD_SET_CONTROL_CURSOR, ENABLE, DISABLE) | + NVDEF(NVC37D, HEAD_SET_CONTROL_CURSOR, FORMAT, A8R8G8B8)); + + PUSH_MTHD(push, NVC37D, HEAD_SET_CONTEXT_DMA_CURSOR(i, 0), 0x00000000); return 0; } From 2aa934ca04bc93e7cf5133cb44a751be13b9df9e Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sun, 21 Jun 2020 12:31:24 +1000 Subject: [PATCH 127/145] drm/nouveau/kms/nv50-: use NVIDIA's headers for core head_base() Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/head507d.c | 12 ++++++------ drivers/gpu/drm/nouveau/dispnv50/head907d.c | 12 ++++++------ drivers/gpu/drm/nouveau/dispnv50/head917d.c | 13 +++++++------ 3 files changed, 19 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/head507d.c b/drivers/gpu/drm/nouveau/dispnv50/head507d.c index de6ab797e7fd..aba913869966 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head507d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head507d.c @@ -95,21 +95,21 @@ head507d_base(struct nv50_head *head, struct nv50_head_atom *asyh) if (asyh->base.cpp) { switch (asyh->base.cpp) { - case 8: bounds |= 0x00000500; break; - case 4: bounds |= 0x00000300; break; - case 2: bounds |= 0x00000100; break; - case 1: bounds |= 0x00000000; break; + case 8: bounds |= NVDEF(NV507D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS, PIXEL_DEPTH, BPP_64); break; + case 4: bounds |= NVDEF(NV507D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS, PIXEL_DEPTH, BPP_32); break; + case 2: bounds |= NVDEF(NV507D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS, PIXEL_DEPTH, BPP_16); break; + case 1: bounds |= NVDEF(NV507D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS, PIXEL_DEPTH, BPP_8); break; default: WARN_ON(1); break; } - bounds |= 0x00000001; + bounds |= NVDEF(NV507D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS, USABLE, TRUE); } if ((ret = PUSH_WAIT(push, 2))) return ret; - PUSH_NVSQ(push, NV507D, 0x0900 + (i * 0x400), bounds); + PUSH_MTHD(push, NV507D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(i), bounds); return 0; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/head907d.c b/drivers/gpu/drm/nouveau/dispnv50/head907d.c index 3683d940f6cc..4dfa6da31753 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head907d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head907d.c @@ -123,21 +123,21 @@ head907d_base(struct nv50_head *head, struct nv50_head_atom *asyh) if (asyh->base.cpp) { switch (asyh->base.cpp) { - case 8: bounds |= 0x00000500; break; - case 4: bounds |= 0x00000300; break; - case 2: bounds |= 0x00000100; break; - case 1: bounds |= 0x00000000; break; + case 8: bounds |= NVDEF(NV907D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS, PIXEL_DEPTH, BPP_64); break; + case 4: bounds |= NVDEF(NV907D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS, PIXEL_DEPTH, BPP_32); break; + case 2: bounds |= NVDEF(NV907D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS, PIXEL_DEPTH, BPP_16); break; + case 1: bounds |= NVDEF(NV907D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS, PIXEL_DEPTH, BPP_8); break; default: WARN_ON(1); break; } - bounds |= 0x00000001; + bounds |= NVDEF(NV907D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS, USABLE, TRUE); } if ((ret = PUSH_WAIT(push, 2))) return ret; - PUSH_NVSQ(push, NV907D, 0x04d0 + (i * 0x300), bounds); + PUSH_MTHD(push, NV907D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(i), bounds); return 0; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/head917d.c b/drivers/gpu/drm/nouveau/dispnv50/head917d.c index e70628b8d733..026cfb44d597 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head917d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head917d.c @@ -52,21 +52,22 @@ head917d_base(struct nv50_head *head, struct nv50_head_atom *asyh) if (asyh->base.cpp) { switch (asyh->base.cpp) { - case 8: bounds |= 0x00000500; break; - case 4: bounds |= 0x00000300; break; - case 2: bounds |= 0x00000100; break; - case 1: bounds |= 0x00000000; break; + case 8: bounds |= NVDEF(NV917D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS, PIXEL_DEPTH, BPP_64); break; + case 4: bounds |= NVDEF(NV917D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS, PIXEL_DEPTH, BPP_32); break; + case 2: bounds |= NVDEF(NV917D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS, PIXEL_DEPTH, BPP_16); break; + case 1: bounds |= NVDEF(NV917D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS, PIXEL_DEPTH, BPP_8); break; default: WARN_ON(1); break; } - bounds |= 0x00020001; + bounds |= NVDEF(NV917D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS, USABLE, TRUE); + bounds |= NVDEF(NV917D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS, BASE_LUT, USAGE_1025); } if ((ret = PUSH_WAIT(push, 2))) return ret; - PUSH_NVSQ(push, NV917D, 0x04d0 + (i * 0x300), bounds); + PUSH_MTHD(push, NV917D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(i), bounds); return 0; } From 35cefc538be76348dcd04378cef626b7c76f156e Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sun, 21 Jun 2020 12:31:42 +1000 Subject: [PATCH 128/145] drm/nouveau/kms/nv50-: use NVIDIA's headers for core head_ovly() Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/head507d.c | 10 +++++----- drivers/gpu/drm/nouveau/dispnv50/head907d.c | 12 ++++++------ 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/head507d.c b/drivers/gpu/drm/nouveau/dispnv50/head507d.c index aba913869966..ed54c6548e1c 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head507d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head507d.c @@ -67,21 +67,21 @@ head507d_ovly(struct nv50_head *head, struct nv50_head_atom *asyh) if (asyh->ovly.cpp) { switch (asyh->ovly.cpp) { - case 4: bounds |= 0x00000300; break; - case 2: bounds |= 0x00000100; break; + case 4: bounds |= NVDEF(NV507D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS, PIXEL_DEPTH, BPP_32); break; + case 2: bounds |= NVDEF(NV507D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS, PIXEL_DEPTH, BPP_16); break; default: WARN_ON(1); break; } - bounds |= 0x00000001; + bounds |= NVDEF(NV507D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS, USABLE, TRUE); } else { - bounds |= 0x00000100; + bounds |= NVDEF(NV507D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS, PIXEL_DEPTH, BPP_16); } if ((ret = PUSH_WAIT(push, 2))) return ret; - PUSH_NVSQ(push, NV507D, 0x0904 + (i * 0x400), bounds); + PUSH_MTHD(push, NV507D, HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(i), bounds); return 0; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/head907d.c b/drivers/gpu/drm/nouveau/dispnv50/head907d.c index 4dfa6da31753..44b9693cebec 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head907d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head907d.c @@ -94,22 +94,22 @@ head907d_ovly(struct nv50_head *head, struct nv50_head_atom *asyh) if (asyh->ovly.cpp) { switch (asyh->ovly.cpp) { - case 8: bounds |= 0x00000500; break; - case 4: bounds |= 0x00000300; break; - case 2: bounds |= 0x00000100; break; + case 8: bounds |= NVDEF(NV907D, HEAD_SET_OVERLAY_USAGE_BOUNDS, PIXEL_DEPTH, BPP_64); break; + case 4: bounds |= NVDEF(NV907D, HEAD_SET_OVERLAY_USAGE_BOUNDS, PIXEL_DEPTH, BPP_32); break; + case 2: bounds |= NVDEF(NV907D, HEAD_SET_OVERLAY_USAGE_BOUNDS, PIXEL_DEPTH, BPP_16); break; default: WARN_ON(1); break; } - bounds |= 0x00000001; + bounds |= NVDEF(NV907D, HEAD_SET_OVERLAY_USAGE_BOUNDS, USABLE, TRUE); } else { - bounds |= 0x00000100; + bounds |= NVDEF(NV907D, HEAD_SET_OVERLAY_USAGE_BOUNDS, PIXEL_DEPTH, BPP_16); } if ((ret = PUSH_WAIT(push, 2))) return ret; - PUSH_NVSQ(push, NV907D, 0x04d4 + (i * 0x300), bounds); + PUSH_MTHD(push, NV907D, HEAD_SET_OVERLAY_USAGE_BOUNDS(i), bounds); return 0; } From f801efb127ad02e2cc6ddb1bf1e30bfe001fb4fe Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sun, 21 Jun 2020 12:35:48 +1000 Subject: [PATCH 129/145] drm/nouveau/kms/nv50-: use NVIDIA's headers for core head_dither() Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/head.c | 6 ++--- drivers/gpu/drm/nouveau/dispnv50/head507d.c | 8 ++++--- drivers/gpu/drm/nouveau/dispnv50/head907d.c | 8 ++++--- drivers/gpu/drm/nouveau/dispnv50/head917d.c | 8 ++++--- drivers/gpu/drm/nouveau/dispnv50/headc37d.c | 9 +++++--- drivers/gpu/drm/nouveau/nouveau_connector.h | 25 +++++++++++++++------ 6 files changed, 42 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/head.c b/drivers/gpu/drm/nouveau/dispnv50/head.c index 2d84eafd7b3e..841edfaf5b9d 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head.c @@ -106,9 +106,9 @@ nv50_head_atomic_check_dither(struct nv50_head_atom *armh, } } - asyh->dither.enable = mode; - asyh->dither.bits = mode >> 1; - asyh->dither.mode = mode >> 3; + asyh->dither.enable = NVVAL_GET(mode, NV507D, HEAD_SET_DITHER_CONTROL, ENABLE); + asyh->dither.bits = NVVAL_GET(mode, NV507D, HEAD_SET_DITHER_CONTROL, BITS); + asyh->dither.mode = NVVAL_GET(mode, NV507D, HEAD_SET_DITHER_CONTROL, MODE); asyh->set.dither = true; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/head507d.c b/drivers/gpu/drm/nouveau/dispnv50/head507d.c index ed54c6548e1c..be9b9fa27dd0 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head507d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head507d.c @@ -51,9 +51,11 @@ head507d_dither(struct nv50_head *head, struct nv50_head_atom *asyh) if ((ret = PUSH_WAIT(push, 2))) return ret; - PUSH_NVSQ(push, NV507D, 0x08a0 + (i * 0x400), asyh->dither.mode << 3 | - asyh->dither.bits << 1 | - asyh->dither.enable); + PUSH_MTHD(push, NV507D, HEAD_SET_DITHER_CONTROL(i), + NVVAL(NV507D, HEAD_SET_DITHER_CONTROL, ENABLE, asyh->dither.enable) | + NVVAL(NV507D, HEAD_SET_DITHER_CONTROL, BITS, asyh->dither.bits) | + NVVAL(NV507D, HEAD_SET_DITHER_CONTROL, MODE, asyh->dither.mode) | + NVVAL(NV507D, HEAD_SET_DITHER_CONTROL, PHASE, 0)); return 0; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/head907d.c b/drivers/gpu/drm/nouveau/dispnv50/head907d.c index 44b9693cebec..f595cc7c514b 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head907d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head907d.c @@ -78,9 +78,11 @@ head907d_dither(struct nv50_head *head, struct nv50_head_atom *asyh) if ((ret = PUSH_WAIT(push, 2))) return ret; - PUSH_NVSQ(push, NV907D, 0x0490 + (i * 0x300), asyh->dither.mode << 3 | - asyh->dither.bits << 1 | - asyh->dither.enable); + PUSH_MTHD(push, NV907D, HEAD_SET_DITHER_CONTROL(i), + NVVAL(NV907D, HEAD_SET_DITHER_CONTROL, ENABLE, asyh->dither.enable) | + NVVAL(NV907D, HEAD_SET_DITHER_CONTROL, BITS, asyh->dither.bits) | + NVVAL(NV907D, HEAD_SET_DITHER_CONTROL, MODE, asyh->dither.mode) | + NVVAL(NV907D, HEAD_SET_DITHER_CONTROL, PHASE, 0)); return 0; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/head917d.c b/drivers/gpu/drm/nouveau/dispnv50/head917d.c index 026cfb44d597..a5d827403660 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head917d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head917d.c @@ -36,9 +36,11 @@ head917d_dither(struct nv50_head *head, struct nv50_head_atom *asyh) if ((ret = PUSH_WAIT(push, 2))) return ret; - PUSH_NVSQ(push, NV917D, 0x04a0 + (i * 0x300), asyh->dither.mode << 3 | - asyh->dither.bits << 1 | - asyh->dither.enable); + PUSH_MTHD(push, NV917D, HEAD_SET_DITHER_CONTROL(i), + NVVAL(NV917D, HEAD_SET_DITHER_CONTROL, ENABLE, asyh->dither.enable) | + NVVAL(NV917D, HEAD_SET_DITHER_CONTROL, BITS, asyh->dither.bits) | + NVVAL(NV917D, HEAD_SET_DITHER_CONTROL, MODE, asyh->dither.mode) | + NVVAL(NV917D, HEAD_SET_DITHER_CONTROL, PHASE, 0)); return 0; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/headc37d.c b/drivers/gpu/drm/nouveau/dispnv50/headc37d.c index 48b8b4dbd693..172773b6f41b 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/headc37d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/headc37d.c @@ -85,9 +85,12 @@ headc37d_dither(struct nv50_head *head, struct nv50_head_atom *asyh) if ((ret = PUSH_WAIT(push, 2))) return ret; - PUSH_NVSQ(push, NV907D, 0x2018 + (i * 0x400), asyh->dither.mode << 8 | - asyh->dither.bits << 4 | - asyh->dither.enable); + PUSH_MTHD(push, NVC37D, HEAD_SET_DITHER_CONTROL(i), + NVVAL(NVC37D, HEAD_SET_DITHER_CONTROL, ENABLE, asyh->dither.enable) | + NVVAL(NVC37D, HEAD_SET_DITHER_CONTROL, BITS, asyh->dither.bits) | + NVDEF(NVC37D, HEAD_SET_DITHER_CONTROL, OFFSET_ENABLE, DISABLE) | + NVVAL(NVC37D, HEAD_SET_DITHER_CONTROL, MODE, asyh->dither.mode) | + NVVAL(NVC37D, HEAD_SET_DITHER_CONTROL, PHASE, 0)); return 0; } diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.h b/drivers/gpu/drm/nouveau/nouveau_connector.h index 9e062c7adec8..d6de5cb8e223 100644 --- a/drivers/gpu/drm/nouveau/nouveau_connector.h +++ b/drivers/gpu/drm/nouveau/nouveau_connector.h @@ -29,6 +29,10 @@ #include +#include +#include +#include + #include #include #include @@ -56,16 +60,23 @@ struct nouveau_conn_atom { * hw values, and the code relies on this. */ enum { - DITHERING_MODE_OFF = 0x00, - DITHERING_MODE_ON = 0x01, - DITHERING_MODE_DYNAMIC2X2 = 0x10 | DITHERING_MODE_ON, - DITHERING_MODE_STATIC2X2 = 0x18 | DITHERING_MODE_ON, - DITHERING_MODE_TEMPORAL = 0x20 | DITHERING_MODE_ON, + DITHERING_MODE_OFF = + NVDEF(NV507D, HEAD_SET_DITHER_CONTROL, ENABLE, DISABLE), + DITHERING_MODE_ON = + NVDEF(NV507D, HEAD_SET_DITHER_CONTROL, ENABLE, ENABLE), + DITHERING_MODE_DYNAMIC2X2 = DITHERING_MODE_ON | + NVDEF(NV507D, HEAD_SET_DITHER_CONTROL, MODE, DYNAMIC_2X2), + DITHERING_MODE_STATIC2X2 = DITHERING_MODE_ON | + NVDEF(NV507D, HEAD_SET_DITHER_CONTROL, MODE, STATIC_2X2), + DITHERING_MODE_TEMPORAL = DITHERING_MODE_ON | + NVDEF(NV907D, HEAD_SET_DITHER_CONTROL, MODE, TEMPORAL), DITHERING_MODE_AUTO } mode; enum { - DITHERING_DEPTH_6BPC = 0x00, - DITHERING_DEPTH_8BPC = 0x02, + DITHERING_DEPTH_6BPC = + NVDEF(NV507D, HEAD_SET_DITHER_CONTROL, BITS, DITHER_TO_6_BITS), + DITHERING_DEPTH_8BPC = + NVDEF(NV507D, HEAD_SET_DITHER_CONTROL, BITS, DITHER_TO_8_BITS), DITHERING_DEPTH_AUTO } depth; } dither; From 29ace860ecdf716164d9059545bbaae14cced901 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sun, 21 Jun 2020 12:40:59 +1000 Subject: [PATCH 130/145] drm/nouveau/kms/nv50-: use NVIDIA's headers for core head_procamp() Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/head507d.c | 8 ++++++-- drivers/gpu/drm/nouveau/dispnv50/head907d.c | 9 +++++++-- drivers/gpu/drm/nouveau/dispnv50/headc37d.c | 11 ++++++++--- drivers/gpu/drm/nouveau/dispnv50/headc57d.c | 5 ++++- 4 files changed, 25 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/head507d.c b/drivers/gpu/drm/nouveau/dispnv50/head507d.c index be9b9fa27dd0..0edd4e520c8e 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head507d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head507d.c @@ -36,8 +36,12 @@ head507d_procamp(struct nv50_head *head, struct nv50_head_atom *asyh) if ((ret = PUSH_WAIT(push, 2))) return ret; - PUSH_NVSQ(push, NV507D, 0x08a8 + (i * 0x400), asyh->procamp.sat.sin << 20 | - asyh->procamp.sat.cos << 8); + PUSH_MTHD(push, NV507D, HEAD_SET_PROCAMP(i), + NVDEF(NV507D, HEAD_SET_PROCAMP, COLOR_SPACE, RGB) | + NVDEF(NV507D, HEAD_SET_PROCAMP, CHROMA_LPF, AUTO) | + NVVAL(NV507D, HEAD_SET_PROCAMP, SAT_COS, asyh->procamp.sat.cos) | + NVVAL(NV507D, HEAD_SET_PROCAMP, SAT_SINE, asyh->procamp.sat.sin) | + NVDEF(NV507D, HEAD_SET_PROCAMP, TRANSITION, HARD)); return 0; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/head907d.c b/drivers/gpu/drm/nouveau/dispnv50/head907d.c index f595cc7c514b..74f7901e953a 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head907d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head907d.c @@ -63,8 +63,13 @@ head907d_procamp(struct nv50_head *head, struct nv50_head_atom *asyh) if ((ret = PUSH_WAIT(push, 2))) return ret; - PUSH_NVSQ(push, NV907D, 0x0498 + (i * 0x300), asyh->procamp.sat.sin << 20 | - asyh->procamp.sat.cos << 8); + PUSH_MTHD(push, NV907D, HEAD_SET_PROCAMP(i), + NVDEF(NV907D, HEAD_SET_PROCAMP, COLOR_SPACE, RGB) | + NVDEF(NV907D, HEAD_SET_PROCAMP, CHROMA_LPF, AUTO) | + NVVAL(NV907D, HEAD_SET_PROCAMP, SAT_COS, asyh->procamp.sat.cos) | + NVVAL(NV907D, HEAD_SET_PROCAMP, SAT_SINE, asyh->procamp.sat.sin) | + NVDEF(NV907D, HEAD_SET_PROCAMP, DYNAMIC_RANGE, VESA) | + NVDEF(NV907D, HEAD_SET_PROCAMP, RANGE_COMPRESSION, DISABLE)); return 0; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/headc37d.c b/drivers/gpu/drm/nouveau/dispnv50/headc37d.c index 172773b6f41b..ba2dc5a64a69 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/headc37d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/headc37d.c @@ -69,9 +69,14 @@ headc37d_procamp(struct nv50_head *head, struct nv50_head_atom *asyh) if ((ret = PUSH_WAIT(push, 2))) return ret; - PUSH_NVSQ(push, NVC37D, 0x2000 + (i * 0x400), 0x80000000 | - asyh->procamp.sat.sin << 16 | - asyh->procamp.sat.cos << 4); + PUSH_MTHD(push, NVC37D, HEAD_SET_PROCAMP(i), + NVDEF(NVC37D, HEAD_SET_PROCAMP, COLOR_SPACE, RGB) | + NVDEF(NVC37D, HEAD_SET_PROCAMP, CHROMA_LPF, DISABLE) | + NVVAL(NVC37D, HEAD_SET_PROCAMP, SAT_COS, asyh->procamp.sat.cos) | + NVVAL(NVC37D, HEAD_SET_PROCAMP, SAT_SINE, asyh->procamp.sat.sin) | + NVDEF(NVC37D, HEAD_SET_PROCAMP, DYNAMIC_RANGE, VESA) | + NVDEF(NVC37D, HEAD_SET_PROCAMP, RANGE_COMPRESSION, DISABLE) | + NVDEF(NVC37D, HEAD_SET_PROCAMP, BLACK_LEVEL, GRAPHICS)); return 0; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/headc57d.c b/drivers/gpu/drm/nouveau/dispnv50/headc57d.c index 3c0001cd0a6a..24c1cd2247c1 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/headc57d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/headc57d.c @@ -71,7 +71,10 @@ headc57d_procamp(struct nv50_head *head, struct nv50_head_atom *asyh) return ret; //TODO: - PUSH_NVSQ(push, NVC57D, 0x2000 + (i * 0x400), 0x00000000); + PUSH_MTHD(push, NVC57D, HEAD_SET_PROCAMP(i), + NVDEF(NVC57D, HEAD_SET_PROCAMP, COLOR_SPACE, RGB) | + NVDEF(NVC57D, HEAD_SET_PROCAMP, CHROMA_LPF, DISABLE) | + NVDEF(NVC57D, HEAD_SET_PROCAMP, DYNAMIC_RANGE, VESA)); return 0; } From c854bf9464500d195f1a1a2c79ef887291b9300b Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Sun, 21 Jun 2020 12:46:31 +1000 Subject: [PATCH 131/145] drm/nouveau/kms/nv50-: use NVIDIA's headers for core head_or() Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/crc.c | 12 +++++------- drivers/gpu/drm/nouveau/dispnv50/head907d.c | 15 ++++++++------- drivers/gpu/drm/nouveau/dispnv50/headc37d.c | 10 ++++++---- drivers/gpu/drm/nouveau/dispnv50/headc57d.c | 12 +++++++----- 4 files changed, 26 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/crc.c b/drivers/gpu/drm/nouveau/dispnv50/crc.c index 4a43cca96328..b8c31b697797 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/crc.c +++ b/drivers/gpu/drm/nouveau/dispnv50/crc.c @@ -9,6 +9,8 @@ #include #include +#include + #include "nouveau_drv.h" #include "core.h" #include "head.h" @@ -478,10 +480,6 @@ void nv50_crc_atomic_clr(struct nv50_head *head) func->set_src(head, 0, NV50_CRC_SOURCE_TYPE_NONE, NULL, 0); } -#define NV50_CRC_RASTER_ACTIVE 0 -#define NV50_CRC_RASTER_COMPLETE 1 -#define NV50_CRC_RASTER_INACTIVE 2 - static inline int nv50_crc_raster_type(enum nv50_crc_source source) { @@ -490,11 +488,11 @@ nv50_crc_raster_type(enum nv50_crc_source source) case NV50_CRC_SOURCE_AUTO: case NV50_CRC_SOURCE_RG: case NV50_CRC_SOURCE_OUTP_ACTIVE: - return NV50_CRC_RASTER_ACTIVE; + return NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_ACTIVE_RASTER; case NV50_CRC_SOURCE_OUTP_COMPLETE: - return NV50_CRC_RASTER_COMPLETE; + return NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_COMPLETE_RASTER; case NV50_CRC_SOURCE_OUTP_INACTIVE: - return NV50_CRC_RASTER_INACTIVE; + return NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_CRC_MODE_NON_ACTIVE_RASTER; } return 0; diff --git a/drivers/gpu/drm/nouveau/dispnv50/head907d.c b/drivers/gpu/drm/nouveau/dispnv50/head907d.c index 74f7901e953a..8f860e9c5224 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head907d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head907d.c @@ -43,13 +43,14 @@ head907d_or(struct nv50_head *head, struct nv50_head_atom *asyh) if ((ret = PUSH_WAIT(push, 3))) return ret; - PUSH_NVSQ(push, NV907D, 0x0404 + (i * 0x300), asyh->or.depth << 6 | - asyh->or.nvsync << 4 | - asyh->or.nhsync << 3 | - asyh->or.crc_raster, - 0x0408 + (i * 0x300), 0x31ec6000 | - head->base.index << 25 | - asyh->mode.interlace); + PUSH_MTHD(push, NV907D, HEAD_SET_CONTROL_OUTPUT_RESOURCE(i), + NVVAL(NV907D, HEAD_SET_CONTROL_OUTPUT_RESOURCE, CRC_MODE, asyh->or.crc_raster) | + NVVAL(NV907D, HEAD_SET_CONTROL_OUTPUT_RESOURCE, HSYNC_POLARITY, asyh->or.nhsync) | + NVVAL(NV907D, HEAD_SET_CONTROL_OUTPUT_RESOURCE, VSYNC_POLARITY, asyh->or.nvsync) | + NVVAL(NV907D, HEAD_SET_CONTROL_OUTPUT_RESOURCE, PIXEL_DEPTH, asyh->or.depth), + + HEAD_SET_CONTROL(i), 0x31ec6000 | head->base.index << 25 | + NVVAL(NV907D, HEAD_SET_CONTROL, STRUCTURE, asyh->mode.interlace)); return 0; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/headc37d.c b/drivers/gpu/drm/nouveau/dispnv50/headc37d.c index ba2dc5a64a69..63adfeba50e5 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/headc37d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/headc37d.c @@ -52,10 +52,12 @@ headc37d_or(struct nv50_head *head, struct nv50_head_atom *asyh) if ((ret = PUSH_WAIT(push, 2))) return ret; - PUSH_NVSQ(push, NVC37D, 0x2004 + (i * 0x400), depth << 4 | - asyh->or.nvsync << 3 | - asyh->or.nhsync << 2 | - asyh->or.crc_raster); + PUSH_MTHD(push, NVC37D, HEAD_SET_CONTROL_OUTPUT_RESOURCE(i), + NVVAL(NVC37D, HEAD_SET_CONTROL_OUTPUT_RESOURCE, CRC_MODE, asyh->or.crc_raster) | + NVVAL(NVC37D, HEAD_SET_CONTROL_OUTPUT_RESOURCE, HSYNC_POLARITY, asyh->or.nhsync) | + NVVAL(NVC37D, HEAD_SET_CONTROL_OUTPUT_RESOURCE, VSYNC_POLARITY, asyh->or.nvsync) | + NVVAL(NVC37D, HEAD_SET_CONTROL_OUTPUT_RESOURCE, PIXEL_DEPTH, depth) | + NVDEF(NVC37D, HEAD_SET_CONTROL_OUTPUT_RESOURCE, COLOR_SPACE_OVERRIDE, DISABLE)); return 0; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/headc57d.c b/drivers/gpu/drm/nouveau/dispnv50/headc57d.c index 24c1cd2247c1..fd51527b56b8 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/headc57d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/headc57d.c @@ -52,11 +52,13 @@ headc57d_or(struct nv50_head *head, struct nv50_head_atom *asyh) if ((ret = PUSH_WAIT(push, 2))) return ret; - PUSH_NVSQ(push, NVC57D, 0x2004 + (i * 0x400), 0xfc000000 | - depth << 4 | - asyh->or.nvsync << 3 | - asyh->or.nhsync << 2 | - asyh->or.crc_raster); + PUSH_MTHD(push, NVC57D, HEAD_SET_CONTROL_OUTPUT_RESOURCE(i), + NVVAL(NVC57D, HEAD_SET_CONTROL_OUTPUT_RESOURCE, CRC_MODE, asyh->or.crc_raster) | + NVVAL(NVC57D, HEAD_SET_CONTROL_OUTPUT_RESOURCE, HSYNC_POLARITY, asyh->or.nhsync) | + NVVAL(NVC57D, HEAD_SET_CONTROL_OUTPUT_RESOURCE, VSYNC_POLARITY, asyh->or.nvsync) | + NVVAL(NVC57D, HEAD_SET_CONTROL_OUTPUT_RESOURCE, PIXEL_DEPTH, depth) | + NVDEF(NVC57D, HEAD_SET_CONTROL_OUTPUT_RESOURCE, COLOR_SPACE_OVERRIDE, DISABLE) | + NVDEF(NVC57D, HEAD_SET_CONTROL_OUTPUT_RESOURCE, EXT_PACKET_WIN, NONE)); return 0; } From 6162638e196f8cf46cc63cb0f5327f7c6ae7d62b Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 20 Jul 2020 07:56:31 +1000 Subject: [PATCH 132/145] drm/nouveau/kms/nv50-: use NVIDIA's headers for core crc_set_src() Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/crc907d.c | 29 +++++++++++++--------- drivers/gpu/drm/nouveau/dispnv50/crcc37d.c | 22 +++++++++------- 2 files changed, 30 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/crc907d.c b/drivers/gpu/drm/nouveau/dispnv50/crc907d.c index 75728dc99b64..3e8842220e7e 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/crc907d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/crc907d.c @@ -8,6 +8,8 @@ #include +#include + #define CRC907D_MAX_ENTRIES 255 struct crc907d_notifier { @@ -25,30 +27,33 @@ crc907d_set_src(struct nv50_head *head, int or, enum nv50_crc_source_type source, struct nv50_crc_notifier_ctx *ctx, u32 wndw) { - struct drm_crtc *crtc = &head->base.base; struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push; const int i = head->base.index; - u32 crc_args = 0xfff00000; + u32 crc_args = NVDEF(NV907D, HEAD_SET_CRC_CONTROL, CONTROLLING_CHANNEL, CORE) | + NVDEF(NV907D, HEAD_SET_CRC_CONTROL, EXPECT_BUFFER_COLLAPSE, FALSE) | + NVDEF(NV907D, HEAD_SET_CRC_CONTROL, TIMESTAMP_MODE, FALSE) | + NVDEF(NV907D, HEAD_SET_CRC_CONTROL, SECONDARY_OUTPUT, NONE) | + NVDEF(NV907D, HEAD_SET_CRC_CONTROL, CRC_DURING_SNOOZE, DISABLE); int ret; switch (source) { case NV50_CRC_SOURCE_TYPE_SOR: - crc_args |= (0x00000f0f + or * 16) << 8; + crc_args |= NVDEF(NV907D, HEAD_SET_CRC_CONTROL, PRIMARY_OUTPUT, SOR(or)); break; case NV50_CRC_SOURCE_TYPE_PIOR: - crc_args |= (0x000000ff + or * 256) << 8; + crc_args |= NVDEF(NV907D, HEAD_SET_CRC_CONTROL, PRIMARY_OUTPUT, PIOR(or)); break; case NV50_CRC_SOURCE_TYPE_DAC: - crc_args |= (0x00000ff0 + or) << 8; + crc_args |= NVDEF(NV907D, HEAD_SET_CRC_CONTROL, PRIMARY_OUTPUT, DAC(or)); break; case NV50_CRC_SOURCE_TYPE_RG: - crc_args |= (0x00000ff8 + drm_crtc_index(crtc)) << 8; + crc_args |= NVDEF(NV907D, HEAD_SET_CRC_CONTROL, PRIMARY_OUTPUT, RG(i)); break; case NV50_CRC_SOURCE_TYPE_SF: - crc_args |= (0x00000f8f + drm_crtc_index(crtc) * 16) << 8; + crc_args |= NVDEF(NV907D, HEAD_SET_CRC_CONTROL, PRIMARY_OUTPUT, SF(i)); break; case NV50_CRC_SOURCE_NONE: - crc_args |= 0x000fff00; + crc_args |= NVDEF(NV907D, HEAD_SET_CRC_CONTROL, PRIMARY_OUTPUT, NONE); break; } @@ -56,11 +61,11 @@ crc907d_set_src(struct nv50_head *head, int or, return ret; if (source) { - PUSH_NVSQ(push, NV907D, 0x0438 + (i * 0x300), ctx->ntfy.handle); - PUSH_NVSQ(push, NV907D, 0x0430 + (i * 0x300), crc_args); + PUSH_MTHD(push, NV907D, HEAD_SET_CONTEXT_DMA_CRC(i), ctx->ntfy.handle); + PUSH_MTHD(push, NV907D, HEAD_SET_CRC_CONTROL(i), crc_args); } else { - PUSH_NVSQ(push, NV907D, 0x0430 + (i * 0x300), crc_args); - PUSH_NVSQ(push, NV907D, 0x0438 + (i * 0x300), 0); + PUSH_MTHD(push, NV907D, HEAD_SET_CRC_CONTROL(i), crc_args); + PUSH_MTHD(push, NV907D, HEAD_SET_CONTEXT_DMA_CRC(i), 0); } return 0; diff --git a/drivers/gpu/drm/nouveau/dispnv50/crcc37d.c b/drivers/gpu/drm/nouveau/dispnv50/crcc37d.c index dd818931db09..fe68e57c5c83 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/crcc37d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/crcc37d.c @@ -8,6 +8,8 @@ #include +#include + #define CRCC37D_MAX_ENTRIES 2047 struct crcc37d_notifier { @@ -39,21 +41,23 @@ crcc37d_set_src(struct nv50_head *head, int or, { struct nvif_push *push = nv50_disp(head->base.base.dev)->core->chan.push; const int i = head->base.index; - u32 crc_args; + u32 crc_args = NVVAL(NVC37D, HEAD_SET_CRC_CONTROL, CONTROLLING_CHANNEL, wndw) | + NVDEF(NVC37D, HEAD_SET_CRC_CONTROL, EXPECT_BUFFER_COLLAPSE, FALSE) | + NVDEF(NVC37D, HEAD_SET_CRC_CONTROL, SECONDARY_CRC, NONE) | + NVDEF(NVC37D, HEAD_SET_CRC_CONTROL, CRC_DURING_SNOOZE, DISABLE); int ret; switch (source) { case NV50_CRC_SOURCE_TYPE_SOR: - crc_args = (0x00000050 + or) << 12; + crc_args |= NVDEF(NVC37D, HEAD_SET_CRC_CONTROL, PRIMARY_CRC, SOR(or)); break; case NV50_CRC_SOURCE_TYPE_PIOR: - crc_args = (0x00000060 + or) << 12; + crc_args |= NVDEF(NVC37D, HEAD_SET_CRC_CONTROL, PRIMARY_CRC, PIOR(or)); break; case NV50_CRC_SOURCE_TYPE_SF: - crc_args = 0x00000030 << 12; + crc_args |= NVDEF(NVC37D, HEAD_SET_CRC_CONTROL, PRIMARY_CRC, SF); break; default: - crc_args = 0; break; } @@ -61,11 +65,11 @@ crcc37d_set_src(struct nv50_head *head, int or, return ret; if (source) { - PUSH_NVSQ(push, NVC37D, 0x2180 + (i * 0x400), ctx->ntfy.handle); - PUSH_NVSQ(push, NVC37D, 0x2184 + (i * 0x400), crc_args | wndw); + PUSH_MTHD(push, NVC37D, HEAD_SET_CONTEXT_DMA_CRC(i), ctx->ntfy.handle); + PUSH_MTHD(push, NVC37D, HEAD_SET_CRC_CONTROL(i), crc_args); } else { - PUSH_NVSQ(push, NVC37D, 0x2184 + (i * 0x400), 0); - PUSH_NVSQ(push, NVC37D, 0x2180 + (i * 0x400), 0); + PUSH_MTHD(push, NVC37D, HEAD_SET_CRC_CONTROL(i), 0); + PUSH_MTHD(push, NVC37D, HEAD_SET_CONTEXT_DMA_CRC(i), 0); } return 0; From 1fad04ceef14eed22a8f52fab9ff9ab031f24057 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 20 Jul 2020 09:49:39 +1000 Subject: [PATCH 133/145] drm/nouveau/kms/nv50-: use NVIDIA's headers for core crc_set_ctx() Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/dispnv50/crc907d.c | 2 +- drivers/gpu/drm/nouveau/dispnv50/crcc37d.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/crc907d.c b/drivers/gpu/drm/nouveau/dispnv50/crc907d.c index 3e8842220e7e..0fb0fdb9f119 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/crc907d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/crc907d.c @@ -81,7 +81,7 @@ crc907d_set_ctx(struct nv50_head *head, struct nv50_crc_notifier_ctx *ctx) if ((ret = PUSH_WAIT(push, 2))) return ret; - PUSH_NVSQ(push, NV907D, 0x0438 + (i * 0x300), ctx ? ctx->ntfy.handle : 0); + PUSH_MTHD(push, NV907D, HEAD_SET_CONTEXT_DMA_CRC(i), ctx ? ctx->ntfy.handle : 0); return 0; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/crcc37d.c b/drivers/gpu/drm/nouveau/dispnv50/crcc37d.c index fe68e57c5c83..9afe9a87bde0 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/crcc37d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/crcc37d.c @@ -85,7 +85,7 @@ crcc37d_set_ctx(struct nv50_head *head, struct nv50_crc_notifier_ctx *ctx) if ((ret = PUSH_WAIT(push, 2))) return ret; - PUSH_NVSQ(push, NVC37D, 0x2180 + (i * 0x400), ctx ? ctx->ntfy.handle : 0); + PUSH_MTHD(push, NVC37D, HEAD_SET_CONTEXT_DMA_CRC(i), ctx ? ctx->ntfy.handle : 0); return 0; } From 5755b1eac0192fb50b69cd40e48078907628f915 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 20 Jul 2020 07:59:22 +1000 Subject: [PATCH 134/145] drm/nouveau/fbcon/nv50-: use NVIDIA's headers for accel_init() Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- .../drm/nouveau/include/nvhw/class/cl502d.h | 337 +++++++++++++++++ .../drm/nouveau/include/nvhw/class/cl902d.h | 357 ++++++++++++++++++ drivers/gpu/drm/nouveau/nv50_fbcon.c | 133 ++++--- drivers/gpu/drm/nouveau/nvc0_fbcon.c | 127 ++++--- 4 files changed, 867 insertions(+), 87 deletions(-) create mode 100644 drivers/gpu/drm/nouveau/include/nvhw/class/cl502d.h create mode 100644 drivers/gpu/drm/nouveau/include/nvhw/class/cl902d.h diff --git a/drivers/gpu/drm/nouveau/include/nvhw/class/cl502d.h b/drivers/gpu/drm/nouveau/include/nvhw/class/cl502d.h new file mode 100644 index 000000000000..47fe91b67e74 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvhw/class/cl502d.h @@ -0,0 +1,337 @@ +/* + * Copyright (c) 2003 - 2004, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_nv50_twod_h_ +#define _cl_nv50_twod_h_ + +#define NV502D_SET_OBJECT 0x0000 +#define NV502D_SET_OBJECT_POINTER 15:0 + +#define NV502D_WAIT_FOR_IDLE 0x0110 +#define NV502D_WAIT_FOR_IDLE_V 31:0 + +#define NV502D_SET_DST_CONTEXT_DMA 0x0184 +#define NV502D_SET_DST_CONTEXT_DMA_HANDLE 31:0 + +#define NV502D_SET_SRC_CONTEXT_DMA 0x0188 +#define NV502D_SET_SRC_CONTEXT_DMA_HANDLE 31:0 + +#define NV502D_SET_SEMAPHORE_CONTEXT_DMA 0x018c +#define NV502D_SET_SEMAPHORE_CONTEXT_DMA_HANDLE 31:0 + +#define NV502D_SET_DST_FORMAT 0x0200 +#define NV502D_SET_DST_FORMAT_V 7:0 +#define NV502D_SET_DST_FORMAT_V_A8R8G8B8 0x000000CF +#define NV502D_SET_DST_FORMAT_V_A8RL8GL8BL8 0x000000D0 +#define NV502D_SET_DST_FORMAT_V_A2R10G10B10 0x000000DF +#define NV502D_SET_DST_FORMAT_V_A8B8G8R8 0x000000D5 +#define NV502D_SET_DST_FORMAT_V_A8BL8GL8RL8 0x000000D6 +#define NV502D_SET_DST_FORMAT_V_A2B10G10R10 0x000000D1 +#define NV502D_SET_DST_FORMAT_V_X8R8G8B8 0x000000E6 +#define NV502D_SET_DST_FORMAT_V_X8RL8GL8BL8 0x000000E7 +#define NV502D_SET_DST_FORMAT_V_X8B8G8R8 0x000000F9 +#define NV502D_SET_DST_FORMAT_V_X8BL8GL8RL8 0x000000FA +#define NV502D_SET_DST_FORMAT_V_R5G6B5 0x000000E8 +#define NV502D_SET_DST_FORMAT_V_A1R5G5B5 0x000000E9 +#define NV502D_SET_DST_FORMAT_V_X1R5G5B5 0x000000F8 +#define NV502D_SET_DST_FORMAT_V_Y8 0x000000F3 +#define NV502D_SET_DST_FORMAT_V_Y16 0x000000EE +#define NV502D_SET_DST_FORMAT_V_Y32 0x000000FF +#define NV502D_SET_DST_FORMAT_V_Z1R5G5B5 0x000000FB +#define NV502D_SET_DST_FORMAT_V_O1R5G5B5 0x000000FC +#define NV502D_SET_DST_FORMAT_V_Z8R8G8B8 0x000000FD +#define NV502D_SET_DST_FORMAT_V_O8R8G8B8 0x000000FE +#define NV502D_SET_DST_FORMAT_V_Y1_8X8 0x0000001C +#define NV502D_SET_DST_FORMAT_V_RF16 0x000000F2 +#define NV502D_SET_DST_FORMAT_V_RF32 0x000000E5 +#define NV502D_SET_DST_FORMAT_V_RF32_GF32 0x000000CB +#define NV502D_SET_DST_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA +#define NV502D_SET_DST_FORMAT_V_RF16_GF16_BF16_X16 0x000000CE +#define NV502D_SET_DST_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0 +#define NV502D_SET_DST_FORMAT_V_RF32_GF32_BF32_X32 0x000000C3 + +#define NV502D_SET_DST_MEMORY_LAYOUT 0x0204 +#define NV502D_SET_DST_MEMORY_LAYOUT_V 0:0 +#define NV502D_SET_DST_MEMORY_LAYOUT_V_BLOCKLINEAR 0x00000000 +#define NV502D_SET_DST_MEMORY_LAYOUT_V_PITCH 0x00000001 + +#define NV502D_SET_DST_PITCH 0x0214 +#define NV502D_SET_DST_PITCH_V 31:0 + +#define NV502D_SET_DST_WIDTH 0x0218 +#define NV502D_SET_DST_WIDTH_V 31:0 + +#define NV502D_SET_DST_HEIGHT 0x021c +#define NV502D_SET_DST_HEIGHT_V 31:0 + +#define NV502D_SET_DST_OFFSET_UPPER 0x0220 +#define NV502D_SET_DST_OFFSET_UPPER_V 7:0 + +#define NV502D_SET_DST_OFFSET_LOWER 0x0224 +#define NV502D_SET_DST_OFFSET_LOWER_V 31:0 + +#define NV502D_SET_SRC_FORMAT 0x0230 +#define NV502D_SET_SRC_FORMAT_V 7:0 +#define NV502D_SET_SRC_FORMAT_V_A8R8G8B8 0x000000CF +#define NV502D_SET_SRC_FORMAT_V_A8RL8GL8BL8 0x000000D0 +#define NV502D_SET_SRC_FORMAT_V_A2R10G10B10 0x000000DF +#define NV502D_SET_SRC_FORMAT_V_A8B8G8R8 0x000000D5 +#define NV502D_SET_SRC_FORMAT_V_A8BL8GL8RL8 0x000000D6 +#define NV502D_SET_SRC_FORMAT_V_A2B10G10R10 0x000000D1 +#define NV502D_SET_SRC_FORMAT_V_X8R8G8B8 0x000000E6 +#define NV502D_SET_SRC_FORMAT_V_X8RL8GL8BL8 0x000000E7 +#define NV502D_SET_SRC_FORMAT_V_X8B8G8R8 0x000000F9 +#define NV502D_SET_SRC_FORMAT_V_X8BL8GL8RL8 0x000000FA +#define NV502D_SET_SRC_FORMAT_V_R5G6B5 0x000000E8 +#define NV502D_SET_SRC_FORMAT_V_A1R5G5B5 0x000000E9 +#define NV502D_SET_SRC_FORMAT_V_X1R5G5B5 0x000000F8 +#define NV502D_SET_SRC_FORMAT_V_Y8 0x000000F3 +#define NV502D_SET_SRC_FORMAT_V_AY8 0x0000001D +#define NV502D_SET_SRC_FORMAT_V_Y16 0x000000EE +#define NV502D_SET_SRC_FORMAT_V_Y32 0x000000FF +#define NV502D_SET_SRC_FORMAT_V_Z1R5G5B5 0x000000FB +#define NV502D_SET_SRC_FORMAT_V_O1R5G5B5 0x000000FC +#define NV502D_SET_SRC_FORMAT_V_Z8R8G8B8 0x000000FD +#define NV502D_SET_SRC_FORMAT_V_O8R8G8B8 0x000000FE +#define NV502D_SET_SRC_FORMAT_V_Y1_8X8 0x0000001C +#define NV502D_SET_SRC_FORMAT_V_RF16 0x000000F2 +#define NV502D_SET_SRC_FORMAT_V_RF32 0x000000E5 +#define NV502D_SET_SRC_FORMAT_V_RF32_GF32 0x000000CB +#define NV502D_SET_SRC_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA +#define NV502D_SET_SRC_FORMAT_V_RF16_GF16_BF16_X16 0x000000CE +#define NV502D_SET_SRC_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0 +#define NV502D_SET_SRC_FORMAT_V_RF32_GF32_BF32_X32 0x000000C3 + +#define NV502D_SET_SRC_MEMORY_LAYOUT 0x0234 +#define NV502D_SET_SRC_MEMORY_LAYOUT_V 0:0 +#define NV502D_SET_SRC_MEMORY_LAYOUT_V_BLOCKLINEAR 0x00000000 +#define NV502D_SET_SRC_MEMORY_LAYOUT_V_PITCH 0x00000001 + +#define NV502D_SET_SRC_PITCH 0x0244 +#define NV502D_SET_SRC_PITCH_V 31:0 + +#define NV502D_SET_SRC_WIDTH 0x0248 +#define NV502D_SET_SRC_WIDTH_V 31:0 + +#define NV502D_SET_SRC_HEIGHT 0x024c +#define NV502D_SET_SRC_HEIGHT_V 31:0 + +#define NV502D_SET_SRC_OFFSET_UPPER 0x0250 +#define NV502D_SET_SRC_OFFSET_UPPER_V 7:0 + +#define NV502D_SET_SRC_OFFSET_LOWER 0x0254 +#define NV502D_SET_SRC_OFFSET_LOWER_V 31:0 + +#define NV502D_SET_CLIP_ENABLE 0x0290 +#define NV502D_SET_CLIP_ENABLE_V 0:0 +#define NV502D_SET_CLIP_ENABLE_V_FALSE 0x00000000 +#define NV502D_SET_CLIP_ENABLE_V_TRUE 0x00000001 + +#define NV502D_SET_ROP 0x02a0 +#define NV502D_SET_ROP_V 7:0 + +#define NV502D_SET_OPERATION 0x02ac +#define NV502D_SET_OPERATION_V 2:0 +#define NV502D_SET_OPERATION_V_SRCCOPY_AND 0x00000000 +#define NV502D_SET_OPERATION_V_ROP_AND 0x00000001 +#define NV502D_SET_OPERATION_V_BLEND_AND 0x00000002 +#define NV502D_SET_OPERATION_V_SRCCOPY 0x00000003 +#define NV502D_SET_OPERATION_V_ROP 0x00000004 +#define NV502D_SET_OPERATION_V_SRCCOPY_PREMULT 0x00000005 +#define NV502D_SET_OPERATION_V_BLEND_PREMULT 0x00000006 + +#define NV502D_SET_MONOCHROME_PATTERN_COLOR_FORMAT 0x02e8 +#define NV502D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V 2:0 +#define NV502D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V_A8X8R5G6B5 0x00000000 +#define NV502D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V_A1R5G5B5 0x00000001 +#define NV502D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V_A8R8G8B8 0x00000002 +#define NV502D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V_A8Y8 0x00000003 +#define NV502D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V_A8X8Y16 0x00000004 +#define NV502D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V_Y32 0x00000005 + +#define NV502D_SET_MONOCHROME_PATTERN_FORMAT 0x02ec +#define NV502D_SET_MONOCHROME_PATTERN_FORMAT_V 0:0 +#define NV502D_SET_MONOCHROME_PATTERN_FORMAT_V_CGA6_M1 0x00000000 +#define NV502D_SET_MONOCHROME_PATTERN_FORMAT_V_LE_M1 0x00000001 + +#define NV502D_RENDER_SOLID_PRIM_MODE 0x0580 +#define NV502D_RENDER_SOLID_PRIM_MODE_V 2:0 +#define NV502D_RENDER_SOLID_PRIM_MODE_V_POINTS 0x00000000 +#define NV502D_RENDER_SOLID_PRIM_MODE_V_LINES 0x00000001 +#define NV502D_RENDER_SOLID_PRIM_MODE_V_POLYLINE 0x00000002 +#define NV502D_RENDER_SOLID_PRIM_MODE_V_TRIANGLES 0x00000003 +#define NV502D_RENDER_SOLID_PRIM_MODE_V_RECTS 0x00000004 + +#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT 0x0584 +#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V 7:0 +#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_A8R8G8B8 0x000000CF +#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_A2R10G10B10 0x000000DF +#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_A8B8G8R8 0x000000D5 +#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_A2B10G10R10 0x000000D1 +#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_X8R8G8B8 0x000000E6 +#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_X8B8G8R8 0x000000F9 +#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_R5G6B5 0x000000E8 +#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_A1R5G5B5 0x000000E9 +#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_X1R5G5B5 0x000000F8 +#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_Y8 0x000000F3 +#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_Y16 0x000000EE +#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_Y32 0x000000FF +#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_Z1R5G5B5 0x000000FB +#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_O1R5G5B5 0x000000FC +#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_Z8R8G8B8 0x000000FD +#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_O8R8G8B8 0x000000FE + +#define NV502D_SET_RENDER_SOLID_PRIM_COLOR 0x0588 +#define NV502D_SET_RENDER_SOLID_PRIM_COLOR_V 31:0 + +#define NV502D_RENDER_SOLID_PRIM_POINT_SET_X(j) (0x0600+(j)*8) +#define NV502D_RENDER_SOLID_PRIM_POINT_SET_X_V 31:0 + +#define NV502D_RENDER_SOLID_PRIM_POINT_Y(j) (0x0604+(j)*8) +#define NV502D_RENDER_SOLID_PRIM_POINT_Y_V 31:0 + +#define NV502D_SET_PIXELS_FROM_CPU_DATA_TYPE 0x0800 +#define NV502D_SET_PIXELS_FROM_CPU_DATA_TYPE_V 0:0 +#define NV502D_SET_PIXELS_FROM_CPU_DATA_TYPE_V_COLOR 0x00000000 +#define NV502D_SET_PIXELS_FROM_CPU_DATA_TYPE_V_INDEX 0x00000001 + +#define NV502D_SET_PIXELS_FROM_CPU_COLOR_FORMAT 0x0804 +#define NV502D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V 7:0 +#define NV502D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_A8R8G8B8 0x000000CF +#define NV502D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_A2R10G10B10 0x000000DF +#define NV502D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_A8B8G8R8 0x000000D5 +#define NV502D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_A2B10G10R10 0x000000D1 +#define NV502D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_X8R8G8B8 0x000000E6 +#define NV502D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_X8B8G8R8 0x000000F9 +#define NV502D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_R5G6B5 0x000000E8 +#define NV502D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_A1R5G5B5 0x000000E9 +#define NV502D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_X1R5G5B5 0x000000F8 +#define NV502D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_Y8 0x000000F3 +#define NV502D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_Y16 0x000000EE +#define NV502D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_Y32 0x000000FF +#define NV502D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_Z1R5G5B5 0x000000FB +#define NV502D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_O1R5G5B5 0x000000FC +#define NV502D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_Z8R8G8B8 0x000000FD +#define NV502D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_O8R8G8B8 0x000000FE + +#define NV502D_SET_PIXELS_FROM_CPU_INDEX_FORMAT 0x0808 +#define NV502D_SET_PIXELS_FROM_CPU_INDEX_FORMAT_V 1:0 +#define NV502D_SET_PIXELS_FROM_CPU_INDEX_FORMAT_V_I1 0x00000000 +#define NV502D_SET_PIXELS_FROM_CPU_INDEX_FORMAT_V_I4 0x00000001 +#define NV502D_SET_PIXELS_FROM_CPU_INDEX_FORMAT_V_I8 0x00000002 + +#define NV502D_SET_PIXELS_FROM_CPU_MONO_FORMAT 0x080c +#define NV502D_SET_PIXELS_FROM_CPU_MONO_FORMAT_V 0:0 +#define NV502D_SET_PIXELS_FROM_CPU_MONO_FORMAT_V_CGA6_M1 0x00000000 +#define NV502D_SET_PIXELS_FROM_CPU_MONO_FORMAT_V_LE_M1 0x00000001 + +#define NV502D_SET_PIXELS_FROM_CPU_WRAP 0x0810 +#define NV502D_SET_PIXELS_FROM_CPU_WRAP_V 1:0 +#define NV502D_SET_PIXELS_FROM_CPU_WRAP_V_WRAP_PIXEL 0x00000000 +#define NV502D_SET_PIXELS_FROM_CPU_WRAP_V_WRAP_BYTE 0x00000001 +#define NV502D_SET_PIXELS_FROM_CPU_WRAP_V_WRAP_DWORD 0x00000002 + +#define NV502D_SET_PIXELS_FROM_CPU_COLOR0 0x0814 +#define NV502D_SET_PIXELS_FROM_CPU_COLOR0_V 31:0 + +#define NV502D_SET_PIXELS_FROM_CPU_COLOR1 0x0818 +#define NV502D_SET_PIXELS_FROM_CPU_COLOR1_V 31:0 + +#define NV502D_SET_PIXELS_FROM_CPU_MONO_OPACITY 0x081c +#define NV502D_SET_PIXELS_FROM_CPU_MONO_OPACITY_V 0:0 +#define NV502D_SET_PIXELS_FROM_CPU_MONO_OPACITY_V_TRANSPARENT 0x00000000 +#define NV502D_SET_PIXELS_FROM_CPU_MONO_OPACITY_V_OPAQUE 0x00000001 + +#define NV502D_SET_PIXELS_FROM_CPU_SRC_WIDTH 0x0838 +#define NV502D_SET_PIXELS_FROM_CPU_SRC_WIDTH_V 31:0 + +#define NV502D_SET_PIXELS_FROM_CPU_SRC_HEIGHT 0x083c +#define NV502D_SET_PIXELS_FROM_CPU_SRC_HEIGHT_V 31:0 + +#define NV502D_SET_PIXELS_FROM_CPU_DX_DU_FRAC 0x0840 +#define NV502D_SET_PIXELS_FROM_CPU_DX_DU_FRAC_V 31:0 + +#define NV502D_SET_PIXELS_FROM_CPU_DX_DU_INT 0x0844 +#define NV502D_SET_PIXELS_FROM_CPU_DX_DU_INT_V 31:0 + +#define NV502D_SET_PIXELS_FROM_CPU_DY_DV_FRAC 0x0848 +#define NV502D_SET_PIXELS_FROM_CPU_DY_DV_FRAC_V 31:0 + +#define NV502D_SET_PIXELS_FROM_CPU_DY_DV_INT 0x084c +#define NV502D_SET_PIXELS_FROM_CPU_DY_DV_INT_V 31:0 + +#define NV502D_SET_PIXELS_FROM_CPU_DST_X0_FRAC 0x0850 +#define NV502D_SET_PIXELS_FROM_CPU_DST_X0_FRAC_V 31:0 + +#define NV502D_SET_PIXELS_FROM_CPU_DST_X0_INT 0x0854 +#define NV502D_SET_PIXELS_FROM_CPU_DST_X0_INT_V 31:0 + +#define NV502D_SET_PIXELS_FROM_CPU_DST_Y0_FRAC 0x0858 +#define NV502D_SET_PIXELS_FROM_CPU_DST_Y0_FRAC_V 31:0 + +#define NV502D_SET_PIXELS_FROM_CPU_DST_Y0_INT 0x085c +#define NV502D_SET_PIXELS_FROM_CPU_DST_Y0_INT_V 31:0 + +#define NV502D_PIXELS_FROM_CPU_DATA 0x0860 +#define NV502D_PIXELS_FROM_CPU_DATA_V 31:0 + +#define NV502D_SET_PIXELS_FROM_MEMORY_SAFE_OVERLAP 0x0888 +#define NV502D_SET_PIXELS_FROM_MEMORY_SAFE_OVERLAP_V 0:0 +#define NV502D_SET_PIXELS_FROM_MEMORY_SAFE_OVERLAP_V_FALSE 0x00000000 +#define NV502D_SET_PIXELS_FROM_MEMORY_SAFE_OVERLAP_V_TRUE 0x00000001 + +#define NV502D_SET_PIXELS_FROM_MEMORY_DST_X0 0x08b0 +#define NV502D_SET_PIXELS_FROM_MEMORY_DST_X0_V 31:0 + +#define NV502D_SET_PIXELS_FROM_MEMORY_DST_Y0 0x08b4 +#define NV502D_SET_PIXELS_FROM_MEMORY_DST_Y0_V 31:0 + +#define NV502D_SET_PIXELS_FROM_MEMORY_DST_WIDTH 0x08b8 +#define NV502D_SET_PIXELS_FROM_MEMORY_DST_WIDTH_V 31:0 + +#define NV502D_SET_PIXELS_FROM_MEMORY_DST_HEIGHT 0x08bc +#define NV502D_SET_PIXELS_FROM_MEMORY_DST_HEIGHT_V 31:0 + +#define NV502D_SET_PIXELS_FROM_MEMORY_DU_DX_FRAC 0x08c0 +#define NV502D_SET_PIXELS_FROM_MEMORY_DU_DX_FRAC_V 31:0 + +#define NV502D_SET_PIXELS_FROM_MEMORY_DU_DX_INT 0x08c4 +#define NV502D_SET_PIXELS_FROM_MEMORY_DU_DX_INT_V 31:0 + +#define NV502D_SET_PIXELS_FROM_MEMORY_DV_DY_FRAC 0x08c8 +#define NV502D_SET_PIXELS_FROM_MEMORY_DV_DY_FRAC_V 31:0 + +#define NV502D_SET_PIXELS_FROM_MEMORY_DV_DY_INT 0x08cc +#define NV502D_SET_PIXELS_FROM_MEMORY_DV_DY_INT_V 31:0 + +#define NV502D_SET_PIXELS_FROM_MEMORY_SRC_X0_FRAC 0x08d0 +#define NV502D_SET_PIXELS_FROM_MEMORY_SRC_X0_FRAC_V 31:0 + +#define NV502D_SET_PIXELS_FROM_MEMORY_SRC_X0_INT 0x08d4 +#define NV502D_SET_PIXELS_FROM_MEMORY_SRC_X0_INT_V 31:0 + +#define NV502D_SET_PIXELS_FROM_MEMORY_SRC_Y0_FRAC 0x08d8 +#define NV502D_SET_PIXELS_FROM_MEMORY_SRC_Y0_FRAC_V 31:0 + +#define NV502D_PIXELS_FROM_MEMORY_SRC_Y0_INT 0x08dc +#define NV502D_PIXELS_FROM_MEMORY_SRC_Y0_INT_V 31:0 +#endif /* _cl_nv50_twod_h_ */ diff --git a/drivers/gpu/drm/nouveau/include/nvhw/class/cl902d.h b/drivers/gpu/drm/nouveau/include/nvhw/class/cl902d.h new file mode 100644 index 000000000000..8d0b42c04e3e --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvhw/class/cl902d.h @@ -0,0 +1,357 @@ +/* + * Copyright (c) 2003 - 2004, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_fermi_twod_a_h_ +#define _cl_fermi_twod_a_h_ + +#define NV902D_SET_OBJECT 0x0000 +#define NV902D_SET_OBJECT_CLASS_ID 15:0 +#define NV902D_SET_OBJECT_ENGINE_ID 20:16 + +#define NV902D_WAIT_FOR_IDLE 0x0110 +#define NV902D_WAIT_FOR_IDLE_V 31:0 + +#define NV902D_SET_DST_FORMAT 0x0200 +#define NV902D_SET_DST_FORMAT_V 7:0 +#define NV902D_SET_DST_FORMAT_V_A8R8G8B8 0x000000CF +#define NV902D_SET_DST_FORMAT_V_A8RL8GL8BL8 0x000000D0 +#define NV902D_SET_DST_FORMAT_V_A2R10G10B10 0x000000DF +#define NV902D_SET_DST_FORMAT_V_A8B8G8R8 0x000000D5 +#define NV902D_SET_DST_FORMAT_V_A8BL8GL8RL8 0x000000D6 +#define NV902D_SET_DST_FORMAT_V_A2B10G10R10 0x000000D1 +#define NV902D_SET_DST_FORMAT_V_X8R8G8B8 0x000000E6 +#define NV902D_SET_DST_FORMAT_V_X8RL8GL8BL8 0x000000E7 +#define NV902D_SET_DST_FORMAT_V_X8B8G8R8 0x000000F9 +#define NV902D_SET_DST_FORMAT_V_X8BL8GL8RL8 0x000000FA +#define NV902D_SET_DST_FORMAT_V_R5G6B5 0x000000E8 +#define NV902D_SET_DST_FORMAT_V_A1R5G5B5 0x000000E9 +#define NV902D_SET_DST_FORMAT_V_X1R5G5B5 0x000000F8 +#define NV902D_SET_DST_FORMAT_V_Y8 0x000000F3 +#define NV902D_SET_DST_FORMAT_V_Y16 0x000000EE +#define NV902D_SET_DST_FORMAT_V_Y32 0x000000FF +#define NV902D_SET_DST_FORMAT_V_Z1R5G5B5 0x000000FB +#define NV902D_SET_DST_FORMAT_V_O1R5G5B5 0x000000FC +#define NV902D_SET_DST_FORMAT_V_Z8R8G8B8 0x000000FD +#define NV902D_SET_DST_FORMAT_V_O8R8G8B8 0x000000FE +#define NV902D_SET_DST_FORMAT_V_Y1_8X8 0x0000001C +#define NV902D_SET_DST_FORMAT_V_RF16 0x000000F2 +#define NV902D_SET_DST_FORMAT_V_RF32 0x000000E5 +#define NV902D_SET_DST_FORMAT_V_RF32_GF32 0x000000CB +#define NV902D_SET_DST_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA +#define NV902D_SET_DST_FORMAT_V_RF16_GF16_BF16_X16 0x000000CE +#define NV902D_SET_DST_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0 +#define NV902D_SET_DST_FORMAT_V_RF32_GF32_BF32_X32 0x000000C3 +#define NV902D_SET_DST_FORMAT_V_R16_G16_B16_A16 0x000000C6 +#define NV902D_SET_DST_FORMAT_V_RN16_GN16_BN16_AN16 0x000000C7 +#define NV902D_SET_DST_FORMAT_V_BF10GF11RF11 0x000000E0 +#define NV902D_SET_DST_FORMAT_V_AN8BN8GN8RN8 0x000000D7 +#define NV902D_SET_DST_FORMAT_V_RF16_GF16 0x000000DE +#define NV902D_SET_DST_FORMAT_V_R16_G16 0x000000DA +#define NV902D_SET_DST_FORMAT_V_RN16_GN16 0x000000DB +#define NV902D_SET_DST_FORMAT_V_G8R8 0x000000EA +#define NV902D_SET_DST_FORMAT_V_GN8RN8 0x000000EB +#define NV902D_SET_DST_FORMAT_V_RN16 0x000000EF +#define NV902D_SET_DST_FORMAT_V_RN8 0x000000F4 +#define NV902D_SET_DST_FORMAT_V_A8 0x000000F7 + +#define NV902D_SET_DST_MEMORY_LAYOUT 0x0204 +#define NV902D_SET_DST_MEMORY_LAYOUT_V 0:0 +#define NV902D_SET_DST_MEMORY_LAYOUT_V_BLOCKLINEAR 0x00000000 +#define NV902D_SET_DST_MEMORY_LAYOUT_V_PITCH 0x00000001 + +#define NV902D_SET_DST_PITCH 0x0214 +#define NV902D_SET_DST_PITCH_V 31:0 + +#define NV902D_SET_DST_WIDTH 0x0218 +#define NV902D_SET_DST_WIDTH_V 31:0 + +#define NV902D_SET_DST_HEIGHT 0x021c +#define NV902D_SET_DST_HEIGHT_V 31:0 + +#define NV902D_SET_DST_OFFSET_UPPER 0x0220 +#define NV902D_SET_DST_OFFSET_UPPER_V 7:0 + +#define NV902D_SET_DST_OFFSET_LOWER 0x0224 +#define NV902D_SET_DST_OFFSET_LOWER_V 31:0 + +#define NV902D_SET_SRC_FORMAT 0x0230 +#define NV902D_SET_SRC_FORMAT_V 7:0 +#define NV902D_SET_SRC_FORMAT_V_A8R8G8B8 0x000000CF +#define NV902D_SET_SRC_FORMAT_V_A8RL8GL8BL8 0x000000D0 +#define NV902D_SET_SRC_FORMAT_V_A2R10G10B10 0x000000DF +#define NV902D_SET_SRC_FORMAT_V_A8B8G8R8 0x000000D5 +#define NV902D_SET_SRC_FORMAT_V_A8BL8GL8RL8 0x000000D6 +#define NV902D_SET_SRC_FORMAT_V_A2B10G10R10 0x000000D1 +#define NV902D_SET_SRC_FORMAT_V_X8R8G8B8 0x000000E6 +#define NV902D_SET_SRC_FORMAT_V_X8RL8GL8BL8 0x000000E7 +#define NV902D_SET_SRC_FORMAT_V_X8B8G8R8 0x000000F9 +#define NV902D_SET_SRC_FORMAT_V_X8BL8GL8RL8 0x000000FA +#define NV902D_SET_SRC_FORMAT_V_R5G6B5 0x000000E8 +#define NV902D_SET_SRC_FORMAT_V_A1R5G5B5 0x000000E9 +#define NV902D_SET_SRC_FORMAT_V_X1R5G5B5 0x000000F8 +#define NV902D_SET_SRC_FORMAT_V_Y8 0x000000F3 +#define NV902D_SET_SRC_FORMAT_V_AY8 0x0000001D +#define NV902D_SET_SRC_FORMAT_V_Y16 0x000000EE +#define NV902D_SET_SRC_FORMAT_V_Y32 0x000000FF +#define NV902D_SET_SRC_FORMAT_V_Z1R5G5B5 0x000000FB +#define NV902D_SET_SRC_FORMAT_V_O1R5G5B5 0x000000FC +#define NV902D_SET_SRC_FORMAT_V_Z8R8G8B8 0x000000FD +#define NV902D_SET_SRC_FORMAT_V_O8R8G8B8 0x000000FE +#define NV902D_SET_SRC_FORMAT_V_Y1_8X8 0x0000001C +#define NV902D_SET_SRC_FORMAT_V_RF16 0x000000F2 +#define NV902D_SET_SRC_FORMAT_V_RF32 0x000000E5 +#define NV902D_SET_SRC_FORMAT_V_RF32_GF32 0x000000CB +#define NV902D_SET_SRC_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA +#define NV902D_SET_SRC_FORMAT_V_RF16_GF16_BF16_X16 0x000000CE +#define NV902D_SET_SRC_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0 +#define NV902D_SET_SRC_FORMAT_V_RF32_GF32_BF32_X32 0x000000C3 +#define NV902D_SET_SRC_FORMAT_V_R16_G16_B16_A16 0x000000C6 +#define NV902D_SET_SRC_FORMAT_V_RN16_GN16_BN16_AN16 0x000000C7 +#define NV902D_SET_SRC_FORMAT_V_BF10GF11RF11 0x000000E0 +#define NV902D_SET_SRC_FORMAT_V_AN8BN8GN8RN8 0x000000D7 +#define NV902D_SET_SRC_FORMAT_V_RF16_GF16 0x000000DE +#define NV902D_SET_SRC_FORMAT_V_R16_G16 0x000000DA +#define NV902D_SET_SRC_FORMAT_V_RN16_GN16 0x000000DB +#define NV902D_SET_SRC_FORMAT_V_G8R8 0x000000EA +#define NV902D_SET_SRC_FORMAT_V_GN8RN8 0x000000EB +#define NV902D_SET_SRC_FORMAT_V_RN16 0x000000EF +#define NV902D_SET_SRC_FORMAT_V_RN8 0x000000F4 +#define NV902D_SET_SRC_FORMAT_V_A8 0x000000F7 + +#define NV902D_SET_SRC_MEMORY_LAYOUT 0x0234 +#define NV902D_SET_SRC_MEMORY_LAYOUT_V 0:0 +#define NV902D_SET_SRC_MEMORY_LAYOUT_V_BLOCKLINEAR 0x00000000 +#define NV902D_SET_SRC_MEMORY_LAYOUT_V_PITCH 0x00000001 + +#define NV902D_SET_SRC_PITCH 0x0244 +#define NV902D_SET_SRC_PITCH_V 31:0 + +#define NV902D_SET_SRC_WIDTH 0x0248 +#define NV902D_SET_SRC_WIDTH_V 31:0 + +#define NV902D_SET_SRC_HEIGHT 0x024c +#define NV902D_SET_SRC_HEIGHT_V 31:0 + +#define NV902D_SET_SRC_OFFSET_UPPER 0x0250 +#define NV902D_SET_SRC_OFFSET_UPPER_V 7:0 + +#define NV902D_SET_SRC_OFFSET_LOWER 0x0254 +#define NV902D_SET_SRC_OFFSET_LOWER_V 31:0 + +#define NV902D_SET_CLIP_ENABLE 0x0290 +#define NV902D_SET_CLIP_ENABLE_V 0:0 +#define NV902D_SET_CLIP_ENABLE_V_FALSE 0x00000000 +#define NV902D_SET_CLIP_ENABLE_V_TRUE 0x00000001 + +#define NV902D_SET_ROP 0x02a0 +#define NV902D_SET_ROP_V 7:0 + +#define NV902D_SET_OPERATION 0x02ac +#define NV902D_SET_OPERATION_V 2:0 +#define NV902D_SET_OPERATION_V_SRCCOPY_AND 0x00000000 +#define NV902D_SET_OPERATION_V_ROP_AND 0x00000001 +#define NV902D_SET_OPERATION_V_BLEND_AND 0x00000002 +#define NV902D_SET_OPERATION_V_SRCCOPY 0x00000003 +#define NV902D_SET_OPERATION_V_ROP 0x00000004 +#define NV902D_SET_OPERATION_V_SRCCOPY_PREMULT 0x00000005 +#define NV902D_SET_OPERATION_V_BLEND_PREMULT 0x00000006 + +#define NV902D_SET_MONOCHROME_PATTERN_COLOR_FORMAT 0x02e8 +#define NV902D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V 2:0 +#define NV902D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V_A8X8R5G6B5 0x00000000 +#define NV902D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V_A1R5G5B5 0x00000001 +#define NV902D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V_A8R8G8B8 0x00000002 +#define NV902D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V_A8Y8 0x00000003 +#define NV902D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V_A8X8Y16 0x00000004 +#define NV902D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V_Y32 0x00000005 +#define NV902D_SET_MONOCHROME_PATTERN_COLOR_FORMAT_V_BYTE_EXPAND 0x00000006 + +#define NV902D_SET_MONOCHROME_PATTERN_FORMAT 0x02ec +#define NV902D_SET_MONOCHROME_PATTERN_FORMAT_V 0:0 +#define NV902D_SET_MONOCHROME_PATTERN_FORMAT_V_CGA6_M1 0x00000000 +#define NV902D_SET_MONOCHROME_PATTERN_FORMAT_V_LE_M1 0x00000001 + +#define NV902D_RENDER_SOLID_PRIM_MODE 0x0580 +#define NV902D_RENDER_SOLID_PRIM_MODE_V 2:0 +#define NV902D_RENDER_SOLID_PRIM_MODE_V_POINTS 0x00000000 +#define NV902D_RENDER_SOLID_PRIM_MODE_V_LINES 0x00000001 +#define NV902D_RENDER_SOLID_PRIM_MODE_V_POLYLINE 0x00000002 +#define NV902D_RENDER_SOLID_PRIM_MODE_V_TRIANGLES 0x00000003 +#define NV902D_RENDER_SOLID_PRIM_MODE_V_RECTS 0x00000004 + +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT 0x0584 +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V 7:0 +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_RF32_GF32_BF32_AF32 0x000000C0 +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_RF16_GF16_BF16_AF16 0x000000CA +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_RF32_GF32 0x000000CB +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_A8R8G8B8 0x000000CF +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_A2R10G10B10 0x000000DF +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_A8B8G8R8 0x000000D5 +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_A2B10G10R10 0x000000D1 +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_X8R8G8B8 0x000000E6 +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_X8B8G8R8 0x000000F9 +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_R5G6B5 0x000000E8 +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_A1R5G5B5 0x000000E9 +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_X1R5G5B5 0x000000F8 +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_Y8 0x000000F3 +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_Y16 0x000000EE +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_Y32 0x000000FF +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_Z1R5G5B5 0x000000FB +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_O1R5G5B5 0x000000FC +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_Z8R8G8B8 0x000000FD +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_FORMAT_V_O8R8G8B8 0x000000FE + +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR 0x0588 +#define NV902D_SET_RENDER_SOLID_PRIM_COLOR_V 31:0 + +#define NV902D_RENDER_SOLID_PRIM_POINT_SET_X(j) (0x0600+(j)*8) +#define NV902D_RENDER_SOLID_PRIM_POINT_SET_X_V 31:0 + +#define NV902D_RENDER_SOLID_PRIM_POINT_Y(j) (0x0604+(j)*8) +#define NV902D_RENDER_SOLID_PRIM_POINT_Y_V 31:0 + +#define NV902D_SET_PIXELS_FROM_CPU_DATA_TYPE 0x0800 +#define NV902D_SET_PIXELS_FROM_CPU_DATA_TYPE_V 0:0 +#define NV902D_SET_PIXELS_FROM_CPU_DATA_TYPE_V_COLOR 0x00000000 +#define NV902D_SET_PIXELS_FROM_CPU_DATA_TYPE_V_INDEX 0x00000001 + +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT 0x0804 +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V 7:0 +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_A8R8G8B8 0x000000CF +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_A2R10G10B10 0x000000DF +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_A8B8G8R8 0x000000D5 +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_A2B10G10R10 0x000000D1 +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_X8R8G8B8 0x000000E6 +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_X8B8G8R8 0x000000F9 +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_R5G6B5 0x000000E8 +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_A1R5G5B5 0x000000E9 +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_X1R5G5B5 0x000000F8 +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_Y8 0x000000F3 +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_Y16 0x000000EE +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_Y32 0x000000FF +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_Z1R5G5B5 0x000000FB +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_O1R5G5B5 0x000000FC +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_Z8R8G8B8 0x000000FD +#define NV902D_SET_PIXELS_FROM_CPU_COLOR_FORMAT_V_O8R8G8B8 0x000000FE + +#define NV902D_SET_PIXELS_FROM_CPU_INDEX_FORMAT 0x0808 +#define NV902D_SET_PIXELS_FROM_CPU_INDEX_FORMAT_V 1:0 +#define NV902D_SET_PIXELS_FROM_CPU_INDEX_FORMAT_V_I1 0x00000000 +#define NV902D_SET_PIXELS_FROM_CPU_INDEX_FORMAT_V_I4 0x00000001 +#define NV902D_SET_PIXELS_FROM_CPU_INDEX_FORMAT_V_I8 0x00000002 + +#define NV902D_SET_PIXELS_FROM_CPU_MONO_FORMAT 0x080c +#define NV902D_SET_PIXELS_FROM_CPU_MONO_FORMAT_V 0:0 +#define NV902D_SET_PIXELS_FROM_CPU_MONO_FORMAT_V_CGA6_M1 0x00000000 +#define NV902D_SET_PIXELS_FROM_CPU_MONO_FORMAT_V_LE_M1 0x00000001 + +#define NV902D_SET_PIXELS_FROM_CPU_WRAP 0x0810 +#define NV902D_SET_PIXELS_FROM_CPU_WRAP_V 1:0 +#define NV902D_SET_PIXELS_FROM_CPU_WRAP_V_WRAP_PIXEL 0x00000000 +#define NV902D_SET_PIXELS_FROM_CPU_WRAP_V_WRAP_BYTE 0x00000001 +#define NV902D_SET_PIXELS_FROM_CPU_WRAP_V_WRAP_DWORD 0x00000002 + +#define NV902D_SET_PIXELS_FROM_CPU_COLOR0 0x0814 +#define NV902D_SET_PIXELS_FROM_CPU_COLOR0_V 31:0 + +#define NV902D_SET_PIXELS_FROM_CPU_COLOR1 0x0818 +#define NV902D_SET_PIXELS_FROM_CPU_COLOR1_V 31:0 + +#define NV902D_SET_PIXELS_FROM_CPU_MONO_OPACITY 0x081c +#define NV902D_SET_PIXELS_FROM_CPU_MONO_OPACITY_V 0:0 +#define NV902D_SET_PIXELS_FROM_CPU_MONO_OPACITY_V_TRANSPARENT 0x00000000 +#define NV902D_SET_PIXELS_FROM_CPU_MONO_OPACITY_V_OPAQUE 0x00000001 + +#define NV902D_SET_PIXELS_FROM_CPU_SRC_WIDTH 0x0838 +#define NV902D_SET_PIXELS_FROM_CPU_SRC_WIDTH_V 31:0 + +#define NV902D_SET_PIXELS_FROM_CPU_SRC_HEIGHT 0x083c +#define NV902D_SET_PIXELS_FROM_CPU_SRC_HEIGHT_V 31:0 + +#define NV902D_SET_PIXELS_FROM_CPU_DX_DU_FRAC 0x0840 +#define NV902D_SET_PIXELS_FROM_CPU_DX_DU_FRAC_V 31:0 + +#define NV902D_SET_PIXELS_FROM_CPU_DX_DU_INT 0x0844 +#define NV902D_SET_PIXELS_FROM_CPU_DX_DU_INT_V 31:0 + +#define NV902D_SET_PIXELS_FROM_CPU_DY_DV_FRAC 0x0848 +#define NV902D_SET_PIXELS_FROM_CPU_DY_DV_FRAC_V 31:0 + +#define NV902D_SET_PIXELS_FROM_CPU_DY_DV_INT 0x084c +#define NV902D_SET_PIXELS_FROM_CPU_DY_DV_INT_V 31:0 + +#define NV902D_SET_PIXELS_FROM_CPU_DST_X0_FRAC 0x0850 +#define NV902D_SET_PIXELS_FROM_CPU_DST_X0_FRAC_V 31:0 + +#define NV902D_SET_PIXELS_FROM_CPU_DST_X0_INT 0x0854 +#define NV902D_SET_PIXELS_FROM_CPU_DST_X0_INT_V 31:0 + +#define NV902D_SET_PIXELS_FROM_CPU_DST_Y0_FRAC 0x0858 +#define NV902D_SET_PIXELS_FROM_CPU_DST_Y0_FRAC_V 31:0 + +#define NV902D_SET_PIXELS_FROM_CPU_DST_Y0_INT 0x085c +#define NV902D_SET_PIXELS_FROM_CPU_DST_Y0_INT_V 31:0 + +#define NV902D_PIXELS_FROM_CPU_DATA 0x0860 +#define NV902D_PIXELS_FROM_CPU_DATA_V 31:0 + +#define NV902D_SET_PIXELS_FROM_MEMORY_SAFE_OVERLAP 0x0888 +#define NV902D_SET_PIXELS_FROM_MEMORY_SAFE_OVERLAP_V 0:0 +#define NV902D_SET_PIXELS_FROM_MEMORY_SAFE_OVERLAP_V_FALSE 0x00000000 +#define NV902D_SET_PIXELS_FROM_MEMORY_SAFE_OVERLAP_V_TRUE 0x00000001 + +#define NV902D_SET_PIXELS_FROM_MEMORY_DST_X0 0x08b0 +#define NV902D_SET_PIXELS_FROM_MEMORY_DST_X0_V 31:0 + +#define NV902D_SET_PIXELS_FROM_MEMORY_DST_Y0 0x08b4 +#define NV902D_SET_PIXELS_FROM_MEMORY_DST_Y0_V 31:0 + +#define NV902D_SET_PIXELS_FROM_MEMORY_DST_WIDTH 0x08b8 +#define NV902D_SET_PIXELS_FROM_MEMORY_DST_WIDTH_V 31:0 + +#define NV902D_SET_PIXELS_FROM_MEMORY_DST_HEIGHT 0x08bc +#define NV902D_SET_PIXELS_FROM_MEMORY_DST_HEIGHT_V 31:0 + +#define NV902D_SET_PIXELS_FROM_MEMORY_DU_DX_FRAC 0x08c0 +#define NV902D_SET_PIXELS_FROM_MEMORY_DU_DX_FRAC_V 31:0 + +#define NV902D_SET_PIXELS_FROM_MEMORY_DU_DX_INT 0x08c4 +#define NV902D_SET_PIXELS_FROM_MEMORY_DU_DX_INT_V 31:0 + +#define NV902D_SET_PIXELS_FROM_MEMORY_DV_DY_FRAC 0x08c8 +#define NV902D_SET_PIXELS_FROM_MEMORY_DV_DY_FRAC_V 31:0 + +#define NV902D_SET_PIXELS_FROM_MEMORY_DV_DY_INT 0x08cc +#define NV902D_SET_PIXELS_FROM_MEMORY_DV_DY_INT_V 31:0 + +#define NV902D_SET_PIXELS_FROM_MEMORY_SRC_X0_FRAC 0x08d0 +#define NV902D_SET_PIXELS_FROM_MEMORY_SRC_X0_FRAC_V 31:0 + +#define NV902D_SET_PIXELS_FROM_MEMORY_SRC_X0_INT 0x08d4 +#define NV902D_SET_PIXELS_FROM_MEMORY_SRC_X0_INT_V 31:0 + +#define NV902D_SET_PIXELS_FROM_MEMORY_SRC_Y0_FRAC 0x08d8 +#define NV902D_SET_PIXELS_FROM_MEMORY_SRC_Y0_FRAC_V 31:0 + +#define NV902D_PIXELS_FROM_MEMORY_SRC_Y0_INT 0x08dc +#define NV902D_PIXELS_FROM_MEMORY_SRC_Y0_INT_V 31:0 +#endif /* _cl_fermi_twod_a_h_ */ diff --git a/drivers/gpu/drm/nouveau/nv50_fbcon.c b/drivers/gpu/drm/nouveau/nv50_fbcon.c index cbdd473acd9f..9001b30f7214 100644 --- a/drivers/gpu/drm/nouveau/nv50_fbcon.c +++ b/drivers/gpu/drm/nouveau/nv50_fbcon.c @@ -29,6 +29,8 @@ #include +#include + int nv50_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect) { @@ -160,22 +162,22 @@ nv50_fbcon_accel_init(struct fb_info *info) switch (info->var.bits_per_pixel) { case 8: - format = 0xf3; + format = NV502D_SET_DST_FORMAT_V_Y8; break; case 15: - format = 0xf8; + format = NV502D_SET_DST_FORMAT_V_X1R5G5B5; break; case 16: - format = 0xe8; + format = NV502D_SET_DST_FORMAT_V_R5G6B5; break; case 32: switch (info->var.transp.length) { case 0: /* depth 24 */ case 8: /* depth 32, just use 24.. */ - format = 0xe6; + format = NV502D_SET_DST_FORMAT_V_X8R8G8B8; break; case 2: /* depth 30 */ - format = 0xd1; + format = NV502D_SET_DST_FORMAT_V_A2B10G10R10; break; default: return -EINVAL; @@ -196,53 +198,94 @@ nv50_fbcon_accel_init(struct fb_info *info) return ret; } - PUSH_NVSQ(push, NV502D, 0x0000, nfbdev->twod.handle); - PUSH_NVSQ(push, NV502D, 0x0184, chan->vram.handle, - 0x0188, chan->vram.handle, - 0x018c, chan->vram.handle); + PUSH_MTHD(push, NV502D, SET_OBJECT, nfbdev->twod.handle); + PUSH_MTHD(push, NV502D, SET_DST_CONTEXT_DMA, chan->vram.handle, + SET_SRC_CONTEXT_DMA, chan->vram.handle, + SET_SEMAPHORE_CONTEXT_DMA, chan->vram.handle); - PUSH_NVSQ(push, NV502D, 0x0200, format, - 0x0204, 1); - PUSH_NVSQ(push, NV502D, 0x0214, info->fix.line_length, - 0x0218, info->var.xres_virtual, - 0x021c, info->var.yres_virtual, - 0x0220, upper_32_bits(nfbdev->vma->addr), - 0x0224, lower_32_bits(nfbdev->vma->addr)); + PUSH_MTHD(push, NV502D, SET_DST_FORMAT, + NVVAL(NV502D, SET_DST_FORMAT, V, format), - PUSH_NVSQ(push, NV502D, 0x0230, format, - 0x0234, 1); - PUSH_NVSQ(push, NV502D, 0x0244, info->fix.line_length, - 0x0248, info->var.xres_virtual, - 0x024c, info->var.yres_virtual, - 0x0250, upper_32_bits(nfbdev->vma->addr), - 0x0254, lower_32_bits(nfbdev->vma->addr)); + SET_DST_MEMORY_LAYOUT, + NVDEF(NV502D, SET_DST_MEMORY_LAYOUT, V, PITCH)); - PUSH_NVSQ(push, NV502D, 0x0290, 0); - PUSH_NVSQ(push, NV502D, 0x02a0, 0x55); - PUSH_NVSQ(push, NV502D, 0x02ac, 3); - PUSH_NVSQ(push, NV502D, 0x02e8, 2, - 0x02ec, 1); + PUSH_MTHD(push, NV502D, SET_DST_PITCH, info->fix.line_length, + SET_DST_WIDTH, info->var.xres_virtual, + SET_DST_HEIGHT, info->var.yres_virtual, - PUSH_NVSQ(push, NV502D, 0X0580, 4, - 0x0584, format); + SET_DST_OFFSET_UPPER, + NVVAL(NV502D, SET_DST_OFFSET_UPPER, V, upper_32_bits(nfbdev->vma->addr)), - PUSH_NVSQ(push, NV502D, 0x0800, 1, - 0x0804, format, - 0x0808, 0, - 0x080c, 0, - 0x0810, 1); - PUSH_NVSQ(push, NV502D, 0x081c, 1); - PUSH_NVSQ(push, NV502D, 0x0840, 0, - 0x0844, 1, - 0x0848, 0, - 0x084c, 1); + SET_DST_OFFSET_LOWER, + NVVAL(NV502D, SET_DST_OFFSET_LOWER, V, lower_32_bits(nfbdev->vma->addr))); - PUSH_NVSQ(push, NV502D, 0x0888, 1); - PUSH_NVSQ(push, NV502D, 0x08c0, 0, - 0x08c4, 1, - 0x08c8, 0, - 0x08cc, 1); + PUSH_MTHD(push, NV502D, SET_SRC_FORMAT, + NVVAL(NV502D, SET_SRC_FORMAT, V, format), + SET_SRC_MEMORY_LAYOUT, + NVDEF(NV502D, SET_SRC_MEMORY_LAYOUT, V, PITCH)); + + PUSH_MTHD(push, NV502D, SET_SRC_PITCH, info->fix.line_length, + SET_SRC_WIDTH, info->var.xres_virtual, + SET_SRC_HEIGHT, info->var.yres_virtual, + + SET_SRC_OFFSET_UPPER, + NVVAL(NV502D, SET_SRC_OFFSET_UPPER, V, upper_32_bits(nfbdev->vma->addr)), + + SET_SRC_OFFSET_LOWER, + NVVAL(NV502D, SET_SRC_OFFSET_LOWER, V, lower_32_bits(nfbdev->vma->addr))); + + PUSH_MTHD(push, NV502D, SET_CLIP_ENABLE, + NVDEF(NV502D, SET_CLIP_ENABLE, V, FALSE)); + + PUSH_MTHD(push, NV502D, SET_ROP, + NVVAL(NV502D, SET_ROP, V, 0x55)); + + PUSH_MTHD(push, NV502D, SET_OPERATION, + NVDEF(NV502D, SET_OPERATION, V, SRCCOPY)); + + PUSH_MTHD(push, NV502D, SET_MONOCHROME_PATTERN_COLOR_FORMAT, + NVDEF(NV502D, SET_MONOCHROME_PATTERN_COLOR_FORMAT, V, A8R8G8B8), + + SET_MONOCHROME_PATTERN_FORMAT, + NVDEF(NV502D, SET_MONOCHROME_PATTERN_FORMAT, V, LE_M1)); + + PUSH_MTHD(push, NV502D, RENDER_SOLID_PRIM_MODE, + NVDEF(NV502D, RENDER_SOLID_PRIM_MODE, V, RECTS), + + SET_RENDER_SOLID_PRIM_COLOR_FORMAT, + NVVAL(NV502D, SET_RENDER_SOLID_PRIM_COLOR_FORMAT, V, format)); + + PUSH_MTHD(push, NV502D, SET_PIXELS_FROM_CPU_DATA_TYPE, + NVDEF(NV502D, SET_PIXELS_FROM_CPU_DATA_TYPE, V, INDEX), + + SET_PIXELS_FROM_CPU_COLOR_FORMAT, + NVVAL(NV502D, SET_PIXELS_FROM_CPU_COLOR_FORMAT, V, format), + + SET_PIXELS_FROM_CPU_INDEX_FORMAT, + NVDEF(NV502D, SET_PIXELS_FROM_CPU_INDEX_FORMAT, V, I1), + + SET_PIXELS_FROM_CPU_MONO_FORMAT, + NVDEF(NV502D, SET_PIXELS_FROM_CPU_MONO_FORMAT, V, CGA6_M1), + + SET_PIXELS_FROM_CPU_WRAP, + NVDEF(NV502D, SET_PIXELS_FROM_CPU_WRAP, V, WRAP_BYTE)); + + PUSH_MTHD(push, NV502D, SET_PIXELS_FROM_CPU_MONO_OPACITY, + NVDEF(NV502D, SET_PIXELS_FROM_CPU_MONO_OPACITY, V, OPAQUE)); + + PUSH_MTHD(push, NV502D, SET_PIXELS_FROM_CPU_DX_DU_FRAC, 0, + SET_PIXELS_FROM_CPU_DX_DU_INT, 1, + SET_PIXELS_FROM_CPU_DY_DV_FRAC, 0, + SET_PIXELS_FROM_CPU_DY_DV_INT, 1); + + PUSH_MTHD(push, NV502D, SET_PIXELS_FROM_MEMORY_SAFE_OVERLAP, + NVDEF(NV502D, SET_PIXELS_FROM_MEMORY_SAFE_OVERLAP, V, TRUE)); + + PUSH_MTHD(push, NV502D, SET_PIXELS_FROM_MEMORY_DU_DX_FRAC, 0, + SET_PIXELS_FROM_MEMORY_DU_DX_INT, 1, + SET_PIXELS_FROM_MEMORY_DV_DY_FRAC, 0, + SET_PIXELS_FROM_MEMORY_DV_DY_INT, 1); PUSH_KICK(push); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvc0_fbcon.c b/drivers/gpu/drm/nouveau/nvc0_fbcon.c index ab1dbf03de7b..1f4ca42b940e 100644 --- a/drivers/gpu/drm/nouveau/nvc0_fbcon.c +++ b/drivers/gpu/drm/nouveau/nvc0_fbcon.c @@ -29,6 +29,8 @@ #include +#include + int nvc0_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect) { @@ -165,22 +167,22 @@ nvc0_fbcon_accel_init(struct fb_info *info) switch (info->var.bits_per_pixel) { case 8: - format = 0xf3; + format = NV902D_SET_DST_FORMAT_V_Y8; break; case 15: - format = 0xf8; + format = NV902D_SET_DST_FORMAT_V_X1R5G5B5; break; case 16: - format = 0xe8; + format = NV902D_SET_DST_FORMAT_V_R5G6B5; break; case 32: switch (info->var.transp.length) { case 0: /* depth 24 */ case 8: /* depth 32, just use 24.. */ - format = 0xe6; + format = NV902D_SET_DST_FORMAT_V_X8R8G8B8; break; case 2: /* depth 30 */ - format = 0xd1; + format = NV902D_SET_DST_FORMAT_V_A2B10G10R10; break; default: return -EINVAL; @@ -197,50 +199,91 @@ nvc0_fbcon_accel_init(struct fb_info *info) return ret; } - PUSH_NVSQ(push, NV902D, 0x0000, nfbdev->twod.handle); + PUSH_MTHD(push, NV902D, SET_OBJECT, nfbdev->twod.handle); - PUSH_NVSQ(push, NV902D, 0x0200, format, - 0x0204, 1); - PUSH_NVSQ(push, NV902D, 0x0214, info->fix.line_length, - 0x0218, info->var.xres_virtual, - 0x021c, info->var.yres_virtual, - 0x0220, upper_32_bits(nfbdev->vma->addr), - 0x0224, lower_32_bits(nfbdev->vma->addr)); + PUSH_MTHD(push, NV902D, SET_DST_FORMAT, + NVVAL(NV902D, SET_DST_FORMAT, V, format), - PUSH_NVSQ(push, NV902D, 0x0230, format, - 0x0234, 1); - PUSH_NVSQ(push, NV902D, 0x0244, info->fix.line_length, - 0x0248, info->var.xres_virtual, - 0x024c, info->var.yres_virtual, - 0x0250, upper_32_bits(nfbdev->vma->addr), - 0x0254, lower_32_bits(nfbdev->vma->addr)); + SET_DST_MEMORY_LAYOUT, + NVDEF(NV902D, SET_DST_MEMORY_LAYOUT, V, PITCH)); - PUSH_NVIM(push, NV902D, 0x0290, 0); - PUSH_NVIM(push, NV902D, 0x02a0, 0x55); - PUSH_NVIM(push, NV902D, 0x02ac, 3); - PUSH_NVSQ(push, NV902D, 0x02e8, 2, - 0x02ec, 1); + PUSH_MTHD(push, NV902D, SET_DST_PITCH, info->fix.line_length, + SET_DST_WIDTH, info->var.xres_virtual, + SET_DST_HEIGHT, info->var.yres_virtual, - PUSH_NVSQ(push, NV902D, 0X0580, 4, - 0x0584, format); + SET_DST_OFFSET_UPPER, + NVVAL(NV902D, SET_DST_OFFSET_UPPER, V, upper_32_bits(nfbdev->vma->addr)), - PUSH_NVSQ(push, NV902D, 0x0800, 1, - 0x0804, format, - 0x0808, 0, - 0x080c, 0, - 0x0810, 1); - PUSH_NVIM(push, NV902D, 0x081c, 1); - PUSH_NVSQ(push, NV902D, 0x0840, 0, - 0x0844, 1, - 0x0848, 0, - 0x084c, 1); + SET_DST_OFFSET_LOWER, + NVVAL(NV902D, SET_DST_OFFSET_LOWER, V, lower_32_bits(nfbdev->vma->addr))); - PUSH_NVIM(push, NV902D, 0x0888, 1); - PUSH_NVSQ(push, NV902D, 0x08c0, 0, - 0x08c4, 1, - 0x08c8, 0, - 0x08cc, 1); + PUSH_MTHD(push, NV902D, SET_SRC_FORMAT, + NVVAL(NV902D, SET_SRC_FORMAT, V, format), + SET_SRC_MEMORY_LAYOUT, + NVDEF(NV902D, SET_SRC_MEMORY_LAYOUT, V, PITCH)); + + PUSH_MTHD(push, NV902D, SET_SRC_PITCH, info->fix.line_length, + SET_SRC_WIDTH, info->var.xres_virtual, + SET_SRC_HEIGHT, info->var.yres_virtual, + + SET_SRC_OFFSET_UPPER, + NVVAL(NV902D, SET_SRC_OFFSET_UPPER, V, upper_32_bits(nfbdev->vma->addr)), + + SET_SRC_OFFSET_LOWER, + NVVAL(NV902D, SET_SRC_OFFSET_LOWER, V, lower_32_bits(nfbdev->vma->addr))); + + PUSH_IMMD(push, NV902D, SET_CLIP_ENABLE, + NVDEF(NV902D, SET_CLIP_ENABLE, V, FALSE)); + + PUSH_IMMD(push, NV902D, SET_ROP, + NVVAL(NV902D, SET_ROP, V, 0x55)); + + PUSH_IMMD(push, NV902D, SET_OPERATION, + NVDEF(NV902D, SET_OPERATION, V, SRCCOPY)); + + PUSH_MTHD(push, NV902D, SET_MONOCHROME_PATTERN_COLOR_FORMAT, + NVDEF(NV902D, SET_MONOCHROME_PATTERN_COLOR_FORMAT, V, A8R8G8B8), + + SET_MONOCHROME_PATTERN_FORMAT, + NVDEF(NV902D, SET_MONOCHROME_PATTERN_FORMAT, V, LE_M1)); + + PUSH_MTHD(push, NV902D, RENDER_SOLID_PRIM_MODE, + NVDEF(NV902D, RENDER_SOLID_PRIM_MODE, V, RECTS), + + SET_RENDER_SOLID_PRIM_COLOR_FORMAT, + NVVAL(NV902D, SET_RENDER_SOLID_PRIM_COLOR_FORMAT, V, format)); + + PUSH_MTHD(push, NV902D, SET_PIXELS_FROM_CPU_DATA_TYPE, + NVDEF(NV902D, SET_PIXELS_FROM_CPU_DATA_TYPE, V, INDEX), + + SET_PIXELS_FROM_CPU_COLOR_FORMAT, + NVVAL(NV902D, SET_PIXELS_FROM_CPU_COLOR_FORMAT, V, format), + + SET_PIXELS_FROM_CPU_INDEX_FORMAT, + NVDEF(NV902D, SET_PIXELS_FROM_CPU_INDEX_FORMAT, V, I1), + + SET_PIXELS_FROM_CPU_MONO_FORMAT, + NVDEF(NV902D, SET_PIXELS_FROM_CPU_MONO_FORMAT, V, CGA6_M1), + + SET_PIXELS_FROM_CPU_WRAP, + NVDEF(NV902D, SET_PIXELS_FROM_CPU_WRAP, V, WRAP_BYTE)); + + PUSH_IMMD(push, NV902D, SET_PIXELS_FROM_CPU_MONO_OPACITY, + NVDEF(NV902D, SET_PIXELS_FROM_CPU_MONO_OPACITY, V, OPAQUE)); + + PUSH_MTHD(push, NV902D, SET_PIXELS_FROM_CPU_DX_DU_FRAC, 0, + SET_PIXELS_FROM_CPU_DX_DU_INT, 1, + SET_PIXELS_FROM_CPU_DY_DV_FRAC, 0, + SET_PIXELS_FROM_CPU_DY_DV_INT, 1); + + PUSH_IMMD(push, NV902D, SET_PIXELS_FROM_MEMORY_SAFE_OVERLAP, + NVDEF(NV902D, SET_PIXELS_FROM_MEMORY_SAFE_OVERLAP, V, TRUE)); + + PUSH_MTHD(push, NV902D, SET_PIXELS_FROM_MEMORY_DU_DX_FRAC, 0, + SET_PIXELS_FROM_MEMORY_DU_DX_INT, 1, + SET_PIXELS_FROM_MEMORY_DV_DY_FRAC, 0, + SET_PIXELS_FROM_MEMORY_DV_DY_INT, 1); PUSH_KICK(push); return 0; } From c7acff989428533f5877f02f57c97743ece6f1f0 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 22 Jun 2020 14:12:07 +1000 Subject: [PATCH 135/145] drm/nouveau/fbcon/nv50-: use NVIDIA's headers for imageblit() Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/nv50_fbcon.c | 20 +++++++++++--------- drivers/gpu/drm/nouveau/nvc0_fbcon.c | 20 +++++++++++--------- 2 files changed, 22 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nv50_fbcon.c b/drivers/gpu/drm/nouveau/nv50_fbcon.c index 9001b30f7214..d99679086043 100644 --- a/drivers/gpu/drm/nouveau/nv50_fbcon.c +++ b/drivers/gpu/drm/nouveau/nv50_fbcon.c @@ -123,14 +123,16 @@ nv50_fbcon_imageblit(struct fb_info *info, const struct fb_image *image) if (ret) return ret; - PUSH_NVSQ(push, NV502D, 0x0814, bg, - 0x0818, fg); - PUSH_NVSQ(push, NV502D, 0x0838, image->width, - 0x083c, image->height); - PUSH_NVSQ(push, NV502D, 0x0850, 0, - 0x0854, image->dx, - 0x0858, 0, - 0x085c, image->dy); + PUSH_MTHD(push, NV502D, SET_PIXELS_FROM_CPU_COLOR0, bg, + SET_PIXELS_FROM_CPU_COLOR1, fg); + + PUSH_MTHD(push, NV502D, SET_PIXELS_FROM_CPU_SRC_WIDTH, image->width, + SET_PIXELS_FROM_CPU_SRC_HEIGHT, image->height); + + PUSH_MTHD(push, NV502D, SET_PIXELS_FROM_CPU_DST_X0_FRAC, 0, + SET_PIXELS_FROM_CPU_DST_X0_INT, image->dx, + SET_PIXELS_FROM_CPU_DST_Y0_FRAC, 0, + SET_PIXELS_FROM_CPU_DST_Y0_INT, image->dy); dwords = ALIGN(ALIGN(image->width, 8) * image->height, 32) >> 5; while (dwords) { @@ -142,7 +144,7 @@ nv50_fbcon_imageblit(struct fb_info *info, const struct fb_image *image) dwords -= count; - PUSH_NVNI(push, NV502D, 0x0860, data, count); + PUSH_NINC(push, NV502D, PIXELS_FROM_CPU_DATA, data, count); data += count; } diff --git a/drivers/gpu/drm/nouveau/nvc0_fbcon.c b/drivers/gpu/drm/nouveau/nvc0_fbcon.c index 1f4ca42b940e..dd8e3e65ad84 100644 --- a/drivers/gpu/drm/nouveau/nvc0_fbcon.c +++ b/drivers/gpu/drm/nouveau/nvc0_fbcon.c @@ -123,14 +123,16 @@ nvc0_fbcon_imageblit(struct fb_info *info, const struct fb_image *image) if (ret) return ret; - PUSH_NVSQ(push, NV902D, 0x0814, bg, - 0x0818, fg); - PUSH_NVSQ(push, NV902D, 0x0838, image->width, - 0x083c, image->height); - PUSH_NVSQ(push, NV902D, 0x0850, 0, - 0x0854, image->dx, - 0x0858, 0, - 0x085c, image->dy); + PUSH_MTHD(push, NV902D, SET_PIXELS_FROM_CPU_COLOR0, bg, + SET_PIXELS_FROM_CPU_COLOR1, fg); + + PUSH_MTHD(push, NV902D, SET_PIXELS_FROM_CPU_SRC_WIDTH, image->width, + SET_PIXELS_FROM_CPU_SRC_HEIGHT, image->height); + + PUSH_MTHD(push, NV902D, SET_PIXELS_FROM_CPU_DST_X0_FRAC, 0, + SET_PIXELS_FROM_CPU_DST_X0_INT, image->dx, + SET_PIXELS_FROM_CPU_DST_Y0_FRAC, 0, + SET_PIXELS_FROM_CPU_DST_Y0_INT, image->dy); dwords = ALIGN(ALIGN(image->width, 8) * image->height, 32) >> 5; while (dwords) { @@ -142,7 +144,7 @@ nvc0_fbcon_imageblit(struct fb_info *info, const struct fb_image *image) dwords -= count; - PUSH_NVNI(push, NV902D, 0x0860, data, count); + PUSH_NINC(push, NV902D, PIXELS_FROM_CPU_DATA, data, count); data += count; } From 95b1469e5cbaad02bc48043d4e159c6562b556b4 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 22 Jun 2020 14:16:03 +1000 Subject: [PATCH 136/145] drm/nouveau/fbcon/nv50-: use NVIDIA's headers for copyarea() Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/nv50_fbcon.c | 20 +++++++++++--------- drivers/gpu/drm/nouveau/nvc0_fbcon.c | 20 +++++++++++--------- 2 files changed, 22 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nv50_fbcon.c b/drivers/gpu/drm/nouveau/nv50_fbcon.c index d99679086043..abab600056ae 100644 --- a/drivers/gpu/drm/nouveau/nv50_fbcon.c +++ b/drivers/gpu/drm/nouveau/nv50_fbcon.c @@ -82,15 +82,17 @@ nv50_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *region) if (ret) return ret; - PUSH_NVSQ(push, NV502D, 0x0110, 0); - PUSH_NVSQ(push, NV502D, 0x08b0, region->dx, - 0x08b4, region->dy, - 0x08b8, region->width, - 0x08bc, region->height); - PUSH_NVSQ(push, NV502D, 0x08d0, 0, - 0x08d4, region->sx, - 0x08d8, 0, - 0x08dc, region->sy); + PUSH_MTHD(push, NV502D, WAIT_FOR_IDLE, 0); + + PUSH_MTHD(push, NV502D, SET_PIXELS_FROM_MEMORY_DST_X0, region->dx, + SET_PIXELS_FROM_MEMORY_DST_Y0, region->dy, + SET_PIXELS_FROM_MEMORY_DST_WIDTH, region->width, + SET_PIXELS_FROM_MEMORY_DST_HEIGHT, region->height); + + PUSH_MTHD(push, NV502D, SET_PIXELS_FROM_MEMORY_SRC_X0_FRAC, 0, + SET_PIXELS_FROM_MEMORY_SRC_X0_INT, region->sx, + SET_PIXELS_FROM_MEMORY_SRC_Y0_FRAC, 0, + PIXELS_FROM_MEMORY_SRC_Y0_INT, region->sy); PUSH_KICK(push); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvc0_fbcon.c b/drivers/gpu/drm/nouveau/nvc0_fbcon.c index dd8e3e65ad84..4a09b7ecb30a 100644 --- a/drivers/gpu/drm/nouveau/nvc0_fbcon.c +++ b/drivers/gpu/drm/nouveau/nvc0_fbcon.c @@ -82,15 +82,17 @@ nvc0_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *region) if (ret) return ret; - PUSH_NVIM(push, NV902D, 0x0110, 0); - PUSH_NVSQ(push, NV902D, 0x08b0, region->dx, - 0x08b4, region->dy, - 0x08b8, region->width, - 0x08bc, region->height); - PUSH_NVSQ(push, NV902D, 0x08d0, 0, - 0x08d4, region->sx, - 0x08d8, 0, - 0x08dc, region->sy); + PUSH_IMMD(push, NV902D, WAIT_FOR_IDLE, 0); + + PUSH_MTHD(push, NV902D, SET_PIXELS_FROM_MEMORY_DST_X0, region->dx, + SET_PIXELS_FROM_MEMORY_DST_Y0, region->dy, + SET_PIXELS_FROM_MEMORY_DST_WIDTH, region->width, + SET_PIXELS_FROM_MEMORY_DST_HEIGHT, region->height); + + PUSH_MTHD(push, NV902D, SET_PIXELS_FROM_MEMORY_SRC_X0_FRAC, 0, + SET_PIXELS_FROM_MEMORY_SRC_X0_INT, region->sx, + SET_PIXELS_FROM_MEMORY_SRC_Y0_FRAC, 0, + PIXELS_FROM_MEMORY_SRC_Y0_INT, region->sy); PUSH_KICK(push); return 0; } From a38f83d9014d14b7c6d0b53fd669b62684a11059 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 22 Jun 2020 14:27:41 +1000 Subject: [PATCH 137/145] drm/nouveau/fbcon/nv50-: use NVIDIA's headers for fillrect() Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/nv50_fbcon.c | 17 ++++++++++------- drivers/gpu/drm/nouveau/nvc0_fbcon.c | 17 ++++++++++------- 2 files changed, 20 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nv50_fbcon.c b/drivers/gpu/drm/nouveau/nv50_fbcon.c index abab600056ae..71f92e4750f9 100644 --- a/drivers/gpu/drm/nouveau/nv50_fbcon.c +++ b/drivers/gpu/drm/nouveau/nv50_fbcon.c @@ -52,17 +52,20 @@ nv50_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect) return ret; if (rect->rop != ROP_COPY) { - PUSH_NVSQ(push, NV502D, 0x02ac, 1); + PUSH_MTHD(push, NV502D, SET_OPERATION, + NVDEF(NV502D, SET_OPERATION, V, ROP_AND)); } - PUSH_NVSQ(push, NV502D, 0x0588, colour); - PUSH_NVSQ(push, NV502D, 0x0600, rect->dx, - 0x0604, rect->dy, - 0x0608, rect->dx + rect->width, - 0x060c, rect->dy + rect->height); + PUSH_MTHD(push, NV502D, SET_RENDER_SOLID_PRIM_COLOR, colour); + + PUSH_MTHD(push, NV502D, RENDER_SOLID_PRIM_POINT_SET_X(0), rect->dx, + RENDER_SOLID_PRIM_POINT_Y(0), rect->dy, + RENDER_SOLID_PRIM_POINT_SET_X(1), rect->dx + rect->width, + RENDER_SOLID_PRIM_POINT_Y(1), rect->dy + rect->height); if (rect->rop != ROP_COPY) { - PUSH_NVSQ(push, NV502D, 0x02ac, 3); + PUSH_MTHD(push, NV502D, SET_OPERATION, + NVDEF(NV502D, SET_OPERATION, V, SRCCOPY)); } PUSH_KICK(push); diff --git a/drivers/gpu/drm/nouveau/nvc0_fbcon.c b/drivers/gpu/drm/nouveau/nvc0_fbcon.c index 4a09b7ecb30a..7908a1a3e00f 100644 --- a/drivers/gpu/drm/nouveau/nvc0_fbcon.c +++ b/drivers/gpu/drm/nouveau/nvc0_fbcon.c @@ -52,17 +52,20 @@ nvc0_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect) return ret; if (rect->rop != ROP_COPY) { - PUSH_NVIM(push, NV902D, 0x02ac, 1); + PUSH_IMMD(push, NV902D, SET_OPERATION, + NVDEF(NV902D, SET_OPERATION, V, ROP_AND)); } - PUSH_NVSQ(push, NV902D, 0x0588, colour); - PUSH_NVSQ(push, NV902D, 0x0600, rect->dx, - 0x0604, rect->dy, - 0x0608, rect->dx + rect->width, - 0x060c, rect->dy + rect->height); + PUSH_MTHD(push, NV902D, SET_RENDER_SOLID_PRIM_COLOR, colour); + + PUSH_MTHD(push, NV902D, RENDER_SOLID_PRIM_POINT_SET_X(0), rect->dx, + RENDER_SOLID_PRIM_POINT_Y(0), rect->dy, + RENDER_SOLID_PRIM_POINT_SET_X(1), rect->dx + rect->width, + RENDER_SOLID_PRIM_POINT_Y(1), rect->dy + rect->height); if (rect->rop != ROP_COPY) { - PUSH_NVIM(push, NV902D, 0x02ac, 3); + PUSH_IMMD(push, NV902D, SET_OPERATION, + NVDEF(NV902D, SET_OPERATION, V, SRCCOPY)); } PUSH_KICK(push); From e767835a52cd6d427a4ab6941118e530cbfa638c Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 22 Jun 2020 16:29:45 +1000 Subject: [PATCH 138/145] drm/nouveau/bo: use NVIDIA's headers for move init() Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- .../drm/nouveau/include/nvhw/class/cl0039.h | 45 ++++++ .../drm/nouveau/include/nvhw/class/cl5039.h | 153 ++++++++++++++++++ .../drm/nouveau/include/nvhw/class/cl9039.h | 74 +++++++++ drivers/gpu/drm/nouveau/nouveau_bo0039.c | 6 +- drivers/gpu/drm/nouveau/nouveau_bo5039.c | 10 +- drivers/gpu/drm/nouveau/nouveau_bo9039.c | 4 +- 6 files changed, 285 insertions(+), 7 deletions(-) create mode 100644 drivers/gpu/drm/nouveau/include/nvhw/class/cl0039.h create mode 100644 drivers/gpu/drm/nouveau/include/nvhw/class/cl5039.h create mode 100644 drivers/gpu/drm/nouveau/include/nvhw/class/cl9039.h diff --git a/drivers/gpu/drm/nouveau/include/nvhw/class/cl0039.h b/drivers/gpu/drm/nouveau/include/nvhw/class/cl0039.h new file mode 100644 index 000000000000..5386ed64ab72 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvhw/class/cl0039.h @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2001-2001, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl0039_h_ +#define _cl0039_h_ + +/* dma method offsets, fields, and values */ +#define NV039_SET_OBJECT (0x00000000) +#define NV039_NO_OPERATION (0x00000100) +#define NV039_SET_CONTEXT_DMA_NOTIFIES (0x00000180) +#define NV039_SET_CONTEXT_DMA_BUFFER_IN (0x00000184) +#define NV039_SET_CONTEXT_DMA_BUFFER_OUT (0x00000188) + +#define NV039_OFFSET_IN (0x0000030C) +#define NV039_OFFSET_OUT (0x00000310) +#define NV039_PITCH_IN (0x00000314) +#define NV039_PITCH_OUT (0x00000318) +#define NV039_LINE_LENGTH_IN (0x0000031C) +#define NV039_LINE_COUNT (0x00000320) +#define NV039_FORMAT (0x00000324) +#define NV039_FORMAT_IN 7:0 +#define NV039_FORMAT_OUT 31:8 +#define NV039_BUFFER_NOTIFY (0x00000328) +#define NV039_BUFFER_NOTIFY_WRITE_ONLY (0x00000000) +#define NV039_BUFFER_NOTIFY_WRITE_THEN_AWAKEN (0x00000001) +#endif /* _cl0039_h_ */ diff --git a/drivers/gpu/drm/nouveau/include/nvhw/class/cl5039.h b/drivers/gpu/drm/nouveau/include/nvhw/class/cl5039.h new file mode 100644 index 000000000000..5b2ca337cf2b --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvhw/class/cl5039.h @@ -0,0 +1,153 @@ +/* + * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_nv50_memory_to_memory_format_h_ +#define _cl_nv50_memory_to_memory_format_h_ + +#define NV5039_SET_OBJECT 0x0000 +#define NV5039_SET_OBJECT_POINTER 15:0 + +#define NV5039_NO_OPERATION 0x0100 +#define NV5039_NO_OPERATION_V 31:0 + +#define NV5039_SET_CONTEXT_DMA_NOTIFY 0x0180 +#define NV5039_SET_CONTEXT_DMA_NOTIFY_HANDLE 31:0 + +#define NV5039_SET_CONTEXT_DMA_BUFFER_IN 0x0184 +#define NV5039_SET_CONTEXT_DMA_BUFFER_IN_HANDLE 31:0 + +#define NV5039_SET_CONTEXT_DMA_BUFFER_OUT 0x0188 +#define NV5039_SET_CONTEXT_DMA_BUFFER_OUT_HANDLE 31:0 + +#define NV5039_SET_SRC_MEMORY_LAYOUT 0x0200 +#define NV5039_SET_SRC_MEMORY_LAYOUT_V 0:0 +#define NV5039_SET_SRC_MEMORY_LAYOUT_V_BLOCKLINEAR 0x00000000 +#define NV5039_SET_SRC_MEMORY_LAYOUT_V_PITCH 0x00000001 + +#define NV5039_SET_SRC_BLOCK_SIZE 0x0204 +#define NV5039_SET_SRC_BLOCK_SIZE_WIDTH 3:0 +#define NV5039_SET_SRC_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NV5039_SET_SRC_BLOCK_SIZE_HEIGHT 7:4 +#define NV5039_SET_SRC_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NV5039_SET_SRC_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NV5039_SET_SRC_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NV5039_SET_SRC_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NV5039_SET_SRC_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NV5039_SET_SRC_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NV5039_SET_SRC_BLOCK_SIZE_DEPTH 11:8 +#define NV5039_SET_SRC_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NV5039_SET_SRC_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NV5039_SET_SRC_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NV5039_SET_SRC_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NV5039_SET_SRC_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NV5039_SET_SRC_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NV5039_SET_SRC_WIDTH 0x0208 +#define NV5039_SET_SRC_WIDTH_V 31:0 + +#define NV5039_SET_SRC_HEIGHT 0x020c +#define NV5039_SET_SRC_HEIGHT_V 31:0 + +#define NV5039_SET_SRC_DEPTH 0x0210 +#define NV5039_SET_SRC_DEPTH_V 31:0 + +#define NV5039_SET_SRC_LAYER 0x0214 +#define NV5039_SET_SRC_LAYER_V 31:0 + +#define NV5039_SET_SRC_ORIGIN 0x0218 +#define NV5039_SET_SRC_ORIGIN_X 15:0 +#define NV5039_SET_SRC_ORIGIN_Y 31:16 + +#define NV5039_SET_DST_MEMORY_LAYOUT 0x021c +#define NV5039_SET_DST_MEMORY_LAYOUT_V 0:0 +#define NV5039_SET_DST_MEMORY_LAYOUT_V_BLOCKLINEAR 0x00000000 +#define NV5039_SET_DST_MEMORY_LAYOUT_V_PITCH 0x00000001 + +#define NV5039_SET_DST_BLOCK_SIZE 0x0220 +#define NV5039_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NV5039_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NV5039_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NV5039_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NV5039_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NV5039_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NV5039_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NV5039_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NV5039_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NV5039_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NV5039_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NV5039_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NV5039_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NV5039_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NV5039_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NV5039_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NV5039_SET_DST_WIDTH 0x0224 +#define NV5039_SET_DST_WIDTH_V 31:0 + +#define NV5039_SET_DST_HEIGHT 0x0228 +#define NV5039_SET_DST_HEIGHT_V 31:0 + +#define NV5039_SET_DST_DEPTH 0x022c +#define NV5039_SET_DST_DEPTH_V 31:0 + +#define NV5039_SET_DST_LAYER 0x0230 +#define NV5039_SET_DST_LAYER_V 31:0 + +#define NV5039_SET_DST_ORIGIN 0x0234 +#define NV5039_SET_DST_ORIGIN_X 15:0 +#define NV5039_SET_DST_ORIGIN_Y 31:16 + +#define NV5039_OFFSET_IN_UPPER 0x0238 +#define NV5039_OFFSET_IN_UPPER_VALUE 7:0 + +#define NV5039_OFFSET_OUT_UPPER 0x023c +#define NV5039_OFFSET_OUT_UPPER_VALUE 7:0 + +#define NV5039_OFFSET_IN 0x030c +#define NV5039_OFFSET_IN_VALUE 31:0 + +#define NV5039_OFFSET_OUT 0x0310 +#define NV5039_OFFSET_OUT_VALUE 31:0 + +#define NV5039_PITCH_IN 0x0314 +#define NV5039_PITCH_IN_VALUE 31:0 + +#define NV5039_PITCH_OUT 0x0318 +#define NV5039_PITCH_OUT_VALUE 31:0 + +#define NV5039_LINE_LENGTH_IN 0x031c +#define NV5039_LINE_LENGTH_IN_VALUE 31:0 + +#define NV5039_LINE_COUNT 0x0320 +#define NV5039_LINE_COUNT_VALUE 31:0 + +#define NV5039_FORMAT 0x0324 +#define NV5039_FORMAT_IN 7:0 +#define NV5039_FORMAT_IN_ONE 0x00000001 +#define NV5039_FORMAT_OUT 15:8 +#define NV5039_FORMAT_OUT_ONE 0x00000001 + +#define NV5039_BUFFER_NOTIFY 0x0328 +#define NV5039_BUFFER_NOTIFY_TYPE 31:0 +#define NV5039_BUFFER_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NV5039_BUFFER_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 +#endif /* _cl_nv50_memory_to_memory_format_h_ */ diff --git a/drivers/gpu/drm/nouveau/include/nvhw/class/cl9039.h b/drivers/gpu/drm/nouveau/include/nvhw/class/cl9039.h new file mode 100644 index 000000000000..b8282a615ec0 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvhw/class/cl9039.h @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_fermi_memory_to_memory_format_a_h_ +#define _cl_fermi_memory_to_memory_format_a_h_ + +#define NV9039_SET_OBJECT 0x0000 +#define NV9039_SET_OBJECT_CLASS_ID 15:0 +#define NV9039_SET_OBJECT_ENGINE_ID 20:16 + +#define NV9039_OFFSET_OUT_UPPER 0x0238 +#define NV9039_OFFSET_OUT_UPPER_VALUE 7:0 + +#define NV9039_OFFSET_OUT 0x023c +#define NV9039_OFFSET_OUT_VALUE 31:0 + +#define NV9039_LAUNCH_DMA 0x0300 +#define NV9039_LAUNCH_DMA_SRC_INLINE 0:0 +#define NV9039_LAUNCH_DMA_SRC_INLINE_FALSE 0x00000000 +#define NV9039_LAUNCH_DMA_SRC_INLINE_TRUE 0x00000001 +#define NV9039_LAUNCH_DMA_SRC_MEMORY_LAYOUT 4:4 +#define NV9039_LAUNCH_DMA_SRC_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NV9039_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH 0x00000001 +#define NV9039_LAUNCH_DMA_DST_MEMORY_LAYOUT 8:8 +#define NV9039_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NV9039_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NV9039_LAUNCH_DMA_COMPLETION_TYPE 13:12 +#define NV9039_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NV9039_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NV9039_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NV9039_LAUNCH_DMA_INTERRUPT_TYPE 17:16 +#define NV9039_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NV9039_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NV9039_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 20:20 +#define NV9039_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NV9039_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 + +#define NV9039_OFFSET_IN_UPPER 0x030c +#define NV9039_OFFSET_IN_UPPER_VALUE 7:0 + +#define NV9039_OFFSET_IN 0x0310 +#define NV9039_OFFSET_IN_VALUE 31:0 + +#define NV9039_PITCH_IN 0x0314 +#define NV9039_PITCH_IN_VALUE 31:0 + +#define NV9039_PITCH_OUT 0x0318 +#define NV9039_PITCH_OUT_VALUE 31:0 + +#define NV9039_LINE_LENGTH_IN 0x031c +#define NV9039_LINE_LENGTH_IN_VALUE 31:0 + +#define NV9039_LINE_COUNT 0x0320 +#define NV9039_LINE_COUNT_VALUE 31:0 +#endif /* _cl_fermi_memory_to_memory_format_a_h_ */ diff --git a/drivers/gpu/drm/nouveau/nouveau_bo0039.c b/drivers/gpu/drm/nouveau/nouveau_bo0039.c index e00ec7cfce5f..8f1f78b0105d 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo0039.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo0039.c @@ -32,6 +32,8 @@ #include +#include + static inline uint32_t nouveau_bo_mem_ctxdma(struct ttm_buffer_object *bo, struct nouveau_channel *chan, struct ttm_mem_reg *reg) @@ -94,7 +96,7 @@ nv04_bo_move_init(struct nouveau_channel *chan, u32 handle) if (ret) return ret; - PUSH_NVSQ(push, NV039, 0x0000, handle); - PUSH_NVSQ(push, NV039, 0x0180, chan->drm->ntfy.handle); + PUSH_MTHD(push, NV039, SET_OBJECT, handle); + PUSH_MTHD(push, NV039, SET_CONTEXT_DMA_NOTIFIES, chan->drm->ntfy.handle); return 0; } diff --git a/drivers/gpu/drm/nouveau/nouveau_bo5039.c b/drivers/gpu/drm/nouveau/nouveau_bo5039.c index 19fb36b35ff9..232877f8b93d 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo5039.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo5039.c @@ -33,6 +33,8 @@ #include +#include + int nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) @@ -111,9 +113,9 @@ nv50_bo_move_init(struct nouveau_channel *chan, u32 handle) if (ret) return ret; - PUSH_NVSQ(push, NV5039, 0x0000, handle); - PUSH_NVSQ(push, NV5039, 0x0180, chan->drm->ntfy.handle, - 0x0184, chan->vram.handle, - 0x0188, chan->vram.handle); + PUSH_MTHD(push, NV5039, SET_OBJECT, handle); + PUSH_MTHD(push, NV5039, SET_CONTEXT_DMA_NOTIFY, chan->drm->ntfy.handle, + SET_CONTEXT_DMA_BUFFER_IN, chan->vram.handle, + SET_CONTEXT_DMA_BUFFER_OUT, chan->vram.handle); return 0; } diff --git a/drivers/gpu/drm/nouveau/nouveau_bo9039.c b/drivers/gpu/drm/nouveau/nouveau_bo9039.c index 995ebe7ffe00..785d831e5d18 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo9039.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo9039.c @@ -32,6 +32,8 @@ #include +#include + int nvc0_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) @@ -79,6 +81,6 @@ nvc0_bo_move_init(struct nouveau_channel *chan, u32 handle) if (ret) return ret; - PUSH_NVSQ(push, NV9039, 0x0000, handle); + PUSH_MTHD(push, NV9039, SET_OBJECT, handle); return 0; } From 6c75137274b050e9baaa5b2904b165a49c671273 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 22 Jun 2020 17:07:31 +1000 Subject: [PATCH 139/145] drm/nouveau/bo: use NVIDIA's headers for move move() Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- .../drm/nouveau/include/nvhw/class/cla0b5.h | 162 ++++++++++++++++++ drivers/gpu/drm/nouveau/nouveau_bo0039.c | 29 ++-- drivers/gpu/drm/nouveau/nouveau_bo5039.c | 84 ++++++--- drivers/gpu/drm/nouveau/nouveau_bo9039.c | 30 +++- drivers/gpu/drm/nouveau/nouveau_boa0b5.c | 37 +++- 5 files changed, 286 insertions(+), 56 deletions(-) create mode 100644 drivers/gpu/drm/nouveau/include/nvhw/class/cla0b5.h diff --git a/drivers/gpu/drm/nouveau/include/nvhw/class/cla0b5.h b/drivers/gpu/drm/nouveau/include/nvhw/class/cla0b5.h new file mode 100644 index 000000000000..fe5d10f05468 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvhw/class/cla0b5.h @@ -0,0 +1,162 @@ +/******************************************************************************* + Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +#ifndef _cla0b5_h_ +#define _cla0b5_h_ + +#define NVA0B5_SET_SRC_PHYS_MODE (0x00000260) +#define NVA0B5_SET_SRC_PHYS_MODE_TARGET 1:0 +#define NVA0B5_SET_SRC_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVA0B5_SET_SRC_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVA0B5_SET_SRC_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVA0B5_SET_DST_PHYS_MODE (0x00000264) +#define NVA0B5_SET_DST_PHYS_MODE_TARGET 1:0 +#define NVA0B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB (0x00000000) +#define NVA0B5_SET_DST_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001) +#define NVA0B5_SET_DST_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002) +#define NVA0B5_LAUNCH_DMA (0x00000300) +#define NVA0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE 1:0 +#define NVA0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NONE (0x00000000) +#define NVA0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_PIPELINED (0x00000001) +#define NVA0B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NON_PIPELINED (0x00000002) +#define NVA0B5_LAUNCH_DMA_FLUSH_ENABLE 2:2 +#define NVA0B5_LAUNCH_DMA_FLUSH_ENABLE_FALSE (0x00000000) +#define NVA0B5_LAUNCH_DMA_FLUSH_ENABLE_TRUE (0x00000001) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_TYPE 4:3 +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_TYPE_NONE (0x00000000) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_ONE_WORD_SEMAPHORE (0x00000001) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_TYPE_RELEASE_FOUR_WORD_SEMAPHORE (0x00000002) +#define NVA0B5_LAUNCH_DMA_INTERRUPT_TYPE 6:5 +#define NVA0B5_LAUNCH_DMA_INTERRUPT_TYPE_NONE (0x00000000) +#define NVA0B5_LAUNCH_DMA_INTERRUPT_TYPE_BLOCKING (0x00000001) +#define NVA0B5_LAUNCH_DMA_INTERRUPT_TYPE_NON_BLOCKING (0x00000002) +#define NVA0B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT 7:7 +#define NVA0B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVA0B5_LAUNCH_DMA_SRC_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVA0B5_LAUNCH_DMA_DST_MEMORY_LAYOUT 8:8 +#define NVA0B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NVA0B5_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH (0x00000001) +#define NVA0B5_LAUNCH_DMA_MULTI_LINE_ENABLE 9:9 +#define NVA0B5_LAUNCH_DMA_MULTI_LINE_ENABLE_FALSE (0x00000000) +#define NVA0B5_LAUNCH_DMA_MULTI_LINE_ENABLE_TRUE (0x00000001) +#define NVA0B5_LAUNCH_DMA_REMAP_ENABLE 10:10 +#define NVA0B5_LAUNCH_DMA_REMAP_ENABLE_FALSE (0x00000000) +#define NVA0B5_LAUNCH_DMA_REMAP_ENABLE_TRUE (0x00000001) +#define NVA0B5_LAUNCH_DMA_BYPASS_L2 11:11 +#define NVA0B5_LAUNCH_DMA_BYPASS_L2_USE_PTE_SETTING (0x00000000) +#define NVA0B5_LAUNCH_DMA_BYPASS_L2_FORCE_VOLATILE (0x00000001) +#define NVA0B5_LAUNCH_DMA_SRC_TYPE 12:12 +#define NVA0B5_LAUNCH_DMA_SRC_TYPE_VIRTUAL (0x00000000) +#define NVA0B5_LAUNCH_DMA_SRC_TYPE_PHYSICAL (0x00000001) +#define NVA0B5_LAUNCH_DMA_DST_TYPE 13:13 +#define NVA0B5_LAUNCH_DMA_DST_TYPE_VIRTUAL (0x00000000) +#define NVA0B5_LAUNCH_DMA_DST_TYPE_PHYSICAL (0x00000001) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION 17:14 +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMIN (0x00000000) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMAX (0x00000001) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IXOR (0x00000002) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IAND (0x00000003) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IOR (0x00000004) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IADD (0x00000005) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_INC (0x00000006) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_DEC (0x00000007) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FADD (0x0000000A) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FMIN (0x0000000B) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FMAX (0x0000000C) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_FMUL (0x0000000D) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_IMUL (0x0000000E) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN 18:18 +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_SIGNED (0x00000000) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_SIGN_UNSIGNED (0x00000001) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE 19:19 +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_FALSE (0x00000000) +#define NVA0B5_LAUNCH_DMA_SEMAPHORE_REDUCTION_ENABLE_TRUE (0x00000001) +#define NVA0B5_OFFSET_IN_UPPER (0x00000400) +#define NVA0B5_OFFSET_IN_UPPER_UPPER 7:0 +#define NVA0B5_OFFSET_IN_LOWER (0x00000404) +#define NVA0B5_OFFSET_IN_LOWER_VALUE 31:0 +#define NVA0B5_OFFSET_OUT_UPPER (0x00000408) +#define NVA0B5_OFFSET_OUT_UPPER_UPPER 7:0 +#define NVA0B5_OFFSET_OUT_LOWER (0x0000040C) +#define NVA0B5_OFFSET_OUT_LOWER_VALUE 31:0 +#define NVA0B5_PITCH_IN (0x00000410) +#define NVA0B5_PITCH_IN_VALUE 31:0 +#define NVA0B5_PITCH_OUT (0x00000414) +#define NVA0B5_PITCH_OUT_VALUE 31:0 +#define NVA0B5_LINE_LENGTH_IN (0x00000418) +#define NVA0B5_LINE_LENGTH_IN_VALUE 31:0 +#define NVA0B5_LINE_COUNT (0x0000041C) +#define NVA0B5_LINE_COUNT_VALUE 31:0 +#define NVA0B5_SET_REMAP_CONST_A (0x00000700) +#define NVA0B5_SET_REMAP_CONST_A_V 31:0 +#define NVA0B5_SET_REMAP_CONST_B (0x00000704) +#define NVA0B5_SET_REMAP_CONST_B_V 31:0 +#define NVA0B5_SET_REMAP_COMPONENTS (0x00000708) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_X 2:0 +#define NVA0B5_SET_REMAP_COMPONENTS_DST_X_SRC_X (0x00000000) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_X_SRC_Y (0x00000001) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_X_SRC_Z (0x00000002) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_X_SRC_W (0x00000003) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_X_CONST_A (0x00000004) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_X_CONST_B (0x00000005) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_X_NO_WRITE (0x00000006) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y 6:4 +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_X (0x00000000) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Y (0x00000001) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_Z (0x00000002) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_SRC_W (0x00000003) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_CONST_A (0x00000004) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_CONST_B (0x00000005) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Y_NO_WRITE (0x00000006) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z 10:8 +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_X (0x00000000) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Y (0x00000001) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_Z (0x00000002) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_SRC_W (0x00000003) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_CONST_A (0x00000004) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_CONST_B (0x00000005) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_Z_NO_WRITE (0x00000006) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_W 14:12 +#define NVA0B5_SET_REMAP_COMPONENTS_DST_W_SRC_X (0x00000000) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_W_SRC_Y (0x00000001) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_W_SRC_Z (0x00000002) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_W_SRC_W (0x00000003) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_W_CONST_A (0x00000004) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_W_CONST_B (0x00000005) +#define NVA0B5_SET_REMAP_COMPONENTS_DST_W_NO_WRITE (0x00000006) +#define NVA0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE 17:16 +#define NVA0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_ONE (0x00000000) +#define NVA0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_TWO (0x00000001) +#define NVA0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_THREE (0x00000002) +#define NVA0B5_SET_REMAP_COMPONENTS_COMPONENT_SIZE_FOUR (0x00000003) +#define NVA0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS 21:20 +#define NVA0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_ONE (0x00000000) +#define NVA0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_TWO (0x00000001) +#define NVA0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_THREE (0x00000002) +#define NVA0B5_SET_REMAP_COMPONENTS_NUM_SRC_COMPONENTS_FOUR (0x00000003) +#define NVA0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS 25:24 +#define NVA0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_ONE (0x00000000) +#define NVA0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_TWO (0x00000001) +#define NVA0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_THREE (0x00000002) +#define NVA0B5_SET_REMAP_COMPONENTS_NUM_DST_COMPONENTS_FOUR (0x00000003) +#endif // _cla0b5_h diff --git a/drivers/gpu/drm/nouveau/nouveau_bo0039.c b/drivers/gpu/drm/nouveau/nouveau_bo0039.c index 8f1f78b0105d..bf7ae2cecaf6 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo0039.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo0039.c @@ -48,7 +48,9 @@ nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) { struct nvif_push *push = chan->chan.push; + u32 src_ctxdma = nouveau_bo_mem_ctxdma(bo, chan, old_reg); u32 src_offset = old_reg->start << PAGE_SHIFT; + u32 dst_ctxdma = nouveau_bo_mem_ctxdma(bo, chan, new_reg); u32 dst_offset = new_reg->start << PAGE_SHIFT; u32 page_count = new_reg->num_pages; int ret; @@ -57,8 +59,8 @@ nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, if (ret) return ret; - PUSH_NVSQ(push, NV039, 0x0184, nouveau_bo_mem_ctxdma(bo, chan, old_reg), - 0x0188, nouveau_bo_mem_ctxdma(bo, chan, new_reg)); + PUSH_MTHD(push, NV039, SET_CONTEXT_DMA_BUFFER_IN, src_ctxdma, + SET_CONTEXT_DMA_BUFFER_OUT, dst_ctxdma); page_count = new_reg->num_pages; while (page_count) { @@ -68,15 +70,20 @@ nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, if (ret) return ret; - PUSH_NVSQ(push, NV039, 0x030c, src_offset, - 0x0310, dst_offset, - 0x0314, PAGE_SIZE, /* src_pitch */ - 0x0318, PAGE_SIZE, /* dst_pitch */ - 0x031c, PAGE_SIZE, /* line_length */ - 0x0320, line_count, - 0x0324, 0x00000101, - 0x0328, 0x00000000); - PUSH_NVSQ(push, NV039, 0x0100, 0x00000000); + PUSH_MTHD(push, NV039, OFFSET_IN, src_offset, + OFFSET_OUT, dst_offset, + PITCH_IN, PAGE_SIZE, + PITCH_OUT, PAGE_SIZE, + LINE_LENGTH_IN, PAGE_SIZE, + LINE_COUNT, line_count, + + FORMAT, + NVVAL(NV039, FORMAT, IN, 1) | + NVVAL(NV039, FORMAT, OUT, 1), + + BUFFER_NOTIFY, NV039_BUFFER_NOTIFY_WRITE_ONLY); + + PUSH_MTHD(push, NV039, NO_OPERATION, 0x00000000); page_count -= line_count; src_offset += (PAGE_SIZE * line_count); diff --git a/drivers/gpu/drm/nouveau/nouveau_bo5039.c b/drivers/gpu/drm/nouveau/nouveau_bo5039.c index 232877f8b93d..f9b9b85abe44 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo5039.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo5039.c @@ -60,40 +60,70 @@ nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, height = amount / stride; if (src_tiled) { - PUSH_NVSQ(push, NV5039, 0x0200, 0, - 0x0204, 0, - 0x0208, stride, - 0x020c, height, - 0x0210, 1, - 0x0214, 0, - 0x0218, 0); + PUSH_MTHD(push, NV5039, SET_SRC_MEMORY_LAYOUT, + NVDEF(NV5039, SET_SRC_MEMORY_LAYOUT, V, BLOCKLINEAR), + + SET_SRC_BLOCK_SIZE, + NVDEF(NV5039, SET_SRC_BLOCK_SIZE, WIDTH, ONE_GOB) | + NVDEF(NV5039, SET_SRC_BLOCK_SIZE, HEIGHT, ONE_GOB) | + NVDEF(NV5039, SET_SRC_BLOCK_SIZE, DEPTH, ONE_GOB), + + SET_SRC_WIDTH, stride, + SET_SRC_HEIGHT, height, + SET_SRC_DEPTH, 1, + SET_SRC_LAYER, 0, + + SET_SRC_ORIGIN, + NVVAL(NV5039, SET_SRC_ORIGIN, X, 0) | + NVVAL(NV5039, SET_SRC_ORIGIN, Y, 0)); } else { - PUSH_NVSQ(push, NV5039, 0x0200, 1); + PUSH_MTHD(push, NV5039, SET_SRC_MEMORY_LAYOUT, + NVDEF(NV5039, SET_SRC_MEMORY_LAYOUT, V, PITCH)); } if (dst_tiled) { - PUSH_NVSQ(push, NV5039, 0x021c, 0, - 0x0220, 0, - 0x0224, stride, - 0x0228, height, - 0x022c, 1, - 0x0230, 0, - 0x0234, 0); + PUSH_MTHD(push, NV5039, SET_DST_MEMORY_LAYOUT, + NVDEF(NV5039, SET_DST_MEMORY_LAYOUT, V, BLOCKLINEAR), + + SET_DST_BLOCK_SIZE, + NVDEF(NV5039, SET_DST_BLOCK_SIZE, WIDTH, ONE_GOB) | + NVDEF(NV5039, SET_DST_BLOCK_SIZE, HEIGHT, ONE_GOB) | + NVDEF(NV5039, SET_DST_BLOCK_SIZE, DEPTH, ONE_GOB), + + SET_DST_WIDTH, stride, + SET_DST_HEIGHT, height, + SET_DST_DEPTH, 1, + SET_DST_LAYER, 0, + + SET_DST_ORIGIN, + NVVAL(NV5039, SET_DST_ORIGIN, X, 0) | + NVVAL(NV5039, SET_DST_ORIGIN, Y, 0)); } else { - PUSH_NVSQ(push, NV5039, 0x021c, 1); + PUSH_MTHD(push, NV5039, SET_DST_MEMORY_LAYOUT, + NVDEF(NV5039, SET_DST_MEMORY_LAYOUT, V, PITCH)); } - PUSH_NVSQ(push, NV5039, 0x0238, upper_32_bits(src_offset), - 0x023c, upper_32_bits(dst_offset)); - PUSH_NVSQ(push, NV5039, 0x030c, lower_32_bits(src_offset), - 0x0310, lower_32_bits(dst_offset), - 0x0314, stride, - 0x0318, stride, - 0x031c, stride, - 0x0320, height, - 0x0324, 0x00000101, - 0x0328, 0x00000000); - PUSH_NVSQ(push, NV5039, 0x0100, 0x00000000); + PUSH_MTHD(push, NV5039, OFFSET_IN_UPPER, + NVVAL(NV5039, OFFSET_IN_UPPER, VALUE, upper_32_bits(src_offset)), + + OFFSET_OUT_UPPER, + NVVAL(NV5039, OFFSET_OUT_UPPER, VALUE, upper_32_bits(dst_offset))); + + PUSH_MTHD(push, NV5039, OFFSET_IN, lower_32_bits(src_offset), + OFFSET_OUT, lower_32_bits(dst_offset), + PITCH_IN, stride, + PITCH_OUT, stride, + LINE_LENGTH_IN, stride, + LINE_COUNT, height, + + FORMAT, + NVDEF(NV5039, FORMAT, IN, ONE) | + NVDEF(NV5039, FORMAT, OUT, ONE), + + BUFFER_NOTIFY, + NVDEF(NV5039, BUFFER_NOTIFY, TYPE, WRITE_ONLY)); + + PUSH_MTHD(push, NV5039, NO_OPERATION, 0x00000000); length -= amount; src_offset += amount; diff --git a/drivers/gpu/drm/nouveau/nouveau_bo9039.c b/drivers/gpu/drm/nouveau/nouveau_bo9039.c index 785d831e5d18..52fefb37064c 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo9039.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo9039.c @@ -53,15 +53,27 @@ nvc0_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, if (ret) return ret; - PUSH_NVSQ(push, NV9039, 0x0238, upper_32_bits(dst_offset), - 0x023c, lower_32_bits(dst_offset)); - PUSH_NVSQ(push, NV9039, 0x030c, upper_32_bits(src_offset), - 0x0310, lower_32_bits(src_offset), - 0x0314, PAGE_SIZE, /* src_pitch */ - 0x0318, PAGE_SIZE, /* dst_pitch */ - 0x031c, PAGE_SIZE, /* line_length */ - 0x0320, line_count); - PUSH_NVSQ(push, NV9039, 0x0300, 0x00100110); + PUSH_MTHD(push, NV9039, OFFSET_OUT_UPPER, + NVVAL(NV9039, OFFSET_OUT_UPPER, VALUE, upper_32_bits(dst_offset)), + + OFFSET_OUT, lower_32_bits(dst_offset)); + + PUSH_MTHD(push, NV9039, OFFSET_IN_UPPER, + NVVAL(NV9039, OFFSET_IN_UPPER, VALUE, upper_32_bits(src_offset)), + + OFFSET_IN, lower_32_bits(src_offset), + PITCH_IN, PAGE_SIZE, + PITCH_OUT, PAGE_SIZE, + LINE_LENGTH_IN, PAGE_SIZE, + LINE_COUNT, line_count); + + PUSH_MTHD(push, NV9039, LAUNCH_DMA, + NVDEF(NV9039, LAUNCH_DMA, SRC_INLINE, FALSE) | + NVDEF(NV9039, LAUNCH_DMA, SRC_MEMORY_LAYOUT, PITCH) | + NVDEF(NV9039, LAUNCH_DMA, DST_MEMORY_LAYOUT, PITCH) | + NVDEF(NV9039, LAUNCH_DMA, COMPLETION_TYPE, FLUSH_DISABLE) | + NVDEF(NV9039, LAUNCH_DMA, INTERRUPT_TYPE, NONE) | + NVDEF(NV9039, LAUNCH_DMA, SEMAPHORE_STRUCT_SIZE, ONE_WORD)); page_count -= line_count; src_offset += (PAGE_SIZE * line_count); diff --git a/drivers/gpu/drm/nouveau/nouveau_boa0b5.c b/drivers/gpu/drm/nouveau/nouveau_boa0b5.c index b1afb2724fb7..394e29012e50 100644 --- a/drivers/gpu/drm/nouveau/nouveau_boa0b5.c +++ b/drivers/gpu/drm/nouveau/nouveau_boa0b5.c @@ -32,6 +32,8 @@ #include +#include + int nve0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo, struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg) @@ -44,15 +46,32 @@ nve0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo, if (ret) return ret; - PUSH_NVSQ(push, NVA0B5, 0x0400, upper_32_bits(mem->vma[0].addr), - 0x0404, lower_32_bits(mem->vma[0].addr), - 0x0408, upper_32_bits(mem->vma[1].addr), - 0x040c, lower_32_bits(mem->vma[1].addr), - 0x0410, PAGE_SIZE, - 0x0414, PAGE_SIZE, - 0x0418, PAGE_SIZE, - 0x041c, new_reg->num_pages); - PUSH_NVIM(push, NVA0B5, 0x0300, 0x0386); + PUSH_MTHD(push, NVA0B5, OFFSET_IN_UPPER, + NVVAL(NVA0B5, OFFSET_IN_UPPER, UPPER, upper_32_bits(mem->vma[0].addr)), + + OFFSET_IN_LOWER, lower_32_bits(mem->vma[0].addr), + + OFFSET_OUT_UPPER, + NVVAL(NVA0B5, OFFSET_OUT_UPPER, UPPER, upper_32_bits(mem->vma[1].addr)), + + OFFSET_OUT_LOWER, lower_32_bits(mem->vma[1].addr), + PITCH_IN, PAGE_SIZE, + PITCH_OUT, PAGE_SIZE, + LINE_LENGTH_IN, PAGE_SIZE, + LINE_COUNT, new_reg->num_pages); + + PUSH_IMMD(push, NVA0B5, LAUNCH_DMA, + NVDEF(NVA0B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, NON_PIPELINED) | + NVDEF(NVA0B5, LAUNCH_DMA, FLUSH_ENABLE, TRUE) | + NVDEF(NVA0B5, LAUNCH_DMA, SEMAPHORE_TYPE, NONE) | + NVDEF(NVA0B5, LAUNCH_DMA, INTERRUPT_TYPE, NONE) | + NVDEF(NVA0B5, LAUNCH_DMA, SRC_MEMORY_LAYOUT, PITCH) | + NVDEF(NVA0B5, LAUNCH_DMA, DST_MEMORY_LAYOUT, PITCH) | + NVDEF(NVA0B5, LAUNCH_DMA, MULTI_LINE_ENABLE, TRUE) | + NVDEF(NVA0B5, LAUNCH_DMA, REMAP_ENABLE, FALSE) | + NVDEF(NVA0B5, LAUNCH_DMA, BYPASS_L2, USE_PTE_SETTING) | + NVDEF(NVA0B5, LAUNCH_DMA, SRC_TYPE, VIRTUAL) | + NVDEF(NVA0B5, LAUNCH_DMA, DST_TYPE, VIRTUAL)); return 0; } From 66c3bdd4e7fa248c188478e05dbe74ab342732e6 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 22 Jun 2020 19:16:31 +1000 Subject: [PATCH 140/145] drm/nouveau/svm: use NVIDIA's headers for migrate_copy() Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/nouveau_dmem.c | 59 +++++++++++++++++--------- 1 file changed, 39 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nouveau_dmem.c b/drivers/gpu/drm/nouveau/nouveau_dmem.c index 6528e60e567e..1943e276a8cf 100644 --- a/drivers/gpu/drm/nouveau/nouveau_dmem.c +++ b/drivers/gpu/drm/nouveau/nouveau_dmem.c @@ -35,6 +35,8 @@ #include #include +#include + #include #include @@ -387,11 +389,7 @@ nvc0b5_migrate_copy(struct nouveau_drm *drm, u64 npages, enum nouveau_aper src_aper, u64 src_addr) { struct nvif_push *push = drm->dmem->migrate.chan->chan.push; - u32 launch_dma = (1 << 9) /* MULTI_LINE_ENABLE. */ | - (1 << 8) /* DST_MEMORY_LAYOUT_PITCH. */ | - (1 << 7) /* SRC_MEMORY_LAYOUT_PITCH. */ | - (1 << 2) /* FLUSH_ENABLE_TRUE. */ | - (2 << 0) /* DATA_TRANSFER_TYPE_NON_PIPELINED. */; + u32 launch_dma = 0; int ret; ret = PUSH_WAIT(push, 13); @@ -401,40 +399,61 @@ nvc0b5_migrate_copy(struct nouveau_drm *drm, u64 npages, if (src_aper != NOUVEAU_APER_VIRT) { switch (src_aper) { case NOUVEAU_APER_VRAM: - PUSH_NVIM(push, NVA0B5, 0x0260, 0); + PUSH_IMMD(push, NVA0B5, SET_SRC_PHYS_MODE, + NVDEF(NVA0B5, SET_SRC_PHYS_MODE, TARGET, LOCAL_FB)); break; case NOUVEAU_APER_HOST: - PUSH_NVIM(push, NVA0B5, 0x0260, 1); + PUSH_IMMD(push, NVA0B5, SET_SRC_PHYS_MODE, + NVDEF(NVA0B5, SET_SRC_PHYS_MODE, TARGET, COHERENT_SYSMEM)); break; default: return -EINVAL; } - launch_dma |= 0x00001000; /* SRC_TYPE_PHYSICAL. */ + + launch_dma |= NVDEF(NVA0B5, LAUNCH_DMA, SRC_TYPE, PHYSICAL); } if (dst_aper != NOUVEAU_APER_VIRT) { switch (dst_aper) { case NOUVEAU_APER_VRAM: - PUSH_NVIM(push, NVA0B5, 0x0264, 0); + PUSH_IMMD(push, NVA0B5, SET_DST_PHYS_MODE, + NVDEF(NVA0B5, SET_DST_PHYS_MODE, TARGET, LOCAL_FB)); break; case NOUVEAU_APER_HOST: - PUSH_NVIM(push, NVA0B5, 0x0264, 1); + PUSH_IMMD(push, NVA0B5, SET_DST_PHYS_MODE, + NVDEF(NVA0B5, SET_DST_PHYS_MODE, TARGET, COHERENT_SYSMEM)); break; default: return -EINVAL; } - launch_dma |= 0x00002000; /* DST_TYPE_PHYSICAL. */ + + launch_dma |= NVDEF(NVA0B5, LAUNCH_DMA, DST_TYPE, PHYSICAL); } - PUSH_NVSQ(push, NVA0B5, 0x0400, upper_32_bits(src_addr), - 0x0404, lower_32_bits(src_addr), - 0x0408, upper_32_bits(dst_addr), - 0x040c, lower_32_bits(dst_addr), - 0x0410, PAGE_SIZE, - 0x0414, PAGE_SIZE, - 0x0418, PAGE_SIZE, - 0x041c, npages); - PUSH_NVSQ(push, NVA0B5, 0x0300, launch_dma); + PUSH_MTHD(push, NVA0B5, OFFSET_IN_UPPER, + NVVAL(NVA0B5, OFFSET_IN_UPPER, UPPER, upper_32_bits(src_addr)), + + OFFSET_IN_LOWER, lower_32_bits(src_addr), + + OFFSET_OUT_UPPER, + NVVAL(NVA0B5, OFFSET_OUT_UPPER, UPPER, upper_32_bits(dst_addr)), + + OFFSET_OUT_LOWER, lower_32_bits(dst_addr), + PITCH_IN, PAGE_SIZE, + PITCH_OUT, PAGE_SIZE, + LINE_LENGTH_IN, PAGE_SIZE, + LINE_COUNT, npages); + + PUSH_MTHD(push, NVA0B5, LAUNCH_DMA, launch_dma | + NVDEF(NVA0B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, NON_PIPELINED) | + NVDEF(NVA0B5, LAUNCH_DMA, FLUSH_ENABLE, TRUE) | + NVDEF(NVA0B5, LAUNCH_DMA, SEMAPHORE_TYPE, NONE) | + NVDEF(NVA0B5, LAUNCH_DMA, INTERRUPT_TYPE, NONE) | + NVDEF(NVA0B5, LAUNCH_DMA, SRC_MEMORY_LAYOUT, PITCH) | + NVDEF(NVA0B5, LAUNCH_DMA, DST_MEMORY_LAYOUT, PITCH) | + NVDEF(NVA0B5, LAUNCH_DMA, MULTI_LINE_ENABLE, TRUE) | + NVDEF(NVA0B5, LAUNCH_DMA, REMAP_ENABLE, FALSE) | + NVDEF(NVA0B5, LAUNCH_DMA, BYPASS_L2, USE_PTE_SETTING)); return 0; } From c47fceca2ef3718cee09bbf2941de44b3701c873 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 22 Jun 2020 19:27:00 +1000 Subject: [PATCH 141/145] drm/nouveau/svm: use NVIDIA's headers for migrate_clear() Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/nouveau_dmem.c | 52 ++++++++++++++++---------- 1 file changed, 33 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nouveau_dmem.c b/drivers/gpu/drm/nouveau/nouveau_dmem.c index 1943e276a8cf..98a1739e01e9 100644 --- a/drivers/gpu/drm/nouveau/nouveau_dmem.c +++ b/drivers/gpu/drm/nouveau/nouveau_dmem.c @@ -462,15 +462,7 @@ nvc0b5_migrate_clear(struct nouveau_drm *drm, u32 length, enum nouveau_aper dst_aper, u64 dst_addr) { struct nvif_push *push = drm->dmem->migrate.chan->chan.push; - u32 launch_dma = (1 << 10) /* REMAP_ENABLE_TRUE */ | - (1 << 8) /* DST_MEMORY_LAYOUT_PITCH. */ | - (1 << 7) /* SRC_MEMORY_LAYOUT_PITCH. */ | - (1 << 2) /* FLUSH_ENABLE_TRUE. */ | - (2 << 0) /* DATA_TRANSFER_TYPE_NON_PIPELINED. */; - u32 remap = (4 << 0) /* DST_X_CONST_A */ | - (5 << 4) /* DST_Y_CONST_B */ | - (3 << 16) /* COMPONENT_SIZE_FOUR */ | - (1 << 24) /* NUM_DST_COMPONENTS_TWO */; + u32 launch_dma = 0; int ret; ret = PUSH_WAIT(push, 12); @@ -479,23 +471,45 @@ nvc0b5_migrate_clear(struct nouveau_drm *drm, u32 length, switch (dst_aper) { case NOUVEAU_APER_VRAM: - PUSH_NVIM(push, NVA0B5, 0x0264, 0); + PUSH_IMMD(push, NVA0B5, SET_DST_PHYS_MODE, + NVDEF(NVA0B5, SET_DST_PHYS_MODE, TARGET, LOCAL_FB)); break; case NOUVEAU_APER_HOST: - PUSH_NVIM(push, NVA0B5, 0x0264, 1); + PUSH_IMMD(push, NVA0B5, SET_DST_PHYS_MODE, + NVDEF(NVA0B5, SET_DST_PHYS_MODE, TARGET, COHERENT_SYSMEM)); break; default: return -EINVAL; } - launch_dma |= 0x00002000; /* DST_TYPE_PHYSICAL. */ - PUSH_NVSQ(push, NVA0B5, 0x0700, 0, - 0x0704, 0, - 0x0708, remap); - PUSH_NVSQ(push, NVA0B5, 0x0408, upper_32_bits(dst_addr), - 0x040c, lower_32_bits(dst_addr)); - PUSH_NVSQ(push, NVA0B5, 0x0418, length >> 3); - PUSH_NVSQ(push, NVA0B5, 0x0300, launch_dma); + launch_dma |= NVDEF(NVA0B5, LAUNCH_DMA, DST_TYPE, PHYSICAL); + + PUSH_MTHD(push, NVA0B5, SET_REMAP_CONST_A, 0, + SET_REMAP_CONST_B, 0, + + SET_REMAP_COMPONENTS, + NVDEF(NVA0B5, SET_REMAP_COMPONENTS, DST_X, CONST_A) | + NVDEF(NVA0B5, SET_REMAP_COMPONENTS, DST_Y, CONST_B) | + NVDEF(NVA0B5, SET_REMAP_COMPONENTS, COMPONENT_SIZE, FOUR) | + NVDEF(NVA0B5, SET_REMAP_COMPONENTS, NUM_DST_COMPONENTS, TWO)); + + PUSH_MTHD(push, NVA0B5, OFFSET_OUT_UPPER, + NVVAL(NVA0B5, OFFSET_OUT_UPPER, UPPER, upper_32_bits(dst_addr)), + + OFFSET_OUT_LOWER, lower_32_bits(dst_addr)); + + PUSH_MTHD(push, NVA0B5, LINE_LENGTH_IN, length >> 3); + + PUSH_MTHD(push, NVA0B5, LAUNCH_DMA, launch_dma | + NVDEF(NVA0B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, NON_PIPELINED) | + NVDEF(NVA0B5, LAUNCH_DMA, FLUSH_ENABLE, TRUE) | + NVDEF(NVA0B5, LAUNCH_DMA, SEMAPHORE_TYPE, NONE) | + NVDEF(NVA0B5, LAUNCH_DMA, INTERRUPT_TYPE, NONE) | + NVDEF(NVA0B5, LAUNCH_DMA, SRC_MEMORY_LAYOUT, PITCH) | + NVDEF(NVA0B5, LAUNCH_DMA, DST_MEMORY_LAYOUT, PITCH) | + NVDEF(NVA0B5, LAUNCH_DMA, MULTI_LINE_ENABLE, FALSE) | + NVDEF(NVA0B5, LAUNCH_DMA, REMAP_ENABLE, TRUE) | + NVDEF(NVA0B5, LAUNCH_DMA, BYPASS_L2, USE_PTE_SETTING)); return 0; } From 60cdadace3208001b4e24a1a4b102f767d5df3c2 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 20 Jul 2020 11:19:14 +1000 Subject: [PATCH 142/145] drm/nouveau/fence: use NVIDIA's headers for emit() Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- .../drm/nouveau/include/nvhw/class/cl006e.h | 30 ++++++++++++++ .../drm/nouveau/include/nvhw/class/cl826f.h | 39 +++++++++++++++++++ drivers/gpu/drm/nouveau/nouveau_dma.h | 5 --- drivers/gpu/drm/nouveau/nv10_fence.c | 4 +- drivers/gpu/drm/nouveau/nv84_fence.c | 22 +++++++---- drivers/gpu/drm/nouveau/nvc0_fence.c | 21 ++++++---- 6 files changed, 100 insertions(+), 21 deletions(-) create mode 100644 drivers/gpu/drm/nouveau/include/nvhw/class/cl006e.h create mode 100644 drivers/gpu/drm/nouveau/include/nvhw/class/cl826f.h diff --git a/drivers/gpu/drm/nouveau/include/nvhw/class/cl006e.h b/drivers/gpu/drm/nouveau/include/nvhw/class/cl006e.h new file mode 100644 index 000000000000..8cfb59662038 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvhw/class/cl006e.h @@ -0,0 +1,30 @@ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ +#ifndef _cl006e_h_ +#define _cl006e_h_ + +/* fields and values */ +#define NV06E_SET_OBJECT (0x00000000) +#define NV06E_REFERENCE (0x00000048) +#define NV06E_SET_REFERENCE (0x00000050) +#endif /* _cl006e_h_ */ diff --git a/drivers/gpu/drm/nouveau/include/nvhw/class/cl826f.h b/drivers/gpu/drm/nouveau/include/nvhw/class/cl826f.h new file mode 100644 index 000000000000..8e7c0fbbbdb8 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvhw/class/cl826f.h @@ -0,0 +1,39 @@ +/******************************************************************************* + Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ +#ifndef _cl826f_h_ +#define _cl826f_h_ + +#define NV826F_SEMAPHOREA (0x00000010) +#define NV826F_SEMAPHOREA_OFFSET_UPPER 7:0 +#define NV826F_SEMAPHOREB (0x00000014) +#define NV826F_SEMAPHOREB_OFFSET_LOWER 31:00 +#define NV826F_SEMAPHOREC (0x00000018) +#define NV826F_SEMAPHOREC_PAYLOAD 31:0 +#define NV826F_SEMAPHORED (0x0000001C) +#define NV826F_SEMAPHORED_OPERATION 2:0 +#define NV826F_SEMAPHORED_OPERATION_ACQUIRE 0x00000001 +#define NV826F_SEMAPHORED_OPERATION_RELEASE 0x00000002 +#define NV826F_SEMAPHORED_OPERATION_ACQ_GEQ 0x00000004 +#define NV826F_NON_STALLED_INTERRUPT (0x00000020) +#define NV826F_SET_CONTEXT_DMA_SEMAPHORE (0x00000060) +#endif /* _cl826f_h_ */ diff --git a/drivers/gpu/drm/nouveau/nouveau_dma.h b/drivers/gpu/drm/nouveau/nouveau_dma.h index 3f86cdff927f..ebe63396ff8b 100644 --- a/drivers/gpu/drm/nouveau/nouveau_dma.h +++ b/drivers/gpu/drm/nouveau/nouveau_dma.h @@ -104,7 +104,6 @@ WIND_RING(struct nouveau_channel *chan) } /* FIFO methods */ -#define NV01_SUBCHAN_OBJECT 0x00000000 #define NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH 0x00000010 #define NV84_SUBCHAN_SEMAPHORE_ADDRESS_LOW 0x00000014 #define NV84_SUBCHAN_SEMAPHORE_SEQUENCE 0x00000018 @@ -113,14 +112,10 @@ WIND_RING(struct nouveau_channel *chan) #define NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG 0x00000002 #define NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL 0x00000004 #define NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD 0x00001000 -#define NV84_SUBCHAN_UEVENT 0x00000020 -#define NV84_SUBCHAN_WRCACHE_FLUSH 0x00000024 -#define NV10_SUBCHAN_REF_CNT 0x00000050 #define NV11_SUBCHAN_DMA_SEMAPHORE 0x00000060 #define NV11_SUBCHAN_SEMAPHORE_OFFSET 0x00000064 #define NV11_SUBCHAN_SEMAPHORE_ACQUIRE 0x00000068 #define NV11_SUBCHAN_SEMAPHORE_RELEASE 0x0000006c -#define NV40_SUBCHAN_YIELD 0x00000080 /* NV_SW object class */ #define NV_SW_DMA_VBLSEM 0x0000018c diff --git a/drivers/gpu/drm/nouveau/nv10_fence.c b/drivers/gpu/drm/nouveau/nv10_fence.c index b5117b0c71c1..8e3f034d6e74 100644 --- a/drivers/gpu/drm/nouveau/nv10_fence.c +++ b/drivers/gpu/drm/nouveau/nv10_fence.c @@ -27,13 +27,15 @@ #include +#include + int nv10_fence_emit(struct nouveau_fence *fence) { struct nvif_push *push = fence->channel->chan.push; int ret = PUSH_WAIT(push, 2); if (ret == 0) { - PUSH_NVSQ(push, NV06E, NV10_SUBCHAN_REF_CNT, fence->base.seqno); + PUSH_MTHD(push, NV06E, SET_REFERENCE, fence->base.seqno); PUSH_KICK(push); } return ret; diff --git a/drivers/gpu/drm/nouveau/nv84_fence.c b/drivers/gpu/drm/nouveau/nv84_fence.c index bc09e64fe6b8..ec282f90d2ac 100644 --- a/drivers/gpu/drm/nouveau/nv84_fence.c +++ b/drivers/gpu/drm/nouveau/nv84_fence.c @@ -30,20 +30,26 @@ #include +#include + static int nv84_fence_emit32(struct nouveau_channel *chan, u64 virtual, u32 sequence) { struct nvif_push *push = chan->chan.push; int ret = PUSH_WAIT(push, 8); if (ret == 0) { - PUSH_NVSQ(push, NV826F, NV11_SUBCHAN_DMA_SEMAPHORE, chan->vram.handle); - PUSH_NVSQ(push, NV826F, - NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, upper_32_bits(virtual), - NV84_SUBCHAN_SEMAPHORE_ADDRESS_LOW, lower_32_bits(virtual), - NV84_SUBCHAN_SEMAPHORE_SEQUENCE, sequence, - NV84_SUBCHAN_SEMAPHORE_TRIGGER, - NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG, - NV84_SUBCHAN_UEVENT, 0x00000000); + PUSH_MTHD(push, NV826F, SET_CONTEXT_DMA_SEMAPHORE, chan->vram.handle); + + PUSH_MTHD(push, NV826F, SEMAPHOREA, + NVVAL(NV826F, SEMAPHOREA, OFFSET_UPPER, upper_32_bits(virtual)), + + SEMAPHOREB, lower_32_bits(virtual), + SEMAPHOREC, sequence, + + SEMAPHORED, + NVDEF(NV826F, SEMAPHORED, OPERATION, RELEASE), + + NON_STALLED_INTERRUPT, 0); PUSH_KICK(push); } return ret; diff --git a/drivers/gpu/drm/nouveau/nvc0_fence.c b/drivers/gpu/drm/nouveau/nvc0_fence.c index 13b1345081d9..f46a8900ac33 100644 --- a/drivers/gpu/drm/nouveau/nvc0_fence.c +++ b/drivers/gpu/drm/nouveau/nvc0_fence.c @@ -29,19 +29,26 @@ #include +#include + static int nvc0_fence_emit32(struct nouveau_channel *chan, u64 virtual, u32 sequence) { struct nvif_push *push = chan->chan.push; int ret = PUSH_WAIT(push, 6); if (ret == 0) { - PUSH_NVSQ(push, NV906F, - NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, upper_32_bits(virtual), - NV84_SUBCHAN_SEMAPHORE_ADDRESS_LOW, lower_32_bits(virtual), - NV84_SUBCHAN_SEMAPHORE_SEQUENCE, sequence, - NV84_SUBCHAN_SEMAPHORE_TRIGGER, - NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG, - NV84_SUBCHAN_UEVENT, 0x00000000); + PUSH_MTHD(push, NV906F, SEMAPHOREA, + NVVAL(NV906F, SEMAPHOREA, OFFSET_UPPER, upper_32_bits(virtual)), + + SEMAPHOREB, lower_32_bits(virtual), + SEMAPHOREC, sequence, + + SEMAPHORED, + NVDEF(NV906F, SEMAPHORED, OPERATION, RELEASE) | + NVDEF(NV906F, SEMAPHORED, RELEASE_WFI, EN) | + NVDEF(NV906F, SEMAPHORED, RELEASE_SIZE, 16BYTE), + + NON_STALL_INTERRUPT, 0); PUSH_KICK(push); } return ret; From 40f1171e7c26e57d71aa2800fb8ad213b4efb09c Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 20 Jul 2020 11:19:26 +1000 Subject: [PATCH 143/145] drm/nouveau/fence: use NVIDIA's headers for sync() Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- .../drm/nouveau/include/nvhw/class/cl176e.h | 10 ++++++++++ drivers/gpu/drm/nouveau/nouveau_dma.h | 14 -------------- drivers/gpu/drm/nouveau/nv17_fence.c | 18 ++++++++++-------- drivers/gpu/drm/nouveau/nv84_fence.c | 17 ++++++++++------- drivers/gpu/drm/nouveau/nvc0_fence.c | 16 +++++++++------- 5 files changed, 39 insertions(+), 36 deletions(-) create mode 100644 drivers/gpu/drm/nouveau/include/nvhw/class/cl176e.h diff --git a/drivers/gpu/drm/nouveau/include/nvhw/class/cl176e.h b/drivers/gpu/drm/nouveau/include/nvhw/class/cl176e.h new file mode 100644 index 000000000000..fa09725c8aea --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvhw/class/cl176e.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _cl176e_h_ +#define _cl176e_h_ + +#define NV176E_SET_OBJECT (0x00000000) +#define NV176E_SET_CONTEXT_DMA_SEMAPHORE (0x00000060) +#define NV176E_SEMAPHORE_OFFSET (0x00000064) +#define NV176E_SEMAPHORE_ACQUIRE (0x00000068) +#define NV176E_SEMAPHORE_RELEASE (0x0000006c) +#endif diff --git a/drivers/gpu/drm/nouveau/nouveau_dma.h b/drivers/gpu/drm/nouveau/nouveau_dma.h index ebe63396ff8b..035a709c7be1 100644 --- a/drivers/gpu/drm/nouveau/nouveau_dma.h +++ b/drivers/gpu/drm/nouveau/nouveau_dma.h @@ -103,20 +103,6 @@ WIND_RING(struct nouveau_channel *chan) chan->dma.cur = chan->dma.put; } -/* FIFO methods */ -#define NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH 0x00000010 -#define NV84_SUBCHAN_SEMAPHORE_ADDRESS_LOW 0x00000014 -#define NV84_SUBCHAN_SEMAPHORE_SEQUENCE 0x00000018 -#define NV84_SUBCHAN_SEMAPHORE_TRIGGER 0x0000001c -#define NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL 0x00000001 -#define NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG 0x00000002 -#define NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL 0x00000004 -#define NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD 0x00001000 -#define NV11_SUBCHAN_DMA_SEMAPHORE 0x00000060 -#define NV11_SUBCHAN_SEMAPHORE_OFFSET 0x00000064 -#define NV11_SUBCHAN_SEMAPHORE_ACQUIRE 0x00000068 -#define NV11_SUBCHAN_SEMAPHORE_RELEASE 0x0000006c - /* NV_SW object class */ #define NV_SW_DMA_VBLSEM 0x0000018c #define NV_SW_VBLSEM_OFFSET 0x00000400 diff --git a/drivers/gpu/drm/nouveau/nv17_fence.c b/drivers/gpu/drm/nouveau/nv17_fence.c index 8d7b4f2479cc..cd1e87a528a4 100644 --- a/drivers/gpu/drm/nouveau/nv17_fence.c +++ b/drivers/gpu/drm/nouveau/nv17_fence.c @@ -30,6 +30,8 @@ #include #include +#include + int nv17_fence_sync(struct nouveau_fence *fence, struct nouveau_channel *prev, struct nouveau_channel *chan) @@ -52,18 +54,18 @@ nv17_fence_sync(struct nouveau_fence *fence, ret = PUSH_WAIT(ppush, 5); if (!ret) { - PUSH_NVSQ(ppush, NV176E, NV11_SUBCHAN_DMA_SEMAPHORE, fctx->sema.handle, - NV11_SUBCHAN_SEMAPHORE_OFFSET, 0, - NV11_SUBCHAN_SEMAPHORE_ACQUIRE, value + 0, - NV11_SUBCHAN_SEMAPHORE_RELEASE, value + 1); + PUSH_MTHD(ppush, NV176E, SET_CONTEXT_DMA_SEMAPHORE, fctx->sema.handle, + SEMAPHORE_OFFSET, 0, + SEMAPHORE_ACQUIRE, value + 0, + SEMAPHORE_RELEASE, value + 1); PUSH_KICK(ppush); } if (!ret && !(ret = PUSH_WAIT(npush, 5))) { - PUSH_NVSQ(npush, NV176E, NV11_SUBCHAN_DMA_SEMAPHORE, fctx->sema.handle, - NV11_SUBCHAN_SEMAPHORE_OFFSET, 0, - NV11_SUBCHAN_SEMAPHORE_ACQUIRE, value + 1, - NV11_SUBCHAN_SEMAPHORE_RELEASE, value + 2); + PUSH_MTHD(npush, NV176E, SET_CONTEXT_DMA_SEMAPHORE, fctx->sema.handle, + SEMAPHORE_OFFSET, 0, + SEMAPHORE_ACQUIRE, value + 1, + SEMAPHORE_RELEASE, value + 2); PUSH_KICK(npush); } diff --git a/drivers/gpu/drm/nouveau/nv84_fence.c b/drivers/gpu/drm/nouveau/nv84_fence.c index ec282f90d2ac..7ed36b3a6b7d 100644 --- a/drivers/gpu/drm/nouveau/nv84_fence.c +++ b/drivers/gpu/drm/nouveau/nv84_fence.c @@ -61,13 +61,16 @@ nv84_fence_sync32(struct nouveau_channel *chan, u64 virtual, u32 sequence) struct nvif_push *push = chan->chan.push; int ret = PUSH_WAIT(push, 7); if (ret == 0) { - PUSH_NVSQ(push, NV826F, NV11_SUBCHAN_DMA_SEMAPHORE, chan->vram.handle); - PUSH_NVSQ(push, NV826F, - NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, upper_32_bits(virtual), - NV84_SUBCHAN_SEMAPHORE_ADDRESS_LOW, lower_32_bits(virtual), - NV84_SUBCHAN_SEMAPHORE_SEQUENCE, sequence, - NV84_SUBCHAN_SEMAPHORE_TRIGGER, - NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL); + PUSH_MTHD(push, NV826F, SET_CONTEXT_DMA_SEMAPHORE, chan->vram.handle); + + PUSH_MTHD(push, NV826F, SEMAPHOREA, + NVVAL(NV826F, SEMAPHOREA, OFFSET_UPPER, upper_32_bits(virtual)), + + SEMAPHOREB, lower_32_bits(virtual), + SEMAPHOREC, sequence, + + SEMAPHORED, + NVDEF(NV826F, SEMAPHORED, OPERATION, ACQ_GEQ)); PUSH_KICK(push); } return ret; diff --git a/drivers/gpu/drm/nouveau/nvc0_fence.c b/drivers/gpu/drm/nouveau/nvc0_fence.c index f46a8900ac33..e1461c0b0779 100644 --- a/drivers/gpu/drm/nouveau/nvc0_fence.c +++ b/drivers/gpu/drm/nouveau/nvc0_fence.c @@ -60,13 +60,15 @@ nvc0_fence_sync32(struct nouveau_channel *chan, u64 virtual, u32 sequence) struct nvif_push *push = chan->chan.push; int ret = PUSH_WAIT(push, 5); if (ret == 0) { - PUSH_NVSQ(push, NV906F, - NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, upper_32_bits(virtual), - NV84_SUBCHAN_SEMAPHORE_ADDRESS_LOW, lower_32_bits(virtual), - NV84_SUBCHAN_SEMAPHORE_SEQUENCE, sequence, - NV84_SUBCHAN_SEMAPHORE_TRIGGER, - NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL | - NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD); + PUSH_MTHD(push, NV906F, SEMAPHOREA, + NVVAL(NV906F, SEMAPHOREA, OFFSET_UPPER, upper_32_bits(virtual)), + + SEMAPHOREB, lower_32_bits(virtual), + SEMAPHOREC, sequence, + + SEMAPHORED, + NVDEF(NV906F, SEMAPHORED, OPERATION, ACQ_GEQ) | + NVDEF(NV906F, SEMAPHORED, ACQUIRE_SWITCH, ENABLED)); PUSH_KICK(push); } return ret; From 2bd43e0ad0f06bb902579294849194a818a0ff96 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Wed, 22 Jul 2020 17:21:59 +1000 Subject: [PATCH 144/145] drm/nouveau/fence: use NVIDIA's headers for read() Signed-off-by: Ben Skeggs Reviewed-by: Lyude Paul --- drivers/gpu/drm/nouveau/nv10_fence.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/nouveau/nv10_fence.c b/drivers/gpu/drm/nouveau/nv10_fence.c index 8e3f034d6e74..c6a0db5b9e21 100644 --- a/drivers/gpu/drm/nouveau/nv10_fence.c +++ b/drivers/gpu/drm/nouveau/nv10_fence.c @@ -52,7 +52,7 @@ nv10_fence_sync(struct nouveau_fence *fence, u32 nv10_fence_read(struct nouveau_channel *chan) { - return nvif_rd32(&chan->user, 0x0048); + return NVIF_RD32(&chan->user, NV06E, REFERENCE); } void From 0059a9081ac37b4513c98ce443b03c1b1f196810 Mon Sep 17 00:00:00 2001 From: Lyude Paul Date: Mon, 20 Jul 2020 16:56:56 -0400 Subject: [PATCH 145/145] drm/nouveau/kms/nv50-: Fix CRC-related compile errors with debugfs disabled MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Looks like I made the mistake of forgetting to check whether or not this would build without CONFIG_DEBUG_FS, as the Kbuild bot reported some issues building with tegra_defconfig: In file included from drivers/gpu/drm/nouveau/nouveau_display.c:47: ./drivers/gpu/drm/nouveau/dispnv50/crc.h: In function ‘nv50_head_crc_late_register’: ./drivers/gpu/drm/nouveau/dispnv50/crc.h:106:47: error: parameter name omitted 106 | static inline int nv50_head_crc_late_register(struct nv50_head *) {} | ^~~~~~~~~~~~~~~~~~ ./drivers/gpu/drm/nouveau/dispnv50/crc.h:106:54: warning: no return statement in function returning non-void [-Wreturn-type] 106 | static inline int nv50_head_crc_late_register(struct nv50_head *) {} | ^~~~~~~~~ ./drivers/gpu/drm/nouveau/dispnv50/crc.h: In function ‘nv50_crc_handle_vblank’: ./drivers/gpu/drm/nouveau/dispnv50/crc.h:108:57: warning: ‘return’ with a value, in function returning void [-Wreturn-type] 108 | nv50_crc_handle_vblank(struct nv50_head *head) { return 0; } | ^ ./drivers/gpu/drm/nouveau/dispnv50/crc.h:108:1: note: declared here 108 | nv50_crc_handle_vblank(struct nv50_head *head) { return 0; } | ^~~~~~~~~~~~~~~~~~~~~~ ./drivers/gpu/drm/nouveau/dispnv50/crc.h: In function ‘nv50_crc_atomic_check’: ./drivers/gpu/drm/nouveau/dispnv50/crc.h:111:23: error: parameter name omitted 111 | nv50_crc_atomic_check(struct nv50_head *, struct nv50_head_atom *, | ^~~~~~~~~~~~~~~~~~ ./drivers/gpu/drm/nouveau/dispnv50/crc.h:111:43: error: parameter name omitted 111 | nv50_crc_atomic_check(struct nv50_head *, struct nv50_head_atom *, | ^~~~~~~~~~~~~~~~~~~~~~~ ./drivers/gpu/drm/nouveau/dispnv50/crc.h:112:9: error: parameter name omitted 112 | struct nv50_head_atom *) {} | ^~~~~~~~~~~~~~~~~~~~~~~ ./drivers/gpu/drm/nouveau/dispnv50/crc.h:112:16: warning: no return statement in function returning non-void [-Wreturn-type] 112 | struct nv50_head_atom *) {} | ^~~~~~~~~~~~~~ ./drivers/gpu/drm/nouveau/dispnv50/crc.h: In function ‘nv50_crc_atomic_stop_reporting’: ./drivers/gpu/drm/nouveau/dispnv50/crc.h:114:32: error: parameter name omitted 114 | nv50_crc_atomic_stop_reporting(struct drm_atomic_state *) {} | ^~~~~~~~~~~~~~~~~~~~~~~~~ ./drivers/gpu/drm/nouveau/dispnv50/crc.h: In function ‘nv50_crc_atomic_prepare_notifier_contexts’: ./drivers/gpu/drm/nouveau/dispnv50/crc.h:116:43: error: parameter name omitted 116 | nv50_crc_atomic_prepare_notifier_contexts(struct drm_atomic_state *) {} | ^~~~~~~~~~~~~~~~~~~~~~~~~ ./drivers/gpu/drm/nouveau/dispnv50/crc.h: In function ‘nv50_crc_atomic_start_reporting’: ./drivers/gpu/drm/nouveau/dispnv50/crc.h:118:33: error: parameter name omitted 118 | nv50_crc_atomic_start_reporting(struct drm_atomic_state *) {} | ^~~~~~~~~~~~~~~~~~~~~~~~~ ./drivers/gpu/drm/nouveau/dispnv50/crc.h: In function ‘nv50_crc_atomic_set’: ./drivers/gpu/drm/nouveau/dispnv50/crc.h:120:21: error: parameter name omitted 120 | nv50_crc_atomic_set(struct nv50_head *, struct nv50_head_atom *) {} | ^~~~~~~~~~~~~~~~~~ ./drivers/gpu/drm/nouveau/dispnv50/crc.h:120:41: error: parameter name omitted 120 | nv50_crc_atomic_set(struct nv50_head *, struct nv50_head_atom *) {} | ^~~~~~~~~~~~~~~~~~~~~~~ ./drivers/gpu/drm/nouveau/dispnv50/crc.h: In function ‘nv50_crc_atomic_clr’: ./drivers/gpu/drm/nouveau/dispnv50/crc.h:122:21: error: parameter name omitted 122 | nv50_crc_atomic_clr(struct nv50_head *) {} | ^~~~~~~~~~~~~~~~~~ drivers/gpu/drm/nouveau/nouveau_display.c: In function ‘nouveau_framebuffer_new’: drivers/gpu/drm/nouveau/nouveau_display.c:286:15: warning: variable ‘width’ set but not used [-Wunused-but-set-variable] 286 | unsigned int width, height, i; | ^~~~~ So, fix the inline function declarations we use in drm/drivers/gpu/drm/nouveau/dispnv50/crc.h when CONFIG_DEBUG_FS is enabled. Fixes: 12885ecbfe62 ("drm/nouveau/kms/nvd9-: Add CRC support") Reported-by: kernel test robot Signed-off-by: Lyude Paul Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/dispnv50/crc.h | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/crc.h b/drivers/gpu/drm/nouveau/dispnv50/crc.h index ffb7b7c19570..4fce871b04c8 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/crc.h +++ b/drivers/gpu/drm/nouveau/dispnv50/crc.h @@ -106,26 +106,27 @@ struct nv50_crc_atom {}; #define nv50_crc_set_source NULL static inline void nv50_crc_init(struct drm_device *dev) {} -static inline int nv50_head_crc_late_register(struct nv50_head *) {} -static inline void -nv50_crc_handle_vblank(struct nv50_head *head) { return 0; } +static inline int +nv50_head_crc_late_register(struct nv50_head *head) { return 0; } +static inline void nv50_crc_handle_vblank(struct nv50_head *head) {} static inline int -nv50_crc_atomic_check_head(struct nv50_head *, struct nv50_head_atom *, - struct nv50_head_atom *) {} +nv50_crc_atomic_check_head(struct nv50_head *head, + struct nv50_head_atom *asyh, + struct nv50_head_atom *armh) { return 0; } static inline void nv50_crc_atomic_check_outp(struct nv50_atom *atom) {} static inline void -nv50_crc_atomic_stop_reporting(struct drm_atomic_state *) {} +nv50_crc_atomic_stop_reporting(struct drm_atomic_state *state) {} static inline void -nv50_crc_atomic_init_notifier_contexts(struct drm_atomic_state *) {} +nv50_crc_atomic_init_notifier_contexts(struct drm_atomic_state *state) {} static inline void -nv50_crc_atomic_release_notifier_contexts(struct drm_atomic_state *) {} +nv50_crc_atomic_release_notifier_contexts(struct drm_atomic_state *state) {} static inline void -nv50_crc_atomic_start_reporting(struct drm_atomic_state *) {} +nv50_crc_atomic_start_reporting(struct drm_atomic_state *state) {} static inline void -nv50_crc_atomic_set(struct nv50_head *, struct nv50_head_atom *) {} +nv50_crc_atomic_set(struct nv50_head *head, struct nv50_head_atom *state) {} static inline void -nv50_crc_atomic_clr(struct nv50_head *) {} +nv50_crc_atomic_clr(struct nv50_head *head) {} #endif /* IS_ENABLED(CONFIG_DEBUG_FS) */ #endif /* !__NV50_CRC_H__ */