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dt-bindings: media: Convert Allwinner hardware codec to a schema 

The Allwinner SoCs have a hardware video codec that is supported in Linux,
with a matching Device Tree binding.

Now that we have the DT validation in place, let's convert the device tree
bindings for that controller over to a YAML schemas.

Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Signed-off-by: Rob Herring <robh@kernel.org>
This commit is contained in:
Maxime Ripard 2019-12-13 08:40:55 +01:00 committed by Rob Herring
parent e4597da1d6
commit fc0b90f63e
2 changed files with 83 additions and 57 deletions
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83
Documentation/devicetree/bindings/media/allwinner,sun4i-a10-video-engine.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/allwinner,sun4i-a10-video-engine.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A10 Video Engine Device Tree Bindings
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <mripard@kernel.org>
properties:
compatible:
enum:
- allwinner,sun4i-a10-video-engine
- allwinner,sun5i-a13-video-engine
- allwinner,sun7i-a20-video-engine
- allwinner,sun8i-a33-video-engine
- allwinner,sun8i-h3-video-engine
- allwinner,sun50i-a64-video-engine
- allwinner,sun50i-h5-video-engine
- allwinner,sun50i-h6-video-engine
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
items:
- description: Bus Clock
- description: Module Clock
- description: RAM Clock
clock-names:
items:
- const: ahb
- const: mod
- const: ram
resets:
maxItems: 1
allwinner,sram:
$ref: /schemas/types.yaml#/definitions/phandle-array
description: Phandle to the device SRAM
memory-region:
description:
CMA pool to use for buffers allocation instead of the default
CMA pool.
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- resets
- allwinner,sram
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/sun7i-a20-ccu.h>
#include <dt-bindings/reset/sun4i-a10-ccu.h>
video-codec@1c0e000 {
compatible = "allwinner,sun7i-a20-video-engine";
reg = <0x01c0e000 0x1000>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>,
<&ccu CLK_DRAM_VE>;
clock-names = "ahb", "mod", "ram";
resets = <&ccu RST_VE>;
allwinner,sram = <&ve_sram 1>;
};
...

57
Documentation/devicetree/bindings/media/cedrus.txt
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@ -1,57 +0,0 @@
Device-tree bindings for the VPU found in Allwinner SoCs, referred to as the
Video Engine (VE) in Allwinner literature.
The VPU can only access the first 256 MiB of DRAM, that are DMA-mapped starting
from the DRAM base. This requires specific memory allocation and handling.
Required properties:
- compatible : must be one of the following compatibles:
- "allwinner,sun4i-a10-video-engine"
- "allwinner,sun5i-a13-video-engine"
- "allwinner,sun7i-a20-video-engine"
- "allwinner,sun8i-a33-video-engine"
- "allwinner,sun8i-h3-video-engine"
- "allwinner,sun50i-a64-video-engine"
- "allwinner,sun50i-h5-video-engine"
- "allwinner,sun50i-h6-video-engine"
- reg : register base and length of VE;
- clocks : list of clock specifiers, corresponding to entries in
the clock-names property;
- clock-names : should contain "ahb", "mod" and "ram" entries;
- resets : phandle for reset;
- interrupts : VE interrupt number;
- allwinner,sram : SRAM region to use with the VE.
Optional properties:
- memory-region : CMA pool to use for buffers allocation instead of the
default CMA pool.
Example:
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
/* Address must be kept in the lower 256 MiBs of DRAM for VE. */
cma_pool: default-pool {
compatible = "shared-dma-pool";
size = <0x6000000>;
alloc-ranges = <0x4a000000 0x6000000>;
reusable;
linux,cma-default;
};
};
video-codec@1c0e000 {
compatible = "allwinner,sun7i-a20-video-engine";
reg = <0x01c0e000 0x1000>;
clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>,
<&ccu CLK_DRAM_VE>;
clock-names = "ahb", "mod", "ram";
resets = <&ccu RST_VE>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
allwinner,sram = <&ve_sram 1>;
};