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net: stmmac: dwxgmac2: Only clear interrupts that are active 

In DMA interrupt handler we were clearing all interrupts status, even
the ones that were not active. Fix this and only clear the active
interrupts.

Cc: Joao Pinto <jpinto@synopsys.com>
Cc: David S. Miller <davem@davemloft.net>
Cc: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Signed-off-by: Jose Abreu <joabreu@synopsys.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Jose Abreu 2019-01-09 10:05:57 +01:00 committed by David S. Miller
parent 6dea7e1881
commit fcc509eb10
1 changed files with 3 additions and 3 deletions
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6
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
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@ -263,6 +263,7 @@ static int dwxgmac2_dma_interrupt(void __iomem *ioaddr,
struct stmmac_extra_stats *x, u32 chan) struct stmmac_extra_stats *x, u32 chan)
{ {
u32 intr_status = readl(ioaddr + XGMAC_DMA_CH_STATUS(chan)); u32 intr_status = readl(ioaddr + XGMAC_DMA_CH_STATUS(chan));
u32 intr_en = readl(ioaddr + XGMAC_DMA_CH_INT_EN(chan));
int ret = 0; int ret = 0;
/* ABNORMAL interrupts */ /* ABNORMAL interrupts */
@ -282,8 +283,7 @@ static int dwxgmac2_dma_interrupt(void __iomem *ioaddr,
x->normal_irq_n++; x->normal_irq_n++;
if (likely(intr_status & XGMAC_RI)) { if (likely(intr_status & XGMAC_RI)) {
u32 value = readl(ioaddr + XGMAC_DMA_CH_INT_EN(chan)); if (likely(intr_en & XGMAC_RIE)) {
if (likely(value & XGMAC_RIE)) {
x->rx_normal_irq_n++; x->rx_normal_irq_n++;
ret |= handle_rx; ret |= handle_rx;
} }
@ -295,7 +295,7 @@ static int dwxgmac2_dma_interrupt(void __iomem *ioaddr,
} }
/* Clear interrupts */ /* Clear interrupts */
writel(~0x0, ioaddr + XGMAC_DMA_CH_STATUS(chan)); writel(intr_en & intr_status, ioaddr + XGMAC_DMA_CH_STATUS(chan));
return ret; return ret;
} }