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ARM: mach-shmobile: clock-r8a7740: add USB clock
R8A7740 USB needs many clocks for workaround, and it has confusing name "usb24s" and "usb24". This "usb24s" will be used by other clocks. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Tested-by: Simon Horman <horms@verge.net.au> Acked-by: Magnus Damm <damm@opensource.se> Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
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@ -47,6 +47,7 @@
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#define PLLC01CR 0xe6150028
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#define PLLC01CR 0xe6150028
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#define SUBCKCR 0xe6150080
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#define SUBCKCR 0xe6150080
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#define USBCKCR 0xe615008c
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#define MSTPSR0 0xe6150030
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#define MSTPSR0 0xe6150030
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#define MSTPSR1 0xe6150038
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#define MSTPSR1 0xe6150038
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@ -181,6 +182,100 @@ static struct clk pllc1_div2_clk = {
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.parent = &pllc1_clk,
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.parent = &pllc1_clk,
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};
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};
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/* USB clock */
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static struct clk *usb24s_parents[] = {
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[0] = &system_clk,
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[1] = &extal2_clk
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};
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static unsigned long usb24s_recalc(struct clk *clk)
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{
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return clk->parent->rate;
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};
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static int usb24s_enable(struct clk *clk)
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{
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__raw_writel(__raw_readl(USBCKCR) & ~(1 << 8), USBCKCR);
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return 0;
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}
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static void usb24s_disable(struct clk *clk)
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{
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__raw_writel(__raw_readl(USBCKCR) | (1 << 8), USBCKCR);
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}
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static int usb24s_set_parent(struct clk *clk, struct clk *parent)
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{
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int i, ret;
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u32 val;
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if (!clk->parent_table || !clk->parent_num)
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return -EINVAL;
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/* Search the parent */
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for (i = 0; i < clk->parent_num; i++)
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if (clk->parent_table[i] == parent)
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break;
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if (i == clk->parent_num)
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return -ENODEV;
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ret = clk_reparent(clk, parent);
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if (ret < 0)
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return ret;
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val = __raw_readl(USBCKCR);
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val &= ~(1 << 7);
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val |= i << 7;
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__raw_writel(val, USBCKCR);
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return 0;
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}
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static struct sh_clk_ops usb24s_clk_ops = {
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.recalc = usb24s_recalc,
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.enable = usb24s_enable,
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.disable = usb24s_disable,
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.set_parent = usb24s_set_parent,
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};
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static struct clk usb24s_clk = {
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.ops = &usb24s_clk_ops,
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.parent_table = usb24s_parents,
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.parent_num = ARRAY_SIZE(usb24s_parents),
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.parent = &system_clk,
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};
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static unsigned long usb24_recalc(struct clk *clk)
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{
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return clk->parent->rate /
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((__raw_readl(USBCKCR) & (1 << 6)) ? 1 : 2);
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};
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static int usb24_set_rate(struct clk *clk, unsigned long rate)
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{
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u32 val;
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/* closer to which ? parent->rate or parent->rate/2 */
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val = __raw_readl(USBCKCR);
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val &= ~(1 << 6);
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val |= (rate > (clk->parent->rate / 4) * 3) << 6;
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__raw_writel(val, USBCKCR);
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return 0;
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}
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static struct sh_clk_ops usb24_clk_ops = {
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.recalc = usb24_recalc,
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.set_rate = usb24_set_rate,
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};
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static struct clk usb24_clk = {
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.ops = &usb24_clk_ops,
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.parent = &usb24s_clk,
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};
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struct clk *main_clks[] = {
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struct clk *main_clks[] = {
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&extalr_clk,
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&extalr_clk,
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&extal1_clk,
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&extal1_clk,
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@ -196,6 +291,8 @@ struct clk *main_clks[] = {
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&pllc0_clk,
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&pllc0_clk,
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&pllc1_clk,
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&pllc1_clk,
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&pllc1_div2_clk,
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&pllc1_div2_clk,
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&usb24s_clk,
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&usb24_clk,
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};
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};
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static void div4_kick(struct clk *clk)
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static void div4_kick(struct clk *clk)
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@ -223,7 +320,7 @@ static struct clk_div4_table div4_table = {
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enum {
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enum {
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DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_HP,
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DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_HP,
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DIV4_HPP, DIV4_S, DIV4_ZB, DIV4_M3, DIV4_CP,
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DIV4_HPP, DIV4_USBP, DIV4_S, DIV4_ZB, DIV4_M3, DIV4_CP,
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DIV4_NR
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DIV4_NR
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};
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};
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@ -234,6 +331,7 @@ struct clk div4_clks[DIV4_NR] = {
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[DIV4_M1] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 4, 0x6fff, CLK_ENABLE_ON_INIT),
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[DIV4_M1] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 4, 0x6fff, CLK_ENABLE_ON_INIT),
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[DIV4_HP] = SH_CLK_DIV4(&pllc1_clk, FRQCRB, 4, 0x6fff, 0),
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[DIV4_HP] = SH_CLK_DIV4(&pllc1_clk, FRQCRB, 4, 0x6fff, 0),
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[DIV4_HPP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 20, 0x6fff, 0),
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[DIV4_HPP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 20, 0x6fff, 0),
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[DIV4_USBP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 16, 0x6fff, 0),
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[DIV4_S] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 12, 0x6fff, 0),
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[DIV4_S] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 12, 0x6fff, 0),
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[DIV4_ZB] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 8, 0x6fff, 0),
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[DIV4_ZB] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 8, 0x6fff, 0),
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[DIV4_M3] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 4, 0x6fff, 0),
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[DIV4_M3] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 4, 0x6fff, 0),
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@ -257,7 +355,9 @@ enum {
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MSTP222,
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MSTP222,
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MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
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MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
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MSTP329, MSTP328, MSTP323,
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MSTP329, MSTP328, MSTP323, MSTP320,
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MSTP416, MSTP407, MSTP406,
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MSTP_NR
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MSTP_NR
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};
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};
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@ -282,6 +382,11 @@ static struct clk mstp_clks[MSTP_NR] = {
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[MSTP329] = SH_CLK_MSTP32(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */
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[MSTP329] = SH_CLK_MSTP32(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */
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[MSTP328] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 28, 0), /* FSI */
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[MSTP328] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 28, 0), /* FSI */
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[MSTP323] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR3, 23, 0), /* IIC1 */
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[MSTP323] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR3, 23, 0), /* IIC1 */
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[MSTP320] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 20, 0), /* USBF */
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[MSTP416] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR4, 16, 0), /* USBHOST */
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[MSTP407] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR4, 7, 0), /* USB-Func */
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[MSTP406] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR4, 6, 0), /* USB Phy */
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};
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};
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static struct clk_lookup lookups[] = {
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static struct clk_lookup lookups[] = {
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@ -300,6 +405,7 @@ static struct clk_lookup lookups[] = {
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CLKDEV_CON_ID("pllc0_clk", &pllc0_clk),
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CLKDEV_CON_ID("pllc0_clk", &pllc0_clk),
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CLKDEV_CON_ID("pllc1_clk", &pllc1_clk),
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CLKDEV_CON_ID("pllc1_clk", &pllc1_clk),
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CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk),
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CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk),
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CLKDEV_CON_ID("usb24s", &usb24s_clk),
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/* DIV4 clocks */
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/* DIV4 clocks */
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CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]),
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CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]),
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@ -337,6 +443,14 @@ static struct clk_lookup lookups[] = {
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CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]),
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CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]),
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CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]),
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CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]),
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CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]),
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CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]),
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CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP320]),
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/* ICK */
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CLKDEV_ICK_ID("host", "renesas_usbhs", &mstp_clks[MSTP416]),
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CLKDEV_ICK_ID("func", "renesas_usbhs", &mstp_clks[MSTP407]),
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CLKDEV_ICK_ID("phy", "renesas_usbhs", &mstp_clks[MSTP406]),
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CLKDEV_ICK_ID("pci", "renesas_usbhs", &div4_clks[DIV4_USBP]),
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CLKDEV_ICK_ID("usb24", "renesas_usbhs", &usb24_clk),
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};
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};
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void __init r8a7740_clock_init(u8 md_ck)
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void __init r8a7740_clock_init(u8 md_ck)
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