mirror of https://gitee.com/openkylin/linux.git
drm/i915: reference counted forcewake
Provide a reference count to track the forcewake state of the GPU and give a safe mechanism for userspace to wake the GT. This also potentially saves a UC read if the GT is known to be awake already. The reference count is atomic, but the register access and hardware wake sequence is protected by struct_mutex. Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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@ -874,7 +874,7 @@ static int i915_cur_delayinfo(struct seq_file *m, void *unused)
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int max_freq;
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/* RPSTAT1 is in the GT power well */
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__gen6_gt_force_wake_get(dev_priv);
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gen6_gt_force_wake_get(dev_priv);
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rpstat = I915_READ(GEN6_RPSTAT1);
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rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
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@ -919,7 +919,7 @@ static int i915_cur_delayinfo(struct seq_file *m, void *unused)
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seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
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max_freq * 50);
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__gen6_gt_force_wake_put(dev_priv);
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gen6_gt_force_wake_put(dev_priv);
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} else {
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seq_printf(m, "no P-state info available\n");
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}
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@ -263,7 +263,7 @@ void intel_detect_pch (struct drm_device *dev)
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}
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}
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void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
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static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
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{
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int count;
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@ -279,12 +279,38 @@ void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
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udelay(10);
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}
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void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
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/*
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* Generally this is called implicitly by the register read function. However,
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* if some sequence requires the GT to not power down then this function should
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* be called at the beginning of the sequence followed by a call to
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* gen6_gt_force_wake_put() at the end of the sequence.
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*/
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void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
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{
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WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));
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/* Forcewake is atomic in case we get in here without the lock */
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if (atomic_add_return(1, &dev_priv->forcewake_count) == 1)
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__gen6_gt_force_wake_get(dev_priv);
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}
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static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
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{
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I915_WRITE_NOTRACE(FORCEWAKE, 0);
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POSTING_READ(FORCEWAKE);
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}
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/*
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* see gen6_gt_force_wake_get()
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*/
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void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
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{
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WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));
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if (atomic_dec_and_test(&dev_priv->forcewake_count))
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__gen6_gt_force_wake_put(dev_priv);
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}
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void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
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{
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int loop = 500;
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@ -709,6 +709,8 @@ typedef struct drm_i915_private {
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struct intel_fbdev *fbdev;
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struct drm_property *broadcast_rgb_property;
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atomic_t forcewake_count;
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} drm_i915_private_t;
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enum i915_cache_level {
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@ -1329,8 +1331,8 @@ extern void intel_display_print_error_state(struct seq_file *m,
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* must be set to prevent GT core from power down and stale values being
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* returned.
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*/
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void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
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void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
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void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
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void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
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void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
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/* We give fast paths for the really cool registers */
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@ -1343,15 +1345,16 @@ void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
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static inline u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
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u##x val = 0; \
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if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
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__gen6_gt_force_wake_get(dev_priv); \
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gen6_gt_force_wake_get(dev_priv); \
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val = read##y(dev_priv->regs + reg); \
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__gen6_gt_force_wake_put(dev_priv); \
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gen6_gt_force_wake_put(dev_priv); \
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} else { \
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val = read##y(dev_priv->regs + reg); \
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} \
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trace_i915_reg_rw(false, reg, val, sizeof(val)); \
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return val; \
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}
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__i915_read(8, b)
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__i915_read(16, w)
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__i915_read(32, l)
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@ -396,7 +396,6 @@ static void gen6_pm_irq_handler(struct drm_device *dev)
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I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
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I915_READ(GEN6_RP_INTERRUPT_LIMITS) & ~0x3f0000);
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}
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}
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gen6_set_rps(dev, new_delay);
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@ -1540,7 +1540,7 @@ static void sandybridge_blit_fbc_update(struct drm_device *dev)
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u32 blt_ecoskpd;
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/* Make sure blitter notifies FBC of writes */
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__gen6_gt_force_wake_get(dev_priv);
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gen6_gt_force_wake_get(dev_priv);
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blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
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blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
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GEN6_BLITTER_LOCK_SHIFT;
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@ -1551,7 +1551,7 @@ static void sandybridge_blit_fbc_update(struct drm_device *dev)
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GEN6_BLITTER_LOCK_SHIFT);
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I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
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POSTING_READ(GEN6_BLITTER_ECOSKPD);
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__gen6_gt_force_wake_put(dev_priv);
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gen6_gt_force_wake_put(dev_priv);
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}
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static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
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@ -6973,7 +6973,7 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv)
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* userspace...
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*/
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I915_WRITE(GEN6_RC_STATE, 0);
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__gen6_gt_force_wake_get(dev_priv);
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gen6_gt_force_wake_get(dev_priv);
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/* disable the counters and set deterministic thresholds */
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I915_WRITE(GEN6_RC_CONTROL, 0);
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@ -7074,7 +7074,7 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv)
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/* enable all PM interrupts */
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I915_WRITE(GEN6_PMINTRMSK, 0);
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__gen6_gt_force_wake_put(dev_priv);
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gen6_gt_force_wake_put(dev_priv);
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}
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void intel_enable_clock_gating(struct drm_device *dev)
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