mirror of https://gitee.com/openkylin/linux.git
pinctrl: mvebu: new driver for Orion platforms
This commit extends the pinctrl mvebu logic with a new driver to cover Orion5x SoC. It supports the definitions for the 5181l, 5182 and 5281 variants of Orion5x, which are the three ones supported by the old style MPP code in arch/arm/mach-orion5x/. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Thomas Petazzoni
Linus Walleij
parent
a076e2ed3f
commit
fd67f88478
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@ -0,0 +1,91 @@
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* Marvell Orion SoC pinctrl driver for mpp
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Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
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part and usage.
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Required properties:
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- compatible: "marvell,88f5181l-pinctrl", "marvell,88f5182-pinctrl",
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"marvell,88f5281-pinctrl"
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- reg: two register areas, the first one describing the first two
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contiguous MPP registers, and the second one describing the single
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final MPP register, separated from the previous one.
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Available mpp pins/groups and functions:
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Note: brackets (x) are not part of the mpp name for marvell,function and given
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only for more detailed description in this document.
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* Marvell Orion 88f5181l
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name pins functions
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================================================================================
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mpp0 0 pcie(rstout), pci(req2), gpio
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mpp1 1 gpio, pci(gnt2)
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mpp2 2 gpio, pci(req3), pci-1(pme)
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mpp3 3 gpio, pci(gnt3)
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mpp4 4 gpio, pci(req4)
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mpp5 5 gpio, pci(gnt4)
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mpp6 6 gpio, pci(req5), pci-1(clk)
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mpp7 7 gpio, pci(gnt5), pci-1(clk)
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mpp8 8 gpio, ge(col)
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mpp9 9 gpio, ge(rxerr)
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mpp10 10 gpio, ge(crs)
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mpp11 11 gpio, ge(txerr)
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mpp12 12 gpio, ge(txd4)
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mpp13 13 gpio, ge(txd5)
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mpp14 14 gpio, ge(txd6)
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mpp15 15 gpio, ge(txd7)
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mpp16 16 ge(rxd4)
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mpp17 17 ge(rxd5)
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mpp18 18 ge(rxd6)
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mpp19 19 ge(rxd7)
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* Marvell Orion 88f5182
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name pins functions
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================================================================================
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mpp0 0 pcie(rstout), pci(req2), gpio
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mpp1 1 gpio, pci(gnt2)
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mpp2 2 gpio, pci(req3), pci-1(pme)
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mpp3 3 gpio, pci(gnt3)
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mpp4 4 gpio, pci(req4), bootnand(re), sata0(prsnt)
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mpp5 5 gpio, pci(gnt4), bootnand(we), sata1(prsnt)
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mpp6 6 gpio, pci(req5), nand(re0), sata0(act)
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mpp7 7 gpio, pci(gnt5), nand(we0), sata1(act)
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mpp8 8 gpio, ge(col)
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mpp9 9 gpio, ge(rxerr)
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mpp10 10 gpio, ge(crs)
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mpp11 11 gpio, ge(txerr)
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mpp12 12 gpio, ge(txd4), nand(re1), sata0(ledprsnt)
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mpp13 13 gpio, ge(txd5), nand(we1), sata1(ledprsnt)
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mpp14 14 gpio, ge(txd6), nand(re2), sata0(ledact)
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mpp15 15 gpio, ge(txd7), nand(we2), sata1(ledact)
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mpp16 16 uart1(rxd), ge(rxd4), gpio
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mpp17 17 uart1(txd), ge(rxd5), gpio
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mpp18 18 uart1(cts), ge(rxd6), gpio
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mpp19 19 uart1(rts), ge(rxd7), gpio
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* Marvell Orion 88f5281
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name pins functions
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================================================================================
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mpp0 0 pcie(rstout), pci(req2), gpio
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mpp1 1 gpio, pci(gnt2)
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mpp2 2 gpio, pci(req3), pci(pme)
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mpp3 3 gpio, pci(gnt3)
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mpp4 4 gpio, pci(req4), bootnand(re)
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mpp5 5 gpio, pci(gnt4), bootnand(we)
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mpp6 6 gpio, pci(req5), nand(re0)
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mpp7 7 gpio, pci(gnt5), nand(we0)
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mpp8 8 gpio, ge(col)
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mpp9 9 gpio, ge(rxerr)
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mpp10 10 gpio, ge(crs)
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mpp11 11 gpio, ge(txerr)
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mpp12 12 gpio, ge(txd4), nand(re1)
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mpp13 13 gpio, ge(txd5), nand(we1)
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mpp14 14 gpio, ge(txd6), nand(re2)
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mpp15 15 gpio, ge(txd7), nand(we2)
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mpp16 16 uart1(rxd), ge(rxd4)
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mpp17 17 uart1(txd), ge(rxd5)
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mpp18 18 uart1(cts), ge(rxd6)
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mpp19 19 uart1(rts), ge(rxd7)
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@ -30,4 +30,8 @@ config PINCTRL_ARMADA_XP
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bool
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select PINCTRL_MVEBU
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config PINCTRL_ORION
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bool
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select PINCTRL_MVEBU
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endif
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@ -5,3 +5,4 @@ obj-$(CONFIG_PINCTRL_ARMADA_370) += pinctrl-armada-370.o
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obj-$(CONFIG_PINCTRL_ARMADA_375) += pinctrl-armada-375.o
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obj-$(CONFIG_PINCTRL_ARMADA_38X) += pinctrl-armada-38x.o
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obj-$(CONFIG_PINCTRL_ARMADA_XP) += pinctrl-armada-xp.o
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obj-$(CONFIG_PINCTRL_ORION) += pinctrl-orion.o
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@ -0,0 +1,261 @@
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/*
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* Marvell Orion pinctrl driver based on mvebu pinctrl core
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*
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* Author: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* The first 16 MPP pins on Orion are easy to handle: they are
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* configured through 2 consecutive registers, located at the base
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* address of the MPP device.
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*
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* However the last 4 MPP pins are handled by a register at offset
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* 0x50 from the base address, so it is not consecutive with the first
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* two registers.
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*/
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/pinctrl/pinctrl.h>
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#include "pinctrl-mvebu.h"
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static void __iomem *mpp_base;
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static void __iomem *high_mpp_base;
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static int orion_mpp_ctrl_get(unsigned pid, unsigned long *config)
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{
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unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
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if (pid < 16) {
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unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
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*config = (readl(mpp_base + off) >> shift) & MVEBU_MPP_MASK;
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}
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else {
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*config = (readl(high_mpp_base) >> shift) & MVEBU_MPP_MASK;
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}
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return 0;
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}
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static int orion_mpp_ctrl_set(unsigned pid, unsigned long config)
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{
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unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
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if (pid < 16) {
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unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
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u32 reg = readl(mpp_base + off) & ~(MVEBU_MPP_MASK << shift);
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writel(reg | (config << shift), mpp_base + off);
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}
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else {
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u32 reg = readl(high_mpp_base) & ~(MVEBU_MPP_MASK << shift);
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writel(reg | (config << shift), high_mpp_base);
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}
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return 0;
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}
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#define V(f5181l, f5182, f5281) \
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((f5181l << 0) | (f5182 << 1) | (f5281 << 2))
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enum orion_variant {
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V_5181L = V(1, 0, 0),
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V_5182 = V(0, 1, 0),
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V_5281 = V(0, 0, 1),
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V_ALL = V(1, 1, 1),
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};
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static struct mvebu_mpp_mode orion_mpp_modes[] = {
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MPP_MODE(0,
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MPP_VAR_FUNCTION(0x0, "pcie", "rstout", V_ALL),
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MPP_VAR_FUNCTION(0x2, "pci", "req2", V_ALL),
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MPP_VAR_FUNCTION(0x3, "gpio", NULL, V_ALL)),
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MPP_MODE(1,
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MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
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MPP_VAR_FUNCTION(0x2, "pci", "gnt2", V_ALL)),
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MPP_MODE(2,
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MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
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MPP_VAR_FUNCTION(0x2, "pci", "req3", V_ALL),
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MPP_VAR_FUNCTION(0x3, "pci-1", "pme", V_ALL)),
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MPP_MODE(3,
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MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
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MPP_VAR_FUNCTION(0x2, "pci", "gnt3", V_ALL)),
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MPP_MODE(4,
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MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
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MPP_VAR_FUNCTION(0x2, "pci", "req4", V_ALL),
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MPP_VAR_FUNCTION(0x4, "bootnand", "re", V_5182 | V_5281),
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MPP_VAR_FUNCTION(0x5, "sata0", "prsnt", V_5182)),
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MPP_MODE(5,
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MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
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MPP_VAR_FUNCTION(0x2, "pci", "gnt4", V_ALL),
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MPP_VAR_FUNCTION(0x4, "bootnand", "we", V_5182 | V_5281),
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MPP_VAR_FUNCTION(0x5, "sata1", "prsnt", V_5182)),
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MPP_MODE(6,
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MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
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MPP_VAR_FUNCTION(0x2, "pci", "req5", V_ALL),
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MPP_VAR_FUNCTION(0x4, "nand", "re0", V_5182 | V_5281),
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MPP_VAR_FUNCTION(0x5, "pci-1", "clk", V_5181L),
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MPP_VAR_FUNCTION(0x5, "sata0", "act", V_5182)),
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MPP_MODE(7,
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MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
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MPP_VAR_FUNCTION(0x2, "pci", "gnt5", V_ALL),
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MPP_VAR_FUNCTION(0x4, "nand", "we0", V_5182 | V_5281),
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MPP_VAR_FUNCTION(0x5, "pci-1", "clk", V_5181L),
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MPP_VAR_FUNCTION(0x5, "sata1", "act", V_5182)),
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MPP_MODE(8,
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MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
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MPP_VAR_FUNCTION(0x1, "ge", "col", V_ALL)),
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MPP_MODE(9,
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MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
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MPP_VAR_FUNCTION(0x1, "ge", "rxerr", V_ALL)),
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MPP_MODE(10,
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MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
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MPP_VAR_FUNCTION(0x1, "ge", "crs", V_ALL)),
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MPP_MODE(11,
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MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
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MPP_VAR_FUNCTION(0x1, "ge", "txerr", V_ALL)),
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MPP_MODE(12,
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MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
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MPP_VAR_FUNCTION(0x1, "ge", "txd4", V_ALL),
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MPP_VAR_FUNCTION(0x4, "nand", "re1", V_5182 | V_5281),
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MPP_VAR_FUNCTION(0x5, "sata0", "ledprsnt", V_5182)),
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MPP_MODE(13,
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MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
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MPP_VAR_FUNCTION(0x1, "ge", "txd5", V_ALL),
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MPP_VAR_FUNCTION(0x4, "nand", "we1", V_5182 | V_5281),
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MPP_VAR_FUNCTION(0x5, "sata1", "ledprsnt", V_5182)),
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MPP_MODE(14,
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MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
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MPP_VAR_FUNCTION(0x1, "ge", "txd6", V_ALL),
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MPP_VAR_FUNCTION(0x4, "nand", "re2", V_5182 | V_5281),
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MPP_VAR_FUNCTION(0x5, "sata0", "ledact", V_5182)),
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MPP_MODE(15,
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MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
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MPP_VAR_FUNCTION(0x1, "ge", "txd7", V_ALL),
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MPP_VAR_FUNCTION(0x4, "nand", "we2", V_5182 | V_5281),
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MPP_VAR_FUNCTION(0x5, "sata1", "ledact", V_5182)),
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MPP_MODE(16,
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MPP_VAR_FUNCTION(0x0, "uart1", "rxd", V_5182 | V_5281),
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MPP_VAR_FUNCTION(0x1, "ge", "rxd4", V_ALL),
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MPP_VAR_FUNCTION(0x5, "gpio", NULL, V_5182)),
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MPP_MODE(17,
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MPP_VAR_FUNCTION(0x0, "uart1", "txd", V_5182 | V_5281),
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MPP_VAR_FUNCTION(0x1, "ge", "rxd5", V_ALL),
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MPP_VAR_FUNCTION(0x5, "gpio", NULL, V_5182)),
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MPP_MODE(18,
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MPP_VAR_FUNCTION(0x0, "uart1", "cts", V_5182 | V_5281),
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MPP_VAR_FUNCTION(0x1, "ge", "rxd6", V_ALL),
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MPP_VAR_FUNCTION(0x5, "gpio", NULL, V_5182)),
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MPP_MODE(19,
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MPP_VAR_FUNCTION(0x0, "uart1", "rts", V_5182 | V_5281),
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MPP_VAR_FUNCTION(0x1, "ge", "rxd7", V_ALL),
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MPP_VAR_FUNCTION(0x5, "gpio", NULL, V_5182)),
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};
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static struct mvebu_mpp_ctrl orion_mpp_controls[] = {
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MPP_FUNC_CTRL(0, 19, NULL, orion_mpp_ctrl),
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};
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static struct pinctrl_gpio_range mv88f5181l_gpio_ranges[] = {
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MPP_GPIO_RANGE(0, 0, 0, 16),
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};
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static struct pinctrl_gpio_range mv88f5182_gpio_ranges[] = {
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MPP_GPIO_RANGE(0, 0, 0, 19),
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};
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static struct pinctrl_gpio_range mv88f5281_gpio_ranges[] = {
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MPP_GPIO_RANGE(0, 0, 0, 16),
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};
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static struct mvebu_pinctrl_soc_info mv88f5181l_info = {
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.variant = V_5181L,
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.controls = orion_mpp_controls,
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.ncontrols = ARRAY_SIZE(orion_mpp_controls),
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.modes = orion_mpp_modes,
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.nmodes = ARRAY_SIZE(orion_mpp_modes),
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.gpioranges = mv88f5181l_gpio_ranges,
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.ngpioranges = ARRAY_SIZE(mv88f5181l_gpio_ranges),
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};
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static struct mvebu_pinctrl_soc_info mv88f5182_info = {
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.variant = V_5182,
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.controls = orion_mpp_controls,
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.ncontrols = ARRAY_SIZE(orion_mpp_controls),
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.modes = orion_mpp_modes,
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.nmodes = ARRAY_SIZE(orion_mpp_modes),
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.gpioranges = mv88f5182_gpio_ranges,
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.ngpioranges = ARRAY_SIZE(mv88f5182_gpio_ranges),
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};
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static struct mvebu_pinctrl_soc_info mv88f5281_info = {
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.variant = V_5281,
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.controls = orion_mpp_controls,
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.ncontrols = ARRAY_SIZE(orion_mpp_controls),
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.modes = orion_mpp_modes,
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.nmodes = ARRAY_SIZE(orion_mpp_modes),
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.gpioranges = mv88f5281_gpio_ranges,
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.ngpioranges = ARRAY_SIZE(mv88f5281_gpio_ranges),
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};
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/*
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* There are multiple variants of the Orion SoCs, but in terms of pin
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* muxing, they are identical.
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*/
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static struct of_device_id orion_pinctrl_of_match[] = {
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{ .compatible = "marvell,88f5181l-pinctrl", .data = &mv88f5181l_info },
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{ .compatible = "marvell,88f5182-pinctrl", .data = &mv88f5182_info },
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{ .compatible = "marvell,88f5281-pinctrl", .data = &mv88f5281_info },
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{ }
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};
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static int orion_pinctrl_probe(struct platform_device *pdev)
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{
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const struct of_device_id *match =
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of_match_device(orion_pinctrl_of_match, &pdev->dev);
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struct resource *res;
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pdev->dev.platform_data = (void*)match->data;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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mpp_base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(mpp_base))
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return PTR_ERR(mpp_base);
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res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
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high_mpp_base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(high_mpp_base))
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return PTR_ERR(high_mpp_base);
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return mvebu_pinctrl_probe(pdev);
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}
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static int orion_pinctrl_remove(struct platform_device *pdev)
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{
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return mvebu_pinctrl_remove(pdev);
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}
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static struct platform_driver orion_pinctrl_driver = {
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.driver = {
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.name = "orion-pinctrl",
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.owner = THIS_MODULE,
|
||||
.of_match_table = of_match_ptr(orion_pinctrl_of_match),
|
||||
},
|
||||
.probe = orion_pinctrl_probe,
|
||||
.remove = orion_pinctrl_remove,
|
||||
};
|
||||
|
||||
module_platform_driver(orion_pinctrl_driver);
|
||||
|
||||
MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
|
||||
MODULE_DESCRIPTION("Marvell Orion pinctrl driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
Loading…
Reference in New Issue