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spi: davinci: setup chip-select timers values only if timer enabled 

Setup chip-select timers values only if timer is enabled
(timer_disbled in spi configuration is false).

As a nice side effect, this patch removes code duplicated in
davinci_spi_bufs_pio() and davinci_spi_bufs_dma().

Signed-off-by: Brian Niebuhr <bniebuhr@efjohnson.com>
Tested-By: Michael Williamson <michael.williamson@criticallink.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
This commit is contained in:
Brian Niebuhr 2010-08-19 12:44:31 +05:30 committed by Sekhar Nori
parent 25f33512f6
commit fd764463fe
1 changed files with 4 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
drivers/spi/davinci_spi.c
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@ -374,6 +374,10 @@ static int davinci_spi_setup_transfer(struct spi_device *spi,
if (spicfg->timer_disable) if (spicfg->timer_disable)
spifmt |= SPIFMT_DISTIMER_MASK; spifmt |= SPIFMT_DISTIMER_MASK;
else
iowrite32((spicfg->c2tdelay << SPI_C2TDELAY_SHIFT) |
(spicfg->t2cdelay << SPI_T2CDELAY_SHIFT),
davinci_spi->base + SPIDELAY);
if (spi->mode & SPI_READY) if (spi->mode & SPI_READY)
spifmt |= SPIFMT_WAITENA_MASK; spifmt |= SPIFMT_WAITENA_MASK;
@ -607,13 +611,9 @@ static int davinci_spi_bufs_pio(struct spi_device *spi, struct spi_transfer *t)
u32 tx_data, data1_reg_val; u32 tx_data, data1_reg_val;
u32 buf_val, flg_val; u32 buf_val, flg_val;
struct davinci_spi_platform_data *pdata; struct davinci_spi_platform_data *pdata;
struct davinci_spi_config *spicfg;
davinci_spi = spi_master_get_devdata(spi->master); davinci_spi = spi_master_get_devdata(spi->master);
pdata = davinci_spi->pdata; pdata = davinci_spi->pdata;
spicfg = (struct davinci_spi_config *)spi->controller_data;
if (!spicfg)
spicfg = &davinci_spi_default_cfg;
davinci_spi->tx = t->tx_buf; davinci_spi->tx = t->tx_buf;
davinci_spi->rx = t->rx_buf; davinci_spi->rx = t->rx_buf;
@ -633,10 +633,6 @@ static int davinci_spi_bufs_pio(struct spi_device *spi, struct spi_transfer *t)
/* Enable SPI */ /* Enable SPI */
set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
iowrite32((spicfg->c2tdelay << SPI_C2TDELAY_SHIFT) |
(spicfg->t2cdelay << SPI_T2CDELAY_SHIFT),
davinci_spi->base + SPIDELAY);
count = davinci_spi->count; count = davinci_spi->count;
/* Determine the command to execute READ or WRITE */ /* Determine the command to execute READ or WRITE */
@ -741,14 +737,10 @@ static int davinci_spi_bufs_dma(struct spi_device *spi, struct spi_transfer *t)
struct davinci_spi_dma *davinci_spi_dma; struct davinci_spi_dma *davinci_spi_dma;
int word_len, data_type, ret; int word_len, data_type, ret;
unsigned long tx_reg, rx_reg; unsigned long tx_reg, rx_reg;
struct davinci_spi_config *spicfg;
struct device *sdev; struct device *sdev;
davinci_spi = spi_master_get_devdata(spi->master); davinci_spi = spi_master_get_devdata(spi->master);
sdev = davinci_spi->bitbang.master->dev.parent; sdev = davinci_spi->bitbang.master->dev.parent;
spicfg = (struct davinci_spi_config *)spi->controller_data;
if (!spicfg)
spicfg = &davinci_spi_default_cfg;
davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select]; davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];
@ -784,11 +776,6 @@ static int davinci_spi_bufs_dma(struct spi_device *spi, struct spi_transfer *t)
if (ret) if (ret)
return ret; return ret;
/* Put delay val if required */
iowrite32((spicfg->c2tdelay << SPI_C2TDELAY_SHIFT) |
(spicfg->t2cdelay << SPI_T2CDELAY_SHIFT),
davinci_spi->base + SPIDELAY);
count = davinci_spi->count; /* the number of elements */ count = davinci_spi->count; /* the number of elements */
/* disable all interrupts for dma transfers */ /* disable all interrupts for dma transfers */