mirror of https://gitee.com/openkylin/linux.git
mmc: mediatek: drop too much code of tuning method
the tuning code is becoming more and more bloated, let's make the set cmd/data delay to inline function to avoid too much redundant code. Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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fd82cc3020
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@ -1661,6 +1661,30 @@ static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay)
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return delay_phase;
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}
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static inline void msdc_set_cmd_delay(struct msdc_host *host, u32 value)
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{
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u32 tune_reg = host->dev_comp->pad_tune_reg;
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if (host->top_base)
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sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY,
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value);
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else
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sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY,
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value);
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}
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static inline void msdc_set_data_delay(struct msdc_host *host, u32 value)
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{
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u32 tune_reg = host->dev_comp->pad_tune_reg;
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if (host->top_base)
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sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
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PAD_DAT_RD_RXDLY, value);
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else
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sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_DATRRDLY,
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value);
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}
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static int msdc_tune_response(struct mmc_host *mmc, u32 opcode)
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{
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struct msdc_host *host = mmc_priv(mmc);
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@ -1681,12 +1705,7 @@ static int msdc_tune_response(struct mmc_host *mmc, u32 opcode)
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sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
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for (i = 0 ; i < PAD_DELAY_MAX; i++) {
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if (host->top_base)
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sdr_set_field(host->top_base + EMMC_TOP_CMD,
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PAD_CMD_RXDLY, i);
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else
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sdr_set_field(host->base + tune_reg,
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MSDC_PAD_TUNE_CMDRDLY, i);
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msdc_set_cmd_delay(host, i);
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/*
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* Using the same parameters, it may sometimes pass the test,
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* but sometimes it may fail. To make sure the parameters are
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@ -1710,12 +1729,7 @@ static int msdc_tune_response(struct mmc_host *mmc, u32 opcode)
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sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
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for (i = 0; i < PAD_DELAY_MAX; i++) {
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if (host->top_base)
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sdr_set_field(host->top_base + EMMC_TOP_CMD,
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PAD_CMD_RXDLY, i);
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else
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sdr_set_field(host->base + tune_reg,
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MSDC_PAD_TUNE_CMDRDLY, i);
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msdc_set_cmd_delay(host, i);
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/*
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* Using the same parameters, it may sometimes pass the test,
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* but sometimes it may fail. To make sure the parameters are
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@ -1739,25 +1753,13 @@ static int msdc_tune_response(struct mmc_host *mmc, u32 opcode)
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final_maxlen = final_fall_delay.maxlen;
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if (final_maxlen == final_rise_delay.maxlen) {
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sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
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if (host->top_base)
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sdr_set_field(host->base + EMMC_TOP_CMD, PAD_CMD_RXDLY,
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final_rise_delay.final_phase);
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else
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sdr_set_field(host->base + tune_reg,
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MSDC_PAD_TUNE_CMDRDLY,
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final_rise_delay.final_phase);
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final_delay = final_rise_delay.final_phase;
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} else {
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sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
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if (host->top_base)
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sdr_set_field(host->base + EMMC_TOP_CMD, PAD_CMD_RXDLY,
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final_fall_delay.final_phase);
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else
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sdr_set_field(host->base + tune_reg,
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MSDC_PAD_TUNE_CMDRDLY,
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final_fall_delay.final_phase);
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final_delay = final_fall_delay.final_phase;
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}
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msdc_set_cmd_delay(host, final_delay);
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if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay)
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goto skip_internal;
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@ -1832,7 +1834,6 @@ static int msdc_tune_data(struct mmc_host *mmc, u32 opcode)
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u32 rise_delay = 0, fall_delay = 0;
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struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
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u8 final_delay, final_maxlen;
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u32 tune_reg = host->dev_comp->pad_tune_reg;
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int i, ret;
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sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL,
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@ -1840,12 +1841,7 @@ static int msdc_tune_data(struct mmc_host *mmc, u32 opcode)
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sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
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sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
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for (i = 0 ; i < PAD_DELAY_MAX; i++) {
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if (host->top_base)
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sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
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PAD_DAT_RD_RXDLY, i);
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else
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sdr_set_field(host->base + tune_reg,
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MSDC_PAD_TUNE_DATRRDLY, i);
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msdc_set_data_delay(host, i);
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ret = mmc_send_tuning(mmc, opcode, NULL);
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if (!ret)
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rise_delay |= (1 << i);
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@ -1859,12 +1855,7 @@ static int msdc_tune_data(struct mmc_host *mmc, u32 opcode)
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sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
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sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
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for (i = 0; i < PAD_DELAY_MAX; i++) {
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if (host->top_base)
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sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
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PAD_DAT_RD_RXDLY, i);
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else
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sdr_set_field(host->base + tune_reg,
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MSDC_PAD_TUNE_DATRRDLY, i);
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msdc_set_data_delay(host, i);
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ret = mmc_send_tuning(mmc, opcode, NULL);
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if (!ret)
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fall_delay |= (1 << i);
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@ -1876,28 +1867,13 @@ static int msdc_tune_data(struct mmc_host *mmc, u32 opcode)
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if (final_maxlen == final_rise_delay.maxlen) {
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sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
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sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
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if (host->top_base)
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sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
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PAD_DAT_RD_RXDLY,
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final_rise_delay.final_phase);
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else
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sdr_set_field(host->base + tune_reg,
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MSDC_PAD_TUNE_DATRRDLY,
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final_rise_delay.final_phase);
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final_delay = final_rise_delay.final_phase;
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} else {
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sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
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sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
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if (host->top_base)
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sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
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PAD_DAT_RD_RXDLY,
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final_fall_delay.final_phase);
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else
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sdr_set_field(host->base + tune_reg,
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MSDC_PAD_TUNE_DATRRDLY,
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final_fall_delay.final_phase);
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final_delay = final_fall_delay.final_phase;
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}
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msdc_set_data_delay(host, final_delay);
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dev_dbg(host->dev, "Final data pad delay: %x\n", final_delay);
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return final_delay == 0xff ? -EIO : 0;
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@ -1913,7 +1889,6 @@ static int msdc_tune_together(struct mmc_host *mmc, u32 opcode)
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u32 rise_delay = 0, fall_delay = 0;
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struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
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u8 final_delay, final_maxlen;
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u32 tune_reg = host->dev_comp->pad_tune_reg;
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int i, ret;
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sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL,
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@ -1923,17 +1898,8 @@ static int msdc_tune_together(struct mmc_host *mmc, u32 opcode)
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sdr_clr_bits(host->base + MSDC_IOCON,
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MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
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for (i = 0 ; i < PAD_DELAY_MAX; i++) {
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if (host->top_base) {
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sdr_set_field(host->top_base + EMMC_TOP_CMD,
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PAD_CMD_RXDLY, i);
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sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
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PAD_DAT_RD_RXDLY, i);
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} else {
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sdr_set_field(host->base + tune_reg,
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MSDC_PAD_TUNE_CMDRDLY, i);
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sdr_set_field(host->base + tune_reg,
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MSDC_PAD_TUNE_DATRRDLY, i);
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}
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msdc_set_cmd_delay(host, i);
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msdc_set_data_delay(host, i);
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ret = mmc_send_tuning(mmc, opcode, NULL);
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if (!ret)
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rise_delay |= (1 << i);
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@ -1948,17 +1914,8 @@ static int msdc_tune_together(struct mmc_host *mmc, u32 opcode)
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sdr_set_bits(host->base + MSDC_IOCON,
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MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
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for (i = 0; i < PAD_DELAY_MAX; i++) {
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if (host->top_base) {
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sdr_set_field(host->top_base + EMMC_TOP_CMD,
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PAD_CMD_RXDLY, i);
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sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
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PAD_DAT_RD_RXDLY, i);
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} else {
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sdr_set_field(host->base + tune_reg,
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MSDC_PAD_TUNE_CMDRDLY, i);
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sdr_set_field(host->base + tune_reg,
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MSDC_PAD_TUNE_DATRRDLY, i);
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}
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msdc_set_cmd_delay(host, i);
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msdc_set_data_delay(host, i);
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ret = mmc_send_tuning(mmc, opcode, NULL);
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if (!ret)
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fall_delay |= (1 << i);
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@ -1979,17 +1936,8 @@ static int msdc_tune_together(struct mmc_host *mmc, u32 opcode)
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final_delay = final_fall_delay.final_phase;
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}
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if (host->top_base) {
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sdr_set_field(host->top_base + EMMC_TOP_CMD,
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PAD_CMD_RXDLY, final_delay);
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sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
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PAD_DAT_RD_RXDLY, final_delay);
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} else {
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sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY,
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final_delay);
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sdr_set_field(host->base + tune_reg,
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MSDC_PAD_TUNE_DATRRDLY, final_delay);
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}
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msdc_set_cmd_delay(host, final_delay);
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msdc_set_data_delay(host, final_delay);
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dev_dbg(host->dev, "Final pad delay: %x\n", final_delay);
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return final_delay == 0xff ? -EIO : 0;
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@ -2006,12 +1954,7 @@ static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode)
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if (host->hs400_mode) {
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sdr_clr_bits(host->base + MSDC_IOCON,
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MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
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if (host->top_base)
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sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
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PAD_DAT_RD_RXDLY, 0);
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else
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sdr_set_field(host->base + tune_reg,
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MSDC_PAD_TUNE_DATRRDLY, 0);
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msdc_set_data_delay(host, 0);
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}
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goto tune_done;
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}
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