mirror of https://gitee.com/openkylin/linux.git
arm64: dts: hi6220: Add CTI options
Adds in CTI device tree information for the Hikey620 board. Signed-off-by: Mike Leach <mike.leach@linaro.org> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> Tested-by: Leo Yan <leo.yan@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
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@ -213,7 +213,7 @@ acpu_funnel_in7: endpoint {
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};
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};
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etm@f659c000 {
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etm0: etm@f659c000 {
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compatible = "arm,coresight-etm4x", "arm,primecell";
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reg = <0 0xf659c000 0 0x1000>;
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@ -232,7 +232,7 @@ etm0_out: endpoint {
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};
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};
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etm@f659d000 {
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etm1: etm@f659d000 {
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compatible = "arm,coresight-etm4x", "arm,primecell";
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reg = <0 0xf659d000 0 0x1000>;
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@ -251,7 +251,7 @@ etm1_out: endpoint {
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};
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};
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etm@f659e000 {
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etm2: etm@f659e000 {
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compatible = "arm,coresight-etm4x", "arm,primecell";
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reg = <0 0xf659e000 0 0x1000>;
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@ -270,7 +270,7 @@ etm2_out: endpoint {
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};
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};
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etm@f659f000 {
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etm3: etm@f659f000 {
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compatible = "arm,coresight-etm4x", "arm,primecell";
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reg = <0 0xf659f000 0 0x1000>;
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@ -289,7 +289,7 @@ etm3_out: endpoint {
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};
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};
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etm@f65dc000 {
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etm4: etm@f65dc000 {
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compatible = "arm,coresight-etm4x", "arm,primecell";
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reg = <0 0xf65dc000 0 0x1000>;
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@ -308,7 +308,7 @@ etm4_out: endpoint {
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};
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};
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etm@f65dd000 {
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etm5: etm@f65dd000 {
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compatible = "arm,coresight-etm4x", "arm,primecell";
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reg = <0 0xf65dd000 0 0x1000>;
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@ -327,7 +327,7 @@ etm5_out: endpoint {
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};
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};
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etm@f65de000 {
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etm6: etm@f65de000 {
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compatible = "arm,coresight-etm4x", "arm,primecell";
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reg = <0 0xf65de000 0 0x1000>;
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@ -346,7 +346,7 @@ etm6_out: endpoint {
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};
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};
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etm@f65df000 {
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etm7: etm@f65df000 {
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compatible = "arm,coresight-etm4x", "arm,primecell";
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reg = <0 0xf65df000 0 0x1000>;
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@ -364,5 +364,119 @@ etm7_out: endpoint {
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};
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};
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};
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/* System CTIs */
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/* CTI 0 - TMC and TPIU connections */
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cti@f6403000 {
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compatible = "arm,coresight-cti", "arm,primecell";
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reg = <0 0xf6403000 0 0x1000>;
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clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
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clock-names = "apb_pclk";
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};
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/* CTI - CPU-0 */
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cti@f6598000 {
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compatible = "arm,coresight-cti-v8-arch",
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"arm,coresight-cti", "arm,primecell";
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reg = <0 0xf6598000 0 0x1000>;
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clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
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clock-names = "apb_pclk";
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cpu = <&cpu0>;
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arm,cs-dev-assoc = <&etm0>;
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};
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/* CTI - CPU-1 */
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cti@f6599000 {
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compatible = "arm,coresight-cti-v8-arch",
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"arm,coresight-cti", "arm,primecell";
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reg = <0 0xf6599000 0 0x1000>;
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clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
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clock-names = "apb_pclk";
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cpu = <&cpu1>;
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arm,cs-dev-assoc = <&etm1>;
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};
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/* CTI - CPU-2 */
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cti@f659a000 {
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compatible = "arm,coresight-cti-v8-arch",
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"arm,coresight-cti", "arm,primecell";
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reg = <0 0xf659a000 0 0x1000>;
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clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
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clock-names = "apb_pclk";
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cpu = <&cpu2>;
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arm,cs-dev-assoc = <&etm2>;
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};
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/* CTI - CPU-3 */
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cti@f659b000 {
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compatible = "arm,coresight-cti-v8-arch",
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"arm,coresight-cti", "arm,primecell";
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reg = <0 0xf659b000 0 0x1000>;
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clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
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clock-names = "apb_pclk";
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cpu = <&cpu3>;
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arm,cs-dev-assoc = <&etm3>;
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};
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/* CTI - CPU-4 */
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cti@f65d8000 {
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compatible = "arm,coresight-cti-v8-arch",
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"arm,coresight-cti", "arm,primecell";
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reg = <0 0xf65d8000 0 0x1000>;
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clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
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clock-names = "apb_pclk";
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cpu = <&cpu4>;
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arm,cs-dev-assoc = <&etm4>;
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};
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/* CTI - CPU-5 */
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cti@f65d9000 {
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compatible = "arm,coresight-cti-v8-arch",
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"arm,coresight-cti", "arm,primecell";
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reg = <0 0xf65d9000 0 0x1000>;
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clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
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clock-names = "apb_pclk";
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cpu = <&cpu5>;
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arm,cs-dev-assoc = <&etm5>;
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};
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/* CTI - CPU-6 */
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cti@f65da000 {
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compatible = "arm,coresight-cti-v8-arch",
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"arm,coresight-cti", "arm,primecell";
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reg = <0 0xf65da000 0 0x1000>;
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clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
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clock-names = "apb_pclk";
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cpu = <&cpu6>;
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arm,cs-dev-assoc = <&etm6>;
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};
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/* CTI - CPU-7 */
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cti@f65db000 {
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compatible = "arm,coresight-cti-v8-arch",
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"arm,coresight-cti", "arm,primecell";
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reg = <0 0xf65db000 0 0x1000>;
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clocks = <&acpu_sctrl HI6220_ACPU_SFT_AT_S>;
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clock-names = "apb_pclk";
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cpu = <&cpu7>;
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arm,cs-dev-assoc = <&etm7>;
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};
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};
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};
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