mirror of https://gitee.com/openkylin/linux.git
clk: renesas: cpg-mssr: Add R7S9210 support
Add support for the R7S9210 (RZ/A2) Clock Pulse Generator and Module Standby. The Module Standby HW in the RZ/A series is very close to R-Car HW, except for how the registers are laid out. The MSTP registers are only 8-bits wide, there are no status registers (MSTPSR), and the register offsets are a little different. Since the RZ/A hardware manuals refer to these registers as the Standby Control Registers, we'll use that name to distinguish the RZ/A type from the R-Car type. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Acked-by: Rob Herring <robh@kernel.org> # DT bits Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Chris Brandt
Geert Uytterhoeven
parent
6207ba0434
commit
fde35c9c7d
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@ -13,6 +13,7 @@ They provide the following functionalities:
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Required Properties:
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- compatible: Must be one of:
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- "renesas,r7s9210-cpg-mssr" for the r7s9210 SoC (RZ/A2)
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- "renesas,r8a7743-cpg-mssr" for the r8a7743 SoC (RZ/G1M)
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- "renesas,r8a7745-cpg-mssr" for the r8a7745 SoC (RZ/G1E)
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- "renesas,r8a77470-cpg-mssr" for the r8a77470 SoC (RZ/G1C)
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@ -36,8 +37,8 @@ Required Properties:
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- clocks: References to external parent clocks, one entry for each entry in
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clock-names
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- clock-names: List of external parent clock names. Valid names are:
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- "extal" (r8a7743, r8a7745, r8a77470, r8a774a1, r8a7790, r8a7791,
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r8a7792, r8a7793, r8a7794, r8a7795, r8a7796, r8a77965,
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- "extal" (r7s9210, r8a7743, r8a7745, r8a77470, r8a774a1, r8a7790,
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r8a7791, r8a7792, r8a7793, r8a7794, r8a7795, r8a7796, r8a77965,
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r8a77970, r8a77980, r8a77990, r8a77995)
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- "extalr" (r8a774a1, r8a7795, r8a7796, r8a77965, r8a77970, r8a77980)
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- "usb_extal" (r8a7743, r8a7745, r8a77470, r8a7790, r8a7791, r8a7793,
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@ -3,6 +3,7 @@ config CLK_RENESAS
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default y if ARCH_RENESAS
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select CLK_EMEV2 if ARCH_EMEV2
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select CLK_RZA1 if ARCH_R7S72100
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select CLK_R7S9210 if ARCH_R7S9210
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select CLK_R8A73A4 if ARCH_R8A73A4
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select CLK_R8A7740 if ARCH_R8A7740
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select CLK_R8A7743 if ARCH_R8A7743
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@ -46,6 +47,10 @@ config CLK_RZA1
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bool "RZ/A1H clock support" if COMPILE_TEST
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select CLK_RENESAS_CPG_MSTP
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config CLK_R7S9210
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bool "RZ/A2 clock support" if COMPILE_TEST
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select CLK_RENESAS_CPG_MSSR
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config CLK_R8A73A4
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bool "R-Mobile APE6 clock support" if COMPILE_TEST
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select CLK_RENESAS_CPG_MSTP
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@ -2,6 +2,7 @@
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# SoC
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obj-$(CONFIG_CLK_EMEV2) += clk-emev2.o
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obj-$(CONFIG_CLK_RZA1) += clk-rz.o
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obj-$(CONFIG_CLK_R7S9210) += r7s9210-cpg-mssr.o
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obj-$(CONFIG_CLK_R8A73A4) += clk-r8a73a4.o
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obj-$(CONFIG_CLK_R8A7740) += clk-r8a7740.o
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obj-$(CONFIG_CLK_R8A7743) += r8a7743-cpg-mssr.o
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@ -0,0 +1,189 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* R7S9210 Clock Pulse Generator / Module Standby
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*
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* Based on r8a7795-cpg-mssr.c
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*
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* Copyright (C) 2018 Chris Brandt
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* Copyright (C) 2018 Renesas Electronics Corp.
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*
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <dt-bindings/clock/r7s9210-cpg-mssr.h>
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#include "renesas-cpg-mssr.h"
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#define CPG_FRQCR 0x00
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static u8 cpg_mode;
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/* Internal Clock ratio table */
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static const struct {
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unsigned int i;
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unsigned int g;
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unsigned int b;
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unsigned int p1;
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/* p0 is always 32 */;
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} ratio_tab[5] = { /* I, G, B, P1 */
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{ 2, 4, 8, 16}, /* FRQCR = 0x012 */
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{ 4, 4, 8, 16}, /* FRQCR = 0x112 */
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{ 8, 4, 8, 16}, /* FRQCR = 0x212 */
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{ 16, 8, 16, 16}, /* FRQCR = 0x322 */
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{ 16, 16, 32, 32}, /* FRQCR = 0x333 */
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};
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enum rz_clk_types {
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CLK_TYPE_RZA_MAIN = CLK_TYPE_CUSTOM,
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CLK_TYPE_RZA_PLL,
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};
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enum clk_ids {
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/* Core Clock Outputs exported to DT */
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LAST_DT_CORE_CLK = R7S9210_CLK_P0,
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/* External Input Clocks */
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CLK_EXTAL,
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/* Internal Core Clocks */
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CLK_MAIN,
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CLK_PLL,
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/* Module Clocks */
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MOD_CLK_BASE
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};
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static struct cpg_core_clk r7s9210_core_clks[] = {
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/* External Clock Inputs */
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DEF_INPUT("extal", CLK_EXTAL),
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/* Internal Core Clocks */
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DEF_BASE(".main", CLK_MAIN, CLK_TYPE_RZA_MAIN, CLK_EXTAL),
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DEF_BASE(".pll", CLK_PLL, CLK_TYPE_RZA_PLL, CLK_MAIN),
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/* Core Clock Outputs */
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DEF_FIXED("i", R7S9210_CLK_I, CLK_PLL, 2, 1),
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DEF_FIXED("g", R7S9210_CLK_G, CLK_PLL, 4, 1),
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DEF_FIXED("b", R7S9210_CLK_B, CLK_PLL, 8, 1),
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DEF_FIXED("p1", R7S9210_CLK_P1, CLK_PLL, 16, 1),
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DEF_FIXED("p1c", R7S9210_CLK_P1C, CLK_PLL, 16, 1),
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DEF_FIXED("p0", R7S9210_CLK_P0, CLK_PLL, 32, 1),
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};
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static const struct mssr_mod_clk r7s9210_mod_clks[] __initconst = {
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DEF_MOD_STB("ostm2", 34, R7S9210_CLK_P1C),
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DEF_MOD_STB("ostm1", 35, R7S9210_CLK_P1C),
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DEF_MOD_STB("ostm0", 36, R7S9210_CLK_P1C),
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DEF_MOD_STB("scif4", 43, R7S9210_CLK_P1C),
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DEF_MOD_STB("scif3", 44, R7S9210_CLK_P1C),
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DEF_MOD_STB("scif2", 45, R7S9210_CLK_P1C),
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DEF_MOD_STB("scif1", 46, R7S9210_CLK_P1C),
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DEF_MOD_STB("scif0", 47, R7S9210_CLK_P1C),
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DEF_MOD_STB("ether1", 64, R7S9210_CLK_B),
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DEF_MOD_STB("ether0", 65, R7S9210_CLK_B),
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DEF_MOD_STB("i2c3", 84, R7S9210_CLK_P1),
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DEF_MOD_STB("i2c2", 85, R7S9210_CLK_P1),
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DEF_MOD_STB("i2c1", 86, R7S9210_CLK_P1),
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DEF_MOD_STB("i2c0", 87, R7S9210_CLK_P1),
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};
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struct clk * __init rza2_cpg_clk_register(struct device *dev,
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const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
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struct clk **clks, void __iomem *base,
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struct raw_notifier_head *notifiers)
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{
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struct clk *parent;
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unsigned int mult = 1;
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unsigned int div = 1;
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u16 frqcr;
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u8 index;
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int i;
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parent = clks[core->parent];
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if (IS_ERR(parent))
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return ERR_CAST(parent);
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switch (core->id) {
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case CLK_MAIN:
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break;
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case CLK_PLL:
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if (cpg_mode)
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mult = 44; /* Divider 1 is 1/2 */
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else
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mult = 88; /* Divider 1 is 1 */
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break;
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default:
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return ERR_PTR(-EINVAL);
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}
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/* Adjust the dividers based on the current FRQCR setting */
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if (core->id == CLK_MAIN) {
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/* If EXTAL is above 12MHz, then we know it is Mode 1 */
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if (clk_get_rate(parent) > 12000000)
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cpg_mode = 1;
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frqcr = clk_readl(base + CPG_FRQCR) & 0xFFF;
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if (frqcr == 0x012)
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index = 0;
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else if (frqcr == 0x112)
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index = 1;
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else if (frqcr == 0x212)
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index = 2;
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else if (frqcr == 0x322)
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index = 3;
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else if (frqcr == 0x333)
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index = 4;
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else
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BUG_ON(1); /* Illegal FRQCR value */
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for (i = 0; i < ARRAY_SIZE(r7s9210_core_clks); i++) {
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switch (r7s9210_core_clks[i].id) {
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case R7S9210_CLK_I:
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r7s9210_core_clks[i].div = ratio_tab[index].i;
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break;
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case R7S9210_CLK_G:
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r7s9210_core_clks[i].div = ratio_tab[index].g;
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break;
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case R7S9210_CLK_B:
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r7s9210_core_clks[i].div = ratio_tab[index].b;
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break;
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case R7S9210_CLK_P1:
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case R7S9210_CLK_P1C:
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r7s9210_core_clks[i].div = ratio_tab[index].p1;
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break;
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case R7S9210_CLK_P0:
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r7s9210_core_clks[i].div = 32;
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break;
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}
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}
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}
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return clk_register_fixed_factor(NULL, core->name,
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__clk_get_name(parent), 0, mult, div);
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}
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const struct cpg_mssr_info r7s9210_cpg_mssr_info __initconst = {
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/* Core Clocks */
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.core_clks = r7s9210_core_clks,
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.num_core_clks = ARRAY_SIZE(r7s9210_core_clks),
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.last_dt_core_clk = LAST_DT_CORE_CLK,
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.num_total_core_clks = MOD_CLK_BASE,
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/* Module Clocks */
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.mod_clks = r7s9210_mod_clks,
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.num_mod_clks = ARRAY_SIZE(r7s9210_mod_clks),
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.num_hw_mod_clks = 11 * 32, /* includes STBCR0 which doesn't exist */
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/* Callbacks */
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.cpg_clk_register = rza2_cpg_clk_register,
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/* RZ/A2 has Standby Control Registers */
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.stbyctrl = true,
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};
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@ -73,6 +73,17 @@ static const u16 smstpcr[] = {
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#define SMSTPCR(i) smstpcr[i]
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/*
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* Standby Control Register offsets (RZ/A)
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* Base address is FRQCR register
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*/
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static const u16 stbcr[] = {
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0xFFFF/*dummy*/, 0x010, 0x014, 0x410, 0x414, 0x418, 0x41C, 0x420,
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0x424, 0x428, 0x42C,
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};
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#define STBCR(i) stbcr[i]
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/*
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* Software Reset Register offsets
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@ -110,6 +121,7 @@ static const u16 srcr[] = {
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* @notifiers: Notifier chain to save/restore clock state for system resume
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* @smstpcr_saved[].mask: Mask of SMSTPCR[] bits under our control
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* @smstpcr_saved[].val: Saved values of SMSTPCR[]
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* @stbyctrl: This device has Standby Control Registers
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*/
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struct cpg_mssr_priv {
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#ifdef CONFIG_RESET_CONTROLLER
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@ -123,6 +135,7 @@ struct cpg_mssr_priv {
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unsigned int num_core_clks;
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unsigned int num_mod_clks;
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unsigned int last_dt_core_clk;
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bool stbyctrl;
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struct raw_notifier_head notifiers;
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struct {
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@ -162,16 +175,29 @@ static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable)
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enable ? "ON" : "OFF");
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spin_lock_irqsave(&priv->rmw_lock, flags);
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value = readl(priv->base + SMSTPCR(reg));
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if (enable)
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value &= ~bitmask;
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else
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value |= bitmask;
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writel(value, priv->base + SMSTPCR(reg));
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if (priv->stbyctrl) {
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value = readb(priv->base + STBCR(reg));
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if (enable)
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value &= ~bitmask;
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else
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value |= bitmask;
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writeb(value, priv->base + STBCR(reg));
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/* dummy read to ensure write has completed */
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readb(priv->base + STBCR(reg));
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barrier_data(priv->base + STBCR(reg));
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} else {
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value = readl(priv->base + SMSTPCR(reg));
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if (enable)
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value &= ~bitmask;
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else
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value |= bitmask;
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writel(value, priv->base + SMSTPCR(reg));
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}
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spin_unlock_irqrestore(&priv->rmw_lock, flags);
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if (!enable)
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if (!enable || priv->stbyctrl)
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return 0;
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for (i = 1000; i > 0; --i) {
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@ -205,7 +231,10 @@ static int cpg_mstp_clock_is_enabled(struct clk_hw *hw)
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struct cpg_mssr_priv *priv = clock->priv;
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u32 value;
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value = readl(priv->base + MSTPSR(clock->index / 32));
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if (priv->stbyctrl)
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value = readb(priv->base + STBCR(clock->index / 32));
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else
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value = readl(priv->base + MSTPSR(clock->index / 32));
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return !(value & BIT(clock->index % 32));
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}
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@ -226,6 +255,7 @@ struct clk *cpg_mssr_clk_src_twocell_get(struct of_phandle_args *clkspec,
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unsigned int idx;
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const char *type;
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struct clk *clk;
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int range_check;
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switch (clkspec->args[0]) {
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case CPG_CORE:
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@ -240,8 +270,14 @@ struct clk *cpg_mssr_clk_src_twocell_get(struct of_phandle_args *clkspec,
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case CPG_MOD:
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type = "module";
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idx = MOD_CLK_PACK(clkidx);
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if (clkidx % 100 > 31 || idx >= priv->num_mod_clks) {
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if (priv->stbyctrl) {
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idx = MOD_CLK_PACK_10(clkidx);
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range_check = 7 - (clkidx % 10);
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} else {
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idx = MOD_CLK_PACK(clkidx);
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range_check = 31 - (clkidx % 100);
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}
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if (range_check < 0 || idx >= priv->num_mod_clks) {
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dev_err(dev, "Invalid %s clock index %u\n", type,
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clkidx);
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return ERR_PTR(-EINVAL);
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@ -646,6 +682,12 @@ static inline int cpg_mssr_reset_controller_register(struct cpg_mssr_priv *priv)
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static const struct of_device_id cpg_mssr_match[] = {
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#ifdef CONFIG_CLK_R7S9210
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{
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.compatible = "renesas,r7s9210-cpg-mssr",
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.data = &r7s9210_cpg_mssr_info,
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},
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#endif
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#ifdef CONFIG_CLK_R8A7743
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{
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.compatible = "renesas,r8a7743-cpg-mssr",
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@ -791,13 +833,23 @@ static int cpg_mssr_resume_noirq(struct device *dev)
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if (!mask)
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continue;
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oldval = readl(priv->base + SMSTPCR(reg));
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if (priv->stbyctrl)
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oldval = readb(priv->base + STBCR(reg));
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else
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oldval = readl(priv->base + SMSTPCR(reg));
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newval = oldval & ~mask;
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newval |= priv->smstpcr_saved[reg].val & mask;
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if (newval == oldval)
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continue;
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writel(newval, priv->base + SMSTPCR(reg));
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if (priv->stbyctrl) {
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writeb(newval, priv->base + STBCR(reg));
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/* dummy read to ensure write has completed */
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readb(priv->base + STBCR(reg));
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barrier_data(priv->base + STBCR(reg));
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continue;
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} else
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writel(newval, priv->base + SMSTPCR(reg));
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/* Wait until enabled clocks are really enabled */
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mask &= ~priv->smstpcr_saved[reg].val;
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@ -869,6 +921,7 @@ static int __init cpg_mssr_probe(struct platform_device *pdev)
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priv->num_mod_clks = info->num_hw_mod_clks;
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priv->last_dt_core_clk = info->last_dt_core_clk;
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RAW_INIT_NOTIFIER_HEAD(&priv->notifiers);
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priv->stbyctrl = info->stbyctrl;
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for (i = 0; i < nclks; i++)
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clks[i] = ERR_PTR(-ENOENT);
|
||||
|
|
@ -894,6 +947,10 @@ static int __init cpg_mssr_probe(struct platform_device *pdev)
|
|||
if (error)
|
||||
return error;
|
||||
|
||||
/* Reset Controller not supported for Standby Control SoCs */
|
||||
if (info->stbyctrl)
|
||||
return 0;
|
||||
|
||||
error = cpg_mssr_reset_controller_register(priv);
|
||||
if (error)
|
||||
return error;
|
||||
|
|
|
|||
|
|
@ -78,6 +78,13 @@ struct mssr_mod_clk {
|
|||
#define DEF_MOD(_name, _mod, _parent...) \
|
||||
{ .name = _name, .id = MOD_CLK_ID(_mod), .parent = _parent }
|
||||
|
||||
/* Convert from sparse base-10 to packed index space */
|
||||
#define MOD_CLK_PACK_10(x) ((x / 10) * 32 + (x % 10))
|
||||
|
||||
#define MOD_CLK_ID_10(x) (MOD_CLK_BASE + MOD_CLK_PACK_10(x))
|
||||
|
||||
#define DEF_MOD_STB(_name, _mod, _parent...) \
|
||||
{ .name = _name, .id = MOD_CLK_ID_10(_mod), .parent = _parent }
|
||||
|
||||
struct device_node;
|
||||
|
||||
|
|
@ -103,6 +110,10 @@ struct device_node;
|
|||
*
|
||||
* @init: Optional callback to perform SoC-specific initialization
|
||||
* @cpg_clk_register: Optional callback to handle special Core Clock types
|
||||
*
|
||||
* @stbyctrl: This device has Standby Control Registers which are 8-bits
|
||||
* wide, no status registers (MSTPSR) and have different address
|
||||
* offsets.
|
||||
*/
|
||||
|
||||
struct cpg_mssr_info {
|
||||
|
|
@ -111,6 +122,7 @@ struct cpg_mssr_info {
|
|||
unsigned int num_core_clks;
|
||||
unsigned int last_dt_core_clk;
|
||||
unsigned int num_total_core_clks;
|
||||
bool stbyctrl;
|
||||
|
||||
/* Module Clocks */
|
||||
const struct mssr_mod_clk *mod_clks;
|
||||
|
|
@ -134,6 +146,7 @@ struct cpg_mssr_info {
|
|||
struct raw_notifier_head *notifiers);
|
||||
};
|
||||
|
||||
extern const struct cpg_mssr_info r7s9210_cpg_mssr_info;
|
||||
extern const struct cpg_mssr_info r8a7743_cpg_mssr_info;
|
||||
extern const struct cpg_mssr_info r8a7745_cpg_mssr_info;
|
||||
extern const struct cpg_mssr_info r8a77470_cpg_mssr_info;
|
||||
|
|
|
|||
|
|
@ -0,0 +1,20 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0
|
||||
*
|
||||
* Copyright (C) 2018 Renesas Electronics Corp.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_R7S9210_CPG_MSSR_H__
|
||||
#define __DT_BINDINGS_CLOCK_R7S9210_CPG_MSSR_H__
|
||||
|
||||
#include <dt-bindings/clock/renesas-cpg-mssr.h>
|
||||
|
||||
/* R7S9210 CPG Core Clocks */
|
||||
#define R7S9210_CLK_I 0
|
||||
#define R7S9210_CLK_G 1
|
||||
#define R7S9210_CLK_B 2
|
||||
#define R7S9210_CLK_P1 3
|
||||
#define R7S9210_CLK_P1C 4
|
||||
#define R7S9210_CLK_P0 5
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_R7S9210_CPG_MSSR_H__ */
|
||||
Loading…
Reference in New Issue