mirror of https://gitee.com/openkylin/linux.git
octeontx2-af: Add SDP interface support
Added support for packet IO via SDK links which is used when Octeon is connected as a end-point. Traffic host to end-point and vice versa flow through SDP links. This patch also support dual SDP blocks supported in 98xx silicon. Signed-off-by: Radha Mohan Chintakuntla <radhac@marvell.com> Signed-off-by: Nalla Pradeep <pnalla@marvell.com> Signed-off-by: Subrahmanyam Nilla <snilla@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
parent
aefaa8c715
commit
fe1939bb23
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@ -10,4 +10,5 @@ obj-$(CONFIG_OCTEONTX2_AF) += rvu_af.o
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rvu_mbox-y := mbox.o rvu_trace.o
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rvu_af-y := cgx.o rvu.o rvu_cgx.o rvu_npa.o rvu_nix.o \
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rvu_reg.o rvu_npc.o rvu_debugfs.o ptp.o rvu_npc_fs.o \
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rvu_cpt.o rvu_devlink.o rpm.o rvu_cn10k.o rvu_switch.o
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rvu_cpt.o rvu_devlink.o rpm.o rvu_cn10k.o rvu_switch.o \
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rvu_sdp.o
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@ -185,13 +185,16 @@ enum nix_scheduler {
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#define NIX_INTF_TYPE_CGX 0
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#define NIX_INTF_TYPE_LBK 1
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#define NIX_INTF_TYPE_SDP 2
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#define MAX_LMAC_PKIND 12
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#define NIX_LINK_CGX_LMAC(a, b) (0 + 4 * (a) + (b))
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#define NIX_LINK_LBK(a) (12 + (a))
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#define NIX_CHAN_CGX_LMAC_CHX(a, b, c) (0x800 + 0x100 * (a) + 0x10 * (b) + (c))
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#define NIX_CHAN_LBK_CHX(a, b) (0 + 0x100 * (a) + (b))
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#define NIX_CHAN_SDP_CH_START (0x700ull)
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#define NIX_CHAN_SDP_CH_START (0x700ull)
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#define NIX_CHAN_SDP_CHX(a) (NIX_CHAN_SDP_CH_START + (a))
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#define NIX_CHAN_SDP_NUM_CHANS 256
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/* The mask is to extract lower 10-bits of channel number
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* which CPT will pass to X2P.
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@ -191,6 +191,9 @@ M(CPT_RD_WR_REGISTER, 0xA02, cpt_rd_wr_register, cpt_rd_wr_reg_msg, \
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M(CPT_STATS, 0xA05, cpt_sts, cpt_sts_req, cpt_sts_rsp) \
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M(CPT_RXC_TIME_CFG, 0xA06, cpt_rxc_time_cfg, cpt_rxc_time_cfg_req, \
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msg_rsp) \
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/* SDP mbox IDs (range 0x1000 - 0x11FF) */ \
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M(SET_SDP_CHAN_INFO, 0x1000, set_sdp_chan_info, sdp_chan_info_msg, msg_rsp) \
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M(GET_SDP_CHAN_INFO, 0x1001, get_sdp_chan_info, msg_req, sdp_get_chan_info_msg) \
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/* NPC mbox IDs (range 0x6000 - 0x7FFF) */ \
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M(NPC_MCAM_ALLOC_ENTRY, 0x6000, npc_mcam_alloc_entry, npc_mcam_alloc_entry_req,\
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npc_mcam_alloc_entry_rsp) \
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@ -1446,6 +1449,27 @@ struct cpt_rxc_time_cfg_req {
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u16 active_limit;
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};
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struct sdp_node_info {
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/* Node to which this PF belons to */
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u8 node_id;
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u8 max_vfs;
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u8 num_pf_rings;
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u8 pf_srn;
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#define SDP_MAX_VFS 128
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u8 vf_rings[SDP_MAX_VFS];
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};
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struct sdp_chan_info_msg {
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struct mbox_msghdr hdr;
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struct sdp_node_info info;
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};
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struct sdp_get_chan_info_msg {
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struct mbox_msghdr hdr;
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u16 chan_base;
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u16 num_chan;
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};
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/* CGX mailbox error codes
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* Range 1101 - 1200.
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*/
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@ -1118,6 +1118,12 @@ static int rvu_setup_hw_resources(struct rvu *rvu)
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goto nix_err;
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}
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err = rvu_sdp_init(rvu);
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if (err) {
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dev_err(rvu->dev, "%s: Failed to initialize sdp\n", __func__);
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goto nix_err;
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}
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rvu_program_channels(rvu);
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return 0;
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@ -1370,9 +1376,10 @@ int rvu_get_nix_blkaddr(struct rvu *rvu, u16 pcifunc)
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int blkaddr = BLKADDR_NIX0, vf;
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struct rvu_pfvf *pf;
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pf = rvu_get_pfvf(rvu, pcifunc & ~RVU_PFVF_FUNC_MASK);
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/* All CGX mapped PFs are set with assigned NIX block during init */
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if (is_pf_cgxmapped(rvu, rvu_get_pf(pcifunc))) {
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pf = rvu_get_pfvf(rvu, pcifunc & ~RVU_PFVF_FUNC_MASK);
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blkaddr = pf->nix_blkaddr;
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} else if (is_afvf(pcifunc)) {
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vf = pcifunc - 1;
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@ -1385,6 +1392,10 @@ int rvu_get_nix_blkaddr(struct rvu *rvu, u16 pcifunc)
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blkaddr = BLKADDR_NIX0;
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}
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/* if SDP1 then the blkaddr is NIX1 */
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if (is_sdp_pfvf(pcifunc) && pf->sdp_info->node_id == 1)
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blkaddr = BLKADDR_NIX1;
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switch (blkaddr) {
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case BLKADDR_NIX1:
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pfvf->nix_blkaddr = BLKADDR_NIX1;
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@ -246,6 +246,7 @@ struct rvu_pfvf {
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u8 lbkid; /* NIX0/1 lbk link ID */
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u64 lmt_base_addr; /* Preseving the pcifunc's lmtst base addr*/
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unsigned long flags;
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struct sdp_node_info *sdp_info;
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};
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enum rvu_pfvf_flags {
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@ -597,6 +598,16 @@ static inline u16 rvu_nix_chan_lbk(struct rvu *rvu, u8 lbkid,
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return rvu->hw->lbk_chan_base + lbkid * lbk_chans + chan;
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}
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static inline u16 rvu_nix_chan_sdp(struct rvu *rvu, u8 chan)
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{
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struct rvu_hwinfo *hw = rvu->hw;
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if (!hw->cap.programmable_chans)
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return NIX_CHAN_SDP_CHX(chan);
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return hw->sdp_chan_base + chan;
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}
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static inline u16 rvu_nix_chan_cpt(struct rvu *rvu, u8 chan)
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{
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return rvu->hw->cpt_chan_base + chan;
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@ -659,10 +670,17 @@ int rvu_aq_alloc(struct rvu *rvu, struct admin_queue **ad_queue,
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int qsize, int inst_size, int res_size);
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void rvu_aq_free(struct rvu *rvu, struct admin_queue *aq);
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/* SDP APIs */
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int rvu_sdp_init(struct rvu *rvu);
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bool is_sdp_pfvf(u16 pcifunc);
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bool is_sdp_pf(u16 pcifunc);
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bool is_sdp_vf(u16 pcifunc);
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/* CGX APIs */
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static inline bool is_pf_cgxmapped(struct rvu *rvu, u8 pf)
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{
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return (pf >= PF_CGXMAP_BASE && pf <= rvu->cgx_mapped_pfs);
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return (pf >= PF_CGXMAP_BASE && pf <= rvu->cgx_mapped_pfs) &&
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!is_sdp_pf(pf << RVU_PFVF_PF_SHIFT);
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}
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static inline void rvu_get_cgx_lmac_id(u8 map, u8 *cgx_id, u8 *lmac_id)
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@ -293,15 +293,19 @@ static bool is_valid_txschq(struct rvu *rvu, int blkaddr,
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static int nix_interface_init(struct rvu *rvu, u16 pcifunc, int type, int nixlf,
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struct nix_lf_alloc_rsp *rsp, bool loop)
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{
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struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);
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struct rvu_pfvf *parent_pf, *pfvf = rvu_get_pfvf(rvu, pcifunc);
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u16 req_chan_base, req_chan_end, req_chan_cnt;
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struct rvu_hwinfo *hw = rvu->hw;
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struct sdp_node_info *sdp_info;
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int pkind, pf, vf, lbkid, vfid;
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struct mac_ops *mac_ops;
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int pkind, pf, vf, lbkid;
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u8 cgx_id, lmac_id;
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bool from_vf;
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int err;
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pf = rvu_get_pf(pcifunc);
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if (!is_pf_cgxmapped(rvu, pf) && type != NIX_INTF_TYPE_LBK)
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if (!is_pf_cgxmapped(rvu, pf) && type != NIX_INTF_TYPE_LBK &&
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type != NIX_INTF_TYPE_SDP)
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return 0;
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switch (type) {
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@ -325,6 +329,7 @@ static int nix_interface_init(struct rvu *rvu, u16 pcifunc, int type, int nixlf,
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rvu_npc_set_pkind(rvu, pkind, pfvf);
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mac_ops = get_mac_ops(rvu_cgx_pdata(cgx_id, rvu));
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/* By default we enable pause frames */
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if ((pcifunc & RVU_PFVF_FUNC_MASK) == 0)
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mac_ops->mac_enadis_pause_frm(rvu_cgx_pdata(cgx_id,
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@ -376,6 +381,45 @@ static int nix_interface_init(struct rvu *rvu, u16 pcifunc, int type, int nixlf,
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rsp->tx_link = hw->cgx_links + lbkid;
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pfvf->lbkid = lbkid;
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rvu_npc_set_pkind(rvu, NPC_RX_LBK_PKIND, pfvf);
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rvu_npc_install_promisc_entry(rvu, pcifunc, nixlf,
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pfvf->rx_chan_base,
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pfvf->rx_chan_cnt);
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break;
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case NIX_INTF_TYPE_SDP:
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from_vf = !!(pcifunc & RVU_PFVF_FUNC_MASK);
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parent_pf = &rvu->pf[rvu_get_pf(pcifunc)];
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sdp_info = parent_pf->sdp_info;
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if (!sdp_info) {
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dev_err(rvu->dev, "Invalid sdp_info pointer\n");
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return -EINVAL;
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}
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if (from_vf) {
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req_chan_base = rvu_nix_chan_sdp(rvu, 0) + sdp_info->pf_srn +
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sdp_info->num_pf_rings;
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vf = (pcifunc & RVU_PFVF_FUNC_MASK) - 1;
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for (vfid = 0; vfid < vf; vfid++)
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req_chan_base += sdp_info->vf_rings[vfid];
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req_chan_cnt = sdp_info->vf_rings[vf];
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req_chan_end = req_chan_base + req_chan_cnt - 1;
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if (req_chan_base < rvu_nix_chan_sdp(rvu, 0) ||
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req_chan_end > rvu_nix_chan_sdp(rvu, 255)) {
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dev_err(rvu->dev,
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"PF_Func 0x%x: Invalid channel base and count\n",
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pcifunc);
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return -EINVAL;
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}
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} else {
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req_chan_base = rvu_nix_chan_sdp(rvu, 0) + sdp_info->pf_srn;
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req_chan_cnt = sdp_info->num_pf_rings;
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}
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pfvf->rx_chan_base = req_chan_base;
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pfvf->rx_chan_cnt = req_chan_cnt;
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pfvf->tx_chan_base = pfvf->rx_chan_base;
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pfvf->tx_chan_cnt = pfvf->rx_chan_cnt;
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rsp->tx_link = hw->cgx_links + hw->lbk_links;
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rvu_npc_install_promisc_entry(rvu, pcifunc, nixlf,
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pfvf->rx_chan_base,
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pfvf->rx_chan_cnt);
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@ -459,9 +503,9 @@ int rvu_mbox_handler_nix_bp_disable(struct rvu *rvu,
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static int rvu_nix_get_bpid(struct rvu *rvu, struct nix_bp_cfg_req *req,
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int type, int chan_id)
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{
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int bpid, blkaddr, lmac_chan_cnt;
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int bpid, blkaddr, lmac_chan_cnt, sdp_chan_cnt;
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u16 cgx_bpid_cnt, lbk_bpid_cnt, sdp_bpid_cnt;
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struct rvu_hwinfo *hw = rvu->hw;
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u16 cgx_bpid_cnt, lbk_bpid_cnt;
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struct rvu_pfvf *pfvf;
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u8 cgx_id, lmac_id;
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u64 cfg;
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@ -470,8 +514,12 @@ static int rvu_nix_get_bpid(struct rvu *rvu, struct nix_bp_cfg_req *req,
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cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST);
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lmac_chan_cnt = cfg & 0xFF;
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cfg = rvu_read64(rvu, blkaddr, NIX_AF_CONST1);
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sdp_chan_cnt = cfg & 0xFFF;
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cgx_bpid_cnt = hw->cgx_links * lmac_chan_cnt;
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lbk_bpid_cnt = hw->lbk_links * ((cfg >> 16) & 0xFF);
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sdp_bpid_cnt = hw->sdp_links * sdp_chan_cnt;
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pfvf = rvu_get_pfvf(rvu, req->hdr.pcifunc);
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@ -509,6 +557,17 @@ static int rvu_nix_get_bpid(struct rvu *rvu, struct nix_bp_cfg_req *req,
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if (bpid > (cgx_bpid_cnt + lbk_bpid_cnt))
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return -EINVAL;
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break;
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case NIX_INTF_TYPE_SDP:
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if ((req->chan_base + req->chan_cnt) > 255)
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return -EINVAL;
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bpid = sdp_bpid_cnt + req->chan_base;
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if (req->bpid_per_chan)
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bpid += chan_id;
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if (bpid > (cgx_bpid_cnt + lbk_bpid_cnt + sdp_bpid_cnt))
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return -EINVAL;
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break;
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default:
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return -EINVAL;
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}
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@ -528,9 +587,12 @@ int rvu_mbox_handler_nix_bp_enable(struct rvu *rvu,
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pf = rvu_get_pf(pcifunc);
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type = is_afvf(pcifunc) ? NIX_INTF_TYPE_LBK : NIX_INTF_TYPE_CGX;
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if (is_sdp_pfvf(pcifunc))
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type = NIX_INTF_TYPE_SDP;
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/* Enable backpressure only for CGX mapped PFs and LBK interface */
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if (!is_pf_cgxmapped(rvu, pf) && type != NIX_INTF_TYPE_LBK)
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/* Enable backpressure only for CGX mapped PFs and LBK/SDP interface */
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if (!is_pf_cgxmapped(rvu, pf) && type != NIX_INTF_TYPE_LBK &&
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type != NIX_INTF_TYPE_SDP)
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return 0;
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pfvf = rvu_get_pfvf(rvu, pcifunc);
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@ -547,8 +609,9 @@ int rvu_mbox_handler_nix_bp_enable(struct rvu *rvu,
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}
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cfg = rvu_read64(rvu, blkaddr, NIX_AF_RX_CHANX_CFG(chan));
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cfg &= ~GENMASK_ULL(8, 0);
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rvu_write64(rvu, blkaddr, NIX_AF_RX_CHANX_CFG(chan),
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cfg | (bpid & 0xFF) | BIT_ULL(16));
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cfg | (bpid & GENMASK_ULL(8, 0)) | BIT_ULL(16));
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chan_id++;
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bpid = rvu_nix_get_bpid(rvu, req, type, chan_id);
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}
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@ -1329,6 +1392,9 @@ int rvu_mbox_handler_nix_lf_alloc(struct rvu *rvu,
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rvu_write64(rvu, blkaddr, NIX_AF_LFX_TX_PARSE_CFG(nixlf), cfg);
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intf = is_afvf(pcifunc) ? NIX_INTF_TYPE_LBK : NIX_INTF_TYPE_CGX;
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if (is_sdp_pfvf(pcifunc))
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intf = NIX_INTF_TYPE_SDP;
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err = nix_interface_init(rvu, pcifunc, intf, nixlf, rsp,
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!!(req->flags & NIX_LF_LBK_BLK_SEL));
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if (err)
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@ -2772,14 +2838,19 @@ static int nix_update_mce_rule(struct rvu *rvu, u16 pcifunc,
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struct npc_mcam *mcam = &rvu->hw->mcam;
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struct rvu_hwinfo *hw = rvu->hw;
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struct nix_mce_list *mce_list;
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int pf;
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/* skip multicast pkt replication for AF's VFs */
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if (is_afvf(pcifunc))
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/* skip multicast pkt replication for AF's VFs & SDP links */
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if (is_afvf(pcifunc) || is_sdp_pfvf(pcifunc))
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return 0;
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if (!hw->cap.nix_rx_multicast)
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return 0;
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pf = rvu_get_pf(pcifunc);
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if (!is_pf_cgxmapped(rvu, pf))
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return 0;
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blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc);
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if (blkaddr < 0)
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return -EINVAL;
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@ -634,8 +634,8 @@ void rvu_npc_install_ucast_entry(struct rvu *rvu, u16 pcifunc,
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struct nix_rx_action action;
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int blkaddr, index;
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/* AF's VFs work in promiscuous mode */
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if (is_afvf(pcifunc))
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/* AF's and SDP VFs work in promiscuous mode */
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if (is_afvf(pcifunc) || is_sdp_vf(pcifunc))
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return;
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blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
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@ -863,7 +863,7 @@ void rvu_npc_install_allmulti_entry(struct rvu *rvu, u16 pcifunc, int nixlf,
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u16 vf_func;
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/* Only CGX PF/VF can add allmulticast entry */
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if (is_afvf(pcifunc))
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if (is_afvf(pcifunc) && is_sdp_vf(pcifunc))
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return;
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blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
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@ -0,0 +1,108 @@
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// SPDX-License-Identifier: GPL-2.0
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/* Marvell OcteonTx2 RVU Admin Function driver
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*
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* Copyright (C) 2021 Marvell.
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*
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*/
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#include <linux/pci.h>
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#include "rvu.h"
|
||||
|
||||
/* SDP PF device id */
|
||||
#define PCI_DEVID_OTX2_SDP_PF 0xA0F6
|
||||
|
||||
/* Maximum SDP blocks in a chip */
|
||||
#define MAX_SDP 2
|
||||
|
||||
/* SDP PF number */
|
||||
static int sdp_pf_num[MAX_SDP] = {-1, -1};
|
||||
|
||||
bool is_sdp_pfvf(u16 pcifunc)
|
||||
{
|
||||
u16 pf = rvu_get_pf(pcifunc);
|
||||
u32 found = 0, i = 0;
|
||||
|
||||
while (i < MAX_SDP) {
|
||||
if (pf == sdp_pf_num[i])
|
||||
found = 1;
|
||||
i++;
|
||||
}
|
||||
|
||||
if (!found)
|
||||
return false;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
bool is_sdp_pf(u16 pcifunc)
|
||||
{
|
||||
return (is_sdp_pfvf(pcifunc) &&
|
||||
!(pcifunc & RVU_PFVF_FUNC_MASK));
|
||||
}
|
||||
|
||||
bool is_sdp_vf(u16 pcifunc)
|
||||
{
|
||||
return (is_sdp_pfvf(pcifunc) &&
|
||||
!!(pcifunc & RVU_PFVF_FUNC_MASK));
|
||||
}
|
||||
|
||||
int rvu_sdp_init(struct rvu *rvu)
|
||||
{
|
||||
struct pci_dev *pdev = NULL;
|
||||
struct rvu_pfvf *pfvf;
|
||||
u32 i = 0;
|
||||
|
||||
while ((i < MAX_SDP) && (pdev = pci_get_device(PCI_VENDOR_ID_CAVIUM,
|
||||
PCI_DEVID_OTX2_SDP_PF,
|
||||
pdev)) != NULL) {
|
||||
/* The RVU PF number is one less than bus number */
|
||||
sdp_pf_num[i] = pdev->bus->number - 1;
|
||||
pfvf = &rvu->pf[sdp_pf_num[i]];
|
||||
|
||||
pfvf->sdp_info = devm_kzalloc(rvu->dev,
|
||||
sizeof(struct sdp_node_info),
|
||||
GFP_KERNEL);
|
||||
if (!pfvf->sdp_info)
|
||||
return -ENOMEM;
|
||||
|
||||
dev_info(rvu->dev, "SDP PF number:%d\n", sdp_pf_num[i]);
|
||||
|
||||
put_device(&pdev->dev);
|
||||
i++;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int
|
||||
rvu_mbox_handler_set_sdp_chan_info(struct rvu *rvu,
|
||||
struct sdp_chan_info_msg *req,
|
||||
struct msg_rsp *rsp)
|
||||
{
|
||||
struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, req->hdr.pcifunc);
|
||||
|
||||
memcpy(pfvf->sdp_info, &req->info, sizeof(struct sdp_node_info));
|
||||
dev_info(rvu->dev, "AF: SDP%d max_vfs %d num_pf_rings %d pf_srn %d\n",
|
||||
req->info.node_id, req->info.max_vfs, req->info.num_pf_rings,
|
||||
req->info.pf_srn);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int
|
||||
rvu_mbox_handler_get_sdp_chan_info(struct rvu *rvu, struct msg_req *req,
|
||||
struct sdp_get_chan_info_msg *rsp)
|
||||
{
|
||||
struct rvu_hwinfo *hw = rvu->hw;
|
||||
int blkaddr;
|
||||
|
||||
if (!hw->cap.programmable_chans) {
|
||||
rsp->chan_base = NIX_CHAN_SDP_CH_START;
|
||||
rsp->num_chan = NIX_CHAN_SDP_NUM_CHANS;
|
||||
} else {
|
||||
blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, 0);
|
||||
rsp->chan_base = hw->sdp_chan_base;
|
||||
rsp->num_chan = rvu_read64(rvu, blkaddr, NIX_AF_CONST1) & 0xFFFUL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
Loading…
Reference in New Issue