mirror of https://gitee.com/openkylin/linux.git
usb: dwc2: Make dwc2_readl/writel functions endianness-agnostic.
Declared dwc2_check_core_endianness() function for dynamicly check core endianness. Added needs_byte_swap flag to hsotg structure, and depending on flag swap value inside dwc2_readl/writel functions. Signed-off-by: Gevorg Sahakyan <sahakyan@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
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@ -857,6 +857,7 @@ struct dwc2_hregs_backup {
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* @gr_backup: Backup of global registers during suspend
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* @gr_backup: Backup of global registers during suspend
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* @dr_backup: Backup of device registers during suspend
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* @dr_backup: Backup of device registers during suspend
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* @hr_backup: Backup of host registers during suspend
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* @hr_backup: Backup of host registers during suspend
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* @needs_byte_swap: Specifies whether the opposite endianness.
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*
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*
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* These are for host mode:
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* These are for host mode:
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*
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*
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@ -1046,6 +1047,7 @@ struct dwc2_hsotg {
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struct dentry *debug_root;
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struct dentry *debug_root;
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struct debugfs_regset32 *regset;
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struct debugfs_regset32 *regset;
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bool needs_byte_swap;
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/* DWC OTG HW Release versions */
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/* DWC OTG HW Release versions */
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#define DWC2_CORE_REV_2_71a 0x4f54271a
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#define DWC2_CORE_REV_2_71a 0x4f54271a
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@ -1164,12 +1166,21 @@ struct dwc2_hsotg {
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/* Normal architectures just use readl/write */
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/* Normal architectures just use readl/write */
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static inline u32 dwc2_readl(struct dwc2_hsotg *hsotg, u32 offset)
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static inline u32 dwc2_readl(struct dwc2_hsotg *hsotg, u32 offset)
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{
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{
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return readl(hsotg->regs + offset);
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u32 val;
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val = readl(hsotg->regs + offset);
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if (hsotg->needs_byte_swap)
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return swab32(val);
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else
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return val;
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}
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}
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static inline void dwc2_writel(struct dwc2_hsotg *hsotg, u32 value, u32 offset)
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static inline void dwc2_writel(struct dwc2_hsotg *hsotg, u32 value, u32 offset)
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{
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{
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writel(value, hsotg->regs + offset);
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if (hsotg->needs_byte_swap)
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writel(swab32(value), hsotg->regs + offset);
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else
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writel(value, hsotg->regs + offset);
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#ifdef DWC2_LOG_WRITES
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#ifdef DWC2_LOG_WRITES
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pr_info("info:: wrote %08x to %p\n", value, hsotg->regs + offset);
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pr_info("info:: wrote %08x to %p\n", value, hsotg->regs + offset);
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@ -352,6 +352,23 @@ static void dwc2_driver_shutdown(struct platform_device *dev)
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disable_irq(hsotg->irq);
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disable_irq(hsotg->irq);
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}
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}
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/**
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* dwc2_check_core_endianness() - Returns true if core and AHB have
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* opposite endianness.
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* @hsotg: Programming view of the DWC_otg controller.
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*/
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static bool dwc2_check_core_endianness(struct dwc2_hsotg *hsotg)
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{
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u32 snpsid;
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snpsid = ioread32(hsotg->regs + GSNPSID);
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if ((snpsid & GSNPSID_ID_MASK) == DWC2_OTG_ID ||
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(snpsid & GSNPSID_ID_MASK) == DWC2_FS_IOT_ID ||
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(snpsid & GSNPSID_ID_MASK) == DWC2_HS_IOT_ID)
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return false;
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return true;
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}
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/**
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/**
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* dwc2_driver_probe() - Called when the DWC_otg core is bound to the DWC_otg
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* dwc2_driver_probe() - Called when the DWC_otg core is bound to the DWC_otg
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* driver
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* driver
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@ -395,6 +412,8 @@ static int dwc2_driver_probe(struct platform_device *dev)
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dev_dbg(&dev->dev, "mapped PA %08lx to VA %p\n",
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dev_dbg(&dev->dev, "mapped PA %08lx to VA %p\n",
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(unsigned long)res->start, hsotg->regs);
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(unsigned long)res->start, hsotg->regs);
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hsotg->needs_byte_swap = dwc2_check_core_endianness(hsotg);
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retval = dwc2_lowlevel_hw_init(hsotg);
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retval = dwc2_lowlevel_hw_init(hsotg);
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if (retval)
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if (retval)
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return retval;
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return retval;
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