openkylin
/
linux
mirror of https://gitee.com/openkylin/linux.git
9
0
Fork 0
Code Issues Projects Releases Wiki Activity

drm/i915/bxt: fix DDI PHY vswing scale value setting 

According to bspec the DDI PHY vswing scale value is "don't care" in
case the scale enable bit [27] is clear. But this doesn't seem to be
correct. The scale value seems to also matter if the scale mode bit
[26] is set. So both bit 26 and 27 depend on the value. Setting the
scale value to 0 while either bit is set results in a failed modeset on
HDMI (sink reports no signal).

After reset the scale value is 0x98, but according to the spec we have
to program it to 0x9a. So for consistency program it always to 0x9a
regardless of the scale enable bit.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Tested-by: Matt Roper <matthew.d.roper@intel.com>
Acked-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
Imre Deak 2015-06-04 18:01:35 +03:00 committed by Jani Nikula
parent a6aaec8be2
commit fe4c63c8cb
1 changed files with 18 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

36
drivers/gpu/drm/i915/intel_ddi.c
View File

@ -181,15 +181,15 @@ struct bxt_ddi_buf_trans {
*/
static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
/* Idx NT mV diff db */
{ 52, 0, 0, 128, true }, /* 0: 400 0 */
{ 78, 0, 0, 85, false }, /* 1: 400 3.5 */
{ 104, 0, 0, 64, false }, /* 2: 400 6 */
{ 154, 0, 0, 43, false }, /* 3: 400 9.5 */
{ 77, 0, 0, 128, false }, /* 4: 600 0 */
{ 116, 0, 0, 85, false }, /* 5: 600 3.5 */
{ 154, 0, 0, 64, false }, /* 6: 600 6 */
{ 102, 0, 0, 128, false }, /* 7: 800 0 */
{ 154, 0, 0, 85, false }, /* 8: 800 3.5 */
{ 52, 0x9A, 0, 128, true }, /* 0: 400 0 */
{ 78, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
{ 104, 0x9A, 0, 64, false }, /* 2: 400 6 */
{ 154, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
{ 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
{ 116, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
{ 154, 0x9A, 0, 64, false }, /* 6: 600 6 */
{ 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
{ 154, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
{ 154, 0x9A, 1, 128, false }, /* 9: 1200 0 */
};
@ -198,15 +198,15 @@ static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
*/
static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
/* Idx NT mV diff db */
{ 52, 0, 0, 128, false }, /* 0: 400 0 */
{ 52, 0, 0, 85, false }, /* 1: 400 3.5 */
{ 52, 0, 0, 64, false }, /* 2: 400 6 */
{ 42, 0, 0, 43, false }, /* 3: 400 9.5 */
{ 77, 0, 0, 128, false }, /* 4: 600 0 */
{ 77, 0, 0, 85, false }, /* 5: 600 3.5 */
{ 77, 0, 0, 64, false }, /* 6: 600 6 */
{ 102, 0, 0, 128, false }, /* 7: 800 0 */
{ 102, 0, 0, 85, false }, /* 8: 800 3.5 */
{ 52, 0x9A, 0, 128, false }, /* 0: 400 0 */
{ 52, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
{ 52, 0x9A, 0, 64, false }, /* 2: 400 6 */
{ 42, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
{ 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
{ 77, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
{ 77, 0x9A, 0, 64, false }, /* 6: 600 6 */
{ 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
{ 102, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
{ 154, 0x9A, 1, 128, true }, /* 9: 1200 0 */
};