mirror of https://gitee.com/openkylin/linux.git
crypto: talitos - Perform auth check in h/w if on sec 2.1 and above
SEC version 2.1 and above adds the capability to do the IPSec ICV memcmp in h/w. Results of the cmp are written back in the descriptor header, along with the done status. A new callback is added that checks these ICCR bits instead of performing the memcmp on the core, and is enabled by h/w capability. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> After testing on different parts, another condition was added before using h/w auth check because different SEC revisions require different handling. The SEC 3.0 allows a more flexible link table where the auth data can span separate link table entries. The SEC 2.4/2.1 does not support this case. So a test was added in the decrypt routine for a fragmented case; the h/w auth check is disallowed for revisions not having the extent in the link table; in this case the hw auth check is done by software. A portion of a previous change for SEC 3.0 link table handling was removed since it became dead code with the hw auth check supported. This seems to be the best compromise for using hw auth check on supporting SEC revisions; it keeps the link table logic simpler for the fragmented cases. Signed-off-by: Lee Nipper <lee.nipper@freescale.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
Kim Phillips
Herbert Xu
parent
1c2e8811ee
commit
fe5720e2b7
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@ -137,6 +137,7 @@ struct talitos_private {
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/* .features flag */
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#define TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT 0x00000001
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#define TALITOS_FTR_HW_AUTH_CHECK 0x00000002
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/*
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* map virtual single (contiguous) pointer to h/w descriptor pointer
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@ -183,6 +184,11 @@ static int reset_channel(struct device *dev, int ch)
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setbits32(priv->reg + TALITOS_CCCR_LO(ch), TALITOS_CCCR_LO_CDWE |
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TALITOS_CCCR_LO_CDIE);
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/* and ICCR writeback, if available */
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if (priv->features & TALITOS_FTR_HW_AUTH_CHECK)
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setbits32(priv->reg + TALITOS_CCCR_LO(ch),
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TALITOS_CCCR_LO_IWSE);
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return 0;
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}
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@ -238,6 +244,11 @@ static int init_device(struct device *dev)
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setbits32(priv->reg + TALITOS_IMR, TALITOS_IMR_INIT);
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setbits32(priv->reg + TALITOS_IMR_LO, TALITOS_IMR_LO_INIT);
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/* disable integrity check error interrupts (use writeback instead) */
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if (priv->features & TALITOS_FTR_HW_AUTH_CHECK)
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setbits32(priv->reg + TALITOS_MDEUICR_LO,
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TALITOS_MDEUICR_LO_ICE);
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return 0;
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}
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@ -375,7 +386,8 @@ static void talitos_done(unsigned long data)
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/* At this point, all completed channels have been processed.
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* Unmask done interrupts for channels completed later on.
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*/
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setbits32(priv->reg + TALITOS_IMR, TALITOS_IMR_DONE);
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setbits32(priv->reg + TALITOS_IMR, TALITOS_IMR_INIT);
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setbits32(priv->reg + TALITOS_IMR_LO, TALITOS_IMR_LO_INIT);
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}
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/*
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@ -812,7 +824,7 @@ static void ipsec_esp_encrypt_done(struct device *dev,
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aead_request_complete(areq, err);
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}
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static void ipsec_esp_decrypt_done(struct device *dev,
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static void ipsec_esp_decrypt_swauth_done(struct device *dev,
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struct talitos_desc *desc, void *context,
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int err)
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{
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@ -844,6 +856,27 @@ static void ipsec_esp_decrypt_done(struct device *dev,
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aead_request_complete(req, err);
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}
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static void ipsec_esp_decrypt_hwauth_done(struct device *dev,
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struct talitos_desc *desc, void *context,
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int err)
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{
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struct aead_request *req = context;
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struct ipsec_esp_edesc *edesc =
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container_of(desc, struct ipsec_esp_edesc, desc);
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ipsec_esp_unmap(dev, edesc, req);
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/* check ICV auth status */
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if (!err)
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if ((desc->hdr_lo & DESC_HDR_LO_ICCR1_MASK) !=
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DESC_HDR_LO_ICCR1_PASS)
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err = -EBADMSG;
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kfree(edesc);
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aead_request_complete(req, err);
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}
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/*
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* convert scatterlist to SEC h/w link table format
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* stop at cryptlen bytes
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@ -897,6 +930,7 @@ static int ipsec_esp(struct ipsec_esp_edesc *edesc, struct aead_request *areq,
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unsigned int authsize = ctx->authsize;
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unsigned int ivsize;
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int sg_count, ret;
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int sg_link_tbl_len;
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/* hmac key */
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map_single_talitos_ptr(dev, &desc->ptr[0], ctx->authkeylen, &ctx->key,
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@ -934,33 +968,19 @@ static int ipsec_esp(struct ipsec_esp_edesc *edesc, struct aead_request *areq,
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if (sg_count == 1) {
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desc->ptr[4].ptr = cpu_to_be32(sg_dma_address(areq->src));
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} else {
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sg_count = sg_to_link_tbl(areq->src, sg_count, cryptlen,
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sg_link_tbl_len = cryptlen;
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if ((edesc->desc.hdr & DESC_HDR_MODE1_MDEU_CICV) &&
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(edesc->desc.hdr & DESC_HDR_MODE0_ENCRYPT) == 0) {
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sg_link_tbl_len = cryptlen + authsize;
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}
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sg_count = sg_to_link_tbl(areq->src, sg_count, sg_link_tbl_len,
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&edesc->link_tbl[0]);
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if (sg_count > 1) {
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struct talitos_ptr *link_tbl_ptr =
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&edesc->link_tbl[sg_count-1];
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struct scatterlist *sg;
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struct talitos_private *priv = dev_get_drvdata(dev);
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desc->ptr[4].j_extent |= DESC_PTR_LNKTBL_JUMP;
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desc->ptr[4].ptr = cpu_to_be32(edesc->dma_link_tbl);
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dma_sync_single_for_device(ctx->dev, edesc->dma_link_tbl,
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edesc->dma_len, DMA_BIDIRECTIONAL);
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/* If necessary for this SEC revision,
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* add a link table entry for ICV.
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*/
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if ((priv->features &
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TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT) &&
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(edesc->desc.hdr & DESC_HDR_MODE0_ENCRYPT) == 0) {
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link_tbl_ptr->j_extent = 0;
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link_tbl_ptr++;
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link_tbl_ptr->j_extent = DESC_PTR_LNKTBL_RETURN;
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link_tbl_ptr->len = cpu_to_be16(authsize);
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sg = sg_last(areq->src, edesc->src_nents ? : 1);
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link_tbl_ptr->ptr = cpu_to_be32(
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(char *)sg_dma_address(sg)
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+ sg->length - authsize);
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}
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} else {
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/* Only one segment now, so no link tbl needed */
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desc->ptr[4].ptr = cpu_to_be32(sg_dma_address(areq->src));
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@ -985,13 +1005,9 @@ static int ipsec_esp(struct ipsec_esp_edesc *edesc, struct aead_request *areq,
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desc->ptr[5].ptr = cpu_to_be32((struct talitos_ptr *)
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edesc->dma_link_tbl +
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edesc->src_nents + 1);
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if (areq->src == areq->dst) {
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memcpy(link_tbl_ptr, &edesc->link_tbl[0],
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edesc->src_nents * sizeof(struct talitos_ptr));
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} else {
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sg_count = sg_to_link_tbl(areq->dst, sg_count, cryptlen,
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link_tbl_ptr);
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}
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sg_count = sg_to_link_tbl(areq->dst, sg_count, cryptlen,
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link_tbl_ptr);
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/* Add an entry to the link table for ICV data */
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link_tbl_ptr += sg_count - 1;
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link_tbl_ptr->j_extent = 0;
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@ -1116,11 +1132,14 @@ static int aead_authenc_encrypt(struct aead_request *req)
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return ipsec_esp(edesc, req, NULL, 0, ipsec_esp_encrypt_done);
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}
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static int aead_authenc_decrypt(struct aead_request *req)
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{
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struct crypto_aead *authenc = crypto_aead_reqtfm(req);
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struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
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unsigned int authsize = ctx->authsize;
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struct talitos_private *priv = dev_get_drvdata(ctx->dev);
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struct ipsec_esp_edesc *edesc;
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struct scatterlist *sg;
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void *icvdata;
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@ -1132,22 +1151,39 @@ static int aead_authenc_decrypt(struct aead_request *req)
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if (IS_ERR(edesc))
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return PTR_ERR(edesc);
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/* stash incoming ICV for later cmp with ICV generated by the h/w */
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if (edesc->dma_len)
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icvdata = &edesc->link_tbl[edesc->src_nents +
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edesc->dst_nents + 2];
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else
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icvdata = &edesc->link_tbl[0];
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if ((priv->features & TALITOS_FTR_HW_AUTH_CHECK) &&
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(((!edesc->src_nents && !edesc->dst_nents) ||
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priv->features & TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT))) {
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sg = sg_last(req->src, edesc->src_nents ? : 1);
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/* decrypt and check the ICV */
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edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND |
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DESC_HDR_MODE1_MDEU_CICV;
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memcpy(icvdata, (char *)sg_virt(sg) + sg->length - ctx->authsize,
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ctx->authsize);
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/* reset integrity check result bits */
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edesc->desc.hdr_lo = 0;
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/* decrypt */
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edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND;
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return ipsec_esp(edesc, req, NULL, 0, ipsec_esp_decrypt_hwauth_done);
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return ipsec_esp(edesc, req, NULL, 0, ipsec_esp_decrypt_done);
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} else {
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/* Have to check the ICV with software */
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edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND;
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/* stash incoming ICV for later cmp with ICV generated by the h/w */
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if (edesc->dma_len)
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icvdata = &edesc->link_tbl[edesc->src_nents +
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edesc->dst_nents + 2];
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else
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icvdata = &edesc->link_tbl[0];
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sg = sg_last(req->src, edesc->src_nents ? : 1);
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memcpy(icvdata, (char *)sg_virt(sg) + sg->length - ctx->authsize,
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ctx->authsize);
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return ipsec_esp(edesc, req, NULL, 0, ipsec_esp_decrypt_swauth_done);
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}
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}
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static int aead_authenc_givencrypt(
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@ -1460,10 +1496,10 @@ static int talitos_probe(struct of_device *ofdev,
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priv->ofdev = ofdev;
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INIT_LIST_HEAD(&priv->alg_list);
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tasklet_init(&priv->done_task, talitos_done, (unsigned long)dev);
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INIT_LIST_HEAD(&priv->alg_list);
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priv->irq = irq_of_parse_and_map(np, 0);
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if (priv->irq == NO_IRQ) {
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@ -1516,6 +1552,9 @@ static int talitos_probe(struct of_device *ofdev,
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if (of_device_is_compatible(np, "fsl,sec3.0"))
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priv->features |= TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT;
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if (of_device_is_compatible(np, "fsl,sec2.1"))
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priv->features |= TALITOS_FTR_HW_AUTH_CHECK;
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priv->head_lock = kmalloc(sizeof(spinlock_t) * priv->num_channels,
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GFP_KERNEL);
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priv->tail_lock = kmalloc(sizeof(spinlock_t) * priv->num_channels,
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@ -56,6 +56,7 @@
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#define TALITOS_CCCR_CONT 0x2 /* channel continue */
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#define TALITOS_CCCR_RESET 0x1 /* channel reset */
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#define TALITOS_CCCR_LO(ch) (ch * TALITOS_CH_STRIDE + 0x110c)
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#define TALITOS_CCCR_LO_IWSE 0x80 /* chan. ICCR writeback enab. */
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#define TALITOS_CCCR_LO_CDWE 0x10 /* chan. done writeback enab. */
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#define TALITOS_CCCR_LO_NT 0x4 /* notification type */
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#define TALITOS_CCCR_LO_CDIE 0x2 /* channel done IRQ enable */
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@ -103,6 +104,9 @@
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#define TALITOS_AESUISR_LO 0x4034
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#define TALITOS_MDEUISR 0x6030 /* message digest unit */
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#define TALITOS_MDEUISR_LO 0x6034
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#define TALITOS_MDEUICR 0x6038 /* interrupt control */
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#define TALITOS_MDEUICR_LO 0x603c
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#define TALITOS_MDEUICR_LO_ICE 0x4000 /* integrity check IRQ enable */
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#define TALITOS_AFEUISR 0x8030 /* arc4 unit */
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#define TALITOS_AFEUISR_LO 0x8034
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#define TALITOS_RNGUISR 0xa030 /* random number unit */
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@ -131,6 +135,9 @@
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/* written back when done */
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#define DESC_HDR_DONE __constant_cpu_to_be32(0xff000000)
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#define DESC_HDR_LO_ICCR1_MASK __constant_cpu_to_be32(0x00180000)
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#define DESC_HDR_LO_ICCR1_PASS __constant_cpu_to_be32(0x00080000)
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#define DESC_HDR_LO_ICCR1_FAIL __constant_cpu_to_be32(0x00100000)
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/* primary execution unit select */
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#define DESC_HDR_SEL0_MASK __constant_cpu_to_be32(0xf0000000)
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@ -169,6 +176,7 @@
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#define DESC_HDR_SEL1_CRCU __constant_cpu_to_be32(0x00080000)
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/* secondary execution unit mode (MODE1) and derivatives */
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#define DESC_HDR_MODE1_MDEU_CICV __constant_cpu_to_be32(0x00004000)
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#define DESC_HDR_MODE1_MDEU_INIT __constant_cpu_to_be32(0x00001000)
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#define DESC_HDR_MODE1_MDEU_HMAC __constant_cpu_to_be32(0x00000800)
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#define DESC_HDR_MODE1_MDEU_PAD __constant_cpu_to_be32(0x00000400)
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