mirror of https://gitee.com/openkylin/linux.git
ARM: sun8i: Add the A33 AHB1 gates clock driver
The A33 has a different gates array than the A23, add the node to the DT. Reported-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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@ -72,6 +72,33 @@ pll11: pll11_clk {
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clock-output-names = "pll11";
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};
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ahb1_gates: clk@01c20060 {
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#clock-cells = <1>;
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compatible = "allwinner,sun8i-a33-ahb1-gates-clk";
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reg = <0x01c20060 0x8>;
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clocks = <&ahb1>;
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clock-indices = <1>, <5>,
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<6>, <8>, <9>,
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<10>, <13>, <14>,
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<19>, <20>,
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<21>, <24>, <26>,
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<29>, <32>, <36>,
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<40>, <44>, <46>,
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<52>, <53>,
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<54>, <57>,
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<58>;
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clock-output-names = "ahb1_mipidsi", "ahb1_ss",
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"ahb1_dma","ahb1_mmc0", "ahb1_mmc1",
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"ahb1_mmc2", "ahb1_nand", "ahb1_sdram",
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"ahb1_hstimer", "ahb1_spi0",
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"ahb1_spi1", "ahb1_otg", "ahb1_ehci",
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"ahb1_ohci", "ahb1_ve", "ahb1_lcd",
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"ahb1_csi", "ahb1_be", "ahb1_fe",
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"ahb1_gpu", "ahb1_msgbox",
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"ahb1_spinlock", "ahb1_drc",
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"ahb1_sat";
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};
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mbus_clk: clk@01c2015c {
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#clock-cells = <0>;
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compatible = "allwinner,sun8i-a23-mbus-clk";
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