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Staging wireless driver for 3.14-rc1 

Here's a single staging driver for a wireless chipset that has shown up
 in the SteamBox hardware.  It is merged separately from the "main"
 staging pull request to sync up with the wireless api changes that came
 in from the networking tree.
 
 It's self-contained and works for me and others.  Larry will be
 replacing it with a "real" driver for 3.15, but for now this one is
 needed.
 
 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v2.0.22 (GNU/Linux)
 
 iEYEABECAAYFAlLrs1oACgkQMUfUDdst+ymymgCdEAZh9GL3PyRDPCcefwYaOzo5
 BZcAoLmtj9XGDxaA2d87y8bN+FyX28Ik
 =l+1d
 -----END PGP SIGNATURE-----

Merge tag 'staging-3.14-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging

Pull rtl8812ae staging wireless driver from Greg KH:
 "Here's a single staging driver for a wireless chipset that has shown
  up in the SteamBox hardware.  It is merged separately from the "main"
  staging pull request to sync up with the wireless api changes that
  came in from the networking tree.

  It's self-contained and works for me and others.  Larry will be
  replacing it with a "real" driver for 3.15, but for now this one is
  needed"

* tag 'staging-3.14-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging:
  staging: r8821ae: Enable build by reverting BROKEN marking
  staging: r8821ae: Fix build problems
  Staging: rtl8812ae: disable due to build errors
  Staging: rtl8821ae: add TODO file
  Staging: rtl8821ae: removed unused functions and variables
  Staging: rtl8821ae: rc.c: fix up function prototypes
  Staging: rtl8812ae: Add Realtek 8821 PCI WIFI driver
This commit is contained in:
Linus Torvalds 2014-02-01 10:29:59 -08:00
parent 04480094de d7216f8f02
commit fea8893da7
75 changed files with 71854 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/staging/Kconfig
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@ -52,6 +52,8 @@ source "drivers/staging/rtl8712/Kconfig"
source "drivers/staging/rtl8188eu/Kconfig"
source "drivers/staging/rtl8821ae/Kconfig"
source "drivers/staging/rts5139/Kconfig"
source "drivers/staging/rts5208/Kconfig"

1
drivers/staging/Makefile
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@ -18,6 +18,7 @@ obj-$(CONFIG_RTL8192U) += rtl8192u/
obj-$(CONFIG_RTL8192E) += rtl8192e/
obj-$(CONFIG_R8712U) += rtl8712/
obj-$(CONFIG_R8188EU) += rtl8188eu/
obj-$(CONFIG_R8821AE) += rtl8821ae/
obj-$(CONFIG_RTS5139) += rts5139/
obj-$(CONFIG_RTS5208) += rts5208/
obj-$(CONFIG_TRANZPORT) += frontier/

11
drivers/staging/rtl8821ae/Kconfig Normal file
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@ -0,0 +1,11 @@
config R8821AE
tristate "RealTek RTL8821AE Wireless LAN NIC driver"
depends on PCI && WLAN
depends on m
select WIRELESS_EXT
select WEXT_PRIV
select EEPROM_93CX6
select CRYPTO
default N
---help---
If built as a module, it will be called r8821ae.ko.

35
drivers/staging/rtl8821ae/Makefile Normal file
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@ -0,0 +1,35 @@
PCI_MAIN_OBJS := base.o \
rc.o \
debug.o \
regd.o \
efuse.o \
cam.o \
ps.o \
core.o \
stats.o \
pci.o \
BT_COEXIST_OBJS:= btcoexist/halbtc8192e2ant.o\
btcoexist/halbtc8723b1ant.o\
btcoexist/halbtc8723b2ant.o\
btcoexist/halbtcoutsrc.o\
btcoexist/rtl_btc.o \
PCI_8821AE_HAL_OBJS:= \
rtl8821ae/hw.o \
rtl8821ae/table.o \
rtl8821ae/sw.o \
rtl8821ae/trx.o \
rtl8821ae/led.o \
rtl8821ae/fw.o \
rtl8821ae/phy.o \
rtl8821ae/rf.o \
rtl8821ae/dm.o \
rtl8821ae/pwrseq.o \
rtl8821ae/pwrseqcmd.o \
rtl8821ae/hal_btc.o \
rtl8821ae/hal_bt_coexist.o \
rtl8821ae-objs += $(BT_COEXIST_OBJS) $(PCI_MAIN_OBJS) $(PCI_8821AE_HAL_OBJS)
obj-$(CONFIG_R8821AE) += rtl8821ae.o

10
drivers/staging/rtl8821ae/TODO Normal file
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@ -0,0 +1,10 @@
Realtek 8821AE PCI wifi driver TODO:
- remove built-in btcoexist module when the "real" one gets upstream
- remove built-in rtlwifi code by porting driver to use the "real" one
in the drivers/net/ directory.
- fix up coding style issues
Please send any patches for this driver to:
Greg Kroah-Hartman <gregkh@linuxfoundation.org>
and the <devel@driverdev.osuosl.org> mailing list.

1873
drivers/staging/rtl8821ae/base.c Normal file
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159
drivers/staging/rtl8821ae/base.h Normal file
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@ -0,0 +1,159 @@
/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __RTL_BASE_H__
#define __RTL_BASE_H__
#include "compat.h"
enum ap_peer {
PEER_UNKNOWN = 0,
PEER_RTL = 1,
PEER_RTL_92SE = 2,
PEER_BROAD = 3,
PEER_RAL = 4,
PEER_ATH = 5,
PEER_CISCO = 6,
PEER_MARV = 7,
PEER_AIRGO = 9,
PEER_MAX = 10,
} ;
#define RTL_DUMMY_OFFSET 0
#define RTL_DUMMY_UNIT 8
#define RTL_TX_DUMMY_SIZE (RTL_DUMMY_OFFSET * RTL_DUMMY_UNIT)
#define RTL_TX_DESC_SIZE 32
#define RTL_TX_HEADER_SIZE (RTL_TX_DESC_SIZE + RTL_TX_DUMMY_SIZE)
#define HT_AMSDU_SIZE_4K 3839
#define HT_AMSDU_SIZE_8K 7935
#define MAX_BIT_RATE_40MHZ_MCS15 300 /* Mbps */
#define MAX_BIT_RATE_40MHZ_MCS7 150 /* Mbps */
#define RTL_RATE_COUNT_LEGACY 12
#define RTL_CHANNEL_COUNT 14
#define FRAME_OFFSET_FRAME_CONTROL 0
#define FRAME_OFFSET_DURATION 2
#define FRAME_OFFSET_ADDRESS1 4
#define FRAME_OFFSET_ADDRESS2 10
#define FRAME_OFFSET_ADDRESS3 16
#define FRAME_OFFSET_SEQUENCE 22
#define FRAME_OFFSET_ADDRESS4 24
#define SET_80211_HDR_FRAME_CONTROL(_hdr, _val) \
WRITEEF2BYTE(_hdr, _val)
#define SET_80211_HDR_TYPE_AND_SUBTYPE(_hdr, _val) \
WRITEEF1BYTE(_hdr, _val)
#define SET_80211_HDR_PWR_MGNT(_hdr, _val) \
SET_BITS_TO_LE_2BYTE(_hdr, 12, 1, _val)
#define SET_80211_HDR_TO_DS(_hdr, _val) \
SET_BITS_TO_LE_2BYTE(_hdr, 8, 1, _val)
#define SET_80211_PS_POLL_AID(_hdr, _val) \
WRITEEF2BYTE(((u8*)(_hdr))+2, _val)
#define SET_80211_PS_POLL_BSSID(_hdr, _val) \
CP_MACADDR(((u8*)(_hdr))+4, (u8*)(_val))
#define SET_80211_PS_POLL_TA(_hdr, _val) \
CP_MACADDR(((u8*)(_hdr))+10, (u8*)(_val))
#define SET_80211_HDR_DURATION(_hdr, _val) \
WRITEEF2BYTE((u8*)(_hdr)+FRAME_OFFSET_DURATION, _val)
#define SET_80211_HDR_ADDRESS1(_hdr, _val) \
CP_MACADDR((u8*)(_hdr)+FRAME_OFFSET_ADDRESS1, (u8*)(_val))
#define SET_80211_HDR_ADDRESS2(_hdr, _val) \
CP_MACADDR((u8*)(_hdr)+FRAME_OFFSET_ADDRESS2, (u8*)(_val))
#define SET_80211_HDR_ADDRESS3(_hdr, _val) \
CP_MACADDR((u8*)(_hdr)+FRAME_OFFSET_ADDRESS3, (u8*)(_val))
#define SET_80211_HDR_FRAGMENT_SEQUENCE(_hdr, _val) \
WRITEEF2BYTE((u8*)(_hdr)+FRAME_OFFSET_SEQUENCE, _val)
#define SET_BEACON_PROBE_RSP_TIME_STAMP_LOW(__phdr, __val) \
WRITEEF4BYTE(((u8*)(__phdr)) + 24, __val)
#define SET_BEACON_PROBE_RSP_TIME_STAMP_HIGH(__phdr, __val) \
WRITEEF4BYTE(((u8*)(__phdr)) + 28, __val)
#define SET_BEACON_PROBE_RSP_BEACON_INTERVAL(__phdr, __val) \
WRITEEF2BYTE(((u8*)(__phdr)) + 32, __val)
#define GET_BEACON_PROBE_RSP_CAPABILITY_INFO(__phdr) \
READEF2BYTE(((u8*)(__phdr)) + 34)
#define SET_BEACON_PROBE_RSP_CAPABILITY_INFO(__phdr, __val) \
WRITEEF2BYTE(((u8*)(__phdr)) + 34, __val)
#define MASK_BEACON_PROBE_RSP_CAPABILITY_INFO(__phdr, __val) \
SET_BEACON_PROBE_RSP_CAPABILITY_INFO(__phdr, \
(GET_BEACON_PROBE_RSP_CAPABILITY_INFO(__phdr) & (~(__val))))
int rtl_init_core(struct ieee80211_hw *hw);
void rtl_deinit_core(struct ieee80211_hw *hw);
void rtl_init_rx_config(struct ieee80211_hw *hw);
void rtl_init_rfkill(struct ieee80211_hw *hw);
void rtl_deinit_rfkill(struct ieee80211_hw *hw);
void rtl_watch_dog_timer_callback(unsigned long data);
void rtl_deinit_deferred_work(struct ieee80211_hw *hw);
bool rtl_action_proc(struct ieee80211_hw *hw, struct sk_buff *skb, u8 is_tx);
bool rtl_tx_mgmt_proc(struct ieee80211_hw *hw, struct sk_buff *skb);
u8 rtl_is_special_data(struct ieee80211_hw *hw, struct sk_buff *skb, u8 is_tx);
void rtl_beacon_statistic(struct ieee80211_hw *hw, struct sk_buff *skb);
void rtl_watch_dog_timer_callback(unsigned long data);
int rtl_tx_agg_start(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
struct ieee80211_sta *sta, u16 tid, u16 * ssn);
int rtl_tx_agg_stop(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
struct ieee80211_sta *sta, u16 tid);
int rtl_tx_agg_oper(struct ieee80211_hw *hw,
struct ieee80211_sta *sta, u16 tid);
int rtl_rx_agg_start(struct ieee80211_hw *hw,
struct ieee80211_sta *sta, u16 tid);
int rtl_rx_agg_stop(struct ieee80211_hw *hw,
struct ieee80211_sta *sta, u16 tid);
void rtl_watchdog_wq_callback(void *data);
void rtl_fwevt_wq_callback(void *data);
void rtl_get_tcb_desc(struct ieee80211_hw *hw,
struct ieee80211_tx_info *info,
struct ieee80211_sta *sta,
struct sk_buff *skb, struct rtl_tcb_desc *tcb_desc);
int rtl_send_smps_action(struct ieee80211_hw *hw,
struct ieee80211_sta *sta,
enum ieee80211_smps_mode smps);
u8 *rtl_find_ie(u8 *data, unsigned int len, u8 ie);
void rtl_recognize_peer(struct ieee80211_hw *hw, u8 *data, unsigned int len);
u8 rtl_tid_to_ac(struct ieee80211_hw *hw, u8 tid);
extern struct attribute_group rtl_attribute_group;
void rtl_easy_concurrent_retrytimer_callback(unsigned long data);
extern struct rtl_global_var global_var;
#ifdef VIF_TODO
struct ieee80211_vif *rtl_get_main_vif(struct ieee80211_hw *hw);
bool rtl_set_vif_info(struct ieee80211_hw *hw, struct ieee80211_vif *vif);
#endif
#endif

3976
drivers/staging/rtl8821ae/btcoexist/HalBtc8812a1Ant.c Normal file
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drivers/staging/rtl8821ae/btcoexist/HalBtc8812a1Ant.h Normal file
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//===========================================
// The following is for 8812A_1ANT BT Co-exist definition
//===========================================
#define BT_INFO_8812A_1ANT_B_FTP BIT7
#define BT_INFO_8812A_1ANT_B_A2DP BIT6
#define BT_INFO_8812A_1ANT_B_HID BIT5
#define BT_INFO_8812A_1ANT_B_SCO_BUSY BIT4
#define BT_INFO_8812A_1ANT_B_ACL_BUSY BIT3
#define BT_INFO_8812A_1ANT_B_INQ_PAGE BIT2
#define BT_INFO_8812A_1ANT_B_SCO_ESCO BIT1
#define BT_INFO_8812A_1ANT_B_CONNECTION BIT0
#define BT_INFO_8812A_1ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_) \
(((_BT_INFO_EXT_&BIT0))? true:false)
#define BTC_RSSI_COEX_THRESH_TOL_8812A_1ANT 2
#define
#define OUT
typedef enum _BT_INFO_SRC_8812A_1ANT{
BT_INFO_SRC_8812A_1ANT_WIFI_FW = 0x0,
BT_INFO_SRC_8812A_1ANT_BT_RSP = 0x1,
BT_INFO_SRC_8812A_1ANT_BT_ACTIVE_SEND = 0x2,
BT_INFO_SRC_8812A_1ANT_MAX
}BT_INFO_SRC_8812A_1ANT,*PBT_INFO_SRC_8812A_1ANT;
typedef enum _BT_8812A_1ANT_BT_STATUS{
BT_8812A_1ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0,
BT_8812A_1ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
BT_8812A_1ANT_BT_STATUS_INQ_PAGE = 0x2,
BT_8812A_1ANT_BT_STATUS_ACL_BUSY = 0x3,
BT_8812A_1ANT_BT_STATUS_SCO_BUSY = 0x4,
BT_8812A_1ANT_BT_STATUS_ACL_SCO_BUSY = 0x5,
BT_8812A_1ANT_BT_STATUS_MAX
}BT_8812A_1ANT_BT_STATUS,*PBT_8812A_1ANT_BT_STATUS;
typedef enum _BT_8812A_1ANT_COEX_ALGO{
BT_8812A_1ANT_COEX_ALGO_UNDEFINED = 0x0,
BT_8812A_1ANT_COEX_ALGO_SCO = 0x1,
BT_8812A_1ANT_COEX_ALGO_HID = 0x2,
BT_8812A_1ANT_COEX_ALGO_A2DP = 0x3,
BT_8812A_1ANT_COEX_ALGO_A2DP_PANHS = 0x4,
BT_8812A_1ANT_COEX_ALGO_PANEDR = 0x5,
BT_8812A_1ANT_COEX_ALGO_PANHS = 0x6,
BT_8812A_1ANT_COEX_ALGO_PANEDR_A2DP = 0x7,
BT_8812A_1ANT_COEX_ALGO_PANEDR_HID = 0x8,
BT_8812A_1ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9,
BT_8812A_1ANT_COEX_ALGO_HID_A2DP = 0xa,
BT_8812A_1ANT_COEX_ALGO_MAX = 0xb,
}BT_8812A_1ANT_COEX_ALGO,*PBT_8812A_1ANT_COEX_ALGO;
typedef struct _COEX_DM_8812A_1ANT{
// fw mechanism
bool pre_dec_bt_pwr;
bool cur_dec_bt_pwr;
bool bPreBtLnaConstrain;
bool bCurBtLnaConstrain;
u8 bPreBtPsdMode;
u8 bCurBtPsdMode;
u8 pre_fw_dac_swing_lvl;
u8 cur_fw_dac_swing_lvl;
bool cur_ignore_wlan_act;
bool pre_ignore_wlan_act;
u8 pre_ps_tdma;
u8 cur_ps_tdma;
u8 ps_tdma_para[5];
u8 ps_tdma_du_adj_type;
bool reset_tdma_adjust;
bool pre_ps_tdma_on;
bool cur_ps_tdma_on;
bool pre_bt_auto_report;
bool cur_bt_auto_report;
u8 pre_lps;
u8 cur_lps;
u8 pre_rpwm;
u8 cur_rpwm;
// sw mechanism
bool pre_rf_rx_lpf_shrink;
bool cur_rf_rx_lpf_shrink;
u32 bt_rf0x1e_backup;
bool pre_low_penalty_ra;
bool cur_low_penalty_ra;
bool pre_dac_swing_on;
u32 pre_dac_swing_lvl;
bool cur_dac_swing_on;
u32 cur_dac_swing_lvl;
bool pre_adc_back_off;
bool cur_adc_back_off;
bool pre_agc_table_en;
bool cur_agc_table_en;
u32 pre_val0x6c0;
u32 cur_val0x6c0;
u32 pre_val0x6c4;
u32 cur_val0x6c4;
u32 pre_val0x6c8;
u32 cur_val0x6c8;
u8 pre_val0x6cc;
u8 cur_val0x6cc;
bool limited_dig;
// algorithm related
u8 pre_algorithm;
u8 cur_algorithm;
u8 bt_status;
u8 wifi_chnl_info[3];
u8 error_condition;
} COEX_DM_8812A_1ANT, *PCOEX_DM_8812A_1ANT;
typedef struct _COEX_STA_8812A_1ANT{
bool under_lps;
bool under_ips;
u32 high_priority_tx;
u32 high_priority_rx;
u32 low_priority_tx;
u32 low_priority_rx;
u8 bt_rssi;
u8 pre_bt_rssi_state;
u8 pre_wifi_rssi_state[4];
bool c2h_bt_info_req_sent;
u8 bt_info_c2h[BT_INFO_SRC_8812A_1ANT_MAX][10];
u32 bt_info_c2h_cnt[BT_INFO_SRC_8812A_1ANT_MAX];
bool c2h_bt_inquiry_page;
u8 bt_retry_cnt;
u8 bt_info_ext;
}COEX_STA_8812A_1ANT, *PCOEX_STA_8812A_1ANT;
//===========================================
// The following is interface which will notify coex module.
//===========================================
void
EXhalbtc8812a1ant_InitHwConfig(
PBTC_COEXIST btcoexist
);
void
EXhalbtc8812a1ant_InitCoexDm(
PBTC_COEXIST btcoexist
);
void
EXhalbtc8812a1ant_IpsNotify(
PBTC_COEXIST btcoexist,
u8 type
);
void
EXhalbtc8812a1ant_LpsNotify(
PBTC_COEXIST btcoexist,
u8 type
);
void
EXhalbtc8812a1ant_ScanNotify(
PBTC_COEXIST btcoexist,
u8 type
);
void
EXhalbtc8812a1ant_ConnectNotify(
PBTC_COEXIST btcoexist,
u8 type
);
void
EXhalbtc8812a1ant_MediaStatusNotify(
PBTC_COEXIST btcoexist,
u8 type
);
void
EXhalbtc8812a1ant_SpecialPacketNotify(
PBTC_COEXIST btcoexist,
u8 type
);
void
EXhalbtc8812a1ant_BtInfoNotify(
PBTC_COEXIST btcoexist,
u8 *tmp_buf,
u8 length
);
void
EXhalbtc8812a1ant_StackOperationNotify(
PBTC_COEXIST btcoexist,
u8 type
);
void
EXhalbtc8812a1ant_HaltNotify(
PBTC_COEXIST btcoexist
);
void
EXhalbtc8812a1ant_PnpNotify(
PBTC_COEXIST btcoexist,
u8 pnpState
);
void
EXhalbtc8812a1ant_Periodical(
PBTC_COEXIST btcoexist
);
void
EXhalbtc8812a1ant_DisplayCoexInfo(
PBTC_COEXIST btcoexist
);
void
EXhalbtc8812a1ant_DbgControl(
PBTC_COEXIST btcoexist,
u8 opCode,
u8 opLen,
u8 *pData
);

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drivers/staging/rtl8821ae/btcoexist/habtc8723a1ant.c Normal file
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//===========================================
// The following is for 8723A 1Ant BT Co-exist definition
//===========================================
#define BT_INFO_8723A_1ANT_B_FTP BIT7
#define BT_INFO_8723A_1ANT_B_A2DP BIT6
#define BT_INFO_8723A_1ANT_B_HID BIT5
#define BT_INFO_8723A_1ANT_B_SCO_BUSY BIT4
#define BT_INFO_8723A_1ANT_B_ACL_BUSY BIT3
#define BT_INFO_8723A_1ANT_B_INQ_PAGE BIT2
#define BT_INFO_8723A_1ANT_B_SCO_ESCO BIT1
#define BT_INFO_8723A_1ANT_B_CONNECTION BIT0
typedef enum _BT_STATE_8723A_1ANT{
BT_STATE_8723A_1ANT_DISABLED = 0,
BT_STATE_8723A_1ANT_NO_CONNECTION = 1,
BT_STATE_8723A_1ANT_CONNECT_IDLE = 2,
BT_STATE_8723A_1ANT_INQ_OR_PAG = 3,
BT_STATE_8723A_1ANT_ACL_ONLY_BUSY = 4,
BT_STATE_8723A_1ANT_SCO_ONLY_BUSY = 5,
BT_STATE_8723A_1ANT_ACL_SCO_BUSY = 6,
BT_STATE_8723A_1ANT_HID_BUSY = 7,
BT_STATE_8723A_1ANT_HID_SCO_BUSY = 8,
BT_STATE_8723A_1ANT_MAX
}BT_STATE_8723A_1ANT, *PBT_STATE_8723A_1ANT;
#define BTC_RSSI_COEX_THRESH_TOL_8723A_1ANT 2
typedef enum _BT_INFO_SRC_8723A_1ANT{
BT_INFO_SRC_8723A_1ANT_WIFI_FW = 0x0,
BT_INFO_SRC_8723A_1ANT_BT_RSP = 0x1,
BT_INFO_SRC_8723A_1ANT_BT_ACTIVE_SEND = 0x2,
BT_INFO_SRC_8723A_1ANT_MAX
}BT_INFO_SRC_8723A_1ANT,*PBT_INFO_SRC_8723A_1ANT;
typedef enum _BT_8723A_1ANT_BT_STATUS{
BT_8723A_1ANT_BT_STATUS_IDLE = 0x0,
BT_8723A_1ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
BT_8723A_1ANT_BT_STATUS_NON_IDLE = 0x2,
BT_8723A_1ANT_BT_STATUS_MAX
}BT_8723A_1ANT_BT_STATUS,*PBT_8723A_1ANT_BT_STATUS;
typedef enum _BT_8723A_1ANT_COEX_ALGO{
BT_8723A_1ANT_COEX_ALGO_UNDEFINED = 0x0,
BT_8723A_1ANT_COEX_ALGO_SCO = 0x1,
BT_8723A_1ANT_COEX_ALGO_HID = 0x2,
BT_8723A_1ANT_COEX_ALGO_A2DP = 0x3,
BT_8723A_1ANT_COEX_ALGO_PANEDR = 0x4,
BT_8723A_1ANT_COEX_ALGO_PANHS = 0x5,
BT_8723A_1ANT_COEX_ALGO_PANEDR_A2DP = 0x6,
BT_8723A_1ANT_COEX_ALGO_PANEDR_HID = 0x7,
BT_8723A_1ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x8,
BT_8723A_1ANT_COEX_ALGO_HID_A2DP = 0x9,
BT_8723A_1ANT_COEX_ALGO_MAX
}BT_8723A_1ANT_COEX_ALGO,*PBT_8723A_1ANT_COEX_ALGO;
typedef struct _COEX_DM_8723A_1ANT{
// fw mechanism
BOOLEAN bCurIgnoreWlanAct;
BOOLEAN bPreIgnoreWlanAct;
u1Byte prePsTdma;
u1Byte curPsTdma;
u1Byte psTdmaPara[5];
u1Byte psTdmaDuAdjType;
u4Byte psTdmaMonitorCnt;
u4Byte psTdmaGlobalCnt;
BOOLEAN bResetTdmaAdjust;
BOOLEAN bPrePsTdmaOn;
BOOLEAN bCurPsTdmaOn;
// sw mechanism
BOOLEAN bPreRfRxLpfShrink;
BOOLEAN bCurRfRxLpfShrink;
u4Byte btRf0x1eBackup;
BOOLEAN bPreLowPenaltyRa;
BOOLEAN bCurLowPenaltyRa;
u4Byte preVal0x6c0;
u4Byte curVal0x6c0;
u4Byte preVal0x6c8;
u4Byte curVal0x6c8;
u1Byte preVal0x6cc;
u1Byte curVal0x6cc;
BOOLEAN limited_dig;
// algorithm related
u1Byte preAlgorithm;
u1Byte curAlgorithm;
u1Byte btStatus;
u1Byte wifiChnlInfo[3];
} COEX_DM_8723A_1ANT, *PCOEX_DM_8723A_1ANT;
typedef struct _COEX_STA_8723A_1ANT{
u4Byte highPriorityTx;
u4Byte highPriorityRx;
u4Byte lowPriorityTx;
u4Byte lowPriorityRx;
u1Byte btRssi;
u1Byte preBtRssiState;
u1Byte preBtRssiState1;
u1Byte preWifiRssiState[4];
BOOLEAN bC2hBtInfoReqSent;
u1Byte btInfoC2h[BT_INFO_SRC_8723A_1ANT_MAX][10];
u4Byte btInfoC2hCnt[BT_INFO_SRC_8723A_1ANT_MAX];
BOOLEAN bC2hBtInquiryPage;
u1Byte btRetryCnt;
u1Byte btInfoExt;
//BOOLEAN bHoldForStackOperation;
//u1Byte bHoldPeriodCnt;
// this is for c2h hang work-around
u4Byte c2hHangDetectCnt;
}COEX_STA_8723A_1ANT, *PCOEX_STA_8723A_1ANT;
//===========================================
// The following is interface which will notify coex module.
//===========================================
VOID
EXhalbtc8723a1ant_InitHwConfig(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8723a1ant_InitCoexDm(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8723a1ant_IpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723a1ant_LpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723a1ant_ScanNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723a1ant_ConnectNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723a1ant_MediaStatusNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723a1ant_SpecialPacketNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723a1ant_BtInfoNotify(
IN PBTC_COEXIST pBtCoexist,
IN pu1Byte tmpBuf,
IN u1Byte length
);
VOID
EXhalbtc8723a1ant_StackOperationNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723a1ant_HaltNotify(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8723a1ant_Periodical(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8723a1ant_DisplayCoexInfo(
IN PBTC_COEXIST pBtCoexist
);

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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __HALBT_PRECOMP_H__
#define __HALBT_PRECOMP_H__
/*************************************************************
* include files
*************************************************************/
#include "../wifi.h"
#include "../efuse.h"
#include "../base.h"
#include "../regd.h"
#include "../cam.h"
#include "../ps.h"
#include "../pci.h"
#include "../rtl8821ae/reg.h"
#include "../rtl8821ae/def.h"
#include "../rtl8821ae/phy.h"
#include "../rtl8821ae/dm.h"
#include "../rtl8821ae/fw.h"
#include "../rtl8821ae/led.h"
#include "../rtl8821ae/hw.h"
#include "../rtl8821ae/pwrseqcmd.h"
#include "../rtl8821ae/pwrseq.h"
#include "halbtcoutsrc.h"
#include "halbtc8192e2ant.h"
#include "halbtc8723b1ant.h"
#include "halbtc8723b2ant.h"
#define GetDefaultAdapter(padapter) padapter
#define BIT0 0x00000001
#define BIT1 0x00000002
#define BIT2 0x00000004
#define BIT3 0x00000008
#define BIT4 0x00000010
#define BIT5 0x00000020
#define BIT6 0x00000040
#define BIT7 0x00000080
#define BIT8 0x00000100
#define BIT9 0x00000200
#define BIT10 0x00000400
#define BIT11 0x00000800
#define BIT12 0x00001000
#define BIT13 0x00002000
#define BIT14 0x00004000
#define BIT15 0x00008000
#define BIT16 0x00010000
#define BIT17 0x00020000
#define BIT18 0x00040000
#define BIT19 0x00080000
#define BIT20 0x00100000
#define BIT21 0x00200000
#define BIT22 0x00400000
#define BIT23 0x00800000
#define BIT24 0x01000000
#define BIT25 0x02000000
#define BIT26 0x04000000
#define BIT27 0x08000000
#define BIT28 0x10000000
#define BIT29 0x20000000
#define BIT30 0x40000000
#define BIT31 0x80000000
#define MASKBYTE0 0xff
#define MASKBYTE1 0xff00
#define MASKBYTE2 0xff0000
#define MASKBYTE3 0xff000000
#define MASKHWORD 0xffff0000
#define MASKLWORD 0x0000ffff
#define MASKDWORD 0xffffffff
#define MASK12BITS 0xfff
#define MASKH4BITS 0xf0000000
#define MASKOFDM_D 0xffc00000
#define MASKCCK 0x3f3f3f3f
#endif /* __HALBT_PRECOMP_H__ */

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//===========================================
// The following is for 8192E_1ANT BT Co-exist definition
//===========================================
#define BT_AUTO_REPORT_ONLY_8192E_1ANT 0
#define BT_INFO_8192E_1ANT_B_FTP BIT7
#define BT_INFO_8192E_1ANT_B_A2DP BIT6
#define BT_INFO_8192E_1ANT_B_HID BIT5
#define BT_INFO_8192E_1ANT_B_SCO_BUSY BIT4
#define BT_INFO_8192E_1ANT_B_ACL_BUSY BIT3
#define BT_INFO_8192E_1ANT_B_INQ_PAGE BIT2
#define BT_INFO_8192E_1ANT_B_SCO_ESCO BIT1
#define BT_INFO_8192E_1ANT_B_CONNECTION BIT0
#define BT_INFO_8192E_1ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_) \
(((_BT_INFO_EXT_&BIT0))? true:FALSE)
#define BTC_RSSI_COEX_THRESH_TOL_8192E_1ANT 2
typedef enum _BT_INFO_SRC_8192E_1ANT{
BT_INFO_SRC_8192E_1ANT_WIFI_FW = 0x0,
BT_INFO_SRC_8192E_1ANT_BT_RSP = 0x1,
BT_INFO_SRC_8192E_1ANT_BT_ACTIVE_SEND = 0x2,
BT_INFO_SRC_8192E_1ANT_MAX
}BT_INFO_SRC_8192E_1ANT,*PBT_INFO_SRC_8192E_1ANT;
typedef enum _BT_8192E_1ANT_BT_STATUS{
BT_8192E_1ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0,
BT_8192E_1ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
BT_8192E_1ANT_BT_STATUS_INQ_PAGE = 0x2,
BT_8192E_1ANT_BT_STATUS_ACL_BUSY = 0x3,
BT_8192E_1ANT_BT_STATUS_SCO_BUSY = 0x4,
BT_8192E_1ANT_BT_STATUS_ACL_SCO_BUSY = 0x5,
BT_8192E_1ANT_BT_STATUS_MAX
}BT_8192E_1ANT_BT_STATUS,*PBT_8192E_1ANT_BT_STATUS;
typedef enum _BT_8192E_1ANT_WIFI_STATUS{
BT_8192E_1ANT_WIFI_STATUS_NON_CONNECTED_IDLE = 0x0,
BT_8192E_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN = 0x1,
BT_8192E_1ANT_WIFI_STATUS_CONNECTED_SCAN = 0x2,
BT_8192E_1ANT_WIFI_STATUS_CONNECTED_SPECIAL_PKT = 0x3,
BT_8192E_1ANT_WIFI_STATUS_CONNECTED_IDLE = 0x4,
BT_8192E_1ANT_WIFI_STATUS_CONNECTED_BUSY = 0x5,
BT_8192E_1ANT_WIFI_STATUS_MAX
}BT_8192E_1ANT_WIFI_STATUS,*PBT_8192E_1ANT_WIFI_STATUS;
typedef enum _BT_8192E_1ANT_COEX_ALGO{
BT_8192E_1ANT_COEX_ALGO_UNDEFINED = 0x0,
BT_8192E_1ANT_COEX_ALGO_SCO = 0x1,
BT_8192E_1ANT_COEX_ALGO_HID = 0x2,
BT_8192E_1ANT_COEX_ALGO_A2DP = 0x3,
BT_8192E_1ANT_COEX_ALGO_A2DP_PANHS = 0x4,
BT_8192E_1ANT_COEX_ALGO_PANEDR = 0x5,
BT_8192E_1ANT_COEX_ALGO_PANHS = 0x6,
BT_8192E_1ANT_COEX_ALGO_PANEDR_A2DP = 0x7,
BT_8192E_1ANT_COEX_ALGO_PANEDR_HID = 0x8,
BT_8192E_1ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9,
BT_8192E_1ANT_COEX_ALGO_HID_A2DP = 0xa,
BT_8192E_1ANT_COEX_ALGO_MAX = 0xb,
}BT_8192E_1ANT_COEX_ALGO,*PBT_8192E_1ANT_COEX_ALGO;
typedef struct _COEX_DM_8192E_1ANT{
// fw mechanism
u1Byte preBtDecPwrLvl;
u1Byte curBtDecPwrLvl;
BOOLEAN bPreBtLnaConstrain;
BOOLEAN bCurBtLnaConstrain;
u1Byte bPreBtPsdMode;
u1Byte bCurBtPsdMode;
u1Byte preFwDacSwingLvl;
u1Byte curFwDacSwingLvl;
BOOLEAN bCurIgnoreWlanAct;
BOOLEAN bPreIgnoreWlanAct;
u1Byte prePsTdma;
u1Byte curPsTdma;
u1Byte psTdmaPara[5];
u1Byte psTdmaDuAdjType;
BOOLEAN bAutoTdmaAdjust;
BOOLEAN bPrePsTdmaOn;
BOOLEAN bCurPsTdmaOn;
BOOLEAN bPreBtAutoReport;
BOOLEAN bCurBtAutoReport;
u1Byte preLps;
u1Byte curLps;
u1Byte preRpwm;
u1Byte curRpwm;
// sw mechanism
BOOLEAN bPreRfRxLpfShrink;
BOOLEAN bCurRfRxLpfShrink;
u4Byte btRf0x1eBackup;
BOOLEAN bPreLowPenaltyRa;
BOOLEAN bCurLowPenaltyRa;
BOOLEAN bPreDacSwingOn;
u4Byte preDacSwingLvl;
BOOLEAN bCurDacSwingOn;
u4Byte curDacSwingLvl;
BOOLEAN bPreAdcBackOff;
BOOLEAN bCurAdcBackOff;
BOOLEAN bPreAgcTableEn;
BOOLEAN bCurAgcTableEn;
u4Byte preVal0x6c0;
u4Byte curVal0x6c0;
u4Byte preVal0x6c4;
u4Byte curVal0x6c4;
u4Byte preVal0x6c8;
u4Byte curVal0x6c8;
u1Byte preVal0x6cc;
u1Byte curVal0x6cc;
BOOLEAN limited_dig;
// algorithm related
u1Byte preAlgorithm;
u1Byte curAlgorithm;
u1Byte btStatus;
u1Byte wifiChnlInfo[3];
u1Byte preSsType;
u1Byte curSsType;
u4Byte prera_mask;
u4Byte curra_mask;
u1Byte errorCondition;
} COEX_DM_8192E_1ANT, *PCOEX_DM_8192E_1ANT;
typedef struct _COEX_STA_8192E_1ANT{
BOOLEAN bBtLinkExist;
BOOLEAN bScoExist;
BOOLEAN bA2dpExist;
BOOLEAN bHidExist;
BOOLEAN bPanExist;
BOOLEAN bUnderLps;
BOOLEAN bUnderIps;
u4Byte highPriorityTx;
u4Byte highPriorityRx;
u4Byte lowPriorityTx;
u4Byte lowPriorityRx;
u1Byte btRssi;
u1Byte preBtRssiState;
u1Byte preWifiRssiState[4];
BOOLEAN bC2hBtInfoReqSent;
u1Byte btInfoC2h[BT_INFO_SRC_8192E_1ANT_MAX][10];
u4Byte btInfoC2hCnt[BT_INFO_SRC_8192E_1ANT_MAX];
BOOLEAN bC2hBtInquiryPage;
u1Byte btRetryCnt;
u1Byte btInfoExt;
}COEX_STA_8192E_1ANT, *PCOEX_STA_8192E_1ANT;
//===========================================
// The following is interface which will notify coex module.
//===========================================
VOID
EXhalbtc8192e1ant_InitHwConfig(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8192e1ant_InitCoexDm(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8192e1ant_IpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8192e1ant_LpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8192e1ant_ScanNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8192e1ant_ConnectNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8192e1ant_MediaStatusNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8192e1ant_SpecialPacketNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8192e1ant_BtInfoNotify(
IN PBTC_COEXIST pBtCoexist,
IN pu1Byte tmpBuf,
IN u1Byte length
);
VOID
EXhalbtc8192e1ant_StackOperationNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8192e1ant_HaltNotify(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8192e1ant_PnpNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte pnpState
);
VOID
EXhalbtc8192e1ant_Periodical(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8192e1ant_DisplayCoexInfo(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8192e1ant_DbgControl(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte opCode,
IN u1Byte opLen,
IN pu1Byte pData
);

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/*****************************************************************
* The following is for 8192E 2Ant BT Co-exist definition
*****************************************************************/
#define BT_AUTO_REPORT_ONLY_8192E_2ANT 0
#define BT_INFO_8192E_2ANT_B_FTP BIT7
#define BT_INFO_8192E_2ANT_B_A2DP BIT6
#define BT_INFO_8192E_2ANT_B_HID BIT5
#define BT_INFO_8192E_2ANT_B_SCO_BUSY BIT4
#define BT_INFO_8192E_2ANT_B_ACL_BUSY BIT3
#define BT_INFO_8192E_2ANT_B_INQ_PAGE BIT2
#define BT_INFO_8192E_2ANT_B_SCO_ESCO BIT1
#define BT_INFO_8192E_2ANT_B_CONNECTION BIT0
#define BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT 2
enum bt_info_src_8192e_2ant{
BT_INFO_SRC_8192E_2ANT_WIFI_FW = 0x0,
BT_INFO_SRC_8192E_2ANT_BT_RSP = 0x1,
BT_INFO_SRC_8192E_2ANT_BT_ACTIVE_SEND = 0x2,
BT_INFO_SRC_8192E_2ANT_MAX
};
enum bt_8192e_2ant_bt_status{
BT_8192E_2ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0,
BT_8192E_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
BT_8192E_2ANT_BT_STATUS_INQ_PAGE = 0x2,
BT_8192E_2ANT_BT_STATUS_ACL_BUSY = 0x3,
BT_8192E_2ANT_BT_STATUS_SCO_BUSY = 0x4,
BT_8192E_2ANT_BT_STATUS_ACL_SCO_BUSY = 0x5,
BT_8192E_2ANT_BT_STATUS_MAX
};
enum bt_8192e_2ant_coex_algo{
BT_8192E_2ANT_COEX_ALGO_UNDEFINED = 0x0,
BT_8192E_2ANT_COEX_ALGO_SCO = 0x1,
BT_8192E_2ANT_COEX_ALGO_SCO_PAN = 0x2,
BT_8192E_2ANT_COEX_ALGO_HID = 0x3,
BT_8192E_2ANT_COEX_ALGO_A2DP = 0x4,
BT_8192E_2ANT_COEX_ALGO_A2DP_PANHS = 0x5,
BT_8192E_2ANT_COEX_ALGO_PANEDR = 0x6,
BT_8192E_2ANT_COEX_ALGO_PANHS = 0x7,
BT_8192E_2ANT_COEX_ALGO_PANEDR_A2DP = 0x8,
BT_8192E_2ANT_COEX_ALGO_PANEDR_HID = 0x9,
BT_8192E_2ANT_COEX_ALGO_HID_A2DP_PANEDR = 0xa,
BT_8192E_2ANT_COEX_ALGO_HID_A2DP = 0xb,
BT_8192E_2ANT_COEX_ALGO_MAX = 0xc
};
struct coex_dm_8192e_2ant{
/* fw mechanism */
u8 pre_dec_bt_pwr;
u8 cur_dec_bt_pwr;
u8 pre_fw_dac_swing_lvl;
u8 cur_fw_dac_swing_lvl;
bool cur_ignore_wlan_act;
bool pre_ignore_wlan_act;
u8 pre_ps_tdma;
u8 cur_ps_tdma;
u8 ps_tdma_para[5];
u8 ps_tdma_du_adj_type;
bool reset_tdma_adjust;
bool auto_tdma_adjust;
bool pre_ps_tdma_on;
bool cur_ps_tdma_on;
bool pre_bt_auto_report;
bool cur_bt_auto_report;
/* sw mechanism */
bool pre_rf_rx_lpf_shrink;
bool cur_rf_rx_lpf_shrink;
u32 bt_rf0x1e_backup;
bool pre_low_penalty_ra;
bool cur_low_penalty_ra;
bool pre_dac_swing_on;
u32 pre_dac_swing_lvl;
bool cur_dac_swing_on;
u32 cur_dac_swing_lvl;
bool pre_adc_back_off;
bool cur_adc_back_off;
bool pre_agc_table_en;
bool cur_agc_table_en;
u32 pre_val0x6c0;
u32 cur_val0x6c0;
u32 pre_val0x6c4;
u32 cur_val0x6c4;
u32 pre_val0x6c8;
u32 cur_val0x6c8;
u8 pre_val0x6cc;
u8 cur_val0x6cc;
bool limited_dig;
u32 backup_arfr_cnt1; /* Auto Rate Fallback Retry cnt */
u32 backup_arfr_cnt2; /* Auto Rate Fallback Retry cnt */
u16 backup_retrylimit;
u8 backup_ampdu_maxtime;
/* algorithm related */
u8 pre_algorithm;
u8 cur_algorithm;
u8 bt_status;
u8 wifi_chnl_info[3];
u8 pre_sstype;
u8 cur_sstype;
u32 prera_mask;
u32 curra_mask;
u8 curra_masktype;
u8 pre_arfrtype;
u8 cur_arfrtype;
u8 pre_retrylimit_type;
u8 cur_retrylimit_type;
u8 pre_ampdutime_type;
u8 cur_ampdutime_type;
};
struct coex_sta_8192e_2ant{
bool bt_link_exist;
bool sco_exist;
bool a2dp_exist;
bool hid_exist;
bool pan_exist;
bool under_lps;
bool under_ips;
u32 high_priority_tx;
u32 high_priority_rx;
u32 low_priority_tx;
u32 low_priority_rx;
u8 bt_rssi;
u8 pre_bt_rssi_state;
u8 pre_wifi_rssi_state[4];
bool c2h_bt_info_req_sent;
u8 bt_info_c2h[BT_INFO_SRC_8192E_2ANT_MAX][10];
u32 bt_info_c2h_cnt[BT_INFO_SRC_8192E_2ANT_MAX];
bool c2h_bt_inquiry_page;
u8 bt_retry_cnt;
u8 bt_info_ext;
};
/****************************************************************
* The following is interface which will notify coex module.
****************************************************************/
void ex_halbtc8192e2ant_init_hwconfig(struct btc_coexist *btcoexist);
void ex_halbtc8192e2ant_init_coex_dm(struct btc_coexist *btcoexist);
void ex_halbtc8192e2ant_ips_notify(struct btc_coexist *btcoexist, u8 type);
void ex_halbtc8192e2ant_lps_notify(struct btc_coexist *btcoexist, u8 type);
void ex_halbtc8192e2ant_scan_notify(struct btc_coexist *btcoexist, u8 type);
void ex_halbtc8192e2ant_connect_notify(struct btc_coexist *btcoexist, u8 type);
void ex_halbtc8192e2ant_media_status_notify(struct btc_coexist *btcoexist,
u8 type);
void ex_halbtc8192e2ant_special_packet_notify(struct btc_coexist *btcoexist,
u8 type);
void ex_halbtc8192e2ant_bt_info_notify(struct btc_coexist *btcoexist,
u8 *tmpBuf,u8 length);
void ex_halbtc8192e2ant_stack_operation_notify(struct btc_coexist *btcoexist,
u8 type);
void ex_halbtc8192e2ant_halt_notify(struct btc_coexist *btcoexist);
void ex_halbtc8192e2ant_periodical(struct btc_coexist *btcoexist);
void ex_halbtc8192e2ant_display_coex_info(struct btc_coexist *btcoexist);

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//===========================================
// The following is for 8723A 2Ant BT Co-exist definition
//===========================================
#define BT_INFO_8723A_2ANT_B_FTP BIT7
#define BT_INFO_8723A_2ANT_B_A2DP BIT6
#define BT_INFO_8723A_2ANT_B_HID BIT5
#define BT_INFO_8723A_2ANT_B_SCO_BUSY BIT4
#define BT_INFO_8723A_2ANT_B_ACL_BUSY BIT3
#define BT_INFO_8723A_2ANT_B_INQ_PAGE BIT2
#define BT_INFO_8723A_2ANT_B_SCO_ESCO BIT1
#define BT_INFO_8723A_2ANT_B_CONNECTION BIT0
#define BTC_RSSI_COEX_THRESH_TOL_8723A_2ANT 2
typedef enum _BT_INFO_SRC_8723A_2ANT{
BT_INFO_SRC_8723A_2ANT_WIFI_FW = 0x0,
BT_INFO_SRC_8723A_2ANT_BT_RSP = 0x1,
BT_INFO_SRC_8723A_2ANT_BT_ACTIVE_SEND = 0x2,
BT_INFO_SRC_8723A_2ANT_MAX
}BT_INFO_SRC_8723A_2ANT,*PBT_INFO_SRC_8723A_2ANT;
typedef enum _BT_8723A_2ANT_BT_STATUS{
BT_8723A_2ANT_BT_STATUS_IDLE = 0x0,
BT_8723A_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
BT_8723A_2ANT_BT_STATUS_NON_IDLE = 0x2,
BT_8723A_2ANT_BT_STATUS_MAX
}BT_8723A_2ANT_BT_STATUS,*PBT_8723A_2ANT_BT_STATUS;
typedef enum _BT_8723A_2ANT_COEX_ALGO{
BT_8723A_2ANT_COEX_ALGO_UNDEFINED = 0x0,
BT_8723A_2ANT_COEX_ALGO_SCO = 0x1,
BT_8723A_2ANT_COEX_ALGO_HID = 0x2,
BT_8723A_2ANT_COEX_ALGO_A2DP = 0x3,
BT_8723A_2ANT_COEX_ALGO_PANEDR = 0x4,
BT_8723A_2ANT_COEX_ALGO_PANHS = 0x5,
BT_8723A_2ANT_COEX_ALGO_PANEDR_A2DP = 0x6,
BT_8723A_2ANT_COEX_ALGO_PANEDR_HID = 0x7,
BT_8723A_2ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x8,
BT_8723A_2ANT_COEX_ALGO_HID_A2DP = 0x9,
BT_8723A_2ANT_COEX_ALGO_MAX
}BT_8723A_2ANT_COEX_ALGO,*PBT_8723A_2ANT_COEX_ALGO;
typedef struct _COEX_DM_8723A_2ANT{
// fw mechanism
BOOLEAN bPreDecBtPwr;
BOOLEAN bCurDecBtPwr;
//BOOLEAN bPreBtLnaConstrain;
//BOOLEAN bCurBtLnaConstrain;
//u1Byte bPreBtPsdMode;
//u1Byte bCurBtPsdMode;
u1Byte preFwDacSwingLvl;
u1Byte curFwDacSwingLvl;
BOOLEAN bCurIgnoreWlanAct;
BOOLEAN bPreIgnoreWlanAct;
u1Byte prePsTdma;
u1Byte curPsTdma;
u1Byte psTdmaPara[5];
u1Byte psTdmaDuAdjType;
BOOLEAN bResetTdmaAdjust;
BOOLEAN bPrePsTdmaOn;
BOOLEAN bCurPsTdmaOn;
//BOOLEAN bPreBtAutoReport;
//BOOLEAN bCurBtAutoReport;
// sw mechanism
BOOLEAN bPreRfRxLpfShrink;
BOOLEAN bCurRfRxLpfShrink;
u4Byte btRf0x1eBackup;
BOOLEAN bPreLowPenaltyRa;
BOOLEAN bCurLowPenaltyRa;
BOOLEAN bPreDacSwingOn;
u4Byte preDacSwingLvl;
BOOLEAN bCurDacSwingOn;
u4Byte curDacSwingLvl;
BOOLEAN bPreAdcBackOff;
BOOLEAN bCurAdcBackOff;
BOOLEAN bPreAgcTableEn;
BOOLEAN bCurAgcTableEn;
u4Byte preVal0x6c0;
u4Byte curVal0x6c0;
u4Byte preVal0x6c8;
u4Byte curVal0x6c8;
u1Byte preVal0x6cc;
u1Byte curVal0x6cc;
BOOLEAN limited_dig;
// algorithm related
u1Byte preAlgorithm;
u1Byte curAlgorithm;
u1Byte btStatus;
u1Byte wifiChnlInfo[3];
} COEX_DM_8723A_2ANT, *PCOEX_DM_8723A_2ANT;
typedef struct _COEX_STA_8723A_2ANT{
u4Byte highPriorityTx;
u4Byte highPriorityRx;
u4Byte lowPriorityTx;
u4Byte lowPriorityRx;
u1Byte btRssi;
u1Byte preBtRssiState;
u1Byte preBtRssiState1;
u1Byte preWifiRssiState[4];
BOOLEAN bC2hBtInfoReqSent;
u1Byte btInfoC2h[BT_INFO_SRC_8723A_2ANT_MAX][10];
u4Byte btInfoC2hCnt[BT_INFO_SRC_8723A_2ANT_MAX];
BOOLEAN bC2hBtInquiryPage;
u1Byte btRetryCnt;
u1Byte btInfoExt;
BOOLEAN bHoldForStackOperation;
u1Byte bHoldPeriodCnt;
// this is for c2h hang work-around
u4Byte c2hHangDetectCnt;
}COEX_STA_8723A_2ANT, *PCOEX_STA_8723A_2ANT;
//===========================================
// The following is interface which will notify coex module.
//===========================================
VOID
EXhalbtc8723a2ant_InitHwConfig(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8723a2ant_InitCoexDm(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8723a2ant_IpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723a2ant_LpsNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723a2ant_ScanNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723a2ant_ConnectNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723a2ant_MediaStatusNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723a2ant_SpecialPacketNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723a2ant_HaltNotify(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8723a2ant_Periodical(
IN PBTC_COEXIST pBtCoexist
);
VOID
EXhalbtc8723a2ant_BtInfoNotify(
IN PBTC_COEXIST pBtCoexist,
IN pu1Byte tmpBuf,
IN u1Byte length
);
VOID
EXhalbtc8723a2ant_StackOperationNotify(
IN PBTC_COEXIST pBtCoexist,
IN u1Byte type
);
VOID
EXhalbtc8723a2ant_DisplayCoexInfo(
IN PBTC_COEXIST pBtCoexist
);

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/**********************************************************************
* The following is for 8723B 1ANT BT Co-exist definition
**********************************************************************/
#define BT_AUTO_REPORT_ONLY_8723B_1ANT 1
#define BT_INFO_8723B_1ANT_B_FTP BIT7
#define BT_INFO_8723B_1ANT_B_A2DP BIT6
#define BT_INFO_8723B_1ANT_B_HID BIT5
#define BT_INFO_8723B_1ANT_B_SCO_BUSY BIT4
#define BT_INFO_8723B_1ANT_B_ACL_BUSY BIT3
#define BT_INFO_8723B_1ANT_B_INQ_PAGE BIT2
#define BT_INFO_8723B_1ANT_B_SCO_ESCO BIT1
#define BT_INFO_8723B_1ANT_B_CONNECTION BIT0
#define BT_INFO_8723B_1ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_) \
(((_BT_INFO_EXT_&BIT0))? true:false)
#define BTC_RSSI_COEX_THRESH_TOL_8723B_1ANT 2
typedef enum _BT_INFO_SRC_8723B_1ANT{
BT_INFO_SRC_8723B_1ANT_WIFI_FW = 0x0,
BT_INFO_SRC_8723B_1ANT_BT_RSP = 0x1,
BT_INFO_SRC_8723B_1ANT_BT_ACTIVE_SEND = 0x2,
BT_INFO_SRC_8723B_1ANT_MAX
}BT_INFO_SRC_8723B_1ANT,*PBT_INFO_SRC_8723B_1ANT;
typedef enum _BT_8723B_1ANT_BT_STATUS{
BT_8723B_1ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0,
BT_8723B_1ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
BT_8723B_1ANT_BT_STATUS_INQ_PAGE = 0x2,
BT_8723B_1ANT_BT_STATUS_ACL_BUSY = 0x3,
BT_8723B_1ANT_BT_STATUS_SCO_BUSY = 0x4,
BT_8723B_1ANT_BT_STATUS_ACL_SCO_BUSY = 0x5,
BT_8723B_1ANT_BT_STATUS_MAX
}BT_8723B_1ANT_BT_STATUS,*PBT_8723B_1ANT_BT_STATUS;
typedef enum _BT_8723B_1ANT_WIFI_STATUS{
BT_8723B_1ANT_WIFI_STATUS_NON_CONNECTED_IDLE = 0x0,
BT_8723B_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN = 0x1,
BT_8723B_1ANT_WIFI_STATUS_CONNECTED_SCAN = 0x2,
BT_8723B_1ANT_WIFI_STATUS_CONNECTED_SPECIAL_PKT = 0x3,
BT_8723B_1ANT_WIFI_STATUS_CONNECTED_IDLE = 0x4,
BT_8723B_1ANT_WIFI_STATUS_CONNECTED_BUSY = 0x5,
BT_8723B_1ANT_WIFI_STATUS_MAX
}BT_8723B_1ANT_WIFI_STATUS,*PBT_8723B_1ANT_WIFI_STATUS;
typedef enum _BT_8723B_1ANT_COEX_ALGO{
BT_8723B_1ANT_COEX_ALGO_UNDEFINED = 0x0,
BT_8723B_1ANT_COEX_ALGO_SCO = 0x1,
BT_8723B_1ANT_COEX_ALGO_HID = 0x2,
BT_8723B_1ANT_COEX_ALGO_A2DP = 0x3,
BT_8723B_1ANT_COEX_ALGO_A2DP_PANHS = 0x4,
BT_8723B_1ANT_COEX_ALGO_PANEDR = 0x5,
BT_8723B_1ANT_COEX_ALGO_PANHS = 0x6,
BT_8723B_1ANT_COEX_ALGO_PANEDR_A2DP = 0x7,
BT_8723B_1ANT_COEX_ALGO_PANEDR_HID = 0x8,
BT_8723B_1ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9,
BT_8723B_1ANT_COEX_ALGO_HID_A2DP = 0xa,
BT_8723B_1ANT_COEX_ALGO_MAX = 0xb,
}BT_8723B_1ANT_COEX_ALGO,*PBT_8723B_1ANT_COEX_ALGO;
struct coex_dm_8723b_1ant{
/* fw mechanism */
bool pre_dec_bt_pwr;
bool cur_dec_bt_pwr;
u8 pre_fw_dac_swing_lvl;
u8 cur_fw_dac_swing_lvl;
bool cur_ignore_wlan_act;
bool pre_ignore_wlan_act;
u8 pre_ps_tdma;
u8 cur_ps_tdma;
u8 ps_tdma_para[5];
u8 ps_tdma_du_adj_type;
bool auto_tdma_adjust;
bool pre_ps_tdma_on;
bool cur_ps_tdma_on;
bool pre_bt_auto_report;
bool cur_bt_auto_report;
u8 pre_lps;
u8 cur_lps;
u8 pre_rpwm;
u8 cur_rpwm;
/* sw mechanism */
bool pre_rf_rx_lpf_shrink;
bool cur_rf_rx_lpf_shrink;
u32 bt_rf0x1e_backup;
bool pre_low_penalty_ra;
bool cur_low_penalty_ra;
bool pre_dac_swing_on;
u32 pre_dac_swing_lvl;
bool cur_dac_swing_on;
u32 cur_dac_swing_lvl;
bool pre_adc_backoff;
bool cur_adc_backoff;
bool pre_agc_table_en;
bool cur_agc_table_en;
u32 pre_val0x6c0;
u32 cur_val0x6c0;
u32 pre_val0x6c4;
u32 cur_val0x6c4;
u32 pre_val0x6c8;
u32 cur_val0x6c8;
u8 pre_val0x6cc;
u8 cur_val0x6cc;
bool limited_dig;
u32 backup_arfr_cnt1; /* Auto Rate Fallback Retry cnt */
u32 backup_arfr_cnt2; /* Auto Rate Fallback Retry cnt */
u16 backup_retry_limit;
u8 backup_ampdu_max_time;
/* algorithm related */
u8 pre_algorithm;
u8 cur_algorithm;
u8 bt_status;
u8 wifi_chnl_info[3];
u32 prera_mask;
u32 curra_mask;
u8 pre_arfr_type;
u8 cur_arfr_type;
u8 pre_retry_limit_type;
u8 cur_retry_limit_type;
u8 pre_ampdu_time_type;
u8 cur_ampdu_time_type;
u8 error_condition;
};
struct coex_sta_8723b_1ant{
bool bt_link_exist;
bool sco_exist;
bool a2dp_exist;
bool hid_exist;
bool pan_exist;
bool under_lps;
bool under_ips;
u32 special_pkt_period_cnt;
u32 high_priority_tx;
u32 high_priority_rx;
u32 low_priority_tx;
u32 low_priority_rx;
u8 bt_rssi;
u8 pre_bt_rssi_state;
u8 pre_wifi_rssi_state[4];
bool c2h_bt_info_req_sent;
u8 bt_info_c2h[BT_INFO_SRC_8723B_1ANT_MAX][10];
u32 bt_info_c2h_cnt[BT_INFO_SRC_8723B_1ANT_MAX];
bool c2h_bt_inquiry_page;
u8 bt_retry_cnt;
u8 bt_info_ext;
};
/*************************************************************************
* The following is interface which will notify coex module.
*************************************************************************/
void ex_halbtc8723b1ant_init_hwconfig(struct btc_coexist *btcoexist);
void ex_halbtc8723b1ant_init_coex_dm(struct btc_coexist *btcoexist);
void ex_halbtc8723b1ant_ips_notify(struct btc_coexist *btcoexist, u8 type);
void ex_halbtc8723b1ant_lps_notify(struct btc_coexist *btcoexist, u8 type);
void ex_halbtc8723b1ant_scan_notify(struct btc_coexist *btcoexist, u8 type);
void ex_halbtc8723b1ant_connect_notify(struct btc_coexist *btcoexist, u8 type);
void ex_halbtc8723b1ant_media_status_notify(struct btc_coexist *btcoexist,
u8 type);
void ex_halbtc8723b1ant_special_packet_notify(struct btc_coexist *btcoexist,
u8 type);
void ex_halbtc8723b1ant_bt_info_notify(struct btc_coexist *btcoexist,
u8 *tmpbuf, u8 length);
void ex_halbtc8723b1ant_halt_notify(struct btc_coexist *btcoexist);
void ex_halbtc8723b1ant_pnp_notify(struct btc_coexist *btcoexist, u8 pnpState);
void ex_halbtc8723b1ant_periodical(struct btc_coexist *btcoexist);
void ex_halbtc8723b1ant_display_coex_info(struct btc_coexist *btcoexist);

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/************************************************************************
* The following is for 8723B 2Ant BT Co-exist definition
************************************************************************/
#define BT_AUTO_REPORT_ONLY_8723B_2ANT 1
#define BT_INFO_8723B_2ANT_B_FTP BIT7
#define BT_INFO_8723B_2ANT_B_A2DP BIT6
#define BT_INFO_8723B_2ANT_B_HID BIT5
#define BT_INFO_8723B_2ANT_B_SCO_BUSY BIT4
#define BT_INFO_8723B_2ANT_B_ACL_BUSY BIT3
#define BT_INFO_8723B_2ANT_B_INQ_PAGE BIT2
#define BT_INFO_8723B_2ANT_B_SCO_ESCO BIT1
#define BT_INFO_8723B_2ANT_B_CONNECTION BIT0
#define BTC_RSSI_COEX_THRESH_TOL_8723B_2ANT 2
typedef enum _BT_INFO_SRC_8723B_2ANT{
BT_INFO_SRC_8723B_2ANT_WIFI_FW = 0x0,
BT_INFO_SRC_8723B_2ANT_BT_RSP = 0x1,
BT_INFO_SRC_8723B_2ANT_BT_ACTIVE_SEND = 0x2,
BT_INFO_SRC_8723B_2ANT_MAX
}BT_INFO_SRC_8723B_2ANT,*PBT_INFO_SRC_8723B_2ANT;
typedef enum _BT_8723B_2ANT_BT_STATUS{
BT_8723B_2ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0,
BT_8723B_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1,
BT_8723B_2ANT_BT_STATUS_INQ_PAGE = 0x2,
BT_8723B_2ANT_BT_STATUS_ACL_BUSY = 0x3,
BT_8723B_2ANT_BT_STATUS_SCO_BUSY = 0x4,
BT_8723B_2ANT_BT_STATUS_ACL_SCO_BUSY = 0x5,
BT_8723B_2ANT_BT_STATUS_MAX
}BT_8723B_2ANT_BT_STATUS,*PBT_8723B_2ANT_BT_STATUS;
typedef enum _BT_8723B_2ANT_COEX_ALGO{
BT_8723B_2ANT_COEX_ALGO_UNDEFINED = 0x0,
BT_8723B_2ANT_COEX_ALGO_SCO = 0x1,
BT_8723B_2ANT_COEX_ALGO_HID = 0x2,
BT_8723B_2ANT_COEX_ALGO_A2DP = 0x3,
BT_8723B_2ANT_COEX_ALGO_A2DP_PANHS = 0x4,
BT_8723B_2ANT_COEX_ALGO_PANEDR = 0x5,
BT_8723B_2ANT_COEX_ALGO_PANHS = 0x6,
BT_8723B_2ANT_COEX_ALGO_PANEDR_A2DP = 0x7,
BT_8723B_2ANT_COEX_ALGO_PANEDR_HID = 0x8,
BT_8723B_2ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9,
BT_8723B_2ANT_COEX_ALGO_HID_A2DP = 0xa,
BT_8723B_2ANT_COEX_ALGO_MAX = 0xb,
}BT_8723B_2ANT_COEX_ALGO,*PBT_8723B_2ANT_COEX_ALGO;
struct coex_dm_8723b_2ant{
/* fw mechanism */
bool pre_dec_bt_pwr;
bool cur_dec_bt_pwr;
u8 pre_fw_dac_swing_lvl;
u8 cur_fw_dac_swing_lvl;
bool cur_ignore_wlan_act;
bool pre_ignore_wlan_act;
u8 pre_ps_tdma;
u8 cur_ps_tdma;
u8 ps_tdma_para[5];
u8 ps_tdma_du_adj_type;
bool reset_tdma_adjust;
bool auto_tdma_adjust;
bool pre_ps_tdma_on;
bool cur_ps_tdma_on;
bool pre_bt_auto_report;
bool cur_bt_auto_report;
/* sw mechanism */
bool pre_rf_rx_lpf_shrink;
bool cur_rf_rx_lpf_shrink;
u32 bt_rf0x1e_backup;
bool pre_low_penalty_ra;
bool cur_low_penalty_ra;
bool pre_dac_swing_on;
u32 pre_dac_swing_lvl;
bool cur_dac_swing_on;
u32 cur_dac_swing_lvl;
bool pre_adc_back_off;
bool cur_adc_back_off;
bool pre_agc_table_en;
bool cur_agc_table_en;
u32 pre_val0x6c0;
u32 cur_val0x6c0;
u32 pre_val0x6c4;
u32 cur_val0x6c4;
u32 pre_val0x6c8;
u32 cur_val0x6c8;
u8 pre_val0x6cc;
u8 cur_val0x6cc;
bool limited_dig;
/* algorithm related */
u8 pre_algorithm;
u8 cur_algorithm;
u8 bt_status;
u8 wifi_chnl_info[3];
bool need_recover_0x948;
u16 backup_0x948;
};
struct coex_sta_8723b_2ant{
bool bt_link_exist;
bool sco_exist;
bool a2dp_exist;
bool hid_exist;
bool pan_exist;
bool under_lps;
bool under_ips;
u32 high_priority_tx;
u32 high_priority_rx;
u32 low_priority_tx;
u32 low_priority_rx;
u8 bt_rssi;
u8 pre_bt_rssi_state;
u8 pre_wifi_rssi_state[4];
bool c2h_bt_info_req_sent;
u8 bt_info_c2h[BT_INFO_SRC_8723B_2ANT_MAX][10];
u32 bt_info_c2h_cnt[BT_INFO_SRC_8723B_2ANT_MAX];
bool c2h_bt_inquiry_page;
u8 bt_retry_cnt;
u8 bt_info_ext;
};
/*********************************************************************
* The following is interface which will notify coex module.
*********************************************************************/
void ex_halbtc8723b2ant_init_hwconfig(struct btc_coexist *btcoexist);
void ex_halbtc8723b2ant_init_coex_dm(struct btc_coexist *btcoexist);
void ex_halbtc8723b2ant_ips_notify(struct btc_coexist *btcoexist, u8 type);
void ex_halbtc8723b2ant_lps_notify(struct btc_coexist *btcoexist, u8 type);
void ex_halbtc8723b2ant_scan_notify(struct btc_coexist *btcoexist, u8 type);
void ex_halbtc8723b2ant_connect_notify(struct btc_coexist *btcoexist, u8 type);
void ex_halbtc8723b2ant_media_status_notify(struct btc_coexist *btcoexist,
u8 type);
void ex_halbtc8723b2ant_special_packet_notify(struct btc_coexist *btcoexist,
u8 type);
void ex_halbtc8723b2ant_bt_info_notify(struct btc_coexist *btcoexist,
u8 *tmpbuf, u8 length);
void ex_halbtc8723b2ant_halt_notify(struct btc_coexist *btcoexist);
void ex_halbtc8723b2ant_periodical(struct btc_coexist * btcoexist);
void ex_halbtc8723b2ant_display_coex_info(struct btc_coexist *btcoexist);

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#ifndef __HALBTC_OUT_SRC_H__
#define __HALBTC_OUT_SRC_H__
#include "../wifi.h"
#define NORMAL_EXEC false
#define FORCE_EXEC true
#define BTC_RF_A RF90_PATH_A
#define BTC_RF_B RF90_PATH_B
#define BTC_RF_C RF90_PATH_C
#define BTC_RF_D RF90_PATH_D
#define BTC_SMSP SINGLEMAC_SINGLEPHY
#define BTC_DMDP DUALMAC_DUALPHY
#define BTC_DMSP DUALMAC_SINGLEPHY
#define BTC_MP_UNKNOWN 0xff
#define IN
#define OUT
#define BT_TMP_BUF_SIZE 100
#define BT_COEX_ANT_TYPE_PG 0
#define BT_COEX_ANT_TYPE_ANTDIV 1
#define BT_COEX_ANT_TYPE_DETECTED 2
#define BTC_MIMO_PS_STATIC 0
#define BTC_MIMO_PS_DYNAMIC 1
#define BTC_RATE_DISABLE 0
#define BTC_RATE_ENABLE 1
/* single Antenna definition */
#define BTC_ANT_PATH_WIFI 0
#define BTC_ANT_PATH_BT 1
#define BTC_ANT_PATH_PTA 2
/* dual Antenna definition */
#define BTC_ANT_WIFI_AT_MAIN 0
#define BTC_ANT_WIFI_AT_AUX 1
/* coupler Antenna definition */
#define BTC_ANT_WIFI_AT_CPL_MAIN 0
#define BTC_ANT_WIFI_AT_CPL_AUX 1
enum btc_chip_interface{
BTC_INTF_UNKNOWN = 0,
BTC_INTF_PCI = 1,
BTC_INTF_USB = 2,
BTC_INTF_SDIO = 3,
BTC_INTF_GSPI = 4,
BTC_INTF_MAX
};
enum btc_chip_type{
BTC_CHIP_UNDEF = 0,
BTC_CHIP_CSR_BC4 = 1,
BTC_CHIP_CSR_BC8 = 2,
BTC_CHIP_RTL8723A = 3,
BTC_CHIP_RTL8821 = 4,
BTC_CHIP_RTL8723B = 5,
BTC_CHIP_MAX
};
enum btc_msg_type{
BTC_MSG_INTERFACE = 0x0,
BTC_MSG_ALGORITHM = 0x1,
BTC_MSG_MAX
};
extern u32 btc_dbg_type[];
/* following is for BTC_MSG_INTERFACE */
#define INTF_INIT BIT0
#define INTF_NOTIFY BIT2
/* following is for BTC_ALGORITHM */
#define ALGO_BT_RSSI_STATE BIT0
#define ALGO_WIFI_RSSI_STATE BIT1
#define ALGO_BT_MONITOR BIT2
#define ALGO_TRACE BIT3
#define ALGO_TRACE_FW BIT4
#define ALGO_TRACE_FW_DETAIL BIT5
#define ALGO_TRACE_FW_EXEC BIT6
#define ALGO_TRACE_SW BIT7
#define ALGO_TRACE_SW_DETAIL BIT8
#define ALGO_TRACE_SW_EXEC BIT9
#define CL_SPRINTF snprintf
#define CL_PRINTF printk
#define BTC_PRINT(dbgtype, dbgflag, printstr, ...) \
do { \
if (unlikely(btc_dbg_type[dbgtype] & dbgflag)) {\
printk(printstr, ##__VA_ARGS__); \
} \
} while(0)
#define BTC_PRINT_F(dbgtype, dbgflag, printstr, ...) \
do { \
if (unlikely(btc_dbg_type[dbgtype] & dbgflag)) {\
printk(KERN_DEBUG "%s: ", __func__); \
printk(printstr, ##__VA_ARGS__); \
} \
} while(0)
#define BTC_PRINT_ADDR(dbgtype, dbgflag, printstr, _ptr) \
do { \
if(unlikely(btc_dbg_type[dbgtype] & dbgflag)) { \
int __i; \
u8* __ptr = (u8*)_Ptr; \
printk printstr; \
for( __i = 0; __i < 6; __i++ ) \
printk("%02X%s", __ptr[__i], (__i==5)?"":"-");\
printk(KERN_DEBUG "\n"); \
}\
} while(0)
#define BTC_PRINT_DATA(dbgtype, dbgflag, _titlestring, _hexdata, _hexdatalen) \
do { \
if(unlikely(btc_dbg_type[dbgtype] & dbgflag) ) { \
int __i; \
u8 *__ptr = (u8*)_hexdata; \
printk(_titlestring); \
for( __i = 0; __i < (int)_hexdatalen; __i++ ) { \
printk("%02X%s", __ptr[__i], (((__i + 1) % 4) \
== 0)?" ":" ");\
if (((__i + 1) % 16) == 0) \
printk("\n"); \
} \
printk(KERN_DEBUG "\n"); \
} \
} while(0)
#define BTC_RSSI_HIGH(_rssi_) \
((_rssi_==BTC_RSSI_STATE_HIGH || _rssi_==BTC_RSSI_STATE_STAY_HIGH) ? \
true : false)
#define BTC_RSSI_MEDIUM(_rssi_) \
((_rssi_==BTC_RSSI_STATE_MEDIUM || _rssi_==BTC_RSSI_STATE_STAY_MEDIUM) \
? true : false)
#define BTC_RSSI_LOW(_rssi_) \
((_rssi_==BTC_RSSI_STATE_LOW || _rssi_==BTC_RSSI_STATE_STAY_LOW) ? \
true : false)
enum btc_power_save_type {
BTC_PS_WIFI_NATIVE = 0,
BTC_PS_LPS_ON = 1,
BTC_PS_LPS_OFF = 2,
BTC_PS_LPS_MAX
};
struct btc_board_info {
/* The following is some board information */
u8 bt_chip_type;
u8 pg_ant_num; /* pg ant number */
u8 btdm_ant_num; /* ant number for btdm */
u8 btdm_ant_pos;
bool bt_exist;
};
enum btc_dbg_opcode{
BTC_DBG_SET_COEX_NORMAL = 0x0,
BTC_DBG_SET_COEX_WIFI_ONLY = 0x1,
BTC_DBG_SET_COEX_BT_ONLY = 0x2,
BTC_DBG_MAX
};
enum btc_rssi_state{
BTC_RSSI_STATE_HIGH = 0x0,
BTC_RSSI_STATE_MEDIUM = 0x1,
BTC_RSSI_STATE_LOW = 0x2,
BTC_RSSI_STATE_STAY_HIGH = 0x3,
BTC_RSSI_STATE_STAY_MEDIUM = 0x4,
BTC_RSSI_STATE_STAY_LOW = 0x5,
BTC_RSSI_MAX
};
enum btc_wifi_role{
BTC_ROLE_STATION = 0x0,
BTC_ROLE_AP = 0x1,
BTC_ROLE_IBSS = 0x2,
BTC_ROLE_HS_MODE = 0x3,
BTC_ROLE_MAX
};
enum btc_wifi_bw_mode{
BTC_WIFI_BW_LEGACY = 0x0,
BTC_WIFI_BW_HT20 = 0x1,
BTC_WIFI_BW_HT40 = 0x2,
BTC_WIFI_BW_MAX
};
enum btc_wifi_traffic_dir{
BTC_WIFI_TRAFFIC_TX = 0x0,
BTC_WIFI_TRAFFIC_RX = 0x1,
BTC_WIFI_TRAFFIC_MAX
};
enum btc_wifi_pnp{
BTC_WIFI_PNP_WAKE_UP = 0x0,
BTC_WIFI_PNP_SLEEP = 0x1,
BTC_WIFI_PNP_MAX
};
enum btc_get_type{
/* type bool */
BTC_GET_BL_HS_OPERATION,
BTC_GET_BL_HS_CONNECTING,
BTC_GET_BL_WIFI_CONNECTED,
BTC_GET_BL_WIFI_BUSY,
BTC_GET_BL_WIFI_SCAN,
BTC_GET_BL_WIFI_LINK,
BTC_GET_BL_WIFI_DHCP,
BTC_GET_BL_WIFI_SOFTAP_IDLE,
BTC_GET_BL_WIFI_SOFTAP_LINKING,
BTC_GET_BL_WIFI_IN_EARLY_SUSPEND,
BTC_GET_BL_WIFI_ROAM,
BTC_GET_BL_WIFI_4_WAY_PROGRESS,
BTC_GET_BL_WIFI_UNDER_5G,
BTC_GET_BL_WIFI_AP_MODE_ENABLE,
BTC_GET_BL_WIFI_ENABLE_ENCRYPTION,
BTC_GET_BL_WIFI_UNDER_B_MODE,
BTC_GET_BL_EXT_SWITCH,
/* type s4Byte */
BTC_GET_S4_WIFI_RSSI,
BTC_GET_S4_HS_RSSI,
/* type u32 */
BTC_GET_U4_WIFI_BW,
BTC_GET_U4_WIFI_TRAFFIC_DIRECTION,
BTC_GET_U4_WIFI_FW_VER,
BTC_GET_U4_BT_PATCH_VER,
/* type u1Byte */
BTC_GET_U1_WIFI_DOT11_CHNL,
BTC_GET_U1_WIFI_CENTRAL_CHNL,
BTC_GET_U1_WIFI_HS_CHNL,
BTC_GET_U1_MAC_PHY_MODE,
BTC_GET_U1_AP_NUM,
/* for 1Ant */
BTC_GET_U1_LPS_MODE,
BTC_GET_BL_BT_SCO_BUSY,
/* for test mode */
BTC_GET_DRIVER_TEST_CFG,
#if 0
BTC_GET_U1_LPS,
BTC_GET_U1_RPWM,
#endif
BTC_GET_MAX
};
enum btc_set_type{
/* type bool */
BTC_SET_BL_BT_DISABLE,
BTC_SET_BL_BT_TRAFFIC_BUSY,
BTC_SET_BL_BT_LIMITED_DIG,
BTC_SET_BL_FORCE_TO_ROAM,
BTC_SET_BL_TO_REJ_AP_AGG_PKT,
BTC_SET_BL_BT_CTRL_AGG_SIZE,
BTC_SET_BL_INC_SCAN_DEV_NUM,
/* type u1Byte */
BTC_SET_U1_RSSI_ADJ_VAL_FOR_AGC_TABLE_ON,
BTC_SET_U1_RSSI_ADJ_VAL_FOR_1ANT_COEX_TYPE,
BTC_SET_UI_SCAN_SIG_COMPENSATION,
BTC_SET_U1_AGG_BUF_SIZE,
/* type trigger some action */
BTC_SET_ACT_GET_BT_RSSI,
BTC_SET_ACT_AGGREGATE_CTRL,
/********* for 1Ant **********/
/* type bool */
BTC_SET_BL_BT_SCO_BUSY,
/* type u1Byte */
BTC_SET_U1_1ANT_LPS,
BTC_SET_U1_1ANT_RPWM,
/* type trigger some action */
BTC_SET_ACT_LEAVE_LPS,
BTC_SET_ACT_ENTER_LPS,
BTC_SET_ACT_NORMAL_LPS,
BTC_SET_ACT_INC_FORCE_EXEC_PWR_CMD_CNT,
BTC_SET_ACT_DISABLE_LOW_POWER,
BTC_SET_ACT_UPDATE_ra_mask,
BTC_SET_ACT_SEND_MIMO_PS,
/* BT Coex related */
BTC_SET_ACT_CTRL_BT_INFO,
BTC_SET_ACT_CTRL_BT_COEX,
/***************************/
BTC_SET_MAX
};
enum btc_dbg_disp_type{
BTC_DBG_DISP_COEX_STATISTICS = 0x0,
BTC_DBG_DISP_BT_LINK_INFO = 0x1,
BTC_DBG_DISP_BT_FW_VER = 0x2,
BTC_DBG_DISP_FW_PWR_MODE_CMD = 0x3,
BTC_DBG_DISP_MAX
};
enum btc_notify_type_ips{
BTC_IPS_LEAVE = 0x0,
BTC_IPS_ENTER = 0x1,
BTC_IPS_MAX
};
enum btc_notify_type_lps{
BTC_LPS_DISABLE = 0x0,
BTC_LPS_ENABLE = 0x1,
BTC_LPS_MAX
};
enum btc_notify_type_scan{
BTC_SCAN_FINISH = 0x0,
BTC_SCAN_START = 0x1,
BTC_SCAN_MAX
};
enum btc_notify_type_associate{
BTC_ASSOCIATE_FINISH = 0x0,
BTC_ASSOCIATE_START = 0x1,
BTC_ASSOCIATE_MAX
};
enum btc_notify_type_media_status{
BTC_MEDIA_DISCONNECT = 0x0,
BTC_MEDIA_CONNECT = 0x1,
BTC_MEDIA_MAX
};
enum btc_notify_type_special_packet{
BTC_PACKET_UNKNOWN = 0x0,
BTC_PACKET_DHCP = 0x1,
BTC_PACKET_ARP = 0x2,
BTC_PACKET_EAPOL = 0x3,
BTC_PACKET_MAX
};
enum btc_notify_type_stack_operation{
BTC_STACK_OP_NONE = 0x0,
BTC_STACK_OP_INQ_PAGE_PAIR_START = 0x1,
BTC_STACK_OP_INQ_PAGE_PAIR_FINISH = 0x2,
BTC_STACK_OP_MAX
};
typedef u8 (*bfp_btc_r1)(void *btc_context, u32 reg_addr);
typedef u16 (*bfp_btc_r2)(void *btc_context, u32 reg_addr);
typedef u32 (*bfp_btc_r4)(void *btc_context, u32 reg_addr);
typedef void (*bfp_btc_w1)(void *btc_context, u32 reg_addr, u8 data);
typedef void (*bfp_btc_w1_bit_mak)(void *btc_context, u32 reg_addr,
u8 bit_mask, u8 data1b);
typedef void (*bfp_btc_w2)(void *btc_context, u32 reg_addr, u16 data);
typedef void (*bfp_btc_w4)(void *btc_context, u32 reg_addr, u32 data);
typedef void (*bfp_btc_wr_1byte_bit_mask)(void *btc_context, u32 reg_addr,
u8 bit_mask, u8 data);
typedef void (*bfp_btc_set_bb_reg)(void *btc_context, u32 reg_addr,
u32 bit_mask, u32 data);
typedef u32 (*bfp_btc_get_bb_reg)(void *btc_context, u32 reg_addr,
u32 bit_mask);
typedef void (*bfp_btc_set_rf_reg)(void *btc_context, u8 rf_path, u32 reg_addr,
u32 bit_mask, u32 data);
typedef u32 (*bfp_btc_get_rf_reg)(void *btc_context, u8 rf_path,
u32 reg_addr, u32 bit_mask);
typedef void (*bfp_btc_fill_h2c)(void *btc_context, u8 element_id,
u32 cmd_len, u8 *cmd_buffer);
typedef bool (*bfp_btc_get)(void *btcoexist, u8 get_type, void *out_buf);
typedef bool (*bfp_btc_set)(void *btcoexist, u8 set_type, void *in_buf);
typedef void (*bfp_btc_disp_dbg_msg)(void *btcoexist, u8 disp_type);
struct btc_bt_info {
bool bt_disabled;
u8 rssi_adjust_for_agc_table_on;
u8 rssi_adjust_for_1ant_coex_type;
bool bt_busy;
u8 agg_buf_size;
bool limited_dig;
bool reject_agg_pkt;
bool b_bt_ctrl_buf_size;
bool increase_scan_dev_num;
u16 bt_hci_ver;
u16 bt_real_fw_ver;
u8 bt_fw_ver;
/* the following is for 1Ant solution */
bool bt_ctrl_lps;
bool bt_pwr_save_mode;
bool bt_lps_on;
bool force_to_roam;
u8 force_exec_pwr_cmd_cnt;
u8 lps_1ant;
u8 rpwm_1ant;
u32 ra_mask;
};
struct btc_stack_info {
bool profile_notified;
u16 hci_version; /* stack hci version */
u8 num_of_link;
bool bt_link_exist;
bool sco_exist;
bool acl_exist;
bool a2dp_exist;
bool hid_exist;
u8 num_of_hid;
bool pan_exist;
bool unknown_acl_exist;
char min_bt_rssi;
};
struct btc_statistics {
u32 cnt_bind;
u32 cnt_init_hw_config;
u32 cnt_init_coex_dm;
u32 cnt_ips_notify;
u32 cnt_lps_notify;
u32 cnt_scan_notify;
u32 cnt_connect_notify;
u32 cnt_media_status_notify;
u32 cnt_special_packet_notify;
u32 cnt_bt_info_notify;
u32 cnt_periodical;
u32 cnt_stack_operation_notify;
u32 cnt_dbg_ctrl;
};
struct btc_bt_link_info {
bool bt_link_exist;
bool sco_exist;
bool sco_only;
bool a2dp_exist;
bool a2dp_only;
bool hid_exist;
bool hid_only;
bool pan_exist;
bool pan_only;
};
enum btc_antenna_pos {
BTC_ANTENNA_AT_MAIN_PORT = 0x1,
BTC_ANTENNA_AT_AUX_PORT = 0x2,
};
struct btc_coexist {
/* make sure only one adapter can bind the data context */
bool binded;
/* default adapter */
void *adapter;
struct btc_board_info board_info;
/* some bt info referenced by non-bt module */
struct btc_bt_info bt_info;
struct btc_stack_info stack_info;
enum btc_chip_interface chip_interface;
struct btc_bt_link_info bt_link_info;
bool initilized;
bool stop_coex_dm;
bool manual_control;
u8 *cli_buf;
struct btc_statistics statistics;
u8 pwr_mode_val[10];
/* function pointers
* io related */
bfp_btc_r1 btc_read_1byte;
bfp_btc_w1 btc_write_1byte;
bfp_btc_w1_bit_mak btc_write_1byte_bitmask;
bfp_btc_r2 btc_read_2byte;
bfp_btc_w2 btc_write_2byte;
bfp_btc_r4 btc_read_4byte;
bfp_btc_w4 btc_write_4byte;
bfp_btc_set_bb_reg btc_set_bb_reg;
bfp_btc_get_bb_reg btc_get_bb_reg;
bfp_btc_set_rf_reg btc_set_rf_reg;
bfp_btc_get_rf_reg btc_get_rf_reg;
bfp_btc_fill_h2c btc_fill_h2c;
bfp_btc_disp_dbg_msg btc_disp_dbg_msg;
bfp_btc_get btc_get;
bfp_btc_set btc_set;
};
bool halbtc_is_wifi_uplink(struct rtl_priv *adapter);
extern struct btc_coexist gl_bt_coexist;
bool exhalbtc_initlize_variables(struct rtl_priv* adapter);
void exhalbtc_init_hw_config(struct btc_coexist *btcoexist);
void exhalbtc_init_coex_dm(struct btc_coexist *btcoexist);
void exhalbtc_ips_notify(struct btc_coexist *btcoexist, u8 type);
void exhalbtc_lps_notify(struct btc_coexist *btcoexist, u8 type);
void exhalbtc_scan_notify(struct btc_coexist *btcoexist, u8 type);
void exhalbtc_connect_notify(struct btc_coexist *btcoexist, u8 action);
void exhalbtc_mediastatus_notify(struct btc_coexist *btcoexist,
enum rt_media_status media_status);
void exhalbtc_special_packet_notify(struct btc_coexist *btcoexist, u8 pkt_type);
void exhalbtc_bt_info_notify(struct btc_coexist *btcoexist, u8 *tmp_buf,
u8 length);
void exhalbtc_stack_operation_notify(struct btc_coexist *btcoexist, u8 type);
void exhalbtc_halt_notify(struct btc_coexist *btcoexist);
void exhalbtc_pnp_notify(struct btc_coexist *btcoexist, u8 pnp_state);
void exhalbtc_periodical(struct btc_coexist *btcoexist);
void exhalbtc_dbg_control(struct btc_coexist *btcoexist, u8 code, u8 len,
u8 *data);
void exhalbtc_stack_update_profile_info(void);
void exhalbtc_set_hci_version(u16 hci_version);
void exhalbtc_set_bt_patch_version(u16 bt_hci_version, u16 bt_patch_version);
void exhalbtc_update_min_bt_rssi(char bt_rssi);
void exhalbtc_set_bt_exist(bool bt_exist);
void exhalbtc_set_chip_type(u8 chip_type);
void exhalbtc_set_ant_num(u8 type, u8 ant_num);
void exhalbtc_display_bt_coex_info(struct btc_coexist *btcoexist);
void exhalbtc_signal_compensation(struct btc_coexist *btcoexist,
u8 *rssi_wifi, u8 *rssi_bt);
void exhalbtc_lps_leave(struct btc_coexist *btcoexist);
void exhalbtc_low_wifi_traffic_notify(struct btc_coexist *btcoexist);
#endif

236
drivers/staging/rtl8821ae/btcoexist/rtl_btc.c Normal file
View File

@ -0,0 +1,236 @@
/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include <linux/vmalloc.h>
#include <linux/module.h>
#include "rtl_btc.h"
#include "halbt_precomp.h"
struct rtl_btc_ops rtl_btc_operation ={
.btc_init_variables = rtl_btc_init_variables,
.btc_init_hal_vars = rtl_btc_init_hal_vars,
.btc_init_hw_config = rtl_btc_init_hw_config,
.btc_ips_notify = rtl_btc_ips_notify,
.btc_scan_notify = rtl_btc_scan_notify,
.btc_connect_notify = rtl_btc_connect_notify,
.btc_mediastatus_notify = rtl_btc_mediastatus_notify,
.btc_periodical = rtl_btc_periodical,
.btc_halt_notify = rtl_btc_halt_notify,
.btc_btinfo_notify = rtl_btc_btinfo_notify,
.btc_is_limited_dig = rtl_btc_is_limited_dig,
.btc_is_disable_edca_turbo = rtl_btc_is_disable_edca_turbo,
.btc_is_bt_disabled = rtl_btc_is_bt_disabled,
};
void rtl_btc_init_variables(struct rtl_priv *rtlpriv)
{
exhalbtc_initlize_variables(rtlpriv);
}
void rtl_btc_init_hal_vars(struct rtl_priv *rtlpriv)
{
u8 ant_num;
u8 bt_exist;
u8 bt_type;
ant_num = rtl_get_hwpg_ant_num(rtlpriv);
RT_TRACE(COMP_INIT, DBG_DMESG, ("%s, antNum is %d\n", __func__, ant_num));
bt_exist = rtl_get_hwpg_bt_exist(rtlpriv);
RT_TRACE(COMP_INIT, DBG_DMESG, ("%s, bt_exist is %d\n", __func__, bt_exist));
exhalbtc_set_bt_exist(bt_exist);
bt_type = rtl_get_hwpg_bt_type(rtlpriv);
RT_TRACE(COMP_INIT, DBG_DMESG, ("%s, bt_type is %d\n", __func__, bt_type));
exhalbtc_set_chip_type(bt_type);
exhalbtc_set_ant_num(BT_COEX_ANT_TYPE_PG, ant_num);
}
void rtl_btc_init_hw_config(struct rtl_priv *rtlpriv)
{
exhalbtc_init_hw_config(&gl_bt_coexist);
exhalbtc_init_coex_dm(&gl_bt_coexist);
}
void rtl_btc_ips_notify(struct rtl_priv *rtlpriv, u8 type)
{
exhalbtc_ips_notify(&gl_bt_coexist, type);
}
void rtl_btc_scan_notify(struct rtl_priv *rtlpriv, u8 scantype)
{
exhalbtc_scan_notify(&gl_bt_coexist, scantype);
}
void rtl_btc_connect_notify(struct rtl_priv *rtlpriv, u8 action)
{
exhalbtc_connect_notify(&gl_bt_coexist, action);
}
void rtl_btc_mediastatus_notify(struct rtl_priv *rtlpriv, enum rt_media_status mstatus)
{
exhalbtc_mediastatus_notify(&gl_bt_coexist, mstatus);
}
void rtl_btc_periodical(struct rtl_priv *rtlpriv)
{
// rtl_bt_dm_monitor();
exhalbtc_periodical(&gl_bt_coexist);
}
void rtl_btc_halt_notify(void)
{
exhalbtc_halt_notify(&gl_bt_coexist);
}
void rtl_btc_btinfo_notify(struct rtl_priv *rtlpriv, u8 * tmp_buf, u8 length)
{
exhalbtc_bt_info_notify(&gl_bt_coexist, tmp_buf, length);
}
bool rtl_btc_is_limited_dig(struct rtl_priv *rtlpriv)
{
return gl_bt_coexist.bt_info.limited_dig;
}
bool rtl_btc_is_disable_edca_turbo(struct rtl_priv *rtlpriv)
{
bool bt_change_edca = false;
u32 cur_edca_val;
u32 edca_bt_hs_uplink = 0x5ea42b, edca_bt_hs_downlink = 0x5ea42b;
u32 edca_hs;
u32 edca_addr = 0x504;
cur_edca_val = rtl_read_dword(rtlpriv, edca_addr);
if (halbtc_is_wifi_uplink(rtlpriv)){
if (cur_edca_val != edca_bt_hs_uplink){
edca_hs = edca_bt_hs_uplink;
bt_change_edca = true;
}
}else{
if (cur_edca_val != edca_bt_hs_downlink){
edca_hs = edca_bt_hs_downlink;
bt_change_edca = true;
}
}
if(bt_change_edca)
rtl_write_dword(rtlpriv, edca_addr, edca_hs);
return true;
}
bool rtl_btc_is_bt_disabled(struct rtl_priv *rtlpriv)
{
if (gl_bt_coexist.bt_info.bt_disabled)
return true;
else
return false;
}
struct rtl_btc_ops *rtl_btc_get_ops_pointer(void)
{
return &rtl_btc_operation;
}
//EXPORT_SYMBOL(rtl_btc_get_ops_pointer);
u8 rtl_get_hwpg_ant_num(struct rtl_priv *rtlpriv)
{
u8 num;
if (rtlpriv->btcoexist.btc_info.ant_num == ANT_X2)
num = 2;
else
num = 1;
return num;
}
#if 0
enum rt_media_status mgnt_link_status_query(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
enum rt_media_status m_status = RT_MEDIA_DISCONNECT;
u8 bibss = (mac->opmode == NL80211_IFTYPE_ADHOC) ? 1 : 0;
if(bibss || rtlpriv->mac80211.link_state >= MAC80211_LINKED) {
m_status = RT_MEDIA_CONNECT;
}
return m_status;
}
#endif
u8 rtl_get_hwpg_bt_exist(struct rtl_priv *rtlpriv)
{
return rtlpriv->btcoexist.btc_info.btcoexist;
}
u8 rtl_get_hwpg_bt_type(struct rtl_priv *rtlpriv)
{
return rtlpriv->btcoexist.btc_info.bt_type;
}
#if 0
MODULE_AUTHOR("Page He <page_he@realsil.com.cn>");
MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>");
MODULE_AUTHOR("Larry Finger <Larry.FInger@lwfinger.net>");
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Realtek 802.11n PCI wireless core");
static int __init rtl_btcoexist_module_init(void)
{
//printk("%s, rtlpriv->btc_ops.btc_init_variables addr is %p\n", __func__, rtlpriv->btc_ops.btc_init_variables);
return 0;
}
static void __exit rtl_btcoexist_module_exit(void)
{
return;
}
module_init(rtl_btcoexist_module_init);
module_exit(rtl_btcoexist_module_exit);
#endif

66
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/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __RTL_BTC_H__
#define __RTL_BTC_H__
#include "halbt_precomp.h"
void rtl_btc_init_variables(struct rtl_priv *rtlpriv);
void rtl_btc_init_hal_vars(struct rtl_priv *rtlpriv);
void rtl_btc_init_hw_config(struct rtl_priv *rtlpriv);
void rtl_btc_ips_notify(struct rtl_priv *rtlpriv, u8 type);
void rtl_btc_scan_notify(struct rtl_priv *rtlpriv, u8 scantype);
void rtl_btc_connect_notify(struct rtl_priv *rtlpriv, u8 action);
void rtl_btc_mediastatus_notify(struct rtl_priv *rtlpriv, enum rt_media_status mstatus);
void rtl_btc_periodical(struct rtl_priv *rtlpriv);
void rtl_btc_halt_notify(void);
void rtl_btc_btinfo_notify(struct rtl_priv *rtlpriv, u8 * tmpBuf, u8 length);
bool rtl_btc_is_limited_dig(struct rtl_priv *rtlpriv);
bool rtl_btc_is_disable_edca_turbo(struct rtl_priv *rtlpriv);
bool rtl_btc_is_bt_disabled(struct rtl_priv *rtlpriv);
//extern struct rtl_btc_ops rtl_btc_operation;
extern struct rtl_btc_ops *rtl_btc_get_ops_pointer(void);
u8 rtl_get_hwpg_ant_num(struct rtl_priv *rtlpriv);
u8 rtl_get_hwpg_bt_exist(struct rtl_priv *rtlpriv);
u8 rtl_get_hwpg_bt_type(struct rtl_priv *rtlpriv);
//enum rt_media_status mgnt_link_status_query(struct ieee80211_hw *hw);
#endif

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/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "wifi.h"
#include "cam.h"
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,0))
#include <linux/export.h>
#endif
void rtl_cam_reset_sec_info(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
rtlpriv->sec.use_defaultkey = false;
rtlpriv->sec.pairwise_enc_algorithm = NO_ENCRYPTION;
rtlpriv->sec.group_enc_algorithm = NO_ENCRYPTION;
memset(rtlpriv->sec.key_buf, 0, KEY_BUF_SIZE * MAX_KEY_LEN);
memset(rtlpriv->sec.key_len, 0, KEY_BUF_SIZE);
rtlpriv->sec.pairwise_key = NULL;
}
static void rtl_cam_program_entry(struct ieee80211_hw *hw, u32 entry_no,
u8 *mac_addr, u8 *key_cont_128, u16 us_config)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
u32 target_command;
u32 target_content = 0;
u8 entry_i;
RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_DMESG, "Key content :",
key_cont_128, 16);
for (entry_i = 0; entry_i < CAM_CONTENT_COUNT; entry_i++) {
target_command = entry_i + CAM_CONTENT_COUNT * entry_no;
target_command = target_command | BIT(31) | BIT(16);
if (entry_i == 0) {
target_content = (u32) (*(mac_addr + 0)) << 16 |
(u32) (*(mac_addr + 1)) << 24 | (u32) us_config;
rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[WCAMI],
target_content);
rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM],
target_command);
RT_TRACE(COMP_SEC, DBG_LOUD,
("WRITE %x: %x \n",
rtlpriv->cfg->maps[WCAMI], target_content));
RT_TRACE(COMP_SEC, DBG_LOUD,
("The Key ID is %d\n", entry_no));
RT_TRACE(COMP_SEC, DBG_LOUD,
("WRITE %x: %x \n",
rtlpriv->cfg->maps[RWCAM], target_command));
} else if (entry_i == 1) {
target_content = (u32) (*(mac_addr + 5)) << 24 |
(u32) (*(mac_addr + 4)) << 16 |
(u32) (*(mac_addr + 3)) << 8 |
(u32) (*(mac_addr + 2));
rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[WCAMI],
target_content);
rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM],
target_command);
RT_TRACE(COMP_SEC, DBG_LOUD,
("WRITE A4: %x \n", target_content));
RT_TRACE(COMP_SEC, DBG_LOUD,
("WRITE A0: %x \n", target_command));
} else {
target_content =
(u32) (*(key_cont_128 + (entry_i * 4 - 8) + 3)) <<
24 | (u32) (*(key_cont_128 + (entry_i * 4 - 8) + 2))
<< 16 |
(u32) (*(key_cont_128 + (entry_i * 4 - 8) + 1)) << 8
| (u32) (*(key_cont_128 + (entry_i * 4 - 8) + 0));
rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[WCAMI],
target_content);
rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM],
target_command);
udelay(100);
RT_TRACE(COMP_SEC, DBG_LOUD,
("WRITE A4: %x \n", target_content));
RT_TRACE(COMP_SEC, DBG_LOUD,
("WRITE A0: %x \n", target_command));
}
}
RT_TRACE(COMP_SEC, DBG_LOUD,
("after set key, usconfig:%x\n", us_config));
}
u8 rtl_cam_add_one_entry(struct ieee80211_hw *hw, u8 *mac_addr,
u32 ul_key_id, u32 ul_entry_idx, u32 ul_enc_alg,
u32 ul_default_key, u8 *key_content)
{
u32 us_config;
struct rtl_priv *rtlpriv = rtl_priv(hw);
RT_TRACE(COMP_SEC, DBG_DMESG,
("EntryNo:%x, ulKeyId=%x, ulEncAlg=%x, "
"ulUseDK=%x MacAddr %pM\n",
ul_entry_idx, ul_key_id, ul_enc_alg,
ul_default_key, mac_addr));
if (ul_key_id == TOTAL_CAM_ENTRY) {
RT_TRACE(COMP_ERR, DBG_WARNING,
("ulKeyId exceed!\n"));
return 0;
}
if (ul_default_key == 1) {
us_config = CFG_VALID | ((u16) (ul_enc_alg) << 2);
} else {
us_config = CFG_VALID | ((ul_enc_alg) << 2) | ul_key_id;
}
rtl_cam_program_entry(hw, ul_entry_idx, mac_addr,
(u8 *) key_content, us_config);
RT_TRACE(COMP_SEC, DBG_DMESG, ("end \n"));
return 1;
}
//EXPORT_SYMBOL(rtl_cam_add_one_entry);
int rtl_cam_delete_one_entry(struct ieee80211_hw *hw,
u8 *mac_addr, u32 ul_key_id)
{
u32 ul_command;
struct rtl_priv *rtlpriv = rtl_priv(hw);
RT_TRACE(COMP_SEC, DBG_DMESG, ("key_idx:%d\n", ul_key_id));
ul_command = ul_key_id * CAM_CONTENT_COUNT;
ul_command = ul_command | BIT(31) | BIT(16);
rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[WCAMI], 0);
rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM], ul_command);
RT_TRACE(COMP_SEC, DBG_DMESG,
("rtl_cam_delete_one_entry(): WRITE A4: %x \n", 0));
RT_TRACE(COMP_SEC, DBG_DMESG,
("rtl_cam_delete_one_entry(): WRITE A0: %x \n", ul_command));
return 0;
}
//EXPORT_SYMBOL(rtl_cam_delete_one_entry);
void rtl_cam_reset_all_entry(struct ieee80211_hw *hw)
{
u32 ul_command;
struct rtl_priv *rtlpriv = rtl_priv(hw);
ul_command = BIT(31) | BIT(30);
rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM], ul_command);
}
//EXPORT_SYMBOL(rtl_cam_reset_all_entry);
void rtl_cam_mark_invalid(struct ieee80211_hw *hw, u8 uc_index)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
u32 ul_command;
u32 ul_content;
u32 ul_enc_algo = rtlpriv->cfg->maps[SEC_CAM_AES];
switch (rtlpriv->sec.pairwise_enc_algorithm) {
case WEP40_ENCRYPTION:
ul_enc_algo = rtlpriv->cfg->maps[SEC_CAM_WEP40];
break;
case WEP104_ENCRYPTION:
ul_enc_algo = rtlpriv->cfg->maps[SEC_CAM_WEP104];
break;
case TKIP_ENCRYPTION:
ul_enc_algo = rtlpriv->cfg->maps[SEC_CAM_TKIP];
break;
case AESCCMP_ENCRYPTION:
ul_enc_algo = rtlpriv->cfg->maps[SEC_CAM_AES];
break;
default:
ul_enc_algo = rtlpriv->cfg->maps[SEC_CAM_AES];
}
ul_content = (uc_index & 3) | ((u16) (ul_enc_algo) << 2);
ul_content |= BIT(15);
ul_command = CAM_CONTENT_COUNT * uc_index;
ul_command = ul_command | BIT(31) | BIT(16);
rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[WCAMI], ul_content);
rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM], ul_command);
RT_TRACE(COMP_SEC, DBG_DMESG,
("rtl_cam_mark_invalid(): WRITE A4: %x \n", ul_content));
RT_TRACE(COMP_SEC, DBG_DMESG,
("rtl_cam_mark_invalid(): WRITE A0: %x \n", ul_command));
}
//EXPORT_SYMBOL(rtl_cam_mark_invalid);
void rtl_cam_empty_entry(struct ieee80211_hw *hw, u8 uc_index)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
u32 ul_command;
u32 ul_content;
u32 ul_encalgo = rtlpriv->cfg->maps[SEC_CAM_AES];
u8 entry_i;
switch (rtlpriv->sec.pairwise_enc_algorithm) {
case WEP40_ENCRYPTION:
ul_encalgo = rtlpriv->cfg->maps[SEC_CAM_WEP40];
break;
case WEP104_ENCRYPTION:
ul_encalgo = rtlpriv->cfg->maps[SEC_CAM_WEP104];
break;
case TKIP_ENCRYPTION:
ul_encalgo = rtlpriv->cfg->maps[SEC_CAM_TKIP];
break;
case AESCCMP_ENCRYPTION:
ul_encalgo = rtlpriv->cfg->maps[SEC_CAM_AES];
break;
default:
ul_encalgo = rtlpriv->cfg->maps[SEC_CAM_AES];
}
for (entry_i = 0; entry_i < CAM_CONTENT_COUNT; entry_i++) {
if (entry_i == 0) {
ul_content =
(uc_index & 0x03) | ((u16) (ul_encalgo) << 2);
ul_content |= BIT(15);
} else {
ul_content = 0;
}
ul_command = CAM_CONTENT_COUNT * uc_index + entry_i;
ul_command = ul_command | BIT(31) | BIT(16);
rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[WCAMI], ul_content);
rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM], ul_command);
RT_TRACE(COMP_SEC, DBG_LOUD,
("rtl_cam_empty_entry(): WRITE A4: %x \n",
ul_content));
RT_TRACE(COMP_SEC, DBG_LOUD,
("rtl_cam_empty_entry(): WRITE A0: %x \n",
ul_command));
}
}
//EXPORT_SYMBOL(rtl_cam_empty_entry);
u8 rtl_cam_get_free_entry(struct ieee80211_hw *hw, u8 *sta_addr)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
u32 bitmap = (rtlpriv->sec.hwsec_cam_bitmap) >> 4;
u8 entry_idx = 0;
u8 i, *addr;
if (NULL == sta_addr) {
RT_TRACE(COMP_SEC, DBG_EMERG,
("sta_addr is NULL.\n"));
return TOTAL_CAM_ENTRY;
}
/* Does STA already exist? */
for (i = 4; i < TOTAL_CAM_ENTRY; i++) {
addr = rtlpriv->sec.hwsec_cam_sta_addr[i];
if(memcmp(addr, sta_addr, ETH_ALEN) == 0)
return i;
}
/* Get a free CAM entry. */
for (entry_idx = 4; entry_idx < TOTAL_CAM_ENTRY; entry_idx++) {
if ((bitmap & BIT(0)) == 0) {
RT_TRACE(COMP_SEC, DBG_EMERG,
("-----hwsec_cam_bitmap: 0x%x entry_idx=%d\n",
rtlpriv->sec.hwsec_cam_bitmap, entry_idx));
rtlpriv->sec.hwsec_cam_bitmap |= BIT(0) << entry_idx;
memcpy(rtlpriv->sec.hwsec_cam_sta_addr[entry_idx],
sta_addr, ETH_ALEN);
return entry_idx;
}
bitmap = bitmap >>1;
}
return TOTAL_CAM_ENTRY;
}
//EXPORT_SYMBOL(rtl_cam_get_free_entry);
void rtl_cam_del_entry(struct ieee80211_hw *hw, u8 *sta_addr)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
u32 bitmap;
u8 i, *addr;
if (NULL == sta_addr) {
RT_TRACE(COMP_SEC, DBG_EMERG,
("sta_addr is NULL.\n"));
}
if ((sta_addr[0]|sta_addr[1]|sta_addr[2]|sta_addr[3]|\
sta_addr[4]|sta_addr[5]) == 0) {
RT_TRACE(COMP_SEC, DBG_EMERG,
("sta_addr is 00:00:00:00:00:00.\n"));
return;
}
/* Does STA already exist? */
for (i = 4; i < TOTAL_CAM_ENTRY; i++) {
addr = rtlpriv->sec.hwsec_cam_sta_addr[i];
bitmap = (rtlpriv->sec.hwsec_cam_bitmap) >> i;
if (((bitmap & BIT(0)) == BIT(0)) &&
(memcmp(addr, sta_addr, ETH_ALEN) == 0)) {
/* Remove from HW Security CAM */
memset(rtlpriv->sec.hwsec_cam_sta_addr[i], 0, ETH_ALEN);
rtlpriv->sec.hwsec_cam_bitmap &= ~(BIT(0) << i);
printk("&&&&&&&&&del entry %d\n",i);
}
}
return;
}
//EXPORT_SYMBOL(rtl_cam_del_entry);

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/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __RTL_CAM_H_
#define __RTL_CAM_H_
#define CAM_CONTENT_COUNT 8
#define CFG_DEFAULT_KEY BIT(5)
#define CFG_VALID BIT(15)
#define PAIRWISE_KEYIDX 0
#define CAM_PAIRWISE_KEY_POSITION 4
#define CAM_CONFIG_USEDK 1
#define CAM_CONFIG_NO_USEDK 0
extern void rtl_cam_reset_all_entry(struct ieee80211_hw *hw);
extern u8 rtl_cam_add_one_entry(struct ieee80211_hw *hw, u8 *mac_addr,
u32 ul_key_id, u32 ul_entry_idx, u32 ul_enc_alg,
u32 ul_default_key, u8 *key_content);
int rtl_cam_delete_one_entry(struct ieee80211_hw *hw, u8 *mac_addr,
u32 ul_key_id);
void rtl_cam_mark_invalid(struct ieee80211_hw *hw, u8 uc_index);
void rtl_cam_empty_entry(struct ieee80211_hw *hw, u8 uc_index);
void rtl_cam_reset_sec_info(struct ieee80211_hw *hw);
u8 rtl_cam_get_free_entry(struct ieee80211_hw *hw, u8 *sta_addr);
void rtl_cam_del_entry(struct ieee80211_hw *hw, u8 *sta_addr);
#endif

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#ifndef __RTL_COMPAT_H__
#define __RTL_COMPAT_H__
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,29))
/*
* Use this if you want to use the same suspend and resume callbacks for suspend
* to RAM and hibernation.
*/
#define SIMPLE_DEV_PM_OPS(name, suspend_fn, resume_fn) \
struct dev_pm_ops name = { \
.suspend = suspend_fn, \
.resume = resume_fn, \
.freeze = suspend_fn, \
.thaw = resume_fn, \
.poweroff = suspend_fn, \
.restore = resume_fn, \
}
#define compat_pci_suspend(fn) \
int fn##_compat(struct pci_dev *pdev, pm_message_t state) \
{ \
int r; \
\
r = fn(&pdev->dev); \
if (r) \
return r; \
\
pci_save_state(pdev); \
pci_disable_device(pdev); \
pci_set_power_state(pdev, PCI_D3hot); \
\
return 0; \
}
#define compat_pci_resume(fn) \
int fn##_compat(struct pci_dev *pdev) \
{ \
int r; \
\
pci_set_power_state(pdev, PCI_D0); \
r = pci_enable_device(pdev); \
if (r) \
return r; \
pci_restore_state(pdev); \
\
return fn(&pdev->dev); \
}
#endif
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,39))
#define RX_FLAG_MACTIME_MPDU RX_FLAG_TSFT
#else
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,8,0))
#define RX_FLAG_MACTIME_MPDU RX_FLAG_MACTIME_START
#else
#endif
//#define NETDEV_TX_OK
#endif
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,7,0))
#define IEEE80211_KEY_FLAG_SW_MGMT IEEE80211_KEY_FLAG_SW_MGMT_TX
#endif
struct ieee80211_mgmt_compat {
__le16 frame_control;
__le16 duration;
u8 da[6];
u8 sa[6];
u8 bssid[6];
__le16 seq_ctrl;
union {
struct {
u8 category;
union {
struct {
u8 action_code;
u8 dialog_token;
u8 status_code;
u8 variable[0];
} __attribute__ ((packed)) wme_action;
struct{
u8 action_code;
u8 dialog_token;
__le16 capab;
__le16 timeout;
__le16 start_seq_num;
} __attribute__((packed)) addba_req;
struct{
u8 action_code;
u8 dialog_token;
__le16 status;
__le16 capab;
__le16 timeout;
} __attribute__((packed)) addba_resp;
struct{
u8 action_code;
__le16 params;
__le16 reason_code;
} __attribute__((packed)) delba;
struct{
u8 action_code;
/* capab_info for open and confirm,
* reason for close
*/
__le16 aux;
/* Followed in plink_confirm by status
* code, AID and supported rates,
* and directly by supported rates in
* plink_open and plink_close
*/
u8 variable[0];
} __attribute__((packed)) plink_action;
struct{
u8 action_code;
u8 variable[0];
} __attribute__((packed)) mesh_action;
struct {
u8 action;
u8 smps_control;
} __attribute__ ((packed)) ht_smps;
} u;
} __attribute__ ((packed)) action;
} u;
} __attribute__ ((packed));
#endif

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43
drivers/staging/rtl8821ae/core.h Normal file
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/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* Tmis program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* Tmis program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* tmis program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* Tme full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __RTL_CORE_H__
#define __RTL_CORE_H__
#define RTL_SUPPORTED_FILTERS \
(FIF_PROMISC_IN_BSS | \
FIF_ALLMULTI | FIF_CONTROL | \
FIF_OTHER_BSS | \
FIF_FCSFAIL | \
FIF_BCN_PRBRESP_PROMISC)
#define RTL_SUPPORTED_CTRL_FILTER 0xFF
extern const struct ieee80211_ops rtl_ops;
#endif

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/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* Tmis program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* Tmis program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* tmis program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* Tme full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "wifi.h"
#include "cam.h"
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0))
#define GET_INODE_DATA(__node) PDE_DATA(__node)
#else
#define GET_INODE_DATA(__node) PDE(__node)->data
#endif
void rtl_dbgp_flag_init(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
u8 i;
rtlpriv->dbg.global_debuglevel = DBG_DMESG;
rtlpriv->dbg.global_debugcomponents =
COMP_ERR |
COMP_FW |
COMP_INIT |
COMP_RECV |
COMP_SEND |
COMP_MLME |
COMP_SCAN |
COMP_INTR |
COMP_LED |
COMP_SEC |
COMP_BEACON |
COMP_RATE |
COMP_RXDESC |
COMP_DIG |
COMP_TXAGC |
COMP_POWER |
COMP_POWER_TRACKING |
COMP_BB_POWERSAVING |
COMP_SWAS |
COMP_RF |
COMP_TURBO |
COMP_RATR |
COMP_CMD |
COMP_EASY_CONCURRENT |
COMP_EFUSE |
COMP_QOS | COMP_MAC80211 | COMP_REGD |
COMP_CHAN |
COMP_BT_COEXIST |
COMP_IQK |
0;
for (i = 0; i < DBGP_TYPE_MAX; i++)
rtlpriv->dbg.dbgp_type[i] = 0;
/*Init Debug flag enable condition */
}
struct proc_dir_entry *proc_topdir;
static int rtl_proc_get_mac_0(struct seq_file *m, void *v)
{
struct ieee80211_hw *hw = m->private;
struct rtl_priv *rtlpriv = rtl_priv(hw);
int i, n, page;
int max = 0xff;
page = 0x000;
for (n = 0; n <= max; ) {
seq_printf(m, "\n%8.8x ", n + page);
for (i = 0; i < 4 && n <= max; i++, n += 4)
seq_printf(m, "%8.8x ",
rtl_read_dword(rtlpriv, (page | n)));
}
seq_puts(m, "\n");
return 0;
}
static int dl_proc_open_mac_0(struct inode *inode, struct file *file)
{
return single_open(file, rtl_proc_get_mac_0, GET_INODE_DATA(inode));
}
static const struct file_operations file_ops_mac_0 = {
.open = dl_proc_open_mac_0,
.read = seq_read,
.llseek = seq_lseek,
.release = seq_release,
};
static int rtl_proc_get_mac_1(struct seq_file *m, void *v)
{
struct ieee80211_hw *hw = m->private;
struct rtl_priv *rtlpriv = rtl_priv(hw);
int i, n, page;
int max = 0xff;
page = 0x100;
for (n = 0; n <= max; ) {
seq_printf(m, "\n%8.8x ", n + page);
for (i = 0; i < 4 && n <= max; i++, n += 4)
seq_printf(m, "%8.8x ",
rtl_read_dword(rtlpriv, (page | n)));
}
seq_puts(m, "\n");
return 0;
}
static int dl_proc_open_mac_1(struct inode *inode, struct file *file)
{
return single_open(file, rtl_proc_get_mac_1, GET_INODE_DATA(inode));
}
static const struct file_operations file_ops_mac_1 = {
.open = dl_proc_open_mac_1,
.read = seq_read,
.llseek = seq_lseek,
.release = seq_release,
};
static int rtl_proc_get_mac_2(struct seq_file *m, void *v)
{
struct ieee80211_hw *hw = m->private;
struct rtl_priv *rtlpriv = rtl_priv(hw);
int i, n, page;
int max = 0xff;
page = 0x200;
for (n = 0; n <= max; ) {
seq_printf(m, "\n%8.8x ", n + page);
for (i = 0; i < 4 && n <= max; i++, n += 4)
seq_printf(m, "%8.8x ",
rtl_read_dword(rtlpriv, (page | n)));
}
seq_puts(m, "\n");
return 0;
}
static int dl_proc_open_mac_2(struct inode *inode, struct file *file)
{
return single_open(file, rtl_proc_get_mac_2, GET_INODE_DATA(inode));
}
static const struct file_operations file_ops_mac_2 = {
.open = dl_proc_open_mac_2,
.read = seq_read,
.llseek = seq_lseek,
.release = seq_release,
};
static int rtl_proc_get_mac_3(struct seq_file *m, void *v)
{
struct ieee80211_hw *hw = m->private;
struct rtl_priv *rtlpriv = rtl_priv(hw);
int i, n, page;
int max = 0xff;
page = 0x300;
for (n = 0; n <= max; ) {
seq_printf(m, "\n%8.8x ", n + page);
for (i = 0; i < 4 && n <= max; i++, n += 4)
seq_printf(m, "%8.8x ",
rtl_read_dword(rtlpriv, (page | n)));
}
seq_puts(m, "\n");
return 0;
}
static int dl_proc_open_mac_3(struct inode *inode, struct file *file)
{
return single_open(file, rtl_proc_get_mac_3, GET_INODE_DATA(inode));
}
static const struct file_operations file_ops_mac_3 = {
.open = dl_proc_open_mac_3,
.read = seq_read,
.llseek = seq_lseek,
.release = seq_release,
};
static int rtl_proc_get_mac_4(struct seq_file *m, void *v)
{
struct ieee80211_hw *hw = m->private;
struct rtl_priv *rtlpriv = rtl_priv(hw);
int i, n, page;
int max = 0xff;
page = 0x400;
for (n = 0; n <= max; ) {
seq_printf(m, "\n%8.8x ", n + page);
for (i = 0; i < 4 && n <= max; i++, n += 4)
seq_printf(m, "%8.8x ",
rtl_read_dword(rtlpriv, (page | n)));
}
seq_puts(m, "\n");
return 0;
}
static int dl_proc_open_mac_4(struct inode *inode, struct file *file)
{
return single_open(file, rtl_proc_get_mac_4, GET_INODE_DATA(inode));
}
static const struct file_operations file_ops_mac_4 = {
.open = dl_proc_open_mac_4,
.read = seq_read,
.llseek = seq_lseek,
.release = seq_release,
};
static int rtl_proc_get_mac_5(struct seq_file *m, void *v)
{
struct ieee80211_hw *hw = m->private;
struct rtl_priv *rtlpriv = rtl_priv(hw);
int i, n, page;
int max = 0xff;
page = 0x500;
for (n = 0; n <= max; ) {
seq_printf(m, "\n%8.8x ", n + page);
for (i = 0; i < 4 && n <= max; i++, n += 4)
seq_printf(m, "%8.8x ",
rtl_read_dword(rtlpriv, (page | n)));
}
seq_puts(m, "\n");
return 0;
}
static int dl_proc_open_mac_5(struct inode *inode, struct file *file)
{
return single_open(file, rtl_proc_get_mac_5, GET_INODE_DATA(inode));
}
static const struct file_operations file_ops_mac_5 = {
.open = dl_proc_open_mac_5,
.read = seq_read,
.llseek = seq_lseek,
.release = seq_release,
};
static int rtl_proc_get_mac_6(struct seq_file *m, void *v)
{
struct ieee80211_hw *hw = m->private;
struct rtl_priv *rtlpriv = rtl_priv(hw);
int i, n, page;
int max = 0xff;
page = 0x600;
for (n = 0; n <= max; ) {
seq_printf(m, "\n%8.8x ", n + page);
for (i = 0; i < 4 && n <= max; i++, n += 4)
seq_printf(m, "%8.8x ",
rtl_read_dword(rtlpriv, (page | n)));
}
seq_puts(m, "\n");
return 0;
}
static int dl_proc_open_mac_6(struct inode *inode, struct file *file)
{
return single_open(file, rtl_proc_get_mac_6, GET_INODE_DATA(inode));
}
static const struct file_operations file_ops_mac_6 = {
.open = dl_proc_open_mac_6,
.read = seq_read,
.llseek = seq_lseek,
.release = seq_release,
};
static int rtl_proc_get_mac_7(struct seq_file *m, void *v)
{
struct ieee80211_hw *hw = m->private;
struct rtl_priv *rtlpriv = rtl_priv(hw);
int i, n, page;
int max = 0xff;
page = 0x700;
for (n = 0; n <= max; ) {
seq_printf(m, "\n%8.8x ", n + page);
for (i = 0; i < 4 && n <= max; i++, n += 4)
seq_printf(m, "%8.8x ",
rtl_read_dword(rtlpriv, (page | n)));
}
seq_puts(m, "\n");
return 0;
}
static int dl_proc_open_mac_7(struct inode *inode, struct file *file)
{
return single_open(file, rtl_proc_get_mac_7, GET_INODE_DATA(inode));
}
static const struct file_operations file_ops_mac_7 = {
.open = dl_proc_open_mac_7,
.read = seq_read,
.llseek = seq_lseek,
.release = seq_release,
};
static int rtl_proc_get_bb_8(struct seq_file *m, void *v)
{
struct ieee80211_hw *hw = m->private;
int i, n, page;
int max = 0xff;
page = 0x800;
for (n = 0; n <= max; ) {
seq_printf(m, "\n%8.8x ", n + page);
for (i = 0; i < 4 && n <= max; i++, n += 4)
seq_printf(m, "%8.8x ",
rtl_get_bbreg(hw, (page | n), 0xffffffff));
}
seq_puts(m, "\n");
return 0;
}
static int dl_proc_open_bb_8(struct inode *inode, struct file *file)
{
return single_open(file, rtl_proc_get_bb_8, GET_INODE_DATA(inode));
}
static const struct file_operations file_ops_bb_8 = {
.open = dl_proc_open_bb_8,
.read = seq_read,
.llseek = seq_lseek,
.release = seq_release,
};
static int rtl_proc_get_bb_9(struct seq_file *m, void *v)
{
struct ieee80211_hw *hw = m->private;
int i, n, page;
int max = 0xff;
page = 0x900;
for (n = 0; n <= max; ) {
seq_printf(m, "\n%8.8x ", n + page);
for (i = 0; i < 4 && n <= max; i++, n += 4)
seq_printf(m, "%8.8x ",
rtl_get_bbreg(hw, (page | n), 0xffffffff));
}
seq_puts(m, "\n");
return 0;
}
static int dl_proc_open_bb_9(struct inode *inode, struct file *file)
{
return single_open(file, rtl_proc_get_bb_9, GET_INODE_DATA(inode));
}
static const struct file_operations file_ops_bb_9 = {
.open = dl_proc_open_bb_9,
.read = seq_read,
.llseek = seq_lseek,
.release = seq_release,
};
static int rtl_proc_get_bb_a(struct seq_file *m, void *v)
{
struct ieee80211_hw *hw = m->private;
int i, n, page;
int max = 0xff;
page = 0xa00;
for (n = 0; n <= max; ) {
seq_printf(m, "\n%8.8x ", n + page);
for (i = 0; i < 4 && n <= max; i++, n += 4)
seq_printf(m, "%8.8x ",
rtl_get_bbreg(hw, (page | n), 0xffffffff));
}
seq_puts(m, "\n");
return 0;
}
static int dl_proc_open_bb_a(struct inode *inode, struct file *file)
{
return single_open(file, rtl_proc_get_bb_a, GET_INODE_DATA(inode));
}
static const struct file_operations file_ops_bb_a = {
.open = dl_proc_open_bb_a,
.read = seq_read,
.llseek = seq_lseek,
.release = seq_release,
};
static int rtl_proc_get_bb_b(struct seq_file *m, void *v)
{
struct ieee80211_hw *hw = m->private;
int i, n, page;
int max = 0xff;
page = 0xb00;
for (n = 0; n <= max; ) {
seq_printf(m, "\n%8.8x ", n + page);
for (i = 0; i < 4 && n <= max; i++, n += 4)
seq_printf(m, "%8.8x ",
rtl_get_bbreg(hw, (page | n), 0xffffffff));
}
seq_puts(m, "\n");
return 0;
}
static int dl_proc_open_bb_b(struct inode *inode, struct file *file)
{
return single_open(file, rtl_proc_get_bb_b, GET_INODE_DATA(inode));
}
static const struct file_operations file_ops_bb_b = {
.open = dl_proc_open_bb_b,
.read = seq_read,
.llseek = seq_lseek,
.release = seq_release,
};
static int rtl_proc_get_bb_c(struct seq_file *m, void *v)
{
struct ieee80211_hw *hw = m->private;
int i, n, page;
int max = 0xff;
page = 0xc00;
for (n = 0; n <= max; ) {
seq_printf(m, "\n%8.8x ", n + page);
for (i = 0; i < 4 && n <= max; i++, n += 4)
seq_printf(m, "%8.8x ",
rtl_get_bbreg(hw, (page | n), 0xffffffff));
}
seq_puts(m, "\n");
return 0;
}
static int dl_proc_open_bb_c(struct inode *inode, struct file *file)
{
return single_open(file, rtl_proc_get_bb_c, GET_INODE_DATA(inode));
}
static const struct file_operations file_ops_bb_c = {
.open = dl_proc_open_bb_c,
.read = seq_read,
.llseek = seq_lseek,
.release = seq_release,
};
static int rtl_proc_get_bb_d(struct seq_file *m, void *v)
{
struct ieee80211_hw *hw = m->private;
int i, n, page;
int max = 0xff;
page = 0xd00;
for (n = 0; n <= max; ) {
seq_printf(m, "\n%8.8x ", n + page);
for (i = 0; i < 4 && n <= max; i++, n += 4)
seq_printf(m, "%8.8x ",
rtl_get_bbreg(hw, (page | n), 0xffffffff));
}
seq_puts(m, "\n");
return 0;
}
static int dl_proc_open_bb_d(struct inode *inode, struct file *file)
{
return single_open(file, rtl_proc_get_bb_d, GET_INODE_DATA(inode));
}
static const struct file_operations file_ops_bb_d = {
.open = dl_proc_open_bb_d,
.read = seq_read,
.llseek = seq_lseek,
.release = seq_release,
};
static int rtl_proc_get_bb_e(struct seq_file *m, void *v)
{
struct ieee80211_hw *hw = m->private;
int i, n, page;
int max = 0xff;
page = 0xe00;
for (n = 0; n <= max; ) {
seq_printf(m, "\n%8.8x ", n + page);
for (i = 0; i < 4 && n <= max; i++, n += 4)
seq_printf(m, "%8.8x ",
rtl_get_bbreg(hw, (page | n), 0xffffffff));
}
seq_puts(m, "\n");
return 0;
}
static int dl_proc_open_bb_e(struct inode *inode, struct file *file)
{
return single_open(file, rtl_proc_get_bb_e, GET_INODE_DATA(inode));
}
static const struct file_operations file_ops_bb_e = {
.open = dl_proc_open_bb_e,
.read = seq_read,
.llseek = seq_lseek,
.release = seq_release,
};
static int rtl_proc_get_bb_f(struct seq_file *m, void *v)
{
struct ieee80211_hw *hw = m->private;
int i, n, page;
int max = 0xff;
page = 0xf00;
for (n = 0; n <= max; ) {
seq_printf(m, "\n%8.8x ", n + page);
for (i = 0; i < 4 && n <= max; i++, n += 4)
seq_printf(m, "%8.8x ",
rtl_get_bbreg(hw, (page | n), 0xffffffff));
}
seq_puts(m, "\n");
return 0;
}
static int dl_proc_open_bb_f(struct inode *inode, struct file *file)
{
return single_open(file, rtl_proc_get_bb_f, GET_INODE_DATA(inode));
}
static const struct file_operations file_ops_bb_f = {
.open = dl_proc_open_bb_f,
.read = seq_read,
.llseek = seq_lseek,
.release = seq_release,
};
static int rtl_proc_get_reg_rf_a(struct seq_file *m, void *v)
{
struct ieee80211_hw *hw = m->private;
int i, n;
int max = 0x40;
for (n = 0; n <= max; ) {
seq_printf(m, "\n%8.8x ", n);
for (i = 0; i < 4 && n <= max; n += 1, i++)
seq_printf(m, "%8.8x ",
rtl_get_rfreg(hw, RF90_PATH_A, n, 0xffffffff));
}
seq_puts(m, "\n");
return 0;
}
static int dl_proc_open_rf_a(struct inode *inode, struct file *file)
{
return single_open(file, rtl_proc_get_reg_rf_a, GET_INODE_DATA(inode));
}
static const struct file_operations file_ops_rf_a = {
.open = dl_proc_open_rf_a,
.read = seq_read,
.llseek = seq_lseek,
.release = seq_release,
};
static int rtl_proc_get_reg_rf_b(struct seq_file *m, void *v)
{
struct ieee80211_hw *hw = m->private;
int i, n;
int max = 0x40;
for (n = 0; n <= max; ) {
seq_printf(m, "\n%8.8x ", n);
for (i = 0; i < 4 && n <= max; n += 1, i++)
seq_printf(m, "%8.8x ",
rtl_get_rfreg(hw, RF90_PATH_B, n,
0xffffffff));
}
seq_puts(m, "\n");
return 0;
}
static int dl_proc_open_rf_b(struct inode *inode, struct file *file)
{
return single_open(file, rtl_proc_get_reg_rf_b, GET_INODE_DATA(inode));
}
static const struct file_operations file_ops_rf_b = {
.open = dl_proc_open_rf_b,
.read = seq_read,
.llseek = seq_lseek,
.release = seq_release,
};
static int rtl_proc_get_cam_register_1(struct seq_file *m, void *v)
{
struct ieee80211_hw *hw = m->private;
struct rtl_priv *rtlpriv = rtl_priv(hw);
u32 target_cmd = 0;
u32 target_val=0;
u8 entry_i=0;
u32 ulstatus;
int i = 100, j = 0;
/* This dump the current register page */
seq_puts(m,
"\n#################### SECURITY CAM (0-10) ##################\n ");
for (j = 0; j < 11; j++) {
seq_printf(m, "\nD: %2x > ", j);
for (entry_i = 0; entry_i < CAM_CONTENT_COUNT; entry_i++) {
/* polling bit, and No Write enable, and address */
target_cmd = entry_i + CAM_CONTENT_COUNT * j;
target_cmd = target_cmd | BIT(31);
/* Check polling bit is clear */
while ((i--) >= 0) {
ulstatus = rtl_read_dword(rtlpriv,
rtlpriv->cfg->maps[RWCAM]);
if (ulstatus & BIT(31)) {
continue;
} else {
break;
}
}
rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM],
target_cmd);
target_val = rtl_read_dword(rtlpriv,
rtlpriv->cfg->maps[RCAMO]);
seq_printf(m, "%8.8x ", target_val);
}
}
seq_puts(m, "\n");
return 0;
}
static int dl_proc_open_cam_1(struct inode *inode, struct file *file)
{
return single_open(file, rtl_proc_get_cam_register_1,
GET_INODE_DATA(inode));
}
static const struct file_operations file_ops_cam_1 = {
.open = dl_proc_open_cam_1,
.read = seq_read,
.llseek = seq_lseek,
.release = seq_release,
};
static int rtl_proc_get_cam_register_2(struct seq_file *m, void *v)
{
struct ieee80211_hw *hw = m->private;
struct rtl_priv *rtlpriv = rtl_priv(hw);
u32 target_cmd = 0;
u32 target_val = 0;
u8 entry_i = 0;
u32 ulstatus;
int i = 100, j = 0;
/* This dump the current register page */
seq_puts(m,
"\n################### SECURITY CAM (11-21) ##################\n ");
for (j = 11; j < 22; j++) {
seq_printf(m, "\nD: %2x > ", j);
for (entry_i = 0; entry_i < CAM_CONTENT_COUNT; entry_i++) {
target_cmd = entry_i + CAM_CONTENT_COUNT * j;
target_cmd = target_cmd | BIT(31);
while ((i--) >= 0) {
ulstatus = rtl_read_dword(rtlpriv,
rtlpriv->cfg->maps[RWCAM]);
if (ulstatus & BIT(31)) {
continue;
} else {
break;
}
}
rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM],
target_cmd);
target_val = rtl_read_dword(rtlpriv,
rtlpriv->cfg->maps[RCAMO]);
seq_printf(m, "%8.8x ", target_val);
}
}
seq_puts(m, "\n");
return 0;
}
static int dl_proc_open_cam_2(struct inode *inode, struct file *file)
{
return single_open(file, rtl_proc_get_cam_register_2,
GET_INODE_DATA(inode));
}
static const struct file_operations file_ops_cam_2 = {
.open = dl_proc_open_cam_2,
.read = seq_read,
.llseek = seq_lseek,
.release = seq_release,
};
static int rtl_proc_get_cam_register_3(struct seq_file *m, void *v)
{
struct ieee80211_hw *hw = m->private;
struct rtl_priv *rtlpriv = rtl_priv(hw);
u32 target_cmd = 0;
u32 target_val = 0;
u8 entry_i = 0;
u32 ulstatus;
int i = 100, j = 0;
/* This dump the current register page */
seq_puts(m,
"\n################### SECURITY CAM (22-31) ##################\n ");
for (j = 22; j < TOTAL_CAM_ENTRY; j++) {
seq_printf(m, "\nD: %2x > ", j);
for (entry_i = 0; entry_i < CAM_CONTENT_COUNT; entry_i++) {
target_cmd = entry_i+CAM_CONTENT_COUNT*j;
target_cmd = target_cmd | BIT(31);
while ((i--) >= 0) {
ulstatus = rtl_read_dword(rtlpriv,
rtlpriv->cfg->maps[RWCAM]);
if (ulstatus & BIT(31)) {
continue;
} else {
break;
}
}
rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM],
target_cmd);
target_val = rtl_read_dword(rtlpriv,
rtlpriv->cfg->maps[RCAMO]);
seq_printf(m, "%8.8x ", target_val);
}
}
seq_puts(m, "\n");
return 0;
}
static int dl_proc_open_cam_3(struct inode *inode, struct file *file)
{
return single_open(file, rtl_proc_get_cam_register_3,
GET_INODE_DATA(inode));
}
static const struct file_operations file_ops_cam_3 = {
.open = dl_proc_open_cam_3,
.read = seq_read,
.llseek = seq_lseek,
.release = seq_release,
};
void rtl_proc_add_one(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
struct proc_dir_entry *entry;
snprintf(rtlpriv->dbg.proc_name, 18, "%x-%x-%x-%x-%x-%x",
rtlefuse->dev_addr[0], rtlefuse->dev_addr[1],
rtlefuse->dev_addr[2], rtlefuse->dev_addr[3],
rtlefuse->dev_addr[4], rtlefuse->dev_addr[5]);
rtlpriv->dbg.proc_dir = proc_mkdir(rtlpriv->dbg.proc_name, proc_topdir);
if (!rtlpriv->dbg.proc_dir) {
RT_TRACE(COMP_INIT, DBG_EMERG, ("Unable to init "
"/proc/net/%s/%s\n", rtlpriv->cfg->name,
rtlpriv->dbg.proc_name));
return;
}
entry = proc_create_data("mac-0", S_IFREG | S_IRUGO,
rtlpriv->dbg.proc_dir, &file_ops_mac_0, hw);
if (!entry)
RT_TRACE(COMP_INIT, DBG_EMERG,
("Unable to initialize /proc/net/%s/%s/mac-0\n",
rtlpriv->cfg->name, rtlpriv->dbg.proc_name));
entry = proc_create_data("mac-1", S_IFREG | S_IRUGO,
rtlpriv->dbg.proc_dir, &file_ops_mac_1, hw);
if (!entry)
RT_TRACE(COMP_INIT, COMP_ERR,
("Unable to initialize /proc/net/%s/%s/mac-1\n",
rtlpriv->cfg->name, rtlpriv->dbg.proc_name));
entry = proc_create_data("mac-2", S_IFREG | S_IRUGO,
rtlpriv->dbg.proc_dir, &file_ops_mac_2, hw);
if (!entry)
RT_TRACE(COMP_INIT, COMP_ERR,
("Unable to initialize /proc/net/%s/%s/mac-2\n",
rtlpriv->cfg->name, rtlpriv->dbg.proc_name));
entry = proc_create_data("mac-3", S_IFREG | S_IRUGO,
rtlpriv->dbg.proc_dir, &file_ops_mac_3, hw);
if (!entry)
RT_TRACE(COMP_INIT, COMP_ERR,
("Unable to initialize /proc/net/%s/%s/mac-3\n",
rtlpriv->cfg->name, rtlpriv->dbg.proc_name));
entry = proc_create_data("mac-4", S_IFREG | S_IRUGO,
rtlpriv->dbg.proc_dir, &file_ops_mac_4, hw);
if (!entry)
RT_TRACE(COMP_INIT, COMP_ERR,
("Unable to initialize /proc/net/%s/%s/mac-4\n",
rtlpriv->cfg->name, rtlpriv->dbg.proc_name));
entry = proc_create_data("mac-5", S_IFREG | S_IRUGO,
rtlpriv->dbg.proc_dir, &file_ops_mac_5, hw);
if (!entry)
RT_TRACE(COMP_INIT, COMP_ERR,
("Unable to initialize /proc/net/%s/%s/mac-5\n",
rtlpriv->cfg->name, rtlpriv->dbg.proc_name));
entry = proc_create_data("mac-6", S_IFREG | S_IRUGO,
rtlpriv->dbg.proc_dir, &file_ops_mac_6, hw);
if (!entry)
RT_TRACE(COMP_INIT, COMP_ERR,
("Unable to initialize /proc/net/%s/%s/mac-6\n",
rtlpriv->cfg->name, rtlpriv->dbg.proc_name));
entry = proc_create_data("mac-7", S_IFREG | S_IRUGO,
rtlpriv->dbg.proc_dir, &file_ops_mac_7, hw);
if (!entry)
RT_TRACE(COMP_INIT, COMP_ERR,
("Unable to initialize /proc/net/%s/%s/mac-7\n",
rtlpriv->cfg->name, rtlpriv->dbg.proc_name));
entry = proc_create_data("bb-8", S_IFREG | S_IRUGO,
rtlpriv->dbg.proc_dir, &file_ops_bb_8, hw);
if (!entry)
RT_TRACE(COMP_INIT, COMP_ERR,
("Unable to initialize /proc/net/%s/%s/bb-8\n",
rtlpriv->cfg->name, rtlpriv->dbg.proc_name));
entry = proc_create_data("bb-9", S_IFREG | S_IRUGO,
rtlpriv->dbg.proc_dir, &file_ops_bb_9, hw);
if (!entry)
RT_TRACE(COMP_INIT, COMP_ERR,
("Unable to initialize /proc/net/%s/%s/bb-9\n",
rtlpriv->cfg->name, rtlpriv->dbg.proc_name));
entry = proc_create_data("bb-a", S_IFREG | S_IRUGO,
rtlpriv->dbg.proc_dir, &file_ops_bb_a, hw);
if (!entry)
RT_TRACE(COMP_INIT, COMP_ERR,
("Unable to initialize /proc/net/%s/%s/bb-a\n",
rtlpriv->cfg->name, rtlpriv->dbg.proc_name));
entry = proc_create_data("bb-b", S_IFREG | S_IRUGO,
rtlpriv->dbg.proc_dir, &file_ops_bb_b, hw);
if (!entry)
RT_TRACE(COMP_INIT, COMP_ERR,
("Unable to initialize /proc/net/%s/%s/bb-b\n",
rtlpriv->cfg->name, rtlpriv->dbg.proc_name));
entry = proc_create_data("bb-c", S_IFREG | S_IRUGO,
rtlpriv->dbg.proc_dir, &file_ops_bb_c, hw);
if (!entry)
RT_TRACE(COMP_INIT, COMP_ERR,
("Unable to initialize /proc/net/%s/%s/bb-c\n",
rtlpriv->cfg->name, rtlpriv->dbg.proc_name));
entry = proc_create_data("bb-d", S_IFREG | S_IRUGO,
rtlpriv->dbg.proc_dir, &file_ops_bb_d, hw);
if (!entry)
RT_TRACE(COMP_INIT, COMP_ERR,
("Unable to initialize /proc/net/%s/%s/bb-d\n",
rtlpriv->cfg->name, rtlpriv->dbg.proc_name));
entry = proc_create_data("bb-e", S_IFREG | S_IRUGO,
rtlpriv->dbg.proc_dir, &file_ops_bb_e, hw);
if (!entry)
RT_TRACE(COMP_INIT, COMP_ERR,
("Unable to initialize /proc/net/%s/%s/bb-e\n",
rtlpriv->cfg->name, rtlpriv->dbg.proc_name));
entry = proc_create_data("bb-f", S_IFREG | S_IRUGO,
rtlpriv->dbg.proc_dir, &file_ops_bb_f, hw);
if (!entry)
RT_TRACE(COMP_INIT, COMP_ERR,
("Unable to initialize /proc/net/%s/%s/bb-f\n",
rtlpriv->cfg->name, rtlpriv->dbg.proc_name));
entry = proc_create_data("rf-a", S_IFREG | S_IRUGO,
rtlpriv->dbg.proc_dir, &file_ops_rf_a, hw);
if (!entry)
RT_TRACE(COMP_INIT, COMP_ERR,
("Unable to initialize /proc/net/%s/%s/rf-a\n",
rtlpriv->cfg->name, rtlpriv->dbg.proc_name));
entry = proc_create_data("rf-b", S_IFREG | S_IRUGO,
rtlpriv->dbg.proc_dir, &file_ops_rf_b, hw);
if (!entry)
RT_TRACE(COMP_INIT, COMP_ERR,
("Unable to initialize /proc/net/%s/%s/rf-b\n",
rtlpriv->cfg->name, rtlpriv->dbg.proc_name));
entry = proc_create_data("cam-1", S_IFREG | S_IRUGO,
rtlpriv->dbg.proc_dir, &file_ops_cam_1, hw);
if (!entry)
RT_TRACE(COMP_INIT, COMP_ERR,
("Unable to initialize /proc/net/%s/%s/cam-1\n",
rtlpriv->cfg->name, rtlpriv->dbg.proc_name));
entry = proc_create_data("cam-2", S_IFREG | S_IRUGO,
rtlpriv->dbg.proc_dir, &file_ops_cam_2, hw);
if (!entry)
RT_TRACE(COMP_INIT, COMP_ERR,
("Unable to initialize /proc/net/%s/%s/cam-2\n",
rtlpriv->cfg->name, rtlpriv->dbg.proc_name));
entry = proc_create_data("cam-3", S_IFREG | S_IRUGO,
rtlpriv->dbg.proc_dir, &file_ops_cam_3, hw);
if (!entry)
RT_TRACE(COMP_INIT, COMP_ERR,
("Unable to initialize /proc/net/%s/%s/cam-3\n",
rtlpriv->cfg->name, rtlpriv->dbg.proc_name));
}
void rtl_proc_remove_one(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
if (rtlpriv->dbg.proc_dir) {
remove_proc_entry("mac-0", rtlpriv->dbg.proc_dir);
remove_proc_entry("mac-1", rtlpriv->dbg.proc_dir);
remove_proc_entry("mac-2", rtlpriv->dbg.proc_dir);
remove_proc_entry("mac-3", rtlpriv->dbg.proc_dir);
remove_proc_entry("mac-4", rtlpriv->dbg.proc_dir);
remove_proc_entry("mac-5", rtlpriv->dbg.proc_dir);
remove_proc_entry("mac-6", rtlpriv->dbg.proc_dir);
remove_proc_entry("mac-7", rtlpriv->dbg.proc_dir);
remove_proc_entry("bb-8", rtlpriv->dbg.proc_dir);
remove_proc_entry("bb-9", rtlpriv->dbg.proc_dir);
remove_proc_entry("bb-a", rtlpriv->dbg.proc_dir);
remove_proc_entry("bb-b", rtlpriv->dbg.proc_dir);
remove_proc_entry("bb-c", rtlpriv->dbg.proc_dir);
remove_proc_entry("bb-d", rtlpriv->dbg.proc_dir);
remove_proc_entry("bb-e", rtlpriv->dbg.proc_dir);
remove_proc_entry("bb-f", rtlpriv->dbg.proc_dir);
remove_proc_entry("rf-a", rtlpriv->dbg.proc_dir);
remove_proc_entry("rf-b", rtlpriv->dbg.proc_dir);
remove_proc_entry("cam-1", rtlpriv->dbg.proc_dir);
remove_proc_entry("cam-2", rtlpriv->dbg.proc_dir);
remove_proc_entry("cam-3", rtlpriv->dbg.proc_dir);
remove_proc_entry(rtlpriv->dbg.proc_name, proc_topdir);
rtlpriv->dbg.proc_dir = NULL;
}
}
void rtl_proc_add_topdir(void)
{
proc_topdir = proc_mkdir("rtlwifi", init_net.proc_net);
}
void rtl_proc_remove_topdir(void)
{
if (proc_topdir)
remove_proc_entry("rtlwifi", init_net.proc_net);
}

227
drivers/staging/rtl8821ae/debug.h Normal file
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/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* Tmis program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* Tmis program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* tmis program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* Tme full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __RTL_DEBUG_H__
#define __RTL_DEBUG_H__
/*--------------------------------------------------------------
Debug level
--------------------------------------------------------------*/
/*
*Fatal bug.
*For example, Tx/Rx/IO locked up,
*memory access violation,
*resource allocation failed,
*unexpected HW behavior, HW BUG
*and so on.
*/
#define DBG_EMERG 0
/*
*Abnormal, rare, or unexpeted cases.
*For example, Packet/IO Ctl canceled,
*device suprisely unremoved and so on.
*/
#define DBG_WARNING 2
/*
*Normal case driver developer should
*open, we can see link status like
*assoc/AddBA/DHCP/adapter start and
*so on basic and useful infromations.
*/
#define DBG_DMESG 3
/*
*Normal case with useful information
*about current SW or HW state.
*For example, Tx/Rx descriptor to fill,
*Tx/Rx descriptor completed status,
*SW protocol state change, dynamic
*mechanism state change and so on.
*/
#define DBG_LOUD 4
/*
*Normal case with detail execution
*flow or information.
*/
#define DBG_TRACE 5
/*--------------------------------------------------------------
Define the rt_trace components
--------------------------------------------------------------*/
#define COMP_ERR BIT(0)
#define COMP_FW BIT(1)
#define COMP_INIT BIT(2) /*For init/deinit */
#define COMP_RECV BIT(3) /*For Rx. */
#define COMP_SEND BIT(4) /*For Tx. */
#define COMP_MLME BIT(5) /*For MLME. */
#define COMP_SCAN BIT(6) /*For Scan. */
#define COMP_INTR BIT(7) /*For interrupt Related. */
#define COMP_LED BIT(8) /*For LED. */
#define COMP_SEC BIT(9) /*For sec. */
#define COMP_BEACON BIT(10) /*For beacon. */
#define COMP_RATE BIT(11) /*For rate. */
#define COMP_RXDESC BIT(12) /*For rx desc. */
#define COMP_DIG BIT(13) /*For DIG */
#define COMP_TXAGC BIT(14) /*For Tx power */
#define COMP_HIPWR BIT(15) /*For High Power Mechanism */
#define COMP_POWER BIT(16) /*For lps/ips/aspm. */
#define COMP_POWER_TRACKING BIT(17) /*For TX POWER TRACKING */
#define COMP_BB_POWERSAVING BIT(18)
#define COMP_SWAS BIT(19) /*For SW Antenna Switch */
#define COMP_RF BIT(20) /*For RF. */
#define COMP_TURBO BIT(21) /*For EDCA TURBO. */
#define COMP_RATR BIT(22)
#define COMP_CMD BIT(23)
#define COMP_EFUSE BIT(24)
#define COMP_QOS BIT(25)
#define COMP_MAC80211 BIT(26)
#define COMP_REGD BIT(27)
#define COMP_CHAN BIT(28)
#define COMP_EASY_CONCURRENT BIT(29)
#define COMP_BT_COEXIST BIT(30)
#define COMP_IQK BIT(31)
/*--------------------------------------------------------------
Define the rt_print components
--------------------------------------------------------------*/
/* Define EEPROM and EFUSE check module bit*/
#define EEPROM_W BIT(0)
#define EFUSE_PG BIT(1)
#define EFUSE_READ_ALL BIT(2)
/* Define init check for module bit*/
#define INIT_EEPROM BIT(0)
#define INIT_TxPower BIT(1)
#define INIT_IQK BIT(2)
#define INIT_RF BIT(3)
/* Define PHY-BB/RF/MAC check module bit */
#define PHY_BBR BIT(0)
#define PHY_BBW BIT(1)
#define PHY_RFR BIT(2)
#define PHY_RFW BIT(3)
#define PHY_MACR BIT(4)
#define PHY_MACW BIT(5)
#define PHY_ALLR BIT(6)
#define PHY_ALLW BIT(7)
#define PHY_TXPWR BIT(8)
#define PHY_PWRDIFF BIT(9)
/* Define Dynamic Mechanism check module bit --> FDM */
#define WA_IOT BIT(0)
#define DM_PWDB BIT(1)
#define DM_MONITOR BIT(2)
#define DM_DIG BIT(3)
#define DM_EDCA_TURBO BIT(4)
enum dbgp_flag_e {
FQOS = 0,
FTX = 1,
FRX = 2,
FSEC = 3,
FMGNT = 4,
FMLME = 5,
FRESOURCE = 6,
FBEACON = 7,
FISR = 8,
FPHY = 9,
FMP = 10,
FEEPROM = 11,
FPWR = 12,
FDM = 13,
FDBGCtrl = 14,
FC2H = 15,
FBT = 16,
FINIT = 17,
FIOCTL = 18,
DBGP_TYPE_MAX
};
#define RT_ASSERT(_exp,fmt) \
do { \
if(!(_exp)) { \
printk(KERN_DEBUG "%s:%s(): ", KBUILD_MODNAME, \
__func__); \
printk fmt; \
} \
} while(0);
#define RT_DISP(dbgtype, dbgflag, printstr)
#define RT_TRACE(comp, level, fmt)\
do { \
if(unlikely(((comp) & rtlpriv->dbg.global_debugcomponents) && \
((level) <= rtlpriv->dbg.global_debuglevel))) {\
printk(KERN_DEBUG "%s-%d:%s():<%lx-%x> ", \
KBUILD_MODNAME, \
rtlpriv->rtlhal.interfaceindex, __func__, \
in_interrupt(), in_atomic()); \
printk fmt; \
}\
} while(0);
#define RTPRINT(rtlpriv, dbgtype, dbgflag, printstr) \
do { \
if (unlikely(rtlpriv->dbg.dbgp_type[dbgtype] & dbgflag)) { \
printk(KERN_DEBUG "%s: ", KBUILD_MODNAME); \
printk printstr; \
} \
} while(0);
#define RT_PRINT_DATA(rtlpriv, _comp, _level, _titlestring, _hexdata, \
_hexdatalen) \
do {\
if(unlikely(((_comp) & rtlpriv->dbg.global_debugcomponents ) &&\
(_level <= rtlpriv->dbg.global_debuglevel ))) { \
int __i; \
u8* ptr = (u8*)_hexdata; \
printk(KERN_DEBUG "%s: ", KBUILD_MODNAME); \
printk(KERN_DEBUG "In process \"%s\" (pid %i):", \
current->comm, \
current->pid); \
printk(_titlestring); \
for( __i=0; __i<(int)_hexdatalen; __i++ ) { \
printk("%02X%s", ptr[__i], (((__i + 1) % 4) \
== 0)?" ":" ");\
if (((__i + 1) % 16) == 0) \
printk("\n"); \
} \
printk(KERN_DEBUG "\n"); \
} \
} while(0);
void rtl_dbgp_flag_init(struct ieee80211_hw *hw);
void rtl_proc_add_one(struct ieee80211_hw *hw);
void rtl_proc_remove_one(struct ieee80211_hw *hw);
void rtl_proc_add_topdir(void);
void rtl_proc_remove_topdir(void);
#endif

1285
drivers/staging/rtl8821ae/efuse.c Normal file
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drivers/staging/rtl8821ae/efuse.h Normal file
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/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __RTL_EFUSE_H_
#define __RTL_EFUSE_H_
#define EFUSE_IC_ID_OFFSET 506
/*
#define EFUSE_REAL_CONTENT_LEN 512
#define EFUSE_MAP_LEN 128
#define EFUSE_MAX_SECTION 16
#define EFUSE_MAX_WORD_UNIT 4
#define EFUSE_IC_ID_OFFSET 506
*/
#define EFUSE_MAX_WORD_UNIT 4
#define EFUSE_INIT_MAP 0
#define EFUSE_MODIFY_MAP 1
#define PG_STATE_HEADER 0x01
#define PG_STATE_WORD_0 0x02
#define PG_STATE_WORD_1 0x04
#define PG_STATE_WORD_2 0x08
#define PG_STATE_WORD_3 0x10
#define PG_STATE_DATA 0x20
#define PG_SWBYTE_H 0x01
#define PG_SWBYTE_L 0x02
#define _POWERON_DELAY_
#define _PRE_EXECUTE_READ_CMD_
#define EFUSE_REPEAT_THRESHOLD_ 3
#define EFUSE_ERROE_HANDLE 1
struct efuse_map {
u8 offset;
u8 word_start;
u8 byte_start;
u8 byte_cnts;
};
struct pgpkt_struct {
u8 offset;
u8 word_en;
u8 data[8];
};
enum efuse_data_item {
EFUSE_CHIP_ID = 0,
EFUSE_LDO_SETTING,
EFUSE_CLK_SETTING,
EFUSE_SDIO_SETTING,
EFUSE_CCCR,
EFUSE_SDIO_MODE,
EFUSE_OCR,
EFUSE_F0CIS,
EFUSE_F1CIS,
EFUSE_MAC_ADDR,
EFUSE_EEPROM_VER,
EFUSE_CHAN_PLAN,
EFUSE_TXPW_TAB
};
enum {
VOLTAGE_V25 = 0x03,
LDOE25_SHIFT = 28,
};
struct efuse_priv {
u8 id[2];
u8 ldo_setting[2];
u8 clk_setting[2];
u8 cccr;
u8 sdio_mode;
u8 ocr[3];
u8 cis0[17];
u8 cis1[48];
u8 mac_addr[6];
u8 eeprom_verno;
u8 channel_plan;
u8 tx_power_b[14];
u8 tx_power_g[14];
};
extern void read_efuse_byte(struct ieee80211_hw *hw, u16 _offset, u8 *pbuf);
extern void efuse_initialize(struct ieee80211_hw *hw);
extern u8 efuse_read_1byte(struct ieee80211_hw *hw, u16 address);
extern int efuse_one_byte_read(struct ieee80211_hw *hw, u16 addr, u8 *data);
extern void efuse_write_1byte(struct ieee80211_hw *hw, u16 address, u8 value);
extern void read_efuse(struct ieee80211_hw *hw, u16 _offset,
u16 _size_byte, u8 * pbuf);
extern void efuse_shadow_read(struct ieee80211_hw *hw, u8 type,
u16 offset, u32 * value);
extern void efuse_shadow_write(struct ieee80211_hw *hw, u8 type,
u16 offset, u32 value);
extern bool efuse_shadow_update(struct ieee80211_hw *hw);
extern bool efuse_shadow_update_chk(struct ieee80211_hw *hw);
extern void rtl_efuse_shadow_map_update(struct ieee80211_hw *hw);
extern void efuse_force_write_vendor_Id(struct ieee80211_hw *hw);
extern void efuse_re_pg_section(struct ieee80211_hw *hw, u8 section_idx);
#endif

2549
drivers/staging/rtl8821ae/pci.c Normal file
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drivers/staging/rtl8821ae/pci.h Normal file
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/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __RTL_PCI_H__
#define __RTL_PCI_H__
#include <linux/pci.h>
/*
1: MSDU packet queue,
2: Rx Command Queue
*/
#define RTL_PCI_RX_MPDU_QUEUE 0
#define RTL_PCI_RX_CMD_QUEUE 1
#define RTL_PCI_MAX_RX_QUEUE 2
#define RTL_PCI_MAX_RX_COUNT 512//64
#define RTL_PCI_MAX_TX_QUEUE_COUNT 9
#define RT_TXDESC_NUM 128
#define TX_DESC_NUM_92E 512
#define RT_TXDESC_NUM_BE_QUEUE 256
#define BK_QUEUE 0
#define BE_QUEUE 1
#define VI_QUEUE 2
#define VO_QUEUE 3
#define BEACON_QUEUE 4
#define TXCMD_QUEUE 5
#define MGNT_QUEUE 6
#define HIGH_QUEUE 7
#define HCCA_QUEUE 8
#define RTL_PCI_DEVICE(vend, dev, cfg) \
.vendor = (vend), \
.device = (dev), \
.subvendor = PCI_ANY_ID, \
.subdevice = PCI_ANY_ID,\
.driver_data = (kernel_ulong_t)&(cfg)
#define INTEL_VENDOR_ID 0x8086
#define SIS_VENDOR_ID 0x1039
#define ATI_VENDOR_ID 0x1002
#define ATI_DEVICE_ID 0x7914
#define AMD_VENDOR_ID 0x1022
#define PCI_MAX_BRIDGE_NUMBER 255
#define PCI_MAX_DEVICES 32
#define PCI_MAX_FUNCTION 8
#define PCI_CONF_ADDRESS 0x0CF8 /*PCI Configuration Space Address */
#define PCI_CONF_DATA 0x0CFC /*PCI Configuration Space Data */
#define PCI_CLASS_BRIDGE_DEV 0x06
#define PCI_SUBCLASS_BR_PCI_TO_PCI 0x04
#define PCI_CAPABILITY_ID_PCI_EXPRESS 0x10
#define PCI_CAP_ID_EXP 0x10
#define U1DONTCARE 0xFF
#define U2DONTCARE 0xFFFF
#define U4DONTCARE 0xFFFFFFFF
#define RTL_PCI_8192_DID 0x8192 /*8192 PCI-E */
#define RTL_PCI_8192SE_DID 0x8192 /*8192 SE */
#define RTL_PCI_8174_DID 0x8174 /*8192 SE */
#define RTL_PCI_8173_DID 0x8173 /*8191 SE Crab */
#define RTL_PCI_8172_DID 0x8172 /*8191 SE RE */
#define RTL_PCI_8171_DID 0x8171 /*8191 SE Unicron */
#define RTL_PCI_0045_DID 0x0045 /*8190 PCI for Ceraga */
#define RTL_PCI_0046_DID 0x0046 /*8190 Cardbus for Ceraga */
#define RTL_PCI_0044_DID 0x0044 /*8192e PCIE for Ceraga */
#define RTL_PCI_0047_DID 0x0047 /*8192e Express Card for Ceraga */
#define RTL_PCI_700F_DID 0x700F
#define RTL_PCI_701F_DID 0x701F
#define RTL_PCI_DLINK_DID 0x3304
#define RTL_PCI_8723AE_DID 0x8723 /*8723e */
#define RTL_PCI_8192CET_DID 0x8191 /*8192ce */
#define RTL_PCI_8192CE_DID 0x8178 /*8192ce */
#define RTL_PCI_8191CE_DID 0x8177 /*8192ce */
#define RTL_PCI_8188CE_DID 0x8176 /*8192ce */
#define RTL_PCI_8192CU_DID 0x8191 /*8192ce */
#define RTL_PCI_8192DE_DID 0x8193 /*8192de */
#define RTL_PCI_8192DE_DID2 0x002B /*92DE*/
#define RTL_PCI_8188EE_DID 0x8179 /*8188ee*/
#define RTL_PCI_8723BE_DID 0xB723 /*8723be*/
#define RTL_PCI_8192EE_DID 0x818B /*8192ee*/
#define RTL_PCI_8821AE_DID 0x8821 /*8821ae*/
#define RTL_PCI_8812AE_DID 0x8812 /*8812ae*/
/*8192 support 16 pages of IO registers*/
#define RTL_MEM_MAPPED_IO_RANGE_8190PCI 0x1000
#define RTL_MEM_MAPPED_IO_RANGE_8192PCIE 0x4000
#define RTL_MEM_MAPPED_IO_RANGE_8192SE 0x4000
#define RTL_MEM_MAPPED_IO_RANGE_8192CE 0x4000
#define RTL_MEM_MAPPED_IO_RANGE_8192DE 0x4000
#define RTL_PCI_REVISION_ID_8190PCI 0x00
#define RTL_PCI_REVISION_ID_8192PCIE 0x01
#define RTL_PCI_REVISION_ID_8192SE 0x10
#define RTL_PCI_REVISION_ID_8192CE 0x1
#define RTL_PCI_REVISION_ID_8192DE 0x0
#define PCI_VENDOR_ID_REALTEK 0x10ec
#define RTL_DEFAULT_HARDWARE_TYPE HARDWARE_TYPE_RTL8192CE
enum pci_bridge_vendor {
PCI_BRIDGE_VENDOR_INTEL = 0x0, /*0b'0000,0001 */
PCI_BRIDGE_VENDOR_ATI, /*0b'0000,0010*/
PCI_BRIDGE_VENDOR_AMD, /*0b'0000,0100*/
PCI_BRIDGE_VENDOR_SIS, /*0b'0000,1000*/
PCI_BRIDGE_VENDOR_UNKNOWN, /*0b'0100,0000*/
PCI_BRIDGE_VENDOR_MAX,
};
struct rtl_pci_capabilities_header {
u8 capability_id;
u8 next;
};
/* In new TRX flow, Buffer_desc is new concept
* But TX wifi info == TX descriptor in old flow
* RX wifi info == RX descriptor in old flow */
struct rtl_tx_buffer_desc {
#if (RTL8192EE_SEG_NUM == 2)
u32 dword[2*(DMA_IS_64BIT + 1)*8]; //seg = 8
#elif (RTL8192EE_SEG_NUM == 1)
u32 dword[2*(DMA_IS_64BIT + 1)*4]; //seg = 4
#elif (RTL8192EE_SEG_NUM == 0)
u32 dword[2*(DMA_IS_64BIT + 1)*2]; //seg = 2
#endif
} __packed;
struct rtl_tx_desc {/*old: tx desc*//*new: tx wifi info*/
u32 dword[16];
} __packed;
struct rtl_rx_buffer_desc { /*rx buffer desc*/
u32 dword[2];
} __packed;
struct rtl_rx_desc { /*old: rx desc*//*new: rx wifi info*/
u32 dword[8];
} __packed;
struct rtl_tx_cmd_desc {
u32 dword[16];
} __packed;
struct rtl8192_tx_ring {
struct rtl_tx_desc *desc; /*tx desc / tx wifi info*/
dma_addr_t dma; /*tx desc dma memory / tx wifi info dma memory*/
unsigned int idx;
unsigned int entries;
struct sk_buff_head queue;
/*add for new trx flow*/
struct rtl_tx_buffer_desc *buffer_desc; /*tx buffer descriptor*/
dma_addr_t buffer_desc_dma; /*tx bufferd desc dma memory*/
u16 avl_desc; /* available_desc_to_write */
u16 cur_tx_wp; /* current_tx_write_point */
u16 cur_tx_rp; /* current_tx_read_point */
};
struct rtl8192_rx_ring {
struct rtl_rx_desc *desc;/*for old trx flow, not uesd in new trx*/
/*dma matches either 'desc' or 'buffer_desc'*/
dma_addr_t dma;
unsigned int idx;
struct sk_buff *rx_buf[RTL_PCI_MAX_RX_COUNT];
/*add for new trx flow*/
struct rtl_rx_buffer_desc *buffer_desc; /*rx buffer descriptor*/
u16 next_rx_rp; /* next_rx_read_point */
};
struct rtl_pci {
struct pci_dev *pdev;
bool irq_enabled;
/*Tx */
struct rtl8192_tx_ring tx_ring[RTL_PCI_MAX_TX_QUEUE_COUNT];
int txringcount[RTL_PCI_MAX_TX_QUEUE_COUNT];
u32 transmit_config;
/*Rx */
struct rtl8192_rx_ring rx_ring[RTL_PCI_MAX_RX_QUEUE];
int rxringcount;
u16 rxbuffersize;
u32 receive_config;
/*irq */
u8 irq_alloc;
u32 irq_mask[2];
u32 sys_irq_mask;
/*Bcn control register setting */
u32 reg_bcn_ctrl_val;
/*ASPM*/ u8 const_pci_aspm;
u8 const_amdpci_aspm;
u8 const_hwsw_rfoff_d3;
u8 const_support_pciaspm;
/*pci-e bridge */
u8 const_hostpci_aspm_setting;
/*pci-e device */
u8 const_devicepci_aspm_setting;
/*If it supports ASPM, Offset[560h] = 0x40,
otherwise Offset[560h] = 0x00. */
bool b_support_aspm;
bool b_support_backdoor;
/*QOS & EDCA */
enum acm_method acm_method;
u16 shortretry_limit;
u16 longretry_limit;
/* MSI support */
bool msi_support;
bool using_msi;
};
struct mp_adapter {
u8 linkctrl_reg;
u8 busnumber;
u8 devnumber;
u8 funcnumber;
u8 pcibridge_busnum;
u8 pcibridge_devnum;
u8 pcibridge_funcnum;
u8 pcibridge_vendor;
u16 pcibridge_vendorid;
u16 pcibridge_deviceid;
u32 pcicfg_addrport;
u8 num4bytes;
u8 pcibridge_pciehdr_offset;
u8 pcibridge_linkctrlreg;
bool amd_l1_patch;
};
struct rtl_pci_priv {
struct rtl_pci dev;
struct mp_adapter ndis_adapter;
struct rtl_led_ctl ledctl;
struct bt_coexist_info btcoexist;
};
#define rtl_pcipriv(hw) (((struct rtl_pci_priv *)(rtl_priv(hw))->priv))
#define rtl_pcidev(pcipriv) (&((pcipriv)->dev))
int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw);
extern struct rtl_intf_ops rtl_pci_ops;
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,8,0))
int rtl_pci_probe(struct pci_dev *pdev,
const struct pci_device_id *id);
#else
int __devinit rtl_pci_probe(struct pci_dev *pdev,
const struct pci_device_id *id);
#endif
void rtl_pci_disconnect(struct pci_dev *pdev);
int rtl_pci_suspend(struct device *dev);
int rtl_pci_resume(struct device *dev);
static inline u8 pci_read8_sync(struct rtl_priv *rtlpriv, u32 addr)
{
return 0xff & readb((u8 __iomem *) rtlpriv->io.pci_mem_start + addr);
}
static inline u16 pci_read16_sync(struct rtl_priv *rtlpriv, u32 addr)
{
return readw((u8 __iomem *) rtlpriv->io.pci_mem_start + addr);
}
static inline u32 pci_read32_sync(struct rtl_priv *rtlpriv, u32 addr)
{
return readl((u8 __iomem *) rtlpriv->io.pci_mem_start + addr);
}
static inline void pci_write8_async(struct rtl_priv *rtlpriv, u32 addr, u8 val)
{
writeb(val, (u8 __iomem *) rtlpriv->io.pci_mem_start + addr);
}
static inline void pci_write16_async(struct rtl_priv *rtlpriv,
u32 addr, u16 val)
{
writew(val, (u8 __iomem *) rtlpriv->io.pci_mem_start + addr);
}
static inline void pci_write32_async(struct rtl_priv *rtlpriv,
u32 addr, u32 val)
{
writel(val, (u8 __iomem *) rtlpriv->io.pci_mem_start + addr);
}
static inline void rtl_pci_raw_write_port_ulong(u32 port, u32 val)
{
outl(val, port);
}
static inline void rtl_pci_raw_write_port_uchar(u32 port, u8 val)
{
outb(val, port);
}
static inline void rtl_pci_raw_read_port_uchar(u32 port, u8 * pval)
{
*pval = inb(port);
}
static inline void rtl_pci_raw_read_port_ushort(u32 port, u16 * pval)
{
*pval = inw(port);
}
static inline void rtl_pci_raw_read_port_ulong(u32 port, u32 * pval)
{
*pval = inl(port);
}
#endif

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/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __REALTEK_RTL_PCI_PS_H__
#define __REALTEK_RTL_PCI_PS_H__
#define MAX_SW_LPS_SLEEP_INTV 5
bool rtl_ps_set_rf_state(struct ieee80211_hw *hw,
enum rf_pwrstate state_toset, u32 changesource,
bool protect_or_not);
bool rtl_ps_enable_nic(struct ieee80211_hw *hw);
bool rtl_ps_disable_nic(struct ieee80211_hw *hw);
void rtl_ips_nic_off(struct ieee80211_hw *hw);
void rtl_ips_nic_on(struct ieee80211_hw *hw);
void rtl_ips_nic_off_wq_callback(void *data);
void rtl_lps_enter(struct ieee80211_hw *hw);
void rtl_lps_leave(struct ieee80211_hw *hw);
void rtl_lps_set_psmode(struct ieee80211_hw *hw, u8 rt_psmode);
void rtl_swlps_beacon(struct ieee80211_hw *hw, void *data, unsigned int len);
void rtl_swlps_wq_callback(void *data);
void rtl_swlps_rfon_wq_callback(void *data);
void rtl_swlps_rf_awake(struct ieee80211_hw *hw);
void rtl_swlps_rf_sleep(struct ieee80211_hw *hw);
void rtl_p2p_ps_cmd(struct ieee80211_hw *hw,u8 p2p_ps_state);
void rtl_p2p_info(struct ieee80211_hw *hw, void *data, unsigned int len);
#endif

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/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "wifi.h"
#include "base.h"
#include "rc.h"
/*
*Finds the highest rate index we can use
*if skb is special data like DHCP/EAPOL, we set should
*it to lowest rate CCK_1M, otherwise we set rate to
*highest rate based on wireless mode used for iwconfig
*show Tx rate.
*/
static u8 _rtl_rc_get_highest_rix(struct rtl_priv *rtlpriv,
struct ieee80211_sta *sta,
struct sk_buff *skb, bool not_data)
{
struct rtl_mac *rtlmac = rtl_mac(rtlpriv);
struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
struct rtl_phy *rtlphy = &(rtlpriv->phy);
struct rtl_sta_info *sta_entry = NULL;
u8 wireless_mode = 0;
/*
*this rate is no use for true rate, firmware
*will control rate at all it just used for
*1.show in iwconfig in B/G mode
*2.in rtl_get_tcb_desc when we check rate is
* 1M we will not use FW rate but user rate.
*/
if (rtlmac->opmode == NL80211_IFTYPE_AP ||
rtlmac->opmode == NL80211_IFTYPE_ADHOC ||
rtlmac->opmode == NL80211_IFTYPE_MESH_POINT) {
if (sta) {
sta_entry = (struct rtl_sta_info *) sta->drv_priv;
wireless_mode = sta_entry->wireless_mode;
} else {
return 0;
}
} else {
wireless_mode = rtlmac->mode;
}
if (rtl_is_special_data(rtlpriv->mac80211.hw, skb, true) || not_data) {
return 0;
} else {
if (rtlhal->current_bandtype == BAND_ON_2_4G) {
if (wireless_mode == WIRELESS_MODE_B) {
return B_MODE_MAX_RIX;
} else if (wireless_mode == WIRELESS_MODE_G) {
return G_MODE_MAX_RIX;
} else {
if (get_rf_type(rtlphy) != RF_2T2R)
return N_MODE_MCS7_RIX;
else
return N_MODE_MCS15_RIX;
}
} else {
if (wireless_mode == WIRELESS_MODE_A) {
return A_MODE_MAX_RIX;
} else {
if (get_rf_type(rtlphy) != RF_2T2R)
return N_MODE_MCS7_RIX;
else
return N_MODE_MCS15_RIX;
}
}
}
}
static void _rtl_rc_rate_set_series(struct rtl_priv *rtlpriv,
struct ieee80211_sta *sta,
struct ieee80211_tx_rate *rate,
struct ieee80211_tx_rate_control *txrc,
u8 tries, char rix, int rtsctsenable,
bool not_data)
{
struct rtl_mac *mac = rtl_mac(rtlpriv);
u8 sgi_20 = 0, sgi_40 = 0;
if (sta) {
sgi_20 = sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20;
sgi_40 = sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40;
}
rate->count = tries;
rate->idx = rix >= 0x00 ? rix : 0x00;
if (!not_data) {
if (txrc->short_preamble)
rate->flags |= IEEE80211_TX_RC_USE_SHORT_PREAMBLE;
if (mac->opmode == NL80211_IFTYPE_AP ||
mac->opmode == NL80211_IFTYPE_ADHOC) {
if (sta && (sta->ht_cap.cap &
IEEE80211_HT_CAP_SUP_WIDTH_20_40))
rate->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
} else {
if (mac->bw_40)
rate->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
}
if (sgi_20 || sgi_40)
rate->flags |= IEEE80211_TX_RC_SHORT_GI;
if (sta && sta->ht_cap.ht_supported)
rate->flags |= IEEE80211_TX_RC_MCS;
}
}
static void rtl_get_rate(void *ppriv, struct ieee80211_sta *sta,
void *priv_sta,
struct ieee80211_tx_rate_control *txrc)
{
struct rtl_priv *rtlpriv = ppriv;
struct sk_buff *skb = txrc->skb;
struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
struct ieee80211_tx_rate *rates = tx_info->control.rates;
__le16 fc = rtl_get_fc(skb);
u8 try_per_rate, i, rix;
bool not_data = !ieee80211_is_data(fc);
if (rate_control_send_low(sta, priv_sta, txrc))
return;
rix = _rtl_rc_get_highest_rix(rtlpriv, sta, skb, not_data);
try_per_rate = 1;
_rtl_rc_rate_set_series(rtlpriv, sta, &rates[0], txrc,
try_per_rate, rix, 1, not_data);
if (!not_data) {
for (i = 1; i < 4; i++)
_rtl_rc_rate_set_series(rtlpriv, sta, &rates[i],
txrc, i, (rix - i), 1,
not_data);
}
}
static bool _rtl_tx_aggr_check(struct rtl_priv *rtlpriv,
struct rtl_sta_info *sta_entry, u16 tid)
{
struct rtl_mac *mac = rtl_mac(rtlpriv);
if (mac->act_scanning)
return false;
if (mac->opmode == NL80211_IFTYPE_STATION &&
mac->cnt_after_linked < 3)
return false;
if (sta_entry->tids[tid].agg.agg_state == RTL_AGG_STOP)
return true;
return false;
}
/*mac80211 Rate Control callbacks*/
static void rtl_tx_status(void *ppriv,
struct ieee80211_supported_band *sband,
struct ieee80211_sta *sta, void *priv_sta,
struct sk_buff *skb)
{
struct rtl_priv *rtlpriv = ppriv;
struct rtl_mac *mac = rtl_mac(rtlpriv);
struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
__le16 fc = rtl_get_fc(skb);
struct rtl_sta_info *sta_entry;
if (!priv_sta || !ieee80211_is_data(fc))
return;
if (rtl_is_special_data(mac->hw, skb, true))
return;
if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) ||
is_broadcast_ether_addr(ieee80211_get_DA(hdr)))
return;
if (sta) {
/* Check if aggregation has to be enabled for this tid */
sta_entry = (struct rtl_sta_info *) sta->drv_priv;
if ((sta->ht_cap.ht_supported == true) &&
!(skb->protocol == cpu_to_be16(ETH_P_PAE))) {
if (ieee80211_is_data_qos(fc)) {
u8 tid = rtl_get_tid(skb);
if (_rtl_tx_aggr_check(rtlpriv, sta_entry,
tid)) {
sta_entry->tids[tid].agg.agg_state =
RTL_AGG_PROGRESS;
/*<delete in kernel start>*/
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38))
/*<delete in kernel end>*/
ieee80211_start_tx_ba_session(sta, tid,
5000);
/*<delete in kernel start>*/
#else
ieee80211_start_tx_ba_session(sta, tid);
#endif
/*<delete in kernel end>*/
}
}
}
}
}
static void rtl_rate_init(void *ppriv,
struct ieee80211_supported_band *sband,
struct cfg80211_chan_def *chandef,
struct ieee80211_sta *sta, void *priv_sta)
{
}
#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,5,0))
static void rtl_rate_update(void *ppriv,
struct ieee80211_supported_band *sband,
struct ieee80211_sta *sta, void *priv_sta,
u32 changed,
enum nl80211_channel_type oper_chan_type)
{
}
#else
static void rtl_rate_update(void *ppriv,
struct ieee80211_supported_band *sband,
struct cfg80211_chan_def *chandef,
struct ieee80211_sta *sta, void *priv_sta,
u32 changed)
{
}
#endif
static void *rtl_rate_alloc(struct ieee80211_hw *hw, struct dentry *debugfsdir)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
return rtlpriv;
}
static void rtl_rate_free(void *rtlpriv)
{
return;
}
static void *rtl_rate_alloc_sta(void *ppriv,
struct ieee80211_sta *sta, gfp_t gfp)
{
struct rtl_priv *rtlpriv = ppriv;
struct rtl_rate_priv *rate_priv;
rate_priv = kzalloc(sizeof(struct rtl_rate_priv), gfp);
if (!rate_priv) {
RT_TRACE(COMP_ERR, DBG_EMERG,
("Unable to allocate private rc structure\n"));
return NULL;
}
rtlpriv->rate_priv = rate_priv;
return rate_priv;
}
static void rtl_rate_free_sta(void *rtlpriv,
struct ieee80211_sta *sta, void *priv_sta)
{
struct rtl_rate_priv *rate_priv = priv_sta;
kfree(rate_priv);
}
static struct rate_control_ops rtl_rate_ops = {
.module = NULL,
.name = "rtl_rc",
.alloc = rtl_rate_alloc,
.free = rtl_rate_free,
.alloc_sta = rtl_rate_alloc_sta,
.free_sta = rtl_rate_free_sta,
.rate_init = rtl_rate_init,
.rate_update = rtl_rate_update,
.tx_status = rtl_tx_status,
.get_rate = rtl_get_rate,
};
int rtl_rate_control_register(void)
{
return ieee80211_rate_control_register(&rtl_rate_ops);
}
void rtl_rate_control_unregister(void)
{
ieee80211_rate_control_unregister(&rtl_rate_ops);
}

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/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __RTL_RC_H__
#define __RTL_RC_H__
#define B_MODE_MAX_RIX 3
#define G_MODE_MAX_RIX 11
#define A_MODE_MAX_RIX 7
/* in mac80211 mcs0-mcs15 is idx0-idx15*/
#define N_MODE_MCS7_RIX 7
#define N_MODE_MCS15_RIX 15
struct rtl_rate_priv {
u8 ht_cap;
};
int rtl_rate_control_register(void);
void rtl_rate_control_unregister(void);
#endif

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/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "wifi.h"
#include "regd.h"
static struct country_code_to_enum_rd allCountries[] = {
{COUNTRY_CODE_FCC, "US"},
{COUNTRY_CODE_IC, "US"},
{COUNTRY_CODE_ETSI, "EC"},
{COUNTRY_CODE_SPAIN, "EC"},
{COUNTRY_CODE_FRANCE, "EC"},
{COUNTRY_CODE_MKK, "JP"},
{COUNTRY_CODE_MKK1, "JP"},
{COUNTRY_CODE_ISRAEL, "EC"},
{COUNTRY_CODE_TELEC, "JP"},
{COUNTRY_CODE_MIC, "JP"},
{COUNTRY_CODE_GLOBAL_DOMAIN, "JP"},
{COUNTRY_CODE_WORLD_WIDE_13, "EC"},
{COUNTRY_CODE_TELEC_NETGEAR, "EC"},
};
/*
*Only these channels all allow active
*scan on all world regulatory domains
*/
#define RTL819x_2GHZ_CH01_11 \
REG_RULE(2412-10, 2462+10, 40, 0, 20, 0)
/*
*We enable active scan on these a case
*by case basis by regulatory domain
*/
#define RTL819x_2GHZ_CH12_13 \
REG_RULE(2467-10, 2472+10, 40, 0, 20,\
NL80211_RRF_PASSIVE_SCAN)
#define RTL819x_2GHZ_CH14 \
REG_RULE(2484-10, 2484+10, 40, 0, 20, \
NL80211_RRF_PASSIVE_SCAN | \
NL80211_RRF_NO_OFDM)
/* 5G chan 36 - chan 64*/
#define RTL819x_5GHZ_5150_5350 \
REG_RULE(5150-10, 5350+10, 40, 0, 30, \
NL80211_RRF_PASSIVE_SCAN | \
NL80211_RRF_NO_IBSS)
/* 5G chan 100 - chan 165*/
#define RTL819x_5GHZ_5470_5850 \
REG_RULE(5470-10, 5850+10, 40, 0, 30, \
NL80211_RRF_PASSIVE_SCAN | \
NL80211_RRF_NO_IBSS)
/* 5G chan 149 - chan 165*/
#define RTL819x_5GHZ_5725_5850 \
REG_RULE(5725-10, 5850+10, 40, 0, 30, \
NL80211_RRF_PASSIVE_SCAN | \
NL80211_RRF_NO_IBSS)
#define RTL819x_5GHZ_ALL \
RTL819x_5GHZ_5150_5350, RTL819x_5GHZ_5470_5850
static const struct ieee80211_regdomain rtl_regdom_11 = {
.n_reg_rules = 1,
.alpha2 = "99",
.reg_rules = {
RTL819x_2GHZ_CH01_11,
}
};
static const struct ieee80211_regdomain rtl_regdom_12_13 = {
.n_reg_rules = 2,
.alpha2 = "99",
.reg_rules = {
RTL819x_2GHZ_CH01_11,
RTL819x_2GHZ_CH12_13,
}
};
static const struct ieee80211_regdomain rtl_regdom_no_midband = {
.n_reg_rules = 3,
.alpha2 = "99",
.reg_rules = {
RTL819x_2GHZ_CH01_11,
RTL819x_5GHZ_5150_5350,
RTL819x_5GHZ_5725_5850,
}
};
static const struct ieee80211_regdomain rtl_regdom_60_64 = {
.n_reg_rules = 3,
.alpha2 = "99",
.reg_rules = {
RTL819x_2GHZ_CH01_11,
RTL819x_2GHZ_CH12_13,
RTL819x_5GHZ_5725_5850,
}
};
static const struct ieee80211_regdomain rtl_regdom_14_60_64 = {
.n_reg_rules = 4,
.alpha2 = "99",
.reg_rules = {
RTL819x_2GHZ_CH01_11,
RTL819x_2GHZ_CH12_13,
RTL819x_2GHZ_CH14,
RTL819x_5GHZ_5725_5850,
}
};
static const struct ieee80211_regdomain rtl_regdom_14 = {
.n_reg_rules = 3,
.alpha2 = "99",
.reg_rules = {
RTL819x_2GHZ_CH01_11,
RTL819x_2GHZ_CH12_13,
RTL819x_2GHZ_CH14,
}
};
static bool _rtl_is_radar_freq(u16 center_freq)
{
return (center_freq >= 5260 && center_freq <= 5700);
}
static void _rtl_reg_apply_beaconing_flags(struct wiphy *wiphy,
enum nl80211_reg_initiator initiator)
{
enum ieee80211_band band;
struct ieee80211_supported_band *sband;
const struct ieee80211_reg_rule *reg_rule;
struct ieee80211_channel *ch;
unsigned int i;
#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,9,0))
u32 bandwidth = 0;
int r;
#endif
for (band = 0; band < IEEE80211_NUM_BANDS; band++) {
if (!wiphy->bands[band])
continue;
sband = wiphy->bands[band];
for (i = 0; i < sband->n_channels; i++) {
ch = &sband->channels[i];
if (_rtl_is_radar_freq(ch->center_freq) ||
(ch->flags & IEEE80211_CHAN_RADAR))
continue;
if (initiator == NL80211_REGDOM_SET_BY_COUNTRY_IE) {
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,9,0))
reg_rule = freq_reg_info(wiphy, ch->center_freq);
if (IS_ERR(reg_rule))
continue;
#else
r = freq_reg_info(wiphy, ch->center_freq,
bandwidth, &reg_rule);
if (r)
continue;
#endif
/*
*If 11d had a rule for this channel ensure
*we enable adhoc/beaconing if it allows us to
*use it. Note that we would have disabled it
*by applying our static world regdomain by
*default during init, prior to calling our
*regulatory_hint().
*/
if (!(reg_rule->flags & NL80211_RRF_NO_IBSS))
ch->flags &= ~IEEE80211_CHAN_NO_IBSS;
if (!(reg_rule->flags &
NL80211_RRF_PASSIVE_SCAN))
ch->flags &=
~IEEE80211_CHAN_PASSIVE_SCAN;
} else {
if (ch->beacon_found)
ch->flags &= ~(IEEE80211_CHAN_NO_IBSS |
IEEE80211_CHAN_PASSIVE_SCAN);
}
}
}
}
/* Allows active scan scan on Ch 12 and 13 */
static void _rtl_reg_apply_active_scan_flags(struct wiphy *wiphy,
enum nl80211_reg_initiator
initiator)
{
struct ieee80211_supported_band *sband;
struct ieee80211_channel *ch;
const struct ieee80211_reg_rule *reg_rule;
#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,9,0))
u32 bandwidth = 0;
int r;
#endif
if (!wiphy->bands[IEEE80211_BAND_2GHZ])
return;
sband = wiphy->bands[IEEE80211_BAND_2GHZ];
/*
*If no country IE has been received always enable active scan
*on these channels. This is only done for specific regulatory SKUs
*/
if (initiator != NL80211_REGDOM_SET_BY_COUNTRY_IE) {
ch = &sband->channels[11]; /* CH 12 */
if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
ch = &sband->channels[12]; /* CH 13 */
if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
return;
}
/*
*If a country IE has been recieved check its rule for this
*channel first before enabling active scan. The passive scan
*would have been enforced by the initial processing of our
*custom regulatory domain.
*/
ch = &sband->channels[11]; /* CH 12 */
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,9,0))
reg_rule = freq_reg_info(wiphy, ch->center_freq);
if (!IS_ERR(reg_rule)) {
#else
r = freq_reg_info(wiphy, ch->center_freq, bandwidth, &reg_rule);
if (!r) {
#endif
if (!(reg_rule->flags & NL80211_RRF_PASSIVE_SCAN))
if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
}
ch = &sband->channels[12]; /* CH 13 */
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,9,0))
reg_rule = freq_reg_info(wiphy, ch->center_freq);
if (!IS_ERR(reg_rule)) {
#else
r = freq_reg_info(wiphy, ch->center_freq, bandwidth, &reg_rule);
if (!r) {
#endif
if (!(reg_rule->flags & NL80211_RRF_PASSIVE_SCAN))
if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
}
}
/*
*Always apply Radar/DFS rules on
*freq range 5260 MHz - 5700 MHz
*/
static void _rtl_reg_apply_radar_flags(struct wiphy *wiphy)
{
struct ieee80211_supported_band *sband;
struct ieee80211_channel *ch;
unsigned int i;
if (!wiphy->bands[IEEE80211_BAND_5GHZ])
return;
sband = wiphy->bands[IEEE80211_BAND_5GHZ];
for (i = 0; i < sband->n_channels; i++) {
ch = &sband->channels[i];
if (!_rtl_is_radar_freq(ch->center_freq))
continue;
/*
*We always enable radar detection/DFS on this
*frequency range. Additionally we also apply on
*this frequency range:
*- If STA mode does not yet have DFS supports disable
* active scanning
*- If adhoc mode does not support DFS yet then disable
* adhoc in the frequency.
*- If AP mode does not yet support radar detection/DFS
*do not allow AP mode
*/
if (!(ch->flags & IEEE80211_CHAN_DISABLED))
ch->flags |= IEEE80211_CHAN_RADAR |
IEEE80211_CHAN_NO_IBSS |
IEEE80211_CHAN_PASSIVE_SCAN;
}
}
static void _rtl_reg_apply_world_flags(struct wiphy *wiphy,
enum nl80211_reg_initiator initiator,
struct rtl_regulatory *reg)
{
_rtl_reg_apply_beaconing_flags(wiphy, initiator);
_rtl_reg_apply_active_scan_flags(wiphy, initiator);
return;
}
static void _rtl_dump_channel_map(struct wiphy *wiphy)
{
enum ieee80211_band band;
struct ieee80211_supported_band *sband;
struct ieee80211_channel *ch;
unsigned int i;
for (band = 0; band < IEEE80211_NUM_BANDS; band++) {
if (!wiphy->bands[band])
continue;
sband = wiphy->bands[band];
for (i = 0; i < sband->n_channels; i++)
ch = &sband->channels[i];
}
}
static int _rtl_reg_notifier_apply(struct wiphy *wiphy,
struct regulatory_request *request,
struct rtl_regulatory *reg)
{
/* We always apply this */
_rtl_reg_apply_radar_flags(wiphy);
switch (request->initiator) {
case NL80211_REGDOM_SET_BY_DRIVER:
case NL80211_REGDOM_SET_BY_CORE:
case NL80211_REGDOM_SET_BY_USER:
break;
case NL80211_REGDOM_SET_BY_COUNTRY_IE:
_rtl_reg_apply_world_flags(wiphy, request->initiator, reg);
break;
}
_rtl_dump_channel_map(wiphy);
return 0;
}
static const struct ieee80211_regdomain *_rtl_regdomain_select(
struct rtl_regulatory *reg)
{
switch (reg->country_code) {
case COUNTRY_CODE_FCC:
return &rtl_regdom_no_midband;
case COUNTRY_CODE_IC:
return &rtl_regdom_11;
case COUNTRY_CODE_ETSI:
case COUNTRY_CODE_TELEC_NETGEAR:
return &rtl_regdom_60_64;
case COUNTRY_CODE_SPAIN:
case COUNTRY_CODE_FRANCE:
case COUNTRY_CODE_ISRAEL:
case COUNTRY_CODE_WORLD_WIDE_13:
return &rtl_regdom_12_13;
case COUNTRY_CODE_MKK:
case COUNTRY_CODE_MKK1:
case COUNTRY_CODE_TELEC:
case COUNTRY_CODE_MIC:
return &rtl_regdom_14_60_64;
case COUNTRY_CODE_GLOBAL_DOMAIN:
return &rtl_regdom_14;
default:
return &rtl_regdom_no_midband;
}
}
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,9,0))
static int _rtl_regd_init_wiphy(struct rtl_regulatory *reg,
struct wiphy *wiphy,
void (*reg_notifier) (struct wiphy * wiphy,
struct regulatory_request *
request))
#else
static int _rtl_regd_init_wiphy(struct rtl_regulatory *reg,
struct wiphy *wiphy,
int (*reg_notifier) (struct wiphy * wiphy,
struct regulatory_request *
request))
#endif
{
const struct ieee80211_regdomain *regd;
wiphy->reg_notifier = reg_notifier;
wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY;
wiphy->flags &= ~WIPHY_FLAG_STRICT_REGULATORY;
wiphy->flags &= ~WIPHY_FLAG_DISABLE_BEACON_HINTS;
regd = _rtl_regdomain_select(reg);
wiphy_apply_custom_regulatory(wiphy, regd);
_rtl_reg_apply_radar_flags(wiphy);
_rtl_reg_apply_world_flags(wiphy, NL80211_REGDOM_SET_BY_DRIVER, reg);
return 0;
}
static struct country_code_to_enum_rd *_rtl_regd_find_country(u16 countrycode)
{
int i;
for (i = 0; i < ARRAY_SIZE(allCountries); i++) {
if (allCountries[i].countrycode == countrycode)
return &allCountries[i];
}
return NULL;
}
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,9,0))
int rtl_regd_init(struct ieee80211_hw *hw,
void (*reg_notifier) (struct wiphy *wiphy,
struct regulatory_request *request))
#else
int rtl_regd_init(struct ieee80211_hw *hw,
int (*reg_notifier) (struct wiphy *wiphy,
struct regulatory_request *request))
#endif
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct wiphy *wiphy = hw->wiphy;
struct country_code_to_enum_rd *country = NULL;
if (wiphy == NULL || &rtlpriv->regd == NULL)
return -EINVAL;
/* init country_code from efuse channel plan */
rtlpriv->regd.country_code = rtlpriv->efuse.channel_plan;
RT_TRACE(COMP_REGD, DBG_TRACE,
(KERN_DEBUG "rtl: EEPROM regdomain: 0x%0x\n",
rtlpriv->regd.country_code));
if (rtlpriv->regd.country_code >= COUNTRY_CODE_MAX) {
RT_TRACE(COMP_REGD, DBG_DMESG,
(KERN_DEBUG "rtl: EEPROM indicates invalid contry code"
"world wide 13 should be used\n"));
rtlpriv->regd.country_code = COUNTRY_CODE_WORLD_WIDE_13;
}
country = _rtl_regd_find_country(rtlpriv->regd.country_code);
if (country) {
rtlpriv->regd.alpha2[0] = country->iso_name[0];
rtlpriv->regd.alpha2[1] = country->iso_name[1];
} else {
rtlpriv->regd.alpha2[0] = '0';
rtlpriv->regd.alpha2[1] = '0';
}
RT_TRACE(COMP_REGD, DBG_TRACE,
(KERN_DEBUG "rtl: Country alpha2 being used: %c%c\n",
rtlpriv->regd.alpha2[0], rtlpriv->regd.alpha2[1]));
_rtl_regd_init_wiphy(&rtlpriv->regd, wiphy, reg_notifier);
return 0;
}
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,9,0))
void rtl_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
{
struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
struct rtl_priv *rtlpriv = rtl_priv(hw);
RT_TRACE(COMP_REGD, DBG_LOUD, ("\n"));
_rtl_reg_notifier_apply(wiphy, request, &rtlpriv->regd);
}
#else
int rtl_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
{
struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
struct rtl_priv *rtlpriv = rtl_priv(hw);
RT_TRACE(COMP_REGD, DBG_LOUD, ("\n"));
return _rtl_reg_notifier_apply(wiphy, request, &rtlpriv->regd);
}
#endif

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drivers/staging/rtl8821ae/regd.h Normal file
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/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __RTL_REGD_H__
#define __RTL_REGD_H__
#define IEEE80211_CHAN_NO_IBSS 1<<2
#define IEEE80211_CHAN_PASSIVE_SCAN 1<<1
#define WIPHY_FLAG_CUSTOM_REGULATORY BIT(0)
#define WIPHY_FLAG_STRICT_REGULATORY BIT(1)
#define WIPHY_FLAG_DISABLE_BEACON_HINTS BIT(2)
struct country_code_to_enum_rd {
u16 countrycode;
const char *iso_name;
};
enum country_code_type_t {
COUNTRY_CODE_FCC = 0,
COUNTRY_CODE_IC = 1,
COUNTRY_CODE_ETSI = 2,
COUNTRY_CODE_SPAIN = 3,
COUNTRY_CODE_FRANCE = 4,
COUNTRY_CODE_MKK = 5,
COUNTRY_CODE_MKK1 = 6,
COUNTRY_CODE_ISRAEL = 7,
COUNTRY_CODE_TELEC = 8,
COUNTRY_CODE_MIC = 9,
COUNTRY_CODE_GLOBAL_DOMAIN = 10,
COUNTRY_CODE_WORLD_WIDE_13 = 11,
COUNTRY_CODE_TELEC_NETGEAR = 12,
/*add new channel plan above this line */
COUNTRY_CODE_MAX
};
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,9,0))
int rtl_regd_init(struct ieee80211_hw *hw,
void (*reg_notifier) (struct wiphy *wiphy,
struct regulatory_request *request));
void rtl_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request);
#else
int rtl_regd_init(struct ieee80211_hw *hw,
int (*reg_notifier) (struct wiphy *wiphy,
struct regulatory_request *request));
int rtl_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request);
#endif
#endif

87
drivers/staging/rtl8821ae/rtl8821ae/btc.h Normal file
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/******************************************************************************
**
** Copyright(c) 2009-2010 Realtek Corporation.
**
** This program is free software; you can redistribute it and/or modify it
** under the terms of version 2 of the GNU General Public License as
** published by the Free Software Foundation.
**
** This program is distributed in the hope that it will be useful, but WITHOUT
** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
** FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
** more details.
**
** You should have received a copy of the GNU General Public License along with
** this program; if not, write to the Free Software Foundation, Inc.,
** 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
**
** The full GNU General Public License is included in this distribution in the
** file called LICENSE.
**
** Contact Information:
** wlanfae <wlanfae@realtek.com>
** Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
** Hsinchu 300, Taiwan.
** Larry Finger <Larry.Finger@lwfinger.net>
**
******************************************************************************/
#ifndef __RTL8821AE_BTC_H__
#define __RTL8821AE_BTC_H__
#include "../wifi.h"
#include "hal_bt_coexist.h"
struct bt_coexist_c2h_info {
u8 no_parse_c2h;
u8 has_c2h;
};
struct btdm_8821ae {
bool b_all_off;
bool b_agc_table_en;
bool b_adc_back_off_on;
bool b2_ant_hid_en;
bool b_low_penalty_rate_adaptive;
bool b_rf_rx_lpf_shrink;
bool b_reject_aggre_pkt;
bool b_tra_tdma_on;
u8 tra_tdma_nav;
u8 tra_tdma_ant;
bool b_tdma_on;
u8 tdma_ant;
u8 tdma_nav;
u8 tdma_dac_swing;
u8 fw_dac_swing_lvl;
bool b_ps_tdma_on;
u8 ps_tdma_byte[5];
bool b_pta_on;
u32 val_0x6c0;
u32 val_0x6c8;
u32 val_0x6cc;
bool b_sw_dac_swing_on;
u32 sw_dac_swing_lvl;
u32 wlan_act_hi;
u32 wlan_act_lo;
u32 bt_retry_index;
bool b_dec_bt_pwr;
bool b_ignore_wlan_act;
};
struct bt_coexist_8821ae {
u32 high_priority_tx;
u32 high_priority_rx;
u32 low_priority_tx;
u32 low_priority_rx;
u8 c2h_bt_info;
bool b_c2h_bt_info_req_sent;
bool b_c2h_bt_inquiry_page;
u32 bt_inq_page_start_time;
u8 bt_retry_cnt;
u8 c2h_bt_info_original;
u8 bt_inquiry_page_cnt;
struct btdm_8821ae btdm;
};
#endif

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drivers/staging/rtl8821ae/rtl8821ae/def.h Normal file
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/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __RTL8821AE_DEF_H__
#define __RTL8821AE_DEF_H__
/*--------------------------Define -------------------------------------------*/
/* BIT 7 HT Rate*/
/*TxHT = 0*/
#define MGN_1M 0x02
#define MGN_2M 0x04
#define MGN_5_5M 0x0b
#define MGN_11M 0x16
#define MGN_6M 0x0c
#define MGN_9M 0x12
#define MGN_12M 0x18
#define MGN_18M 0x24
#define MGN_24M 0x30
#define MGN_36M 0x48
#define MGN_48M 0x60
#define MGN_54M 0x6c
// TxHT = 1
#define MGN_MCS0 0x80
#define MGN_MCS1 0x81
#define MGN_MCS2 0x82
#define MGN_MCS3 0x83
#define MGN_MCS4 0x84
#define MGN_MCS5 0x85
#define MGN_MCS6 0x86
#define MGN_MCS7 0x87
#define MGN_MCS8 0x88
#define MGN_MCS9 0x89
#define MGN_MCS10 0x8a
#define MGN_MCS11 0x8b
#define MGN_MCS12 0x8c
#define MGN_MCS13 0x8d
#define MGN_MCS14 0x8e
#define MGN_MCS15 0x8f
//VHT rate
#define MGN_VHT1SS_MCS0 0x90
#define MGN_VHT1SS_MCS1 0x91
#define MGN_VHT1SS_MCS2 0x92
#define MGN_VHT1SS_MCS3 0x93
#define MGN_VHT1SS_MCS4 0x94
#define MGN_VHT1SS_MCS5 0x95
#define MGN_VHT1SS_MCS6 0x96
#define MGN_VHT1SS_MCS7 0x97
#define MGN_VHT1SS_MCS8 0x98
#define MGN_VHT1SS_MCS9 0x99
#define MGN_VHT2SS_MCS0 0x9a
#define MGN_VHT2SS_MCS1 0x9b
#define MGN_VHT2SS_MCS2 0x9c
#define MGN_VHT2SS_MCS3 0x9d
#define MGN_VHT2SS_MCS4 0x9e
#define MGN_VHT2SS_MCS5 0x9f
#define MGN_VHT2SS_MCS6 0xa0
#define MGN_VHT2SS_MCS7 0xa1
#define MGN_VHT2SS_MCS8 0xa2
#define MGN_VHT2SS_MCS9 0xa3
#define MGN_VHT3SS_MCS0 0xa4
#define MGN_VHT3SS_MCS1 0xa5
#define MGN_VHT3SS_MCS2 0xa6
#define MGN_VHT3SS_MCS3 0xa7
#define MGN_VHT3SS_MCS4 0xa8
#define MGN_VHT3SS_MCS5 0xa9
#define MGN_VHT3SS_MCS6 0xaa
#define MGN_VHT3SS_MCS7 0xab
#define MGN_VHT3SS_MCS8 0xac
#define MGN_VHT3SS_MCS9 0xad
#define MGN_MCS0_SG 0xc0
#define MGN_MCS1_SG 0xc1
#define MGN_MCS2_SG 0xc2
#define MGN_MCS3_SG 0xc3
#define MGN_MCS4_SG 0xc4
#define MGN_MCS5_SG 0xc5
#define MGN_MCS6_SG 0xc6
#define MGN_MCS7_SG 0xc7
#define MGN_MCS8_SG 0xc8
#define MGN_MCS9_SG 0xc9
#define MGN_MCS10_SG 0xca
#define MGN_MCS11_SG 0xcb
#define MGN_MCS12_SG 0xcc
#define MGN_MCS13_SG 0xcd
#define MGN_MCS14_SG 0xce
#define MGN_MCS15_SG 0xcf
#define MGN_UNKNOWN 0xff
/* 30 ms */
#define WIFI_NAV_UPPER_US 30000
#define HAL_92C_NAV_UPPER_UNIT 128
#define HAL_RETRY_LIMIT_INFRA 48
#define HAL_RETRY_LIMIT_AP_ADHOC 7
#define RESET_DELAY_8185 20
#define RT_IBSS_INT_MASKS (IMR_BCNINT | IMR_TBDOK | IMR_TBDER)
#define RT_AC_INT_MASKS (IMR_VIDOK | IMR_VODOK | IMR_BEDOK|IMR_BKDOK)
#define NUM_OF_FIRMWARE_QUEUE 10
#define NUM_OF_PAGES_IN_FW 0x100
#define NUM_OF_PAGE_IN_FW_QUEUE_BK 0x07
#define NUM_OF_PAGE_IN_FW_QUEUE_BE 0x07
#define NUM_OF_PAGE_IN_FW_QUEUE_VI 0x07
#define NUM_OF_PAGE_IN_FW_QUEUE_VO 0x07
#define NUM_OF_PAGE_IN_FW_QUEUE_HCCA 0x0
#define NUM_OF_PAGE_IN_FW_QUEUE_CMD 0x0
#define NUM_OF_PAGE_IN_FW_QUEUE_MGNT 0x02
#define NUM_OF_PAGE_IN_FW_QUEUE_HIGH 0x02
#define NUM_OF_PAGE_IN_FW_QUEUE_BCN 0x2
#define NUM_OF_PAGE_IN_FW_QUEUE_PUB 0xA1
#define NUM_OF_PAGE_IN_FW_QUEUE_BK_DTM 0x026
#define NUM_OF_PAGE_IN_FW_QUEUE_BE_DTM 0x048
#define NUM_OF_PAGE_IN_FW_QUEUE_VI_DTM 0x048
#define NUM_OF_PAGE_IN_FW_QUEUE_VO_DTM 0x026
#define NUM_OF_PAGE_IN_FW_QUEUE_PUB_DTM 0x00
#define MAX_RX_DMA_BUFFER_SIZE 0x3E80
#define MAX_LINES_HWCONFIG_TXT 1000
#define MAX_BYTES_LINE_HWCONFIG_TXT 256
#define SW_THREE_WIRE 0
#define HW_THREE_WIRE 2
#define BT_DEMO_BOARD 0
#define BT_QA_BOARD 1
#define BT_FPGA 2
#define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0
#define HAL_PRIME_CHNL_OFFSET_LOWER 1
#define HAL_PRIME_CHNL_OFFSET_UPPER 2
#define MAX_H2C_QUEUE_NUM 10
#define RX_MPDU_QUEUE 0
#define RX_CMD_QUEUE 1
#define RX_MAX_QUEUE 2
#define AC2QUEUEID(_AC) (_AC)
#define C2H_RX_CMD_HDR_LEN 8
#define GET_C2H_CMD_CMD_LEN(__prxhdr) \
LE_BITS_TO_4BYTE((__prxhdr), 0, 16)
#define GET_C2H_CMD_ELEMENT_ID(__prxhdr) \
LE_BITS_TO_4BYTE((__prxhdr), 16, 8)
#define GET_C2H_CMD_CMD_SEQ(__prxhdr) \
LE_BITS_TO_4BYTE((__prxhdr), 24, 7)
#define GET_C2H_CMD_CONTINUE(__prxhdr) \
LE_BITS_TO_4BYTE((__prxhdr), 31, 1)
#define GET_C2H_CMD_CONTENT(__prxhdr) \
((u8*)(__prxhdr) + C2H_RX_CMD_HDR_LEN)
#define GET_C2H_CMD_FEEDBACK_ELEMENT_ID(__pcmdfbhdr) \
LE_BITS_TO_4BYTE((__pcmdfbhdr), 0, 8)
#define GET_C2H_CMD_FEEDBACK_CCX_LEN(__pcmdfbhdr) \
LE_BITS_TO_4BYTE((__pcmdfbhdr), 8, 8)
#define GET_C2H_CMD_FEEDBACK_CCX_CMD_CNT(__pcmdfbhdr) \
LE_BITS_TO_4BYTE((__pcmdfbhdr), 16, 16)
#define GET_C2H_CMD_FEEDBACK_CCX_MAC_ID(__pcmdfbhdr) \
LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 0, 5)
#define GET_C2H_CMD_FEEDBACK_CCX_VALID(__pcmdfbhdr) \
LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 7, 1)
#define GET_C2H_CMD_FEEDBACK_CCX_RETRY_CNT(__pcmdfbhdr) \
LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 8, 5)
#define GET_C2H_CMD_FEEDBACK_CCX_TOK(__pcmdfbhdr) \
LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 15, 1)
#define GET_C2H_CMD_FEEDBACK_CCX_QSEL(__pcmdfbhdr) \
LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 16, 4)
#define GET_C2H_CMD_FEEDBACK_CCX_SEQ(__pcmdfbhdr) \
LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 20, 12)
#define CHIP_BONDING_IDENTIFIER(_value) (((_value)>>22)&0x3)
#define CHIP_8812 BIT(2)
#define CHIP_8821 (BIT(0)|BIT(2))
#define CHIP_8821A (BIT(0)|BIT(2))
#define NORMAL_CHIP BIT(3)
#define RF_TYPE_1T1R (~(BIT(4)|BIT(5)|BIT(6)))
#define RF_TYPE_1T2R BIT(4)
#define RF_TYPE_2T2R BIT(5)
#define CHIP_VENDOR_UMC BIT(7)
#define B_CUT_VERSION BIT(12)
#define C_CUT_VERSION BIT(13)
#define D_CUT_VERSION ((BIT(12)|BIT(13)))
#define E_CUT_VERSION BIT(14)
#define RF_RL_ID (BIT(31)|BIT(30)|BIT(29)|BIT(28))
enum version_8821ae {
VERSION_TEST_CHIP_1T1R_8812 = 0x0004,
VERSION_TEST_CHIP_2T2R_8812 = 0x0024,
VERSION_NORMAL_TSMC_CHIP_1T1R_8812 = 0x100c,
VERSION_NORMAL_TSMC_CHIP_2T2R_8812 = 0x102c,
VERSION_NORMAL_TSMC_CHIP_1T1R_8812_C_CUT = 0x200c,
VERSION_NORMAL_TSMC_CHIP_2T2R_8812_C_CUT = 0x202c,
VERSION_TEST_CHIP_8821 = 0x0005,
VERSION_NORMAL_TSMC_CHIP_8821 = 0x000d,
VERSION_NORMAL_TSMC_CHIP_8821_B_CUT = 0x100d,
VERSION_UNKNOWN = 0xFF,
};
enum vht_data_sc{
VHT_DATA_SC_DONOT_CARE = 0,
VHT_DATA_SC_20_UPPER_OF_80MHZ = 1,
VHT_DATA_SC_20_LOWER_OF_80MHZ = 2,
VHT_DATA_SC_20_UPPERST_OF_80MHZ = 3,
VHT_DATA_SC_20_LOWEST_OF_80MHZ = 4,
VHT_DATA_SC_20_RECV1 = 5,
VHT_DATA_SC_20_RECV2 = 6,
VHT_DATA_SC_20_RECV3 = 7,
VHT_DATA_SC_20_RECV4 = 8,
VHT_DATA_SC_40_UPPER_OF_80MHZ = 9,
VHT_DATA_SC_40_LOWER_OF_80MHZ = 10,
};
/* MASK */
#define IC_TYPE_MASK (BIT(0)|BIT(1)|BIT(2))
#define CHIP_TYPE_MASK BIT(3)
#define RF_TYPE_MASK (BIT(4)|BIT(5)|BIT(6))
#define MANUFACTUER_MASK BIT(7)
#define ROM_VERSION_MASK (BIT(11)|BIT(10)|BIT(9)|BIT(8))
#define CUT_VERSION_MASK (BIT(15)|BIT(14)|BIT(13)|BIT(12))
/* Get element */
#define GET_CVID_IC_TYPE(version) ((version) & IC_TYPE_MASK)
#define GET_CVID_CHIP_TYPE(version) ((version) & CHIP_TYPE_MASK)
#define GET_CVID_RF_TYPE(version) ((version) & RF_TYPE_MASK)
#define GET_CVID_MANUFACTUER(version) ((version) & MANUFACTUER_MASK)
#define GET_CVID_ROM_VERSION(version) ((version) & ROM_VERSION_MASK)
#define GET_CVID_CUT_VERSION(version) ((version) & CUT_VERSION_MASK)
#define IS_1T1R(version) ((GET_CVID_RF_TYPE(version))? false : true)
#define IS_1T2R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_1T2R)\
? true : false)
#define IS_2T2R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_2T2R)\
? true : false)
#define IS_8812_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8812)? \
true : false)
#define IS_8821_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8821)? \
true : false)
#define IS_VENDOR_8812A_TEST_CHIP(version) ((IS_8812_SERIES(version)) ? \
((IS_NORMAL_CHIP(version)) ? \
false : true) : false)
#define IS_VENDOR_8812A_MP_CHIP(version) ((IS_8812_SERIES(version)) ? \
((IS_NORMAL_CHIP(version)) ? \
true : false) : false)
#define IS_VENDOR_8812A_C_CUT(version) ((IS_8812_SERIES(version)) ? \
((GET_CVID_CUT_VERSION(version) == C_CUT_VERSION) ? \
true : false) : false)
#define IS_VENDOR_8821A_TEST_CHIP(version) ((IS_8821_SERIES(version)) ? \
((IS_NORMAL_CHIP(version)) ? \
false : true) : false)
#define IS_VENDOR_8821A_MP_CHIP(version) ((IS_8821_SERIES(version)) ? \
((IS_NORMAL_CHIP(version)) ? \
true : false) : false)
#define IS_VENDOR_8821A_B_CUT(version) ((IS_8821_SERIES(version)) ? \
((GET_CVID_CUT_VERSION(version) == B_CUT_VERSION) ? \
true : false) : false)
enum rf_optype {
RF_OP_BY_SW_3WIRE = 0,
RF_OP_BY_FW,
RF_OP_MAX
};
enum rf_power_state {
RF_ON,
RF_OFF,
RF_SLEEP,
RF_SHUT_DOWN,
};
enum power_save_mode {
POWER_SAVE_MODE_ACTIVE,
POWER_SAVE_MODE_SAVE,
};
enum power_polocy_config {
POWERCFG_MAX_POWER_SAVINGS,
POWERCFG_GLOBAL_POWER_SAVINGS,
POWERCFG_LOCAL_POWER_SAVINGS,
POWERCFG_LENOVO,
};
enum interface_select_pci {
INTF_SEL1_MINICARD = 0,
INTF_SEL0_PCIE = 1,
INTF_SEL2_RSV = 2,
INTF_SEL3_RSV = 3,
};
enum hal_fw_c2h_cmd_id {
HAL_FW_C2H_CMD_Read_MACREG = 0,
HAL_FW_C2H_CMD_Read_BBREG = 1,
HAL_FW_C2H_CMD_Read_RFREG = 2,
HAL_FW_C2H_CMD_Read_EEPROM = 3,
HAL_FW_C2H_CMD_Read_EFUSE = 4,
HAL_FW_C2H_CMD_Read_CAM = 5,
HAL_FW_C2H_CMD_Get_BasicRate = 6,
HAL_FW_C2H_CMD_Get_DataRate = 7,
HAL_FW_C2H_CMD_Survey = 8,
HAL_FW_C2H_CMD_SurveyDone = 9,
HAL_FW_C2H_CMD_JoinBss = 10,
HAL_FW_C2H_CMD_AddSTA = 11,
HAL_FW_C2H_CMD_DelSTA = 12,
HAL_FW_C2H_CMD_AtimDone = 13,
HAL_FW_C2H_CMD_TX_Report = 14,
HAL_FW_C2H_CMD_CCX_Report = 15,
HAL_FW_C2H_CMD_DTM_Report = 16,
HAL_FW_C2H_CMD_TX_Rate_Statistics = 17,
HAL_FW_C2H_CMD_C2HLBK = 18,
HAL_FW_C2H_CMD_C2HDBG = 19,
HAL_FW_C2H_CMD_C2HFEEDBACK = 20,
HAL_FW_C2H_CMD_MAX
};
enum rtl_desc_qsel {
QSLT_BK = 0x2,
QSLT_BE = 0x0,
QSLT_VI = 0x5,
QSLT_VO = 0x7,
QSLT_BEACON = 0x10,
QSLT_HIGH = 0x11,
QSLT_MGNT = 0x12,
QSLT_CMD = 0x13,
};
enum rtl_desc8821ae_rate {
DESC_RATE1M = 0x00,
DESC_RATE2M = 0x01,
DESC_RATE5_5M = 0x02,
DESC_RATE11M = 0x03,
DESC_RATE6M = 0x04,
DESC_RATE9M = 0x05,
DESC_RATE12M = 0x06,
DESC_RATE18M = 0x07,
DESC_RATE24M = 0x08,
DESC_RATE36M = 0x09,
DESC_RATE48M = 0x0a,
DESC_RATE54M = 0x0b,
DESC_RATEMCS0 = 0x0c,
DESC_RATEMCS1 = 0x0d,
DESC_RATEMCS2 = 0x0e,
DESC_RATEMCS3 = 0x0f,
DESC_RATEMCS4 = 0x10,
DESC_RATEMCS5 = 0x11,
DESC_RATEMCS6 = 0x12,
DESC_RATEMCS7 = 0x13,
DESC_RATEMCS8 = 0x14,
DESC_RATEMCS9 = 0x15,
DESC_RATEMCS10 = 0x16,
DESC_RATEMCS11 = 0x17,
DESC_RATEMCS12 = 0x18,
DESC_RATEMCS13 = 0x19,
DESC_RATEMCS14 = 0x1a,
DESC_RATEMCS15 = 0x1b,
DESC_RATEVHT1SS_MCS0 = 0x1c,
DESC_RATEVHT1SS_MCS1 = 0x1d,
DESC_RATEVHT1SS_MCS2 = 0x1e,
DESC_RATEVHT1SS_MCS3 = 0x1f,
DESC_RATEVHT1SS_MCS4 = 0x20,
DESC_RATEVHT1SS_MCS5 = 0x21,
DESC_RATEVHT1SS_MCS6 = 0x22,
DESC_RATEVHT1SS_MCS7 = 0x23,
DESC_RATEVHT1SS_MCS8 = 0x24,
DESC_RATEVHT1SS_MCS9 = 0x25,
DESC_RATEVHT2SS_MCS0 = 0x26,
DESC_RATEVHT2SS_MCS1 = 0x27,
DESC_RATEVHT2SS_MCS2 = 0x28,
DESC_RATEVHT2SS_MCS3 = 0x29,
DESC_RATEVHT2SS_MCS4 = 0x2a,
DESC_RATEVHT2SS_MCS5 = 0x2b,
DESC_RATEVHT2SS_MCS6 = 0x2c,
DESC_RATEVHT2SS_MCS7 = 0x2d,
DESC_RATEVHT2SS_MCS8 = 0x2e,
DESC_RATEVHT2SS_MCS9 = 0x2f,
};
enum rx_packet_type{
NORMAL_RX,
TX_REPORT1,
TX_REPORT2,
HIS_REPORT,
C2H_PACKET,
};
struct phy_sts_cck_8821ae_t {
u8 adc_pwdb_X[4];
u8 sq_rpt;
u8 cck_agc_rpt;
};
struct h2c_cmd_8821ae {
u8 element_id;
u32 cmd_len;
u8 *p_cmdbuffer;
};
#endif

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/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __RTL8821AE_DM_H__
#define __RTL8821AE_DM_H__
#define MAIN_ANT 0
#define AUX_ANT 1
#define MAIN_ANT_CG_TRX 1
#define AUX_ANT_CG_TRX 0
#define MAIN_ANT_CGCS_RX 0
#define AUX_ANT_CGCS_RX 1
#define TXSCALE_TABLE_SIZE 37
/*RF REG LIST*/
#define DM_REG_RF_MODE_11N 0x00
#define DM_REG_RF_0B_11N 0x0B
#define DM_REG_CHNBW_11N 0x18
#define DM_REG_T_METER_11N 0x24
#define DM_REG_RF_25_11N 0x25
#define DM_REG_RF_26_11N 0x26
#define DM_REG_RF_27_11N 0x27
#define DM_REG_RF_2B_11N 0x2B
#define DM_REG_RF_2C_11N 0x2C
#define DM_REG_RXRF_A3_11N 0x3C
#define DM_REG_T_METER_92D_11N 0x42
#define DM_REG_T_METER_88E_11N 0x42
/*BB REG LIST*/
/*PAGE 8 */
#define DM_REG_BB_CTRL_11N 0x800
#define DM_REG_RF_PIN_11N 0x804
#define DM_REG_PSD_CTRL_11N 0x808
#define DM_REG_TX_ANT_CTRL_11N 0x80C
#define DM_REG_BB_PWR_SAV5_11N 0x818
#define DM_REG_CCK_RPT_FORMAT_11N 0x824
#define DM_REG_RX_DEFUALT_A_11N 0x858
#define DM_REG_RX_DEFUALT_B_11N 0x85A
#define DM_REG_BB_PWR_SAV3_11N 0x85C
#define DM_REG_ANTSEL_CTRL_11N 0x860
#define DM_REG_RX_ANT_CTRL_11N 0x864
#define DM_REG_PIN_CTRL_11N 0x870
#define DM_REG_BB_PWR_SAV1_11N 0x874
#define DM_REG_ANTSEL_PATH_11N 0x878
#define DM_REG_BB_3WIRE_11N 0x88C
#define DM_REG_SC_CNT_11N 0x8C4
#define DM_REG_PSD_DATA_11N 0x8B4
/*PAGE 9*/
#define DM_REG_ANT_MAPPING1_11N 0x914
#define DM_REG_ANT_MAPPING2_11N 0x918
/*PAGE A*/
#define DM_REG_CCK_ANTDIV_PARA1_11N 0xA00
#define DM_REG_CCK_CCA_11N 0xA0A
#define DM_REG_CCK_CCA_11AC 0xA0A
#define DM_REG_CCK_ANTDIV_PARA2_11N 0xA0C
#define DM_REG_CCK_ANTDIV_PARA3_11N 0xA10
#define DM_REG_CCK_ANTDIV_PARA4_11N 0xA14
#define DM_REG_CCK_FILTER_PARA1_11N 0xA22
#define DM_REG_CCK_FILTER_PARA2_11N 0xA23
#define DM_REG_CCK_FILTER_PARA3_11N 0xA24
#define DM_REG_CCK_FILTER_PARA4_11N 0xA25
#define DM_REG_CCK_FILTER_PARA5_11N 0xA26
#define DM_REG_CCK_FILTER_PARA6_11N 0xA27
#define DM_REG_CCK_FILTER_PARA7_11N 0xA28
#define DM_REG_CCK_FILTER_PARA8_11N 0xA29
#define DM_REG_CCK_FA_RST_11N 0xA2C
#define DM_REG_CCK_FA_MSB_11N 0xA58
#define DM_REG_CCK_FA_LSB_11N 0xA5C
#define DM_REG_CCK_CCA_CNT_11N 0xA60
#define DM_REG_BB_PWR_SAV4_11N 0xA74
/*PAGE B */
#define DM_REG_LNA_SWITCH_11N 0xB2C
#define DM_REG_PATH_SWITCH_11N 0xB30
#define DM_REG_RSSI_CTRL_11N 0xB38
#define DM_REG_CONFIG_ANTA_11N 0xB68
#define DM_REG_RSSI_BT_11N 0xB9C
/*PAGE C */
#define DM_REG_OFDM_FA_HOLDC_11N 0xC00
#define DM_REG_RX_PATH_11N 0xC04
#define DM_REG_TRMUX_11N 0xC08
#define DM_REG_OFDM_FA_RSTC_11N 0xC0C
#define DM_REG_RXIQI_MATRIX_11N 0xC14
#define DM_REG_TXIQK_MATRIX_LSB1_11N 0xC4C
#define DM_REG_IGI_A_11N 0xC50
#define DM_REG_IGI_A_11AC 0xC50
#define DM_REG_ANTDIV_PARA2_11N 0xC54
#define DM_REG_IGI_B_11N 0xC58
#define DM_REG_IGI_B_11AC 0xE50
#define DM_REG_ANTDIV_PARA3_11N 0xC5C
#define DM_REG_BB_PWR_SAV2_11N 0xC70
#define DM_REG_RX_OFF_11N 0xC7C
#define DM_REG_TXIQK_MATRIXA_11N 0xC80
#define DM_REG_TXIQK_MATRIXB_11N 0xC88
#define DM_REG_TXIQK_MATRIXA_LSB2_11N 0xC94
#define DM_REG_TXIQK_MATRIXB_LSB2_11N 0xC9C
#define DM_REG_RXIQK_MATRIX_LSB_11N 0xCA0
#define DM_REG_ANTDIV_PARA1_11N 0xCA4
#define DM_REG_OFDM_FA_TYPE1_11N 0xCF0
/*PAGE D */
#define DM_REG_OFDM_FA_RSTD_11N 0xD00
#define DM_REG_OFDM_FA_TYPE2_11N 0xDA0
#define DM_REG_OFDM_FA_TYPE3_11N 0xDA4
#define DM_REG_OFDM_FA_TYPE4_11N 0xDA8
/*PAGE E */
#define DM_REG_TXAGC_A_6_18_11N 0xE00
#define DM_REG_TXAGC_A_24_54_11N 0xE04
#define DM_REG_TXAGC_A_1_MCS32_11N 0xE08
#define DM_REG_TXAGC_A_MCS0_3_11N 0xE10
#define DM_REG_TXAGC_A_MCS4_7_11N 0xE14
#define DM_REG_TXAGC_A_MCS8_11_11N 0xE18
#define DM_REG_TXAGC_A_MCS12_15_11N 0xE1C
#define DM_REG_FPGA0_IQK_11N 0xE28
#define DM_REG_TXIQK_TONE_A_11N 0xE30
#define DM_REG_RXIQK_TONE_A_11N 0xE34
#define DM_REG_TXIQK_PI_A_11N 0xE38
#define DM_REG_RXIQK_PI_A_11N 0xE3C
#define DM_REG_TXIQK_11N 0xE40
#define DM_REG_RXIQK_11N 0xE44
#define DM_REG_IQK_AGC_PTS_11N 0xE48
#define DM_REG_IQK_AGC_RSP_11N 0xE4C
#define DM_REG_BLUETOOTH_11N 0xE6C
#define DM_REG_RX_WAIT_CCA_11N 0xE70
#define DM_REG_TX_CCK_RFON_11N 0xE74
#define DM_REG_TX_CCK_BBON_11N 0xE78
#define DM_REG_OFDM_RFON_11N 0xE7C
#define DM_REG_OFDM_BBON_11N 0xE80
#define DM_REG_TX2RX_11N 0xE84
#define DM_REG_TX2TX_11N 0xE88
#define DM_REG_RX_CCK_11N 0xE8C
#define DM_REG_RX_OFDM_11N 0xED0
#define DM_REG_RX_WAIT_RIFS_11N 0xED4
#define DM_REG_RX2RX_11N 0xED8
#define DM_REG_STANDBY_11N 0xEDC
#define DM_REG_SLEEP_11N 0xEE0
#define DM_REG_PMPD_ANAEN_11N 0xEEC
/*MAC REG LIST*/
#define DM_REG_BB_RST_11N 0x02
#define DM_REG_ANTSEL_PIN_11N 0x4C
#define DM_REG_EARLY_MODE_11N 0x4D0
#define DM_REG_RSSI_MONITOR_11N 0x4FE
#define DM_REG_EDCA_VO_11N 0x500
#define DM_REG_EDCA_VI_11N 0x504
#define DM_REG_EDCA_BE_11N 0x508
#define DM_REG_EDCA_BK_11N 0x50C
#define DM_REG_TXPAUSE_11N 0x522
#define DM_REG_RESP_TX_11N 0x6D8
#define DM_REG_ANT_TRAIN_PARA1_11N 0x7b0
#define DM_REG_ANT_TRAIN_PARA2_11N 0x7b4
/*DIG Related*/
#define DM_BIT_IGI_11N 0x0000007F
#define DM_BIT_IGI_11AC 0xFFFFFFFF
#define HAL_DM_DIG_DISABLE BIT(0)
#define HAL_DM_HIPWR_DISABLE BIT(1)
#define OFDM_TABLE_LENGTH 43
#define CCK_TABLE_LENGTH 33
#define OFDM_TABLE_SIZE 37
#define CCK_TABLE_SIZE 33
#define BW_AUTO_SWITCH_HIGH_LOW 25
#define BW_AUTO_SWITCH_LOW_HIGH 30
#define DM_DIG_THRESH_HIGH 40
#define DM_DIG_THRESH_LOW 35
#define DM_FALSEALARM_THRESH_LOW 400
#define DM_FALSEALARM_THRESH_HIGH 1000
#define DM_DIG_MAX 0x3e
#define DM_DIG_MIN 0x1e
#define DM_DIG_MAX_AP 0x32
#define DM_DIG_MIN_AP 0x20
#define DM_DIG_FA_UPPER 0x3e
#define DM_DIG_FA_LOWER 0x1e
#define DM_DIG_FA_TH0 0x200
#define DM_DIG_FA_TH1 0x300
#define DM_DIG_FA_TH2 0x400
#define DM_DIG_BACKOFF_MAX 12
#define DM_DIG_BACKOFF_MIN -4
#define DM_DIG_BACKOFF_DEFAULT 10
#define RXPATHSELECTION_SS_TH_lOW 30
#define RXPATHSELECTION_DIFF_TH 18
#define DM_RATR_STA_INIT 0
#define DM_RATR_STA_HIGH 1
#define DM_RATR_STA_MIDDLE 2
#define DM_RATR_STA_LOW 3
#define CTS2SELF_THVAL 30
#define REGC38_TH 20
#define WAIOTTHVal 25
#define TXHIGHPWRLEVEL_NORMAL 0
#define TXHIGHPWRLEVEL_LEVEL1 1
#define TXHIGHPWRLEVEL_LEVEL2 2
#define TXHIGHPWRLEVEL_BT1 3
#define TXHIGHPWRLEVEL_BT2 4
#define DM_TYPE_BYFW 0
#define DM_TYPE_BYDRIVER 1
#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74
#define TX_POWER_NEAR_FIELD_THRESH_LVL1 67
#define TXPWRTRACK_MAX_IDX 6
/* Dynamic ATC switch */
#define ATC_STATUS_OFF 0x0 /* enable */
#define ATC_STATUS_ON 0x1 /* disable */
#define CFO_THRESHOLD_XTAL 10 /* kHz */
#define CFO_THRESHOLD_ATC 80 /* kHz */
#define AVG_THERMAL_NUM_8812A 4
#define TXPWR_TRACK_TABLE_SIZE 30
#define MAX_PATH_NUM_8812A 2
#define MAX_PATH_NUM_8821A 1
struct ps_t {
u8 pre_ccastate;
u8 cur_ccasate;
u8 pre_rfstate;
u8 cur_rfstate;
u8 initialize;
long rssi_val_min;
};
struct dig_t {
u8 dig_enable_flag;
u8 dig_ext_port_stage;
u32 rssi_lowthresh;
u32 rssi_highthresh;
u32 fa_lowthresh;
u32 fa_highthresh;
u8 cursta_connectctate;
u8 presta_connectstate;
u8 curmultista_connectstate;
u8 pre_igvalue;
u8 cur_igvalue;
u8 bt30_cur_igi;
u8 backup_igvalue;
u8 stop_dig;
char backoff_val;
char backoff_val_range_max;
char backoff_val_range_min;
u8 rx_gain_range_max;
u8 rx_gain_range_min;
u8 rssi_val_min;
u8 pre_cck_cca_thres;
u8 cur_cck_cca_thres;
u8 pre_cck_pd_state;
u8 cur_cck_pd_state;
u8 large_fa_hit;
u8 forbidden_igi;
u32 recover_cnt;
u8 dig_dynamic_min_0;
u8 dig_dynamic_min_1;
bool b_media_connect_0;
bool b_media_connect_1;
u32 antdiv_rssi_max;
u32 rssi_max;
};
enum FAT_STATE {
FAT_NORMAL_STATE = 0,
FAT_TRAINING_STATE = 1,
};
enum tag_dynamic_init_gain_operation_type_definition {
DIG_TYPE_THRESH_HIGH = 0,
DIG_TYPE_THRESH_LOW = 1,
DIG_TYPE_BACKOFF = 2,
DIG_TYPE_RX_GAIN_MIN = 3,
DIG_TYPE_RX_GAIN_MAX = 4,
DIG_TYPE_ENABLE = 5,
DIG_TYPE_DISABLE = 6,
DIG_OP_TYPE_MAX
};
enum tag_cck_packet_detection_threshold_type_definition {
CCK_PD_STAGE_LowRssi = 0,
CCK_PD_STAGE_HighRssi = 1,
CCK_FA_STAGE_Low = 2,
CCK_FA_STAGE_High = 3,
CCK_PD_STAGE_MAX = 4,
};
enum dm_1r_cca_e {
CCA_1R = 0,
CCA_2R = 1,
CCA_MAX = 2,
};
enum dm_rf_e {
RF_SAVE = 0,
RF_NORMAL = 1,
RF_MAX = 2,
};
enum dm_sw_ant_switch_e {
ANS_ANTENNA_B = 1,
ANS_ANTENNA_A = 2,
ANS_ANTENNA_MAX = 3,
};
enum dm_dig_ext_port_alg_e {
DIG_EXT_PORT_STAGE_0 = 0,
DIG_EXT_PORT_STAGE_1 = 1,
DIG_EXT_PORT_STAGE_2 = 2,
DIG_EXT_PORT_STAGE_3 = 3,
DIG_EXT_PORT_STAGE_MAX = 4,
};
enum dm_dig_connect_e {
DIG_STA_DISCONNECT = 0,
DIG_STA_CONNECT = 1,
DIG_STA_BEFORE_CONNECT = 2,
DIG_MULTISTA_DISCONNECT = 3,
DIG_MULTISTA_CONNECT = 4,
DIG_CONNECT_MAX
};
enum pwr_track_control_method {
BBSWING,
TXAGC,
MIX_MODE
};
#define BT_RSSI_STATE_NORMAL_POWER BIT_OFFSET_LEN_MASK_32(0, 1)
#define BT_RSSI_STATE_AMDPU_OFF BIT_OFFSET_LEN_MASK_32(1, 1)
#define BT_RSSI_STATE_SPECIAL_LOW BIT_OFFSET_LEN_MASK_32(2, 1)
#define BT_RSSI_STATE_BG_EDCA_LOW BIT_OFFSET_LEN_MASK_32(3, 1)
#define BT_RSSI_STATE_TXPOWER_LOW BIT_OFFSET_LEN_MASK_32(4, 1)
#define GET_UNDECORATED_AVERAGE_RSSI(_priv) \
(((struct rtl_priv *)(_priv))->mac80211.opmode == NL80211_IFTYPE_ADHOC)? \
(((struct rtl_priv *)(_priv))->dm.entry_min_undecoratedsmoothed_pwdb): \
(((struct rtl_priv *)(_priv))->dm.undecorated_smoothed_pwdb)
extern struct dig_t dm_digtable;
void rtl8821ae_dm_set_tx_ant_by_tx_info(struct ieee80211_hw *hw,
u8 *pdesc, u32 mac_id);
void rtl8821ae_dm_ant_sel_statistics(struct ieee80211_hw *hw,
u8 antsel_tr_mux, u32 mac_id,
u32 rx_pwdb_all);
void rtl8821ae_dm_fast_antenna_trainning_callback(unsigned long data);
void rtl8821ae_dm_init(struct ieee80211_hw *hw);
void rtl8821ae_dm_watchdog(struct ieee80211_hw *hw);
void rtl8821ae_dm_write_dig(struct ieee80211_hw *hw, u8 current_igi);
void rtl8821ae_dm_init_edca_turbo(struct ieee80211_hw *hw);
void rtl8821ae_dm_check_txpower_tracking_thermalmeter(struct ieee80211_hw *hw);
void rtl8821ae_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw);
void rtl8821ae_dm_txpower_track_adjust(struct ieee80211_hw *hw,
u8 type,u8 *pdirection,
u32 *poutwrite_val);
void rtl8821ae_dm_clear_txpower_tracking_state(struct ieee80211_hw *hw);
void rtl8821ae_dm_write_cck_cca_thres(struct ieee80211_hw *hw, u8 current_cca);
void rtl8821ae_dm_initialize_txpower_tracking_thermalmeter(struct ieee80211_hw *hw);
void rtl8812ae_dm_path_diversity(struct ieee80211_hw *hw);
void rtl8812ae_dm_path_diversity_init(struct ieee80211_hw *hw);
void rtl8812ae_dm_path_statistics(struct ieee80211_hw *hw,
u32 rssi_a, u32 rssi_b);
void rtl812ae_dm_set_txpath_by_txinfo(struct ieee80211_hw *hw,
u8 *pdesc);
void rtl8812ae_dm_txpwr_track_set_pwr(struct ieee80211_hw *hw,
enum pwr_track_control_method method,
u8 rf_path,
u8 channel_mapped_index);
void rtl8821ae_dm_txpwr_track_set_pwr(struct ieee80211_hw *hw,
enum pwr_track_control_method method, u8 rf_path, u8 channel_mapped_index);
void rtl8812ae_dm_update_init_rate(struct ieee80211_hw *hw, u8 rate);
u8 rtl8812ae_hw_rate_to_mrate(struct ieee80211_hw *hw, u8 rate);
void rtl8812ae_dm_txpower_tracking_callback_thermalmeter(struct ieee80211_hw *hw);
void rtl8821ae_dm_txpower_tracking_callback_thermalmeter(struct ieee80211_hw *hw);
#endif

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/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __RTL8821AE__FW__H__
#define __RTL8821AE__FW__H__
#define FW_8821AE_SIZE 0x8000
#define FW_8821AE_START_ADDRESS 0x1000
#define FW_8821AE_END_ADDRESS 0x5FFF
#define FW_8821AE_PAGE_SIZE 4096
#define FW_8821AE_POLLING_DELAY 5
#define FW_8821AE_POLLING_TIMEOUT_COUNT 6000
#define IS_FW_HEADER_EXIST_8812(_pfwhdr) \
((_pfwhdr->signature&0xFFF0) == 0x9500 )
#define IS_FW_HEADER_EXIST_8821(_pfwhdr) \
((_pfwhdr->signature&0xFFF0) == 0x2100 )
#define USE_OLD_WOWLAN_DEBUG_FW 0
#define H2C_8821AE_RSVDPAGE_LOC_LEN 5
#define H2C_8821AE_PWEMODE_LENGTH 5
#define H2C_8821AE_JOINBSSRPT_LENGTH 1
#define H2C_8821AE_AP_OFFLOAD_LENGTH 3
#define H2C_8821AE_WOWLAN_LENGTH 3
#define H2C_8821AE_KEEP_ALIVE_CTRL_LENGTH 3
#if(USE_OLD_WOWLAN_DEBUG_FW == 0)
#define H2C_8821AE_REMOTE_WAKE_CTRL_LEN 1
#else
#define H2C_8821AE_REMOTE_WAKE_CTRL_LEN 3
#endif
#define H2C_8821AE_AOAC_GLOBAL_INFO_LEN 2
#define H2C_8821AE_AOAC_RSVDPAGE_LOC_LEN 7
/* Fw PS state for RPWM.
*BIT[2:0] = HW state
*BIT[3] = Protocol PS state, 1: register active state , 0: register sleep state
*BIT[4] = sub-state
*/
#define FW_PS_GO_ON BIT(0)
#define FW_PS_TX_NULL BIT(1)
#define FW_PS_RF_ON BIT(2)
#define FW_PS_REGISTER_ACTIVE BIT(3)
#define FW_PS_DPS BIT(0)
#define FW_PS_LCLK (FW_PS_DPS)
#define FW_PS_RF_OFF BIT(1)
#define FW_PS_ALL_ON BIT(2)
#define FW_PS_ST_ACTIVE BIT(3)
#define FW_PS_ISR_ENABLE BIT(4)
#define FW_PS_IMR_ENABLE BIT(5)
#define FW_PS_ACK BIT(6)
#define FW_PS_TOGGLE BIT(7)
/* 8821AE RPWM value*/
/* BIT[0] = 1: 32k, 0: 40M*/
#define FW_PS_CLOCK_OFF BIT(0) /* 32k*/
#define FW_PS_CLOCK_ON 0 /*40M*/
#define FW_PS_STATE_MASK (0x0F)
#define FW_PS_STATE_HW_MASK (0x07)
#define FW_PS_STATE_INT_MASK (0x3F) /*ISR_ENABLE, IMR_ENABLE, and PS mode should be inherited.*/
#define FW_PS_STATE(x) (FW_PS_STATE_MASK & (x))
#define FW_PS_STATE_HW(x) (FW_PS_STATE_HW_MASK & (x))
#define FW_PS_STATE_INT(x) (FW_PS_STATE_INT_MASK & (x))
#define FW_PS_ISR_VAL(x) ((x) & 0x70)
#define FW_PS_IMR_MASK(x) ((x) & 0xDF)
#define FW_PS_KEEP_IMR(x) ((x) & 0x20)
#define FW_PS_STATE_S0 (FW_PS_DPS)
#define FW_PS_STATE_S1 (FW_PS_LCLK)
#define FW_PS_STATE_S2 (FW_PS_RF_OFF)
#define FW_PS_STATE_S3 (FW_PS_ALL_ON)
#define FW_PS_STATE_S4 ((FW_PS_ST_ACTIVE) | (FW_PS_ALL_ON))
#define FW_PS_STATE_ALL_ON_8821AE (FW_PS_CLOCK_ON) /* ((FW_PS_RF_ON) | (FW_PS_REGISTER_ACTIVE))*/
#define FW_PS_STATE_RF_ON_8821AE (FW_PS_CLOCK_ON) /* (FW_PS_RF_ON)*/
#define FW_PS_STATE_RF_OFF_8821AE (FW_PS_CLOCK_ON) /* 0x0*/
#define FW_PS_STATE_RF_OFF_LOW_PWR_8821AE (FW_PS_CLOCK_OFF) /* (FW_PS_STATE_RF_OFF)*/
#define FW_PS_STATE_ALL_ON_92C (FW_PS_STATE_S4)
#define FW_PS_STATE_RF_ON_92C (FW_PS_STATE_S3)
#define FW_PS_STATE_RF_OFF_92C (FW_PS_STATE_S2)
#define FW_PS_STATE_RF_OFF_LOW_PWR_92C (FW_PS_STATE_S1)
/* For 8821AE H2C PwrMode Cmd ID 5.*/
#define FW_PWR_STATE_ACTIVE ((FW_PS_RF_ON) | (FW_PS_REGISTER_ACTIVE))
#define FW_PWR_STATE_RF_OFF 0
#define FW_PS_IS_ACK(x) ((x) & FW_PS_ACK )
#define FW_PS_IS_CLK_ON(x) ((x) & (FW_PS_RF_OFF |FW_PS_ALL_ON ))
#define FW_PS_IS_RF_ON(x) ((x) & (FW_PS_ALL_ON))
#define FW_PS_IS_ACTIVE(x) ((x) & (FW_PS_ST_ACTIVE))
#define FW_PS_IS_CPWM_INT(x) ((x) & 0x40)
#define FW_CLR_PS_STATE(x) ((x) = ((x) & (0xF0)))
#define IS_IN_LOW_POWER_STATE_8821AE(FwPSState) \
(FW_PS_STATE(FwPSState) == FW_PS_CLOCK_OFF)
#define FW_PWR_STATE_ACTIVE ((FW_PS_RF_ON) | (FW_PS_REGISTER_ACTIVE))
#define FW_PWR_STATE_RF_OFF 0
struct rtl8821a_firmware_header {
u16 signature;
u8 category;
u8 function;
u16 version;
u8 subversion;
u8 rsvd1;
u8 month;
u8 date;
u8 hour;
u8 minute;
u16 ramcodeSize;
u16 rsvd2;
u32 svnindex;
u32 rsvd3;
u32 rsvd4;
u32 rsvd5;
};
enum rtl8812_c2h_evt{
C2H_8812_DBG = 0,
C2H_8812_LB = 1,
C2H_8812_TXBF = 2,
C2H_8812_TX_REPORT = 3,
C2H_8812_BT_INFO = 9,
C2H_8812_BT_MP = 11,
C2H_8812_RA_RPT=12,
C2H_8812_FW_SWCHNL = 0x10,
C2H_8812_IQK_FINISH = 0x11,
MAX_8812_C2HEVENT
};
enum rtl8821a_h2c_cmd {
H2C_8821AE_RSVDPAGE = 0,
H2C_8821AE_JOINBSSRPT = 1,
H2C_8821AE_SCAN = 2,
H2C_8821AE_KEEP_ALIVE_CTRL = 3,
H2C_8821AE_DISCONNECT_DECISION = 4,
#if(USE_OLD_WOWLAN_DEBUG_FW == 1)
H2C_8821AE_WO_WLAN = 5,
#endif
H2C_8821AE_INIT_OFFLOAD = 6,
#if(USE_OLD_WOWLAN_DEBUG_FW == 1)
H2C_8821AE_REMOTE_WAKE_CTRL = 7,
#endif
H2C_8821AE_AP_OFFLOAD = 8,
H2C_8821AE_BCN_RSVDPAGE = 9,
H2C_8821AE_PROBERSP_RSVDPAGE = 10,
H2C_8821AE_SETPWRMODE = 0x20,
H2C_8821AE_PS_TUNING_PARA = 0x21,
H2C_8821AE_PS_TUNING_PARA2 = 0x22,
H2C_8821AE_PS_LPS_PARA = 0x23,
H2C_8821AE_P2P_PS_OFFLOAD = 024,
#if(USE_OLD_WOWLAN_DEBUG_FW == 0)
H2C_8821AE_WO_WLAN = 0x80,
H2C_8821AE_REMOTE_WAKE_CTRL = 0x81,
H2C_8821AE_AOAC_GLOBAL_INFO = 0x82,
H2C_8821AE_AOAC_RSVDPAGE = 0x83,
#endif
H2C_RSSI_REPORT = 0x42,
H2C_8821AE_RA_MASK = 0x40,
H2C_8821AE_SELECTIVE_SUSPEND_ROF_CMD,
H2C_8821AE_P2P_PS_MODE,
H2C_8821AE_PSD_RESULT,
/*Not defined CTW CMD for P2P yet*/
H2C_8821AE_P2P_PS_CTW_CMD,
MAX_8821AE_H2CCMD
};
#define pagenum_128(_len) (u32)(((_len)>>7) + ((_len)&0x7F ? 1:0))
#define SET_8821AE_H2CCMD_WOWLAN_FUNC_ENABLE(__pH2CCmd, __Value) \
SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
#define SET_8821AE_H2CCMD_WOWLAN_PATTERN_MATCH_ENABLE(__pH2CCmd, __Value) \
SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
#define SET_8821AE_H2CCMD_WOWLAN_MAGIC_PKT_ENABLE(__pH2CCmd, __Value) \
SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
#define SET_8821AE_H2CCMD_WOWLAN_UNICAST_PKT_ENABLE(__pH2CCmd, __Value) \
SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value)
#define SET_8821AE_H2CCMD_WOWLAN_ALL_PKT_DROP(__pH2CCmd, __Value) \
SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value)
#define SET_8821AE_H2CCMD_WOWLAN_GPIO_ACTIVE(__pH2CCmd, __Value) \
SET_BITS_TO_LE_1BYTE(__pH2CCmd, 5, 1, __Value)
#define SET_8821AE_H2CCMD_WOWLAN_REKEY_WAKE_UP(__pH2CCmd, __Value) \
SET_BITS_TO_LE_1BYTE(__pH2CCmd, 6, 1, __Value)
#define SET_8821AE_H2CCMD_WOWLAN_DISCONNECT_WAKE_UP(__pH2CCmd, __Value) \
SET_BITS_TO_LE_1BYTE(__pH2CCmd, 7, 1, __Value)
#define SET_8821AE_H2CCMD_WOWLAN_GPIONUM(__pH2CCmd, __Value) \
SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
#define SET_8821AE_H2CCMD_WOWLAN_GPIO_DURATION(__pH2CCmd, __Value) \
SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
#define SET_H2CCMD_PWRMODE_PARM_MODE(__ph2ccmd, __val) \
SET_BITS_TO_LE_1BYTE(__ph2ccmd, 0, 8, __val)
#define SET_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value) \
SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value)
#define SET_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value) \
SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value)
#define SET_H2CCMD_PWRMODE_PARM_AWAKE_INTERVAL(__pH2CCmd, __Value) \
SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
#define SET_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value) \
SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
#define SET_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value) \
SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
#define GET_8821AE_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd) \
LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8)
#define SET_H2CCMD_JOINBSSRPT_PARM_OPMODE(__ph2ccmd, __val) \
SET_BITS_TO_LE_1BYTE(__ph2ccmd, 0, 8, __val)
#define SET_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__ph2ccmd, __val) \
SET_BITS_TO_LE_1BYTE(__ph2ccmd, 0, 8, __val)
#define SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(__ph2ccmd, __val) \
SET_BITS_TO_LE_1BYTE((__ph2ccmd)+1, 0, 8, __val)
#define SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__ph2ccmd, __val) \
SET_BITS_TO_LE_1BYTE((__ph2ccmd)+2, 0, 8, __val)
/* AP_OFFLOAD */
#define SET_H2CCMD_AP_OFFLOAD_ON(__pH2CCmd, __Value) \
SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
#define SET_H2CCMD_AP_OFFLOAD_HIDDEN(__pH2CCmd, __Value) \
SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
#define SET_H2CCMD_AP_OFFLOAD_DENYANY(__pH2CCmd, __Value) \
SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
#define SET_H2CCMD_AP_OFFLOAD_WAKEUP_EVT_RPT(__pH2CCmd, __Value) \
SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
/* Keep Alive Control*/
#define SET_8821AE_H2CCMD_KEEP_ALIVE_ENABLE(__pH2CCmd, __Value) \
SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
#define SET_8821AE_H2CCMD_KEEP_ALIVE_ACCPEPT_USER_DEFINED(__pH2CCmd, __Value) \
SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
#define SET_8821AE_H2CCMD_KEEP_ALIVE_PERIOD(__pH2CCmd, __Value) \
SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
/*REMOTE_WAKE_CTRL */
#define SET_8821AE_H2CCMD_REMOTE_WAKE_CTRL_EN(__pH2CCmd, __Value) \
SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
#if(USE_OLD_WOWLAN_DEBUG_FW == 0)
#define SET_8821AE_H2CCMD_REMOTE_WAKE_CTRL_ARP_OFFLOAD_EN(__pH2CCmd, __Value) \
SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
#define SET_8821AE_H2CCMD_REMOTE_WAKE_CTRL_NDP_OFFLOAD_EN(__pH2CCmd, __Value) \
SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
#define SET_8821AE_H2CCMD_REMOTE_WAKE_CTRL_GTK_OFFLOAD_EN(__pH2CCmd, __Value) \
SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value)
#else
#define SET_8821AE_H2CCMD_REMOTE_WAKE_CTRL_PAIRWISE_ENC_ALG(__pH2CCmd, __Value) \
SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
#define SET_8821AE_H2CCMD_REMOTE_WAKE_CTRL_GROUP_ENC_ALG(__pH2CCmd, __Value) \
SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
#endif
/* GTK_OFFLOAD */
#define SET_8821AE_H2CCMD_AOAC_GLOBAL_INFO_PAIRWISE_ENC_ALG(__pH2CCmd, __Value) \
SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
#define SET_8821AE_H2CCMD_AOAC_GLOBAL_INFO_GROUP_ENC_ALG(__pH2CCmd, __Value) \
SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
/* AOAC_RSVDPAGE_LOC */
#define SET_8821AE_H2CCMD_AOAC_RSVDPAGE_LOC_REMOTE_WAKE_CTRL_INFO(__pH2CCmd, __Value) \
SET_BITS_TO_LE_1BYTE((__pH2CCmd), 0, 8, __Value)
#define SET_8821AE_H2CCMD_AOAC_RSVDPAGE_LOC_ARP_RSP(__pH2CCmd, __Value) \
SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
#define SET_8821AE_H2CCMD_AOAC_RSVDPAGE_LOC_NEIGHBOR_ADV(__pH2CCmd, __Value) \
SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
#define SET_8821AE_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_RSP(__pH2CCmd, __Value) \
SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
#define SET_8821AE_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_INFO(__pH2CCmd, __Value) \
SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
int rtl8821ae_download_fw(struct ieee80211_hw *hw,
bool buse_wake_on_wlan_fw);
void rtl8821ae_fill_h2c_cmd(struct ieee80211_hw *hw, u8 element_id,
u32 cmd_len, u8 *p_cmdbuffer);
void rtl8821ae_firmware_selfreset(struct ieee80211_hw *hw);
void rtl8821ae_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 mode);
void rtl8821ae_set_fw_joinbss_report_cmd(struct ieee80211_hw *hw, u8 mstatus);
void rtl8821ae_set_fw_ap_off_load_cmd(struct ieee80211_hw *hw, u8 ap_offload_enable);
void rtl8821ae_set_fw_rsvdpagepkt(struct ieee80211_hw *hw, bool b_dl_finished);
void rtl8812ae_set_fw_rsvdpagepkt(struct ieee80211_hw *hw, bool b_dl_finished);
void rtl8821ae_set_p2p_ps_offload_cmd(struct ieee80211_hw *hw, u8 p2p_ps_state);
void rtl8812ae_c2h_packet_handler(struct ieee80211_hw *hw, u8 *buffer, u8 length);
#endif

519
drivers/staging/rtl8821ae/rtl8821ae/hal_bt_coexist.c Normal file
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@ -0,0 +1,519 @@
/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "hal_bt_coexist.h"
#include "../pci.h"
#include "dm.h"
#include "fw.h"
#include "phy.h"
#include "reg.h"
#include "hal_btc.h"
static bool bt_operation_on = false;
void rtl8821ae_dm_bt_reject_ap_aggregated_packet(struct ieee80211_hw *hw, bool b_reject)
{
#if 0
struct rtl_priv rtlpriv = rtl_priv(hw);
PRX_TS_RECORD pRxTs = NULL;
if(b_reject){
// Do not allow receiving A-MPDU aggregation.
if (rtlpriv->mac80211.vendor == PEER_CISCO) {
if (pHTInfo->bAcceptAddbaReq) {
RTPRINT(FBT, BT_TRACE, ("BT_Disallow AMPDU \n"));
pHTInfo->bAcceptAddbaReq = FALSE;
if(GetTs(Adapter, (PTS_COMMON_INFO*)(&pRxTs), pMgntInfo->Bssid, 0, RX_DIR, FALSE))
TsInitDelBA(Adapter, (PTS_COMMON_INFO)pRxTs, RX_DIR);
}
} else {
if (!pHTInfo->bAcceptAddbaReq) {
RTPRINT(FBT, BT_TRACE, ("BT_Allow AMPDU BT Idle\n"));
pHTInfo->bAcceptAddbaReq = TRUE;
}
}
} else {
if(rtlpriv->mac80211.vendor == PEER_CISCO) {
if (!pHTInfo->bAcceptAddbaReq) {
RTPRINT(FBT, BT_TRACE, ("BT_Allow AMPDU \n"));
pHTInfo->bAcceptAddbaReq = TRUE;
}
}
}
#endif
}
void _rtl8821ae_dm_bt_check_wifi_state(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
struct rtl_phy *rtlphy = &(rtlpriv->phy);
if (rtlpriv->link_info.b_busytraffic) {
rtlpcipriv->btcoexist.current_state &= ~BT_COEX_STATE_WIFI_IDLE;
if(rtlpriv->link_info.b_tx_busy_traffic) {
rtlpcipriv->btcoexist.current_state |= BT_COEX_STATE_WIFI_UPLINK;
} else {
rtlpcipriv->btcoexist.current_state &= ~BT_COEX_STATE_WIFI_UPLINK;
}
if(rtlpriv->link_info.b_rx_busy_traffic) {
rtlpcipriv->btcoexist.current_state |= BT_COEX_STATE_WIFI_DOWNLINK;
} else {
rtlpcipriv->btcoexist.current_state &= ~BT_COEX_STATE_WIFI_DOWNLINK;
}
} else {
rtlpcipriv->btcoexist.current_state |= BT_COEX_STATE_WIFI_IDLE;
rtlpcipriv->btcoexist.current_state &= ~BT_COEX_STATE_WIFI_UPLINK;
rtlpcipriv->btcoexist.current_state &= ~BT_COEX_STATE_WIFI_DOWNLINK;
}
if (rtlpriv->mac80211.mode == WIRELESS_MODE_G
|| rtlpriv->mac80211.mode == WIRELESS_MODE_B) {
rtlpcipriv->btcoexist.current_state |= BT_COEX_STATE_WIFI_LEGACY;
rtlpcipriv->btcoexist.current_state &= ~BT_COEX_STATE_WIFI_HT20;
rtlpcipriv->btcoexist.current_state &= ~BT_COEX_STATE_WIFI_HT40;
} else {
rtlpcipriv->btcoexist.current_state &= ~BT_COEX_STATE_WIFI_LEGACY;
if(rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) {
rtlpcipriv->btcoexist.current_state |= BT_COEX_STATE_WIFI_HT40;
rtlpcipriv->btcoexist.current_state &= ~BT_COEX_STATE_WIFI_HT20;
} else {
rtlpcipriv->btcoexist.current_state |= BT_COEX_STATE_WIFI_HT20;
rtlpcipriv->btcoexist.current_state &= ~BT_COEX_STATE_WIFI_HT40;
}
}
if (bt_operation_on) {
rtlpcipriv->btcoexist.current_state |= BT_COEX_STATE_BT30;
} else {
rtlpcipriv->btcoexist.current_state &= ~BT_COEX_STATE_BT30;
}
}
u8 rtl8821ae_dm_bt_check_coex_rssi_state1(struct ieee80211_hw *hw,
u8 level_num, u8 rssi_thresh, u8 rssi_thresh1)
{
struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
struct rtl_priv *rtlpriv = rtl_priv(hw);
long undecoratedsmoothed_pwdb = 0;
u8 bt_rssi_state = 0;
undecoratedsmoothed_pwdb = rtl8821ae_dm_bt_get_rx_ss(hw);
if(level_num == 2) {
rtlpcipriv->btcoexist.current_state &= ~BT_COEX_STATE_WIFI_RSSI_1_MEDIUM;
if( (rtlpcipriv->btcoexist.bt_pre_rssi_state == BT_RSSI_STATE_LOW) ||
(rtlpcipriv->btcoexist.bt_pre_rssi_state == BT_RSSI_STATE_STAY_LOW)) {
if(undecoratedsmoothed_pwdb >= (rssi_thresh + BT_FW_COEX_THRESH_TOL)) {
bt_rssi_state = BT_RSSI_STATE_HIGH;
rtlpcipriv->btcoexist.current_state |= BT_COEX_STATE_WIFI_RSSI_1_HIGH;
rtlpcipriv->btcoexist.current_state &= ~BT_COEX_STATE_WIFI_RSSI_1_LOW;
RT_TRACE(COMP_BT_COEXIST, DBG_TRACE, ("[DM][BT], RSSI_1 state switch to High\n"));
} else {
bt_rssi_state = BT_RSSI_STATE_STAY_LOW;
RT_TRACE(COMP_BT_COEXIST, DBG_TRACE, ("[DM][BT], RSSI_1 state stay at Low\n"));
}
} else {
if(undecoratedsmoothed_pwdb < rssi_thresh) {
bt_rssi_state = BT_RSSI_STATE_LOW;
rtlpcipriv->btcoexist.current_state |= BT_COEX_STATE_WIFI_RSSI_1_LOW;
rtlpcipriv->btcoexist.current_state &= ~BT_COEX_STATE_WIFI_RSSI_1_HIGH;
RT_TRACE(COMP_BT_COEXIST, DBG_TRACE, ("[DM][BT], RSSI_1 state switch to Low\n"));
} else {
bt_rssi_state = BT_RSSI_STATE_STAY_HIGH;
RT_TRACE(COMP_BT_COEXIST, DBG_TRACE, ("[DM][BT], RSSI_1 state stay at High\n"));
}
}
} else if(level_num == 3) {
if(rssi_thresh > rssi_thresh1) {
RT_TRACE(COMP_BT_COEXIST, DBG_TRACE, ("[DM][BT], RSSI_1 thresh error!!\n"));
return rtlpcipriv->btcoexist.bt_pre_rssi_state;
}
if( (rtlpcipriv->btcoexist.bt_pre_rssi_state == BT_RSSI_STATE_LOW) ||
(rtlpcipriv->btcoexist.bt_pre_rssi_state == BT_RSSI_STATE_STAY_LOW)) {
if(undecoratedsmoothed_pwdb >= (rssi_thresh+BT_FW_COEX_THRESH_TOL)) {
bt_rssi_state = BT_RSSI_STATE_MEDIUM;
rtlpcipriv->btcoexist.current_state |= BT_COEX_STATE_WIFI_RSSI_1_MEDIUM;
rtlpcipriv->btcoexist.current_state &= ~BT_COEX_STATE_WIFI_RSSI_1_LOW;
rtlpcipriv->btcoexist.current_state &= ~BT_COEX_STATE_WIFI_RSSI_1_HIGH;
RT_TRACE(COMP_BT_COEXIST, DBG_TRACE, ("[DM][BT], RSSI_1 state switch to Medium\n"));
} else {
bt_rssi_state = BT_RSSI_STATE_STAY_LOW;
RT_TRACE(COMP_BT_COEXIST, DBG_TRACE, ("[DM][BT], RSSI_1 state stay at Low\n"));
}
} else if( (rtlpcipriv->btcoexist.bt_pre_rssi_state == BT_RSSI_STATE_MEDIUM) ||
(rtlpcipriv->btcoexist.bt_pre_rssi_state == BT_RSSI_STATE_STAY_MEDIUM)) {
if(undecoratedsmoothed_pwdb >= (rssi_thresh1 + BT_FW_COEX_THRESH_TOL)) {
bt_rssi_state = BT_RSSI_STATE_HIGH;
rtlpcipriv->btcoexist.current_state |= BT_COEX_STATE_WIFI_RSSI_1_HIGH;
rtlpcipriv->btcoexist.current_state &= ~BT_COEX_STATE_WIFI_RSSI_1_LOW;
rtlpcipriv->btcoexist.current_state &= ~BT_COEX_STATE_WIFI_RSSI_1_MEDIUM;
RT_TRACE(COMP_BT_COEXIST, DBG_TRACE, ("[DM][BT], RSSI_1 state switch to High\n"));
} else if(undecoratedsmoothed_pwdb < rssi_thresh) {
bt_rssi_state = BT_RSSI_STATE_LOW;
rtlpcipriv->btcoexist.current_state |= BT_COEX_STATE_WIFI_RSSI_1_LOW;
rtlpcipriv->btcoexist.current_state &= ~BT_COEX_STATE_WIFI_RSSI_1_HIGH;
rtlpcipriv->btcoexist.current_state &= ~BT_COEX_STATE_WIFI_RSSI_1_MEDIUM;
RT_TRACE(COMP_BT_COEXIST, DBG_TRACE, ("[DM][BT], RSSI_1 state switch to Low\n"));
} else {
bt_rssi_state = BT_RSSI_STATE_STAY_MEDIUM;
RT_TRACE(COMP_BT_COEXIST, DBG_TRACE, ("[DM][BT], RSSI_1 state stay at Medium\n"));
}
} else {
if(undecoratedsmoothed_pwdb < rssi_thresh1) {
bt_rssi_state = BT_RSSI_STATE_MEDIUM;
rtlpcipriv->btcoexist.current_state |= BT_COEX_STATE_WIFI_RSSI_1_MEDIUM;
rtlpcipriv->btcoexist.current_state &= ~BT_COEX_STATE_WIFI_RSSI_1_HIGH;
rtlpcipriv->btcoexist.current_state &= ~BT_COEX_STATE_WIFI_RSSI_1_LOW;
RT_TRACE(COMP_BT_COEXIST, DBG_TRACE,("[DM][BT], RSSI_1 state switch to Medium\n"));
} else {
bt_rssi_state = BT_RSSI_STATE_STAY_HIGH;
RT_TRACE(COMP_BT_COEXIST, DBG_TRACE, ("[DM][BT], RSSI_1 state stay at High\n"));
}
}
}
rtlpcipriv->btcoexist.bt_pre_rssi_state1 = bt_rssi_state;
return bt_rssi_state;
}
u8 rtl8821ae_dm_bt_check_coex_rssi_state(struct ieee80211_hw *hw,
u8 level_num, u8 rssi_thresh, u8 rssi_thresh1)
{
struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
struct rtl_priv *rtlpriv = rtl_priv(hw);
long undecoratedsmoothed_pwdb = 0;
u8 bt_rssi_state = 0;
undecoratedsmoothed_pwdb = rtl8821ae_dm_bt_get_rx_ss(hw);
if (level_num == 2) {
rtlpcipriv->btcoexist.current_state &= ~BT_COEX_STATE_WIFI_RSSI_MEDIUM;
if ((rtlpcipriv->btcoexist.bt_pre_rssi_state == BT_RSSI_STATE_LOW) ||
(rtlpcipriv->btcoexist.bt_pre_rssi_state == BT_RSSI_STATE_STAY_LOW)){
if (undecoratedsmoothed_pwdb
>= (rssi_thresh + BT_FW_COEX_THRESH_TOL)) {
bt_rssi_state = BT_RSSI_STATE_HIGH;
rtlpcipriv->btcoexist.current_state
|= BT_COEX_STATE_WIFI_RSSI_HIGH;
rtlpcipriv->btcoexist.current_state
&= ~BT_COEX_STATE_WIFI_RSSI_LOW;
RT_TRACE(COMP_BT_COEXIST, DBG_TRACE,
("[DM][BT], RSSI state switch to High\n"));
} else {
bt_rssi_state = BT_RSSI_STATE_STAY_LOW;
RT_TRACE(COMP_BT_COEXIST, DBG_TRACE,
("[DM][BT], RSSI state stay at Low\n"));
}
} else {
if (undecoratedsmoothed_pwdb < rssi_thresh) {
bt_rssi_state = BT_RSSI_STATE_LOW;
rtlpcipriv->btcoexist.current_state
|= BT_COEX_STATE_WIFI_RSSI_LOW;
rtlpcipriv->btcoexist.current_state
&= ~BT_COEX_STATE_WIFI_RSSI_HIGH;
RT_TRACE(COMP_BT_COEXIST, DBG_TRACE,
("[DM][BT], RSSI state switch to Low\n"));
} else {
bt_rssi_state = BT_RSSI_STATE_STAY_HIGH;
RT_TRACE(COMP_BT_COEXIST, DBG_TRACE,
("[DM][BT], RSSI state stay at High\n"));
}
}
}
else if (level_num == 3) {
if (rssi_thresh > rssi_thresh1) {
RT_TRACE(COMP_BT_COEXIST, DBG_TRACE,
("[DM][BT], RSSI thresh error!!\n"));
return rtlpcipriv->btcoexist.bt_pre_rssi_state;
}
if ((rtlpcipriv->btcoexist.bt_pre_rssi_state == BT_RSSI_STATE_LOW) ||
(rtlpcipriv->btcoexist.bt_pre_rssi_state == BT_RSSI_STATE_STAY_LOW)) {
if(undecoratedsmoothed_pwdb
>= (rssi_thresh + BT_FW_COEX_THRESH_TOL)) {
bt_rssi_state = BT_RSSI_STATE_MEDIUM;
rtlpcipriv->btcoexist.current_state
|= BT_COEX_STATE_WIFI_RSSI_MEDIUM;
rtlpcipriv->btcoexist.current_state
&= ~BT_COEX_STATE_WIFI_RSSI_LOW;
rtlpcipriv->btcoexist.current_state
&= ~BT_COEX_STATE_WIFI_RSSI_HIGH;
RT_TRACE(COMP_BT_COEXIST, DBG_TRACE,
("[DM][BT], RSSI state switch to Medium\n"));
} else {
bt_rssi_state = BT_RSSI_STATE_STAY_LOW;
RT_TRACE(COMP_BT_COEXIST, DBG_TRACE,
("[DM][BT], RSSI state stay at Low\n"));
}
} else if ((rtlpcipriv->btcoexist.bt_pre_rssi_state == BT_RSSI_STATE_MEDIUM) ||
(rtlpcipriv->btcoexist.bt_pre_rssi_state == BT_RSSI_STATE_STAY_MEDIUM)) {
if (undecoratedsmoothed_pwdb
>= (rssi_thresh1 + BT_FW_COEX_THRESH_TOL)) {
bt_rssi_state = BT_RSSI_STATE_HIGH;
rtlpcipriv->btcoexist.current_state
|= BT_COEX_STATE_WIFI_RSSI_HIGH;
rtlpcipriv->btcoexist.current_state
&= ~BT_COEX_STATE_WIFI_RSSI_LOW;
rtlpcipriv->btcoexist.current_state
&= ~BT_COEX_STATE_WIFI_RSSI_MEDIUM;
RT_TRACE(COMP_BT_COEXIST, DBG_TRACE,
("[DM][BT], RSSI state switch to High\n"));
} else if(undecoratedsmoothed_pwdb < rssi_thresh)
{
bt_rssi_state = BT_RSSI_STATE_LOW;
rtlpcipriv->btcoexist.current_state
|= BT_COEX_STATE_WIFI_RSSI_LOW;
rtlpcipriv->btcoexist.current_state
&= ~BT_COEX_STATE_WIFI_RSSI_HIGH;
rtlpcipriv->btcoexist.current_state
&= ~BT_COEX_STATE_WIFI_RSSI_MEDIUM;
RT_TRACE(COMP_BT_COEXIST, DBG_TRACE,
("[DM][BT], RSSI state switch to Low\n"));
} else {
bt_rssi_state = BT_RSSI_STATE_STAY_MEDIUM;
RT_TRACE(COMP_BT_COEXIST, DBG_TRACE,
("[DM][BT], RSSI state stay at Medium\n"));
}
} else {
if(undecoratedsmoothed_pwdb < rssi_thresh1) {
bt_rssi_state = BT_RSSI_STATE_MEDIUM;
rtlpcipriv->btcoexist.current_state
|= BT_COEX_STATE_WIFI_RSSI_MEDIUM;
rtlpcipriv->btcoexist.current_state
&= ~BT_COEX_STATE_WIFI_RSSI_HIGH;
rtlpcipriv->btcoexist.current_state
&= ~BT_COEX_STATE_WIFI_RSSI_LOW;
RT_TRACE(COMP_BT_COEXIST, DBG_TRACE,
("[DM][BT], RSSI state switch to Medium\n"));
} else {
bt_rssi_state = BT_RSSI_STATE_STAY_HIGH;
RT_TRACE(COMP_BT_COEXIST, DBG_TRACE,
("[DM][BT], RSSI state stay at High\n"));
}
}
}
rtlpcipriv->btcoexist.bt_pre_rssi_state = bt_rssi_state;
return bt_rssi_state;
}
long rtl8821ae_dm_bt_get_rx_ss(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
long undecoratedsmoothed_pwdb = 0;
if (rtlpriv->mac80211.link_state >= MAC80211_LINKED) {
undecoratedsmoothed_pwdb = GET_UNDECORATED_AVERAGE_RSSI(rtlpriv);
} else {
undecoratedsmoothed_pwdb
= rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
}
RT_TRACE(COMP_BT_COEXIST, DBG_TRACE,
("rtl8821ae_dm_bt_get_rx_ss() = %ld\n", undecoratedsmoothed_pwdb));
return undecoratedsmoothed_pwdb;
}
void rtl8821ae_dm_bt_balance(struct ieee80211_hw *hw,
bool b_balance_on, u8 ms0, u8 ms1)
{
struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
struct rtl_priv *rtlpriv = rtl_priv(hw);
u8 h2c_parameter[3] ={0};
if (b_balance_on) {
h2c_parameter[2] = 1;
h2c_parameter[1] = ms1;
h2c_parameter[0] = ms0;
rtlpcipriv->btcoexist.b_fw_coexist_all_off = false;
} else {
h2c_parameter[2] = 0;
h2c_parameter[1] = 0;
h2c_parameter[0] = 0;
}
rtlpcipriv->btcoexist.b_balance_on = b_balance_on;
RT_TRACE(COMP_BT_COEXIST, DBG_TRACE,
("[DM][BT], Balance=[%s:%dms:%dms], write 0xc=0x%x\n",
b_balance_on?"ON":"OFF", ms0, ms1,
h2c_parameter[0]<<16 | h2c_parameter[1]<<8 | h2c_parameter[2]));
rtl8821ae_fill_h2c_cmd(hw, 0xc, 3, h2c_parameter);
}
void rtl8821ae_dm_bt_agc_table(struct ieee80211_hw *hw, u8 type)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
if (type == BT_AGCTABLE_OFF) {
RT_TRACE(COMP_BT_COEXIST, DBG_TRACE, ("[BT]AGCTable Off!\n"));
rtl_write_dword(rtlpriv, 0xc78,0x641c0001);
rtl_write_dword(rtlpriv, 0xc78,0x631d0001);
rtl_write_dword(rtlpriv, 0xc78,0x621e0001);
rtl_write_dword(rtlpriv, 0xc78,0x611f0001);
rtl_write_dword(rtlpriv, 0xc78,0x60200001);
rtl8821ae_phy_set_rf_reg(hw, RF90_PATH_A,
RF_RX_AGC_HP, 0xfffff, 0x32000);
rtl8821ae_phy_set_rf_reg(hw, RF90_PATH_A,
RF_RX_AGC_HP, 0xfffff, 0x71000);
rtl8821ae_phy_set_rf_reg(hw, RF90_PATH_A,
RF_RX_AGC_HP, 0xfffff, 0xb0000);
rtl8821ae_phy_set_rf_reg(hw, RF90_PATH_A,
RF_RX_AGC_HP, 0xfffff, 0xfc000);
rtl8821ae_phy_set_rf_reg(hw, RF90_PATH_A,
RF_RX_G1, 0xfffff, 0x30355);
} else if (type == BT_AGCTABLE_ON) {
RT_TRACE(COMP_BT_COEXIST, DBG_TRACE, ("[BT]AGCTable On!\n"));
rtl_write_dword(rtlpriv, 0xc78,0x4e1c0001);
rtl_write_dword(rtlpriv, 0xc78,0x4d1d0001);
rtl_write_dword(rtlpriv, 0xc78,0x4c1e0001);
rtl_write_dword(rtlpriv, 0xc78,0x4b1f0001);
rtl_write_dword(rtlpriv, 0xc78,0x4a200001);
rtl8821ae_phy_set_rf_reg(hw, RF90_PATH_A,
RF_RX_AGC_HP, 0xfffff, 0xdc000);
rtl8821ae_phy_set_rf_reg(hw, RF90_PATH_A,
RF_RX_AGC_HP, 0xfffff, 0x90000);
rtl8821ae_phy_set_rf_reg(hw, RF90_PATH_A,
RF_RX_AGC_HP, 0xfffff, 0x51000);
rtl8821ae_phy_set_rf_reg(hw, RF90_PATH_A,
RF_RX_AGC_HP, 0xfffff, 0x12000);
rtl8821ae_phy_set_rf_reg(hw, RF90_PATH_A,
RF_RX_G1, 0xfffff, 0x00355);
rtlpcipriv->btcoexist.b_sw_coexist_all_off = false;
}
}
void rtl8821ae_dm_bt_bb_back_off_level(struct ieee80211_hw *hw, u8 type)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
if (type == BT_BB_BACKOFF_OFF) {
RT_TRACE(COMP_BT_COEXIST, DBG_TRACE, ("[BT]BBBackOffLevel Off!\n"));
rtl_write_dword(rtlpriv, 0xc04,0x3a05611);
} else if (type == BT_BB_BACKOFF_ON) {
RT_TRACE(COMP_BT_COEXIST, DBG_TRACE, ("[BT]BBBackOffLevel On!\n"));
rtl_write_dword(rtlpriv, 0xc04,0x3a07611);
rtlpcipriv->btcoexist.b_sw_coexist_all_off = false;
}
}
void rtl8821ae_dm_bt_fw_coex_all_off(struct ieee80211_hw *hw)
{
struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
struct rtl_priv *rtlpriv = rtl_priv(hw);
RT_TRACE(COMP_BT_COEXIST, DBG_TRACE,
("rtl8821ae_dm_bt_fw_coex_all_off()\n"));
if(rtlpcipriv->btcoexist.b_fw_coexist_all_off)
return;
RT_TRACE(COMP_BT_COEXIST, DBG_TRACE,
("rtl8821ae_dm_bt_fw_coex_all_off(), real Do\n"));
rtl8821ae_dm_bt_fw_coex_all_off_8723a(hw);
rtlpcipriv->btcoexist.b_fw_coexist_all_off = true;
}
void rtl8821ae_dm_bt_sw_coex_all_off(struct ieee80211_hw *hw)
{
struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
struct rtl_priv *rtlpriv = rtl_priv(hw);
RT_TRACE(COMP_BT_COEXIST, DBG_TRACE,
("rtl8821ae_dm_bt_sw_coex_all_off()\n"));
if(rtlpcipriv->btcoexist.b_sw_coexist_all_off)
return;
RT_TRACE(COMP_BT_COEXIST, DBG_TRACE,
("rtl8821ae_dm_bt_sw_coex_all_off(), real Do\n"));
rtl8821ae_dm_bt_sw_coex_all_off_8723a(hw);
rtlpcipriv->btcoexist.b_sw_coexist_all_off = true;
}
void rtl8821ae_dm_bt_hw_coex_all_off(struct ieee80211_hw *hw)
{
struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
struct rtl_priv *rtlpriv = rtl_priv(hw);
RT_TRACE(COMP_BT_COEXIST, DBG_TRACE,
("rtl8821ae_dm_bt_hw_coex_all_off()\n"));
if(rtlpcipriv->btcoexist.b_hw_coexist_all_off)
return;
RT_TRACE(COMP_BT_COEXIST, DBG_TRACE,
("rtl8821ae_dm_bt_hw_coex_all_off(), real Do\n"));
rtl8821ae_dm_bt_hw_coex_all_off_8723a(hw);
rtlpcipriv->btcoexist.b_hw_coexist_all_off = true;
}
void rtl8821ae_btdm_coex_all_off(struct ieee80211_hw *hw)
{
rtl8821ae_dm_bt_fw_coex_all_off(hw);
rtl8821ae_dm_bt_sw_coex_all_off(hw);
rtl8821ae_dm_bt_hw_coex_all_off(hw);
}
bool rtl8821ae_dm_bt_is_coexist_state_changed(struct ieee80211_hw *hw)
{
struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
if((rtlpcipriv->btcoexist.previous_state
== rtlpcipriv->btcoexist.current_state)
&& (rtlpcipriv->btcoexist.previous_state_h
== rtlpcipriv->btcoexist.current_state_h))
return false;
else
return true;
}
bool rtl8821ae_dm_bt_is_wifi_up_link(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
if (rtlpriv->link_info.b_tx_busy_traffic)
return true;
else
return false;
}

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/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __RTL8821AE_HAL_BT_COEXIST_H__
#define __RTL8821AE_HAL_BT_COEXIST_H__
#include "../wifi.h"
/* The reg define is for 8723 */
#define REG_HIGH_PRIORITY_TXRX 0x770
#define REG_LOW_PRIORITY_TXRX 0x774
#define BT_FW_COEX_THRESH_TOL 6
#define BT_FW_COEX_THRESH_20 20
#define BT_FW_COEX_THRESH_23 23
#define BT_FW_COEX_THRESH_25 25
#define BT_FW_COEX_THRESH_30 30
#define BT_FW_COEX_THRESH_35 35
#define BT_FW_COEX_THRESH_40 40
#define BT_FW_COEX_THRESH_45 45
#define BT_FW_COEX_THRESH_47 47
#define BT_FW_COEX_THRESH_50 50
#define BT_FW_COEX_THRESH_55 55
#define BT_COEX_STATE_BT30 BIT(0)
#define BT_COEX_STATE_WIFI_HT20 BIT(1)
#define BT_COEX_STATE_WIFI_HT40 BIT(2)
#define BT_COEX_STATE_WIFI_LEGACY BIT(3)
#define BT_COEX_STATE_WIFI_RSSI_LOW BIT(4)
#define BT_COEX_STATE_WIFI_RSSI_MEDIUM BIT(5)
#define BT_COEX_STATE_WIFI_RSSI_HIGH BIT(6)
#define BT_COEX_STATE_DEC_BT_POWER BIT(7)
#define BT_COEX_STATE_WIFI_IDLE BIT(8)
#define BT_COEX_STATE_WIFI_UPLINK BIT(9)
#define BT_COEX_STATE_WIFI_DOWNLINK BIT(10)
#define BT_COEX_STATE_BT_INQ_PAGE BIT(11)
#define BT_COEX_STATE_BT_IDLE BIT(12)
#define BT_COEX_STATE_BT_UPLINK BIT(13)
#define BT_COEX_STATE_BT_DOWNLINK BIT(14)
#define BT_COEX_STATE_HOLD_FOR_BT_OPERATION BIT(15)
#define BT_COEX_STATE_BT_RSSI_LOW BIT(19)
#define BT_COEX_STATE_PROFILE_HID BIT(20)
#define BT_COEX_STATE_PROFILE_A2DP BIT(21)
#define BT_COEX_STATE_PROFILE_PAN BIT(22)
#define BT_COEX_STATE_PROFILE_SCO BIT(23)
#define BT_COEX_STATE_WIFI_RSSI_1_LOW BIT(24)
#define BT_COEX_STATE_WIFI_RSSI_1_MEDIUM BIT(25)
#define BT_COEX_STATE_WIFI_RSSI_1_HIGH BIT(26)
#define BT_COEX_STATE_BTINFO_COMMON BIT(30)
#define BT_COEX_STATE_BTINFO_B_HID_SCOESCO BIT(31)
#define BT_COEX_STATE_BTINFO_B_FTP_A2DP BIT(29)
#define BT_COEX_STATE_BT_CNT_LEVEL_0 BIT(0)
#define BT_COEX_STATE_BT_CNT_LEVEL_1 BIT(1)
#define BT_COEX_STATE_BT_CNT_LEVEL_2 BIT(2)
#define BT_COEX_STATE_BT_CNT_LEVEL_3 BIT(3)
#define BT_RSSI_STATE_HIGH 0
#define BT_RSSI_STATE_MEDIUM 1
#define BT_RSSI_STATE_LOW 2
#define BT_RSSI_STATE_STAY_HIGH 3
#define BT_RSSI_STATE_STAY_MEDIUM 4
#define BT_RSSI_STATE_STAY_LOW 5
#define BT_AGCTABLE_OFF 0
#define BT_AGCTABLE_ON 1
#define BT_BB_BACKOFF_OFF 0
#define BT_BB_BACKOFF_ON 1
#define BT_FW_NAV_OFF 0
#define BT_FW_NAV_ON 1
#define BT_COEX_MECH_NONE 0
#define BT_COEX_MECH_SCO 1
#define BT_COEX_MECH_HID 2
#define BT_COEX_MECH_A2DP 3
#define BT_COEX_MECH_PAN 4
#define BT_COEX_MECH_HID_A2DP 5
#define BT_COEX_MECH_HID_PAN 6
#define BT_COEX_MECH_PAN_A2DP 7
#define BT_COEX_MECH_HID_SCO_ESCO 8
#define BT_COEX_MECH_FTP_A2DP 9
#define BT_COEX_MECH_COMMON 10
#define BT_COEX_MECH_MAX 11
#define BT_DBG_PROFILE_NONE 0
#define BT_DBG_PROFILE_SCO 1
#define BT_DBG_PROFILE_HID 2
#define BT_DBG_PROFILE_A2DP 3
#define BT_DBG_PROFILE_PAN 4
#define BT_DBG_PROFILE_HID_A2DP 5
#define BT_DBG_PROFILE_HID_PAN 6
#define BT_DBG_PROFILE_PAN_A2DP 7
#define BT_DBG_PROFILE_MAX 9
#define BTINFO_B_FTP BIT(7)
#define BTINFO_B_A2DP BIT(6)
#define BTINFO_B_HID BIT(5)
#define BTINFO_B_SCO_BUSY BIT(4)
#define BTINFO_B_ACL_BUSY BIT(3)
#define BTINFO_B_INQ_PAGE BIT(2)
#define BTINFO_B_SCO_ESCO BIT(1)
#define BTINFO_B_CONNECTION BIT(0)
void rtl8821ae_btdm_coex_all_off(struct ieee80211_hw *hw);
void rtl8821ae_dm_bt_fw_coex_all_off(struct ieee80211_hw *hw);
void rtl8821ae_dm_bt_sw_coex_all_off(struct ieee80211_hw *hw);
void rtl8821ae_dm_bt_hw_coex_all_off(struct ieee80211_hw *hw);
long rtl8821ae_dm_bt_get_rx_ss(struct ieee80211_hw *hw);
void rtl8821ae_dm_bt_balance(struct ieee80211_hw *hw,
bool b_balance_on, u8 ms0, u8 ms1);
void rtl8821ae_dm_bt_agc_table(struct ieee80211_hw *hw, u8 tyep);
void rtl8821ae_dm_bt_bb_back_off_level(struct ieee80211_hw *hw, u8 type);
u8 rtl8821ae_dm_bt_check_coex_rssi_state(struct ieee80211_hw *hw,
u8 level_num, u8 rssi_thresh, u8 rssi_thresh1);
u8 rtl8821ae_dm_bt_check_coex_rssi_state1(struct ieee80211_hw *hw,
u8 level_num, u8 rssi_thresh, u8 rssi_thresh1);
void _rtl8821ae_dm_bt_check_wifi_state(struct ieee80211_hw *hw);
void rtl8821ae_dm_bt_reject_ap_aggregated_packet(struct ieee80211_hw *hw,
bool b_reject);
#if 0
VOID
BTDM_PWDBMonitor(
PADAPTER Adapter
);
BOOLEAN
BTDM_DIGByBTRSSI(
PADAPTER Adapter
);
#endif
bool rtl8821ae_dm_bt_is_coexist_state_changed(struct ieee80211_hw *hw);
bool rtl8821ae_dm_bt_is_wifi_up_link(struct ieee80211_hw *hw);
#endif

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/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __RTL8821AE_HAL_BTC_H__
#define __RTL8821AE_HAL_BTC_H__
#include "../wifi.h"
#include "btc.h"
#include "hal_bt_coexist.h"
#define BT_TXRX_CNT_THRES_1 1200
#define BT_TXRX_CNT_THRES_2 1400
#define BT_TXRX_CNT_THRES_3 3000
#define BT_TXRX_CNT_LEVEL_0 0 // < 1200
#define BT_TXRX_CNT_LEVEL_1 1 // >= 1200 && < 1400
#define BT_TXRX_CNT_LEVEL_2 2 // >= 1400
#define BT_TXRX_CNT_LEVEL_3 3
#define BT_COEX_DISABLE 0
#define BT_Q_PKT_OFF 0
#define BT_Q_PKT_ON 1
#define BT_TX_PWR_OFF 0
#define BT_TX_PWR_ON 1
/* TDMA mode definition */
#define TDMA_2ANT 0
#define TDMA_1ANT 1
#define TDMA_NAV_OFF 0
#define TDMA_NAV_ON 1
#define TDMA_DAC_SWING_OFF 0
#define TDMA_DAC_SWING_ON 1
/* PTA mode related definition */
#define BT_PTA_MODE_OFF 0
#define BT_PTA_MODE_ON 1
/* Penalty Tx Rate Adaptive */
#define BT_TX_RATE_ADAPTIVE_NORMAL 0
#define BT_TX_RATE_ADAPTIVE_LOW_PENALTY 1
/* RF Corner */
#define BT_RF_RX_LPF_CORNER_RESUME 0
#define BT_RF_RX_LPF_CORNER_SHRINK 1
#define C2H_EVT_HOST_CLOSE 0x00
#define C2H_EVT_FW_CLOSE 0xFF
enum bt_traffic_mode {
BT_MOTOR_EXT_BE = 0x00,
BT_MOTOR_EXT_GUL = 0x01,
BT_MOTOR_EXT_GUB = 0x02,
BT_MOTOR_EXT_GULB = 0x03
};
enum bt_traffic_mode_profile {
BT_PROFILE_NONE,
BT_PROFILE_A2DP,
BT_PROFILE_PAN,
BT_PROFILE_HID,
BT_PROFILE_SCO
};
enum hci_ext_bt_operation {
HCI_BT_OP_NONE = 0x0,
HCI_BT_OP_INQUIRE_START = 0x1,
HCI_BT_OP_INQUIRE_FINISH = 0x2,
HCI_BT_OP_PAGING_START = 0x3,
HCI_BT_OP_PAGING_SUCCESS = 0x4,
HCI_BT_OP_PAGING_UNSUCCESS = 0x5,
HCI_BT_OP_PAIRING_START = 0x6,
HCI_BT_OP_PAIRING_FINISH = 0x7,
HCI_BT_OP_BT_DEV_ENABLE = 0x8,
HCI_BT_OP_BT_DEV_DISABLE = 0x9,
HCI_BT_OP_MAX,
};
enum bt_spec {
BT_SPEC_1_0_b = 0x00,
BT_SPEC_1_1 = 0x01,
BT_SPEC_1_2 = 0x02,
BT_SPEC_2_0_EDR = 0x03,
BT_SPEC_2_1_EDR = 0x04,
BT_SPEC_3_0_HS = 0x05,
BT_SPEC_4_0 = 0x06
};
struct c2h_evt_hdr {
u8 cmd_id;
u8 cmd_len;
u8 cmd_seq;
};
enum bt_state{
BT_INFO_STATE_DISABLED = 0,
BT_INFO_STATE_NO_CONNECTION = 1,
BT_INFO_STATE_CONNECT_IDLE = 2,
BT_INFO_STATE_INQ_OR_PAG = 3,
BT_INFO_STATE_ACL_ONLY_BUSY = 4,
BT_INFO_STATE_SCO_ONLY_BUSY = 5,
BT_INFO_STATE_ACL_SCO_BUSY = 6,
BT_INFO_STATE_HID_BUSY = 7,
BT_INFO_STATE_HID_SCO_BUSY = 8,
BT_INFO_STATE_MAX = 7
};
enum rtl8723be_c2h_evt {
C2H_DBG = 0,
C2H_TSF = 1,
C2H_AP_RPT_RSP = 2,
C2H_CCX_TX_RPT = 3, // The FW notify the report of the specific tx packet.
C2H_BT_RSSI = 4,
C2H_BT_OP_MODE = 5,
C2H_HW_INFO_EXCH = 10,
C2H_C2H_H2C_TEST = 11,
BT_INFO = 9,
MAX_C2HEVENT
};
void rtl8821ae_dm_bt_fw_coex_all_off_8723a(struct ieee80211_hw *hw);
void rtl8821ae_dm_bt_sw_coex_all_off_8723a(struct ieee80211_hw *hw);
void rtl8821ae_dm_bt_hw_coex_all_off_8723a(struct ieee80211_hw *hw);
void rtl8821ae_dm_bt_coexist(struct ieee80211_hw *hw);
void rtl8821ae_dm_bt_set_bt_dm(struct ieee80211_hw *hw, struct btdm_8821ae *p_btdm);
void rtl_8821ae_c2h_command_handle(struct ieee80211_hw * hw);
void rtl_8821ae_bt_wifi_media_status_notify(struct ieee80211_hw * hw, bool mstatus);
void rtl8821ae_dm_bt_turn_off_bt_coexist_before_enter_lps(struct ieee80211_hw *hw);
#endif

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/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __RTL8821AE_HW_H__
#define __RTL8821AE_HW_H__
void rtl8821ae_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val);
void rtl8821ae_read_eeprom_info(struct ieee80211_hw *hw);
void rtl8821ae_interrupt_recognized(struct ieee80211_hw *hw,
u32 *p_inta, u32 *p_intb);
int rtl8821ae_hw_init(struct ieee80211_hw *hw);
void rtl8821ae_card_disable(struct ieee80211_hw *hw);
void rtl8821ae_enable_interrupt(struct ieee80211_hw *hw);
void rtl8821ae_disable_interrupt(struct ieee80211_hw *hw);
int rtl8821ae_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type);
void rtl8821ae_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid);
void rtl8821ae_set_qos(struct ieee80211_hw *hw, int aci);
void rtl8821ae_set_beacon_related_registers(struct ieee80211_hw *hw);
void rtl8821ae_set_beacon_interval(struct ieee80211_hw *hw);
void rtl8821ae_update_interrupt_mask(struct ieee80211_hw *hw,
u32 add_msr, u32 rm_msr);
void rtl8821ae_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val);
void rtl8821ae_update_hal_rate_tbl(struct ieee80211_hw *hw,
struct ieee80211_sta *sta,
u8 rssi_level);
void rtl8821ae_update_channel_access_setting(struct ieee80211_hw *hw);
bool rtl8821ae_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid);
void rtl8821ae_enable_hw_security_config(struct ieee80211_hw *hw);
void rtl8821ae_set_key(struct ieee80211_hw *hw, u32 key_index,
u8 *p_macaddr, bool is_group, u8 enc_algo,
bool is_wepkey, bool clear_all);
void rtl8821ae_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
bool autoload_fail,
u8* hwinfo);
void rtl8812ae_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
bool autoload_fail,
u8* hwinfo);
void rtl8821ae_bt_reg_init(struct ieee80211_hw* hw);
void rtl8821ae_bt_hw_init(struct ieee80211_hw* hw);
void rtl8821ae_suspend(struct ieee80211_hw *hw);
void rtl8821ae_resume(struct ieee80211_hw *hw);
void rtl8821ae_allow_all_destaddr(struct ieee80211_hw *hw,
bool allow_all_da,
bool write_into_reg);
void _rtl8821ae_stop_tx_beacon(struct ieee80211_hw *hw);
void _rtl8821ae_resume_tx_beacon(struct ieee80211_hw *hw);
#endif

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/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "../wifi.h"
#include "../pci.h"
#include "reg.h"
static void _rtl8821ae_init_led(struct ieee80211_hw *hw,
struct rtl_led *pled,
enum rtl_led_pin ledpin)
{
pled->hw = hw;
pled->ledpin = ledpin;
pled->b_ledon = false;
}
void rtl8821ae_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled)
{
u8 ledcfg;
struct rtl_priv *rtlpriv = rtl_priv(hw);
RT_TRACE(COMP_LED, DBG_LOUD,
("LedAddr:%X ledpin=%d\n", REG_LEDCFG2, pled->ledpin));
switch (pled->ledpin) {
case LED_PIN_GPIO0:
break;
case LED_PIN_LED0:
ledcfg = rtl_read_byte(rtlpriv, REG_LEDCFG2);
ledcfg &= ~BIT(6);
rtl_write_byte(rtlpriv,
REG_LEDCFG2, (ledcfg & 0xf0) | BIT(5));
break;
case LED_PIN_LED1:
ledcfg = rtl_read_byte(rtlpriv, REG_LEDCFG1);
rtl_write_byte(rtlpriv, REG_LEDCFG1, ledcfg & 0x10);
break;
default:
RT_TRACE(COMP_ERR, DBG_EMERG,
("switch case not process \n"));
break;
}
pled->b_ledon = true;
}
void rtl8812ae_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled)
{
u16 ledreg = REG_LEDCFG1;
u8 ledcfg = 0;
struct rtl_priv *rtlpriv = rtl_priv(hw);
switch (pled->ledpin) {
case LED_PIN_LED0:
ledreg = REG_LEDCFG1;
break;
case LED_PIN_LED1:
ledreg = REG_LEDCFG2;
break;
case LED_PIN_GPIO0:
default:
break;
}
RT_TRACE(COMP_LED, DBG_LOUD, ("In SwLedOn, LedAddr:%X LEDPIN=%d \n", ledreg, pled->ledpin));
ledcfg = rtl_read_byte(rtlpriv, ledreg);
ledcfg |= BIT(5); /*Set 0x4c[21]*/
ledcfg &= ~(BIT(7) | BIT(6) | BIT(3) |BIT(2) | BIT(1) |BIT(0));
/*Clear 0x4c[23:22] and 0x4c[19:16]*/
rtl_write_byte(rtlpriv, ledreg, ledcfg); /*SW control led0 on.*/
pled->b_ledon = true;
}
void rtl8821ae_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
u8 ledcfg;
RT_TRACE(COMP_LED, DBG_LOUD,
("LedAddr:%X ledpin=%d\n", REG_LEDCFG2, pled->ledpin));
ledcfg = rtl_read_byte(rtlpriv, REG_LEDCFG2);
switch (pled->ledpin) {
case LED_PIN_GPIO0:
break;
case LED_PIN_LED0:
ledcfg &= 0xf0;
if (pcipriv->ledctl.bled_opendrain == true) {
ledcfg &= 0x90; /* Set to software control. */
rtl_write_byte(rtlpriv, REG_LEDCFG2, (ledcfg|BIT(3)));
ledcfg = rtl_read_byte(rtlpriv, REG_MAC_PINMUX_CFG);
ledcfg &= 0xFE;
rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG, ledcfg);
}
else {
ledcfg &= ~BIT(6);
rtl_write_byte(rtlpriv, REG_LEDCFG2,
(ledcfg | BIT(3) | BIT(5)));
}
break;
case LED_PIN_LED1:
ledcfg = rtl_read_byte(rtlpriv, REG_LEDCFG1);
ledcfg &= 0x10; /* Set to software control. */
rtl_write_byte(rtlpriv, REG_LEDCFG1, ledcfg|BIT(3));
break;
default:
RT_TRACE(COMP_ERR, DBG_EMERG,
("switch case not process \n"));
break;
}
pled->b_ledon = false;
}
void rtl8812ae_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled){
u16 ledreg = REG_LEDCFG1;
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
switch(pled->ledpin)
{
case LED_PIN_LED0:
ledreg = REG_LEDCFG1;
break;
case LED_PIN_LED1:
ledreg = REG_LEDCFG2;
break;
case LED_PIN_GPIO0:
default:
break;
}
RT_TRACE(COMP_LED,DBG_LOUD,("In SwLedOff,LedAddr:%X LEDPIN=%d\n", ledreg, pled->ledpin));
if(pcipriv->ledctl.bled_opendrain == true) /*Open-drain arrangement for controlling the LED*/
{
u8 ledcfg = rtl_read_byte(rtlpriv, ledreg);
ledreg &= 0xd0; /* Set to software control.*/
rtl_write_byte(rtlpriv, ledreg, (ledcfg | BIT(3)));
/*Open-drain arrangement*/
ledcfg = rtl_read_byte(rtlpriv, REG_MAC_PINMUX_CFG);
ledcfg &= 0xFE;/*Set GPIO[8] to input mode*/
rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG, ledcfg);
}
else
{
rtl_write_byte(rtlpriv, ledreg, 0x28);
}
pled->b_ledon = false;
}
void rtl8821ae_init_sw_leds(struct ieee80211_hw *hw)
{
struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
_rtl8821ae_init_led(hw, &(pcipriv->ledctl.sw_led0), LED_PIN_LED0);
_rtl8821ae_init_led(hw, &(pcipriv->ledctl.sw_led1), LED_PIN_LED1);
}
static void _rtl8821ae_sw_led_control(struct ieee80211_hw *hw,
enum led_ctl_mode ledaction)
{
struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
switch (ledaction) {
case LED_CTL_POWER_ON:
case LED_CTL_LINK:
case LED_CTL_NO_LINK:
if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
rtl8812ae_sw_led_on(hw, pLed0);
else
rtl8821ae_sw_led_on(hw, pLed0);
break;
case LED_CTL_POWER_OFF:
if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)\
rtl8812ae_sw_led_off(hw, pLed0);
else
rtl8821ae_sw_led_off(hw, pLed0);
break;
default:
break;
}
}
void rtl8821ae_led_control(struct ieee80211_hw *hw,
enum led_ctl_mode ledaction)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
if ((ppsc->rfoff_reason > RF_CHANGE_BY_PS) &&
(ledaction == LED_CTL_TX ||
ledaction == LED_CTL_RX ||
ledaction == LED_CTL_SITE_SURVEY ||
ledaction == LED_CTL_LINK ||
ledaction == LED_CTL_NO_LINK ||
ledaction == LED_CTL_START_TO_LINK ||
ledaction == LED_CTL_POWER_ON)) {
return;
}
RT_TRACE(COMP_LED, DBG_LOUD, ("ledaction %d, \n",
ledaction));
_rtl8821ae_sw_led_control(hw, ledaction);
}

40
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/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __RTL8821AE_LED_H__
#define __RTL8821AE_LED_H__
void rtl8821ae_init_sw_leds(struct ieee80211_hw *hw);
void rtl8821ae_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled);
void rtl8812ae_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled);
void rtl8821ae_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled);
void rtl8812ae_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled);
void rtl8821ae_led_control(struct ieee80211_hw *hw, enum led_ctl_mode ledaction);
#endif

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258
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/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __RTL8821AE_PHY_H__
#define __RTL8821AE_PHY_H__
/*It must always set to 4, otherwise read efuse table secquence will be wrong.*/
#define MAX_TX_COUNT 4
#define TX_1S 0
#define TX_2S 1
#define TX_3S 2
#define TX_4S 3
#define MAX_POWER_INDEX 0x3F
#define MAX_PRECMD_CNT 16
#define MAX_RFDEPENDCMD_CNT 16
#define MAX_POSTCMD_CNT 16
#define MAX_DOZE_WAITING_TIMES_9x 64
#define RT_CANNOT_IO(hw) false
#define HIGHPOWER_RADIOA_ARRAYLEN 22
#define IQK_ADDA_REG_NUM 16
#define IQK_BB_REG_NUM 9
#define MAX_TOLERANCE 5
#define IQK_DELAY_TIME 10
#define index_mapping_NUM 15
#define APK_BB_REG_NUM 5
#define APK_AFE_REG_NUM 16
#define APK_CURVE_REG_NUM 4
#define PATH_NUM 2
#define LOOP_LIMIT 5
#define MAX_STALL_TIME 50
#define AntennaDiversityValue 0x80
#define MAX_TXPWR_IDX_NMODE_92S 63
#define Reset_Cnt_Limit 3
#define IQK_ADDA_REG_NUM 16
#define IQK_MAC_REG_NUM 4
#define RF6052_MAX_PATH 2
#define CT_OFFSET_MAC_ADDR 0X16
#define CT_OFFSET_CCK_TX_PWR_IDX 0x5A
#define CT_OFFSET_HT401S_TX_PWR_IDX 0x60
#define CT_OFFSET_HT402S_TX_PWR_IDX_DIFF 0x66
#define CT_OFFSET_HT20_TX_PWR_IDX_DIFF 0x69
#define CT_OFFSET_OFDM_TX_PWR_IDX_DIFF 0x6C
#define CT_OFFSET_HT40_MAX_PWR_OFFSET 0x6F
#define CT_OFFSET_HT20_MAX_PWR_OFFSET 0x72
#define CT_OFFSET_CHANNEL_PLAH 0x75
#define CT_OFFSET_THERMAL_METER 0x78
#define CT_OFFSET_RF_OPTION 0x79
#define CT_OFFSET_VERSION 0x7E
#define CT_OFFSET_CUSTOMER_ID 0x7F
#define RTL8821AE_MAX_PATH_NUM 2
#define TARGET_CHNL_NUM_2G_5G_8812 59
enum swchnlcmd_id {
CMDID_END,
CMDID_SET_TXPOWEROWER_LEVEL,
CMDID_BBREGWRITE10,
CMDID_WRITEPORT_ULONG,
CMDID_WRITEPORT_USHORT,
CMDID_WRITEPORT_UCHAR,
CMDID_RF_WRITEREG,
};
struct swchnlcmd {
enum swchnlcmd_id cmdid;
u32 para1;
u32 para2;
u32 msdelay;
};
enum hw90_block_e {
HW90_BLOCK_MAC = 0,
HW90_BLOCK_PHY0 = 1,
HW90_BLOCK_PHY1 = 2,
HW90_BLOCK_RF = 3,
HW90_BLOCK_MAXIMUM = 4,
};
enum baseband_config_type {
BASEBAND_CONFIG_PHY_REG = 0,
BASEBAND_CONFIG_AGC_TAB = 1,
};
enum ra_offset_area {
RA_OFFSET_LEGACY_OFDM1,
RA_OFFSET_LEGACY_OFDM2,
RA_OFFSET_HT_OFDM1,
RA_OFFSET_HT_OFDM2,
RA_OFFSET_HT_OFDM3,
RA_OFFSET_HT_OFDM4,
RA_OFFSET_HT_CCK,
};
enum antenna_path {
ANTENNA_NONE,
ANTENNA_D,
ANTENNA_C,
ANTENNA_CD,
ANTENNA_B,
ANTENNA_BD,
ANTENNA_BC,
ANTENNA_BCD,
ANTENNA_A,
ANTENNA_AD,
ANTENNA_AC,
ANTENNA_ACD,
ANTENNA_AB,
ANTENNA_ABD,
ANTENNA_ABC,
ANTENNA_ABCD
};
struct r_antenna_select_ofdm {
u32 r_tx_antenna:4;
u32 r_ant_l:4;
u32 r_ant_non_ht:4;
u32 r_ant_ht1:4;
u32 r_ant_ht2:4;
u32 r_ant_ht_s1:4;
u32 r_ant_non_ht_s1:4;
u32 ofdm_txsc:2;
u32 reserved:2;
};
struct r_antenna_select_cck {
u8 r_cckrx_enable_2:2;
u8 r_cckrx_enable:2;
u8 r_ccktx_enable:4;
};
struct efuse_contents {
u8 mac_addr[ETH_ALEN];
u8 cck_tx_power_idx[6];
u8 ht40_1s_tx_power_idx[6];
u8 ht40_2s_tx_power_idx_diff[3];
u8 ht20_tx_power_idx_diff[3];
u8 ofdm_tx_power_idx_diff[3];
u8 ht40_max_power_offset[3];
u8 ht20_max_power_offset[3];
u8 channel_plan;
u8 thermal_meter;
u8 rf_option[5];
u8 version;
u8 oem_id;
u8 regulatory;
};
struct tx_power_struct {
u8 cck[RTL8821AE_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
u8 ht40_1s[RTL8821AE_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
u8 ht40_2s[RTL8821AE_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
u8 ht20_diff[RTL8821AE_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
u8 legacy_ht_diff[RTL8821AE_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
u8 legacy_ht_txpowerdiff;
u8 groupht20[RTL8821AE_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
u8 groupht40[RTL8821AE_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
u8 pwrgroup_cnt;
u32 mcs_original_offset[4][16];
};
enum _ANT_DIV_TYPE
{
NO_ANTDIV = 0xFF,
CG_TRX_HW_ANTDIV = 0x01,
CGCS_RX_HW_ANTDIV = 0x02,
FIXED_HW_ANTDIV = 0x03,
CG_TRX_SMART_ANTDIV = 0x04,
CGCS_RX_SW_ANTDIV = 0x05,
};
extern u32 rtl8821ae_phy_query_bb_reg(struct ieee80211_hw *hw,
u32 regaddr, u32 bitmask);
extern void rtl8821ae_phy_set_bb_reg(struct ieee80211_hw *hw,
u32 regaddr, u32 bitmask, u32 data);
extern u32 rtl8821ae_phy_query_rf_reg(struct ieee80211_hw *hw,
enum radio_path rfpath, u32 regaddr,
u32 bitmask);
extern void rtl8821ae_phy_set_rf_reg(struct ieee80211_hw *hw,
enum radio_path rfpath, u32 regaddr,
u32 bitmask, u32 data);
extern bool rtl8821ae_phy_mac_config(struct ieee80211_hw *hw);
extern bool rtl8821ae_phy_bb_config(struct ieee80211_hw *hw);
extern bool rtl8821ae_phy_rf_config(struct ieee80211_hw *hw);
extern void rtl8821ae_phy_switch_wirelessband(struct ieee80211_hw *hw, u8 band);
extern void rtl8821ae_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw);
extern void rtl8821ae_phy_get_txpower_level(struct ieee80211_hw *hw,
long *powerlevel);
extern void rtl8821ae_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel);
extern void rtl8821ae_phy_scan_operation_backup(struct ieee80211_hw *hw,
u8 operation);
extern void rtl8821ae_phy_set_bw_mode_callback(struct ieee80211_hw *hw);
extern void rtl8821ae_phy_set_bw_mode(struct ieee80211_hw *hw,
enum nl80211_channel_type ch_type);
extern void rtl8821ae_phy_sw_chnl_callback(struct ieee80211_hw *hw);
extern u8 rtl8821ae_phy_sw_chnl(struct ieee80211_hw *hw);
extern void rtl8821ae_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery);
extern void rtl8812ae_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery);
void rtl8821ae_phy_ap_calibrate(struct ieee80211_hw *hw, char delta);
void rtl8821ae_phy_lc_calibrate(struct ieee80211_hw *hw);
void rtl8821ae_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain);
bool rtl8812ae_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
enum radio_path rfpath);
bool rtl8821ae_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
enum radio_path rfpath);
bool rtl8821ae_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype);
extern bool rtl8821ae_phy_set_rf_power_state(struct ieee80211_hw *hw,
enum rf_pwrstate rfpwr_state);
u8 _rtl8812ae_get_right_chnl_place_for_iqk(u8 chnl);
void rtl8821ae_phy_set_txpower_level_by_path(struct ieee80211_hw *hw, u8 channel, u8 path);
void rtl8812ae_do_iqk(struct ieee80211_hw *hw,u8 delta_thermal_index,
u8 thermal_value, u8 threshold);
void rtl8821ae_do_iqk(struct ieee80211_hw *hw,u8 delta_thermal_index,
u8 thermal_value, u8 threshold);
void rtl8821ae_reset_iqk_result(struct ieee80211_hw *hw);
#endif

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/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "pwrseqcmd.h"
#include "pwrseq.h"
/*
drivers should parse below arrays and do the corresponding actions
*/
//3 Power on Array
struct wlan_pwr_cfg rtl8812_power_on_flow[RTL8812_TRANS_CARDEMU_TO_ACT_STEPS+RTL8812_TRANS_END_STEPS]=
{
RTL8812_TRANS_CARDEMU_TO_ACT
RTL8812_TRANS_END
};
//3Radio off GPIO Array
struct wlan_pwr_cfg rtl8812_radio_off_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS+RTL8812_TRANS_END_STEPS]=
{
RTL8812_TRANS_ACT_TO_CARDEMU
RTL8812_TRANS_END
};
//3Card Disable Array
struct wlan_pwr_cfg rtl8812_card_disable_flow[ RTL8812_TRANS_ACT_TO_CARDEMU_STEPS
+ RTL8812_TRANS_CARDEMU_TO_PDN_STEPS
+ RTL8812_TRANS_END_STEPS ] =
{
RTL8812_TRANS_ACT_TO_CARDEMU
RTL8812_TRANS_CARDEMU_TO_CARDDIS
RTL8812_TRANS_END
};
//3 Card Enable Array
struct wlan_pwr_cfg rtl8812_card_enable_flow[ RTL8812_TRANS_ACT_TO_CARDEMU_STEPS
+ RTL8812_TRANS_CARDEMU_TO_PDN_STEPS
+ RTL8812_TRANS_END_STEPS ] =
{
RTL8812_TRANS_CARDDIS_TO_CARDEMU
RTL8812_TRANS_CARDEMU_TO_ACT
RTL8812_TRANS_END
};
//3Suspend Array
struct wlan_pwr_cfg rtl8812_suspend_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS+RTL8812_TRANS_CARDEMU_TO_SUS_STEPS+RTL8812_TRANS_END_STEPS]=
{
RTL8812_TRANS_ACT_TO_CARDEMU
RTL8812_TRANS_CARDEMU_TO_SUS
RTL8812_TRANS_END
};
//3 Resume Array
struct wlan_pwr_cfg rtl8812_resume_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS+RTL8812_TRANS_CARDEMU_TO_SUS_STEPS+RTL8812_TRANS_END_STEPS]=
{
RTL8812_TRANS_SUS_TO_CARDEMU
RTL8812_TRANS_CARDEMU_TO_ACT
RTL8812_TRANS_END
};
//3HWPDN Array
struct wlan_pwr_cfg rtl8812_hwpdn_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS+RTL8812_TRANS_CARDEMU_TO_PDN_STEPS+RTL8812_TRANS_END_STEPS]=
{
RTL8812_TRANS_ACT_TO_CARDEMU
RTL8812_TRANS_CARDEMU_TO_PDN
RTL8812_TRANS_END
};
//3 Enter LPS
struct wlan_pwr_cfg rtl8812_enter_lps_flow[RTL8812_TRANS_ACT_TO_LPS_STEPS+RTL8812_TRANS_END_STEPS]=
{
//FW behavior
RTL8812_TRANS_ACT_TO_LPS
RTL8812_TRANS_END
};
//3 Leave LPS
struct wlan_pwr_cfg rtl8812_leave_lps_flow[RTL8812_TRANS_LPS_TO_ACT_STEPS+RTL8812_TRANS_END_STEPS]=
{
//FW behavior
RTL8812_TRANS_LPS_TO_ACT
RTL8812_TRANS_END
};
/*
drivers should parse below arrays and do the corresponding actions
*/
/*3 Power on Array*/
struct wlan_pwr_cfg rtl8821A_power_on_flow[RTL8821A_TRANS_CARDEMU_TO_ACT_STEPS
+ RTL8821A_TRANS_END_STEPS] =
{
RTL8821A_TRANS_CARDEMU_TO_ACT
RTL8821A_TRANS_END
};
/*3Radio off GPIO Array */
struct wlan_pwr_cfg rtl8821A_radio_off_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS
+ RTL8821A_TRANS_END_STEPS] =
{
RTL8821A_TRANS_ACT_TO_CARDEMU
RTL8821A_TRANS_END
};
/*3Card Disable Array*/
struct wlan_pwr_cfg rtl8821A_card_disable_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS
+ RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS
+ RTL8821A_TRANS_END_STEPS] =
{
RTL8821A_TRANS_ACT_TO_CARDEMU
RTL8821A_TRANS_CARDEMU_TO_CARDDIS
RTL8821A_TRANS_END
};
/*3 Card Enable Array*/
struct wlan_pwr_cfg rtl8821A_card_enable_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS
+ RTL8821A_TRANS_CARDEMU_TO_ACT_STEPS /*RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS*/
+ RTL8821A_TRANS_END_STEPS] =
{
RTL8821A_TRANS_CARDDIS_TO_CARDEMU
RTL8821A_TRANS_CARDEMU_TO_ACT
RTL8821A_TRANS_END
};
/*3Suspend Array*/
struct wlan_pwr_cfg rtl8821A_suspend_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS
+ RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS
+ RTL8821A_TRANS_END_STEPS] =
{
RTL8821A_TRANS_ACT_TO_CARDEMU
RTL8821A_TRANS_CARDEMU_TO_SUS
RTL8821A_TRANS_END
};
/*3 Resume Array*/
struct wlan_pwr_cfg rtl8821A_resume_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS
+ RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS
+ RTL8821A_TRANS_END_STEPS] =
{
RTL8821A_TRANS_SUS_TO_CARDEMU
RTL8821A_TRANS_CARDEMU_TO_ACT
RTL8821A_TRANS_END
};
/*3HWPDN Array*/
struct wlan_pwr_cfg rtl8821A_hwpdn_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS
+ RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS
+ RTL8821A_TRANS_END_STEPS] =
{
RTL8821A_TRANS_ACT_TO_CARDEMU
RTL8821A_TRANS_CARDEMU_TO_PDN
RTL8821A_TRANS_END
};
/*3 Enter LPS */
struct wlan_pwr_cfg rtl8821A_enter_lps_flow[RTL8821A_TRANS_ACT_TO_LPS_STEPS
+ RTL8821A_TRANS_END_STEPS] =
{
/*FW behavior*/
RTL8821A_TRANS_ACT_TO_LPS
RTL8821A_TRANS_END
};
/*3 Leave LPS */
struct wlan_pwr_cfg rtl8821A_leave_lps_flow[RTL8821A_TRANS_LPS_TO_ACT_STEPS
+ RTL8821A_TRANS_END_STEPS] =
{
/*FW behavior*/
RTL8821A_TRANS_LPS_TO_ACT
RTL8821A_TRANS_END
};

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/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __RTL8821AE_PWRSEQ_H__
#define __RTL8821AE_PWRSEQ_H__
#include "pwrseqcmd.h"
#include "../btcoexist/halbt_precomp.h"
#define RTL8812_TRANS_CARDEMU_TO_ACT_STEPS 15
#define RTL8812_TRANS_ACT_TO_CARDEMU_STEPS 15
#define RTL8812_TRANS_CARDEMU_TO_SUS_STEPS 15
#define RTL8812_TRANS_SUS_TO_CARDEMU_STEPS 15
#define RTL8812_TRANS_CARDEMU_TO_PDN_STEPS 25
#define RTL8812_TRANS_PDN_TO_CARDEMU_STEPS 15
#define RTL8812_TRANS_ACT_TO_LPS_STEPS 15
#define RTL8812_TRANS_LPS_TO_ACT_STEPS 15
#define RTL8812_TRANS_END_STEPS 1
#define RTL8812_TRANS_CARDEMU_TO_ACT \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, 0},/* disable SW LPS 0x04[10]=0*/ \
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]=0*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3, 0},/* disable WL suspend*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT0, 0},/**/
#define RTL8812_TRANS_ACT_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0c00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xc00[7:0] = 4 turn off 3-wire */ \
{0x0e00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xe00[7:0] = 4 turn off 3-wire */ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /* 0x2[0] = 0 RESET BB, CLOSE RF */ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0}, /* Whole BB is reset*/ \
/*{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},//0x1F[7:0] = 0 turn off RF*/ \
/*{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},//0x4C[23] = 0x4E[7] = 0, switch DPDT_SEL_P output from register 0x65[2] */ \
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x2A}, /* 0x07[7:0] = 0x28 sps pwm mode 0x2a for BT coex*/ \
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x02, 0},/*0x8[1] = 0 ANA clk =500k */ \
/*{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0|BIT1, 0}, // 0x02[1:0] = 0 reset BB */ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/
#define RTL8812_TRANS_CARDEMU_TO_SUS \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xF0, 0xcc},\
{0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xF0, 0xEC},\
{0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x07},/* gpio11 input mode, gpio10~8 output mode */ \
{0x0045, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/* gpio 0~7 output same value as input ?? */ \
{0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xff},/* gpio0~7 output mode */ \
{0x0047, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/* 0x47[7:0] = 00 gpio mode */ \
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/* suspend option all off */ \
{0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x80, BIT7},/*0x14[7] = 1 turn on ZCD */ \
{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x01, BIT0},/* 0x15[0] =1 trun on ZCD */ \
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x10, BIT4},/*0x23[4] = 1 hpon LDO sleep mode */ \
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x02, 0},/*0x8[1] = 0 ANA clk =500k */ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3, BIT3}, /*0x04[11] = 2b'11 enable WL suspend for PCIe*/
#define RTL8812_TRANS_SUS_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3, 0}, /*0x04[11] = 2b'01enable WL suspend*/ \
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x10, 0},/*0x23[4] = 0 hpon LDO sleep mode leave */ \
{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x01, 0},/* 0x15[0] =0 trun off ZCD */ \
{0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x80, 0},/*0x14[7] = 0 turn off ZCD */ \
{0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/* gpio0~7 input mode */ \
{0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/* gpio11 input mode, gpio10~8 input mode */
#define RTL8812_TRANS_CARDEMU_TO_CARDDIS \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
/**{0x0194, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, //0x194[0]=0 , disable 32K clock*/ \
/**{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x94}, //0x93=0x94 , 90[30] =0 enable 500k ANA clock .switch clock from 12M to 500K , 90 [26] =0 disable EEprom loader clock*/ \
{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, 0}, /*0x03[2] = 0, reset 8051*/ \
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x05}, /*0x80=05h if reload fw, fill the default value of host_CPU handshake field*/ \
{0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xF0, 0xcc},\
{0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xF0, 0xEC},\
{0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x07},/* gpio11 input mode, gpio10~8 output mode */ \
{0x0045, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/* gpio 0~7 output same value as input ?? */ \
{0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xff},/* gpio0~7 output mode */ \
{0x0047, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/* 0x47[7:0] = 00 gpio mode */ \
{0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x80, BIT7},/*0x14[7] = 1 turn on ZCD */ \
{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x01, BIT0},/* 0x15[0] =1 trun on ZCD */ \
{0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x01, 0},/*0x12[0] = 0 force PFM mode */ \
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x10, BIT4},/*0x23[4] = 1 hpon LDO sleep mode */ \
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x02, 0},/*0x8[1] = 0 ANA clk =500k */ \
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07=0x20 , SOP option to disable BG/MB*/ \
{0x001f, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0}, /*0x01f[1]=0 , disable RFC_0 control REG_RF_CTRL_8812 */ \
{0x0076, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0}, /*0x076[1]=0 , disable RFC_1 control REG_OPT_CTRL_8812 +2 */ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3, BIT3}, /*0x04[11] = 2b'01 enable WL suspend*/
#define RTL8812_TRANS_CARDDIS_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/*0x12[0] = 1 force PWM mode */ \
{0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x80, 0},/*0x14[7] = 0 turn off ZCD */ \
{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x01, 0},/* 0x15[0] =0 trun off ZCD */ \
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x10, 0},/*0x23[4] = 0 hpon LDO leave sleep mode */ \
{0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/* gpio0~7 input mode */ \
{0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/* gpio11 input mode, gpio10~8 input mode */ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, 0}, /*0x04[10] = 0, enable SW LPS PCIE only*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3, 0}, /*0x04[11] = 2b'01enable WL suspend*/ \
{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, BIT2}, /*0x03[2] = 1, enable 8051*/ \
{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/
#define RTL8812_TRANS_CARDEMU_TO_PDN \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
#define RTL8812_TRANS_PDN_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
#define RTL8812_TRANS_ACT_TO_LPS \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/ \
{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x0c00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xc00[7:0] = 4 turn off 3-wire */ \
{0x0e00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x04}, /* 0xe00[7:0] = 4 turn off 3-wire */ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated,and RF closed*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0}, /* Whole BB is reset*/ \
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/ \
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \
{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/
#define RTL8812_TRANS_LPS_TO_ACT \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/ \
{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/ \
{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/ \
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*. 0x08[4] = 0 switch TSF to 40M*/ \
{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0 TSF in 40M*/ \
{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6|BIT7, 0}, /*. 0x29[7:6] = 2b'00 enable BB clock*/ \
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/ \
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/ \
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/
#define RTL8812_TRANS_END \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,0,PWR_CMD_END, 0, 0}, //
extern struct wlan_pwr_cfg rtl8812_power_on_flow[RTL8812_TRANS_CARDEMU_TO_ACT_STEPS+RTL8812_TRANS_END_STEPS];
extern struct wlan_pwr_cfg rtl8812_radio_off_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS+RTL8812_TRANS_END_STEPS];
extern struct wlan_pwr_cfg rtl8812_card_disable_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS+RTL8812_TRANS_CARDEMU_TO_PDN_STEPS+RTL8812_TRANS_END_STEPS];
extern struct wlan_pwr_cfg rtl8812_card_enable_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS+RTL8812_TRANS_CARDEMU_TO_PDN_STEPS+RTL8812_TRANS_END_STEPS];
extern struct wlan_pwr_cfg rtl8812_suspend_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS+RTL8812_TRANS_CARDEMU_TO_SUS_STEPS+RTL8812_TRANS_END_STEPS];
extern struct wlan_pwr_cfg rtl8812_resume_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS+RTL8812_TRANS_CARDEMU_TO_SUS_STEPS+RTL8812_TRANS_END_STEPS];
extern struct wlan_pwr_cfg rtl8812_hwpdn_flow[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS+RTL8812_TRANS_CARDEMU_TO_PDN_STEPS+RTL8812_TRANS_END_STEPS];
extern struct wlan_pwr_cfg rtl8812_enter_lps_flow[RTL8812_TRANS_ACT_TO_LPS_STEPS+RTL8812_TRANS_END_STEPS];
extern struct wlan_pwr_cfg rtl8812_leave_lps_flow[RTL8812_TRANS_LPS_TO_ACT_STEPS+RTL8812_TRANS_END_STEPS];
/*
Check document WM-20130516-JackieLau-RTL8821A_Power_Architecture-R10.vsd
There are 6 HW Power States:
0: POFF--Power Off
1: PDN--Power Down
2: CARDEMU--Card Emulation
3: ACT--Active Mode
4: LPS--Low Power State
5: SUS--Suspend
The transision from different states are defined below
TRANS_CARDEMU_TO_ACT
TRANS_ACT_TO_CARDEMU
TRANS_CARDEMU_TO_SUS
TRANS_SUS_TO_CARDEMU
TRANS_CARDEMU_TO_PDN
TRANS_ACT_TO_LPS
TRANS_LPS_TO_ACT
TRANS_END
*/
#define RTL8821A_TRANS_CARDEMU_TO_ACT_STEPS 25
#define RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS 15
#define RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS 15
#define RTL8821A_TRANS_SUS_TO_CARDEMU_STEPS 15
#define RTL8821A_TRANS_CARDDIS_TO_CARDEMU_STEPS 15
#define RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS 15
#define RTL8821A_TRANS_PDN_TO_CARDEMU_STEPS 15
#define RTL8821A_TRANS_ACT_TO_LPS_STEPS 15
#define RTL8821A_TRANS_LPS_TO_ACT_STEPS 15
#define RTL8821A_TRANS_END_STEPS 1
#define RTL8821A_TRANS_CARDEMU_TO_ACT \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/ \
{0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x67[0] = 0 to disable BT_GPS_SEL pins*/ \
{0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS},/*Delay 1ms*/ \
{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, 0}, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT4|BIT3|BIT2), 0},/* disable SW LPS 0x04[10]=0 and WLSUS_EN 0x04[12:11]=0*/ \
{0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0 , BIT0},/* Disable USB suspend */ \
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \
{0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0 , 0},/* Enable USB suspend */ \
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset 0x04[16]=1*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]=0*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT4|BIT3), 0},/* disable WL suspend*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT0, 0},/**/ \
{0x004F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/*0x4C[24] = 0x4F[0] = 1, switch DPDT_SEL_P output from WL BB */\
{0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT5|BIT4), (BIT5|BIT4)},/*0x66[13] = 0x67[5] = 1, switch for PAPE_G/PAPE_A from WL BB ; 0x66[12] = 0x67[4] = 1, switch LNAON from WL BB */\
{0x0025, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6, 0},/*anapar_mac<118> , 0x25[6]=0 by wlan single function*/\
{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1},/*Enable falling edge triggering interrupt*/\
{0x0063, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1},/*Enable GPIO9 interrupt mode*/\
{0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Enable GPIO9 input mode*/\
{0x0058, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/*Enable HSISR GPIO[C:0] interrupt*/\
{0x005A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1},/*Enable HSISR GPIO9 interrupt*/\
{0x007A, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x3A},/*0x7A = 0x3A start BT*/\
{0x002E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF , 0x82 },/* 0x2C[23:12]=0x820 ; XTAL trim */ \
{0x0010, PWR_CUT_A_MSK , PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6 , BIT6 },/* 0x10[6]=1 ; MP新增對於0x2C的控制權，須把0x10[6]設為1才能讓WLAN控制 */ \
#define RTL8821A_TRANS_ACT_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/ \
{0x004F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*0x4C[24] = 0x4F[0] = 0, switch DPDT_SEL_P output from register 0x65[2] */\
{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Enable rising edge triggering interrupt*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \
{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5}, /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/ \
{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/ \
#define RTL8821A_TRANS_CARDEMU_TO_SUS \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
#define RTL8821A_TRANS_SUS_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
#define RTL8821A_TRANS_CARDEMU_TO_CARDDIS \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07=0x20 , SOP option to disable BG/MB*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] = 1, enable SW LPS*/ \
{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 1}, /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/ \
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
#define RTL8821A_TRANS_CARDDIS_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \
{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/
#define RTL8821A_TRANS_CARDEMU_TO_PDN \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK|PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/ \
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
#define RTL8821A_TRANS_PDN_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
#define RTL8821A_TRANS_ACT_TO_LPS \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/ \
{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/ \
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/ \
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \
{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/ \
{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/ \
#define RTL8821A_TRANS_LPS_TO_ACT \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\
{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*. 0x08[4] = 0 switch TSF to 40M*/\
{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0 TSF in 40M*/\
{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6|BIT7, 0}, /*. 0x29[7:6] = 2b'00 enable BB clock*/\
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/\
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/
#define RTL8821A_TRANS_END \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,0,PWR_CMD_END, 0, 0}, //
extern struct wlan_pwr_cfg rtl8821A_power_on_flow[RTL8821A_TRANS_CARDEMU_TO_ACT_STEPS
+ RTL8821A_TRANS_END_STEPS];
extern struct wlan_pwr_cfg rtl8821A_radio_off_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS
+ RTL8821A_TRANS_END_STEPS];
extern struct wlan_pwr_cfg rtl8821A_card_disable_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS
+ RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS
+ RTL8821A_TRANS_END_STEPS];
extern struct wlan_pwr_cfg rtl8821A_card_enable_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS
+ RTL8821A_TRANS_CARDEMU_TO_ACT_STEPS/*RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS*/
+ RTL8821A_TRANS_END_STEPS];
extern struct wlan_pwr_cfg rtl8821A_suspend_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS
+ RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS
+ RTL8821A_TRANS_END_STEPS];
extern struct wlan_pwr_cfg rtl8821A_resume_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS
+ RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS
+ RTL8821A_TRANS_END_STEPS];
extern struct wlan_pwr_cfg rtl8821A_hwpdn_flow[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS
+ RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS
+ RTL8821A_TRANS_END_STEPS];
extern struct wlan_pwr_cfg rtl8821A_enter_lps_flow[RTL8821A_TRANS_ACT_TO_LPS_STEPS
+ RTL8821A_TRANS_END_STEPS];
extern struct wlan_pwr_cfg rtl8821A_leave_lps_flow[RTL8821A_TRANS_LPS_TO_ACT_STEPS
+ RTL8821A_TRANS_END_STEPS];
/*RTL8812 Power Configuration CMDs for PCIe interface*/
#define RTL8812_NIC_PWR_ON_FLOW rtl8812_power_on_flow
#define RTL8812_NIC_RF_OFF_FLOW rtl8812_radio_off_flow
#define RTL8812_NIC_DISABLE_FLOW rtl8812_card_disable_flow
#define RTL8812_NIC_ENABLE_FLOW rtl8812_card_enable_flow
#define RTL8812_NIC_SUSPEND_FLOW rtl8812_suspend_flow
#define RTL8812_NIC_RESUME_FLOW rtl8812_resume_flow
#define RTL8812_NIC_PDN_FLOW rtl8812_hwpdn_flow
#define RTL8812_NIC_LPS_ENTER_FLOW rtl8812_enter_lps_flow
#define RTL8812_NIC_LPS_LEAVE_FLOW rtl8812_leave_lps_flow
/* RTL8821 Power Configuration CMDs for PCIe interface */
#define RTL8821A_NIC_PWR_ON_FLOW rtl8821A_power_on_flow
#define RTL8821A_NIC_RF_OFF_FLOW rtl8821A_radio_off_flow
#define RTL8821A_NIC_DISABLE_FLOW rtl8821A_card_disable_flow
#define RTL8821A_NIC_ENABLE_FLOW rtl8821A_card_enable_flow
#define RTL8821A_NIC_SUSPEND_FLOW rtl8821A_suspend_flow
#define RTL8821A_NIC_RESUME_FLOW rtl8821A_resume_flow
#define RTL8821A_NIC_PDN_FLOW rtl8821A_hwpdn_flow
#define RTL8821A_NIC_LPS_ENTER_FLOW rtl8821A_enter_lps_flow
#define RTL8821A_NIC_LPS_LEAVE_FLOW rtl8821A_leave_lps_flow
#endif

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/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "pwrseq.h"
/*
* Description:
* This routine deal with the Power Configuration CMDs
* parsing for RTL8723/RTL8188E Series IC.
* Assumption:
* We should follow specific format which was released from HW SD.
*
* 2011.07.07, added by Roger.
*/
bool rtl_hal_pwrseqcmdparsing (struct rtl_priv* rtlpriv, u8 cut_version,
u8 fab_version, u8 interface_type,
struct wlan_pwr_cfg pwrcfgcmd[])
{
struct wlan_pwr_cfg pwr_cfg_cmd = {0};
bool polling_bit = false;
u32 ary_idx=0;
u8 value = 0;
u32 offset = 0;
u32 polling_count = 0;
u32 max_polling_cnt = 5000;
do {
pwr_cfg_cmd = pwrcfgcmd[ary_idx];
RT_TRACE(COMP_INIT, DBG_TRACE,
("rtl_hal_pwrseqcmdparsing(): offset(%#x),cut_msk(%#x), fab_msk(%#x),"
"interface_msk(%#x), base(%#x), cmd(%#x), msk(%#x), value(%#x)\n",
GET_PWR_CFG_OFFSET(pwr_cfg_cmd), GET_PWR_CFG_CUT_MASK(pwr_cfg_cmd),
GET_PWR_CFG_FAB_MASK(pwr_cfg_cmd), GET_PWR_CFG_INTF_MASK(pwr_cfg_cmd),
GET_PWR_CFG_BASE(pwr_cfg_cmd), GET_PWR_CFG_CMD(pwr_cfg_cmd),
GET_PWR_CFG_MASK(pwr_cfg_cmd), GET_PWR_CFG_VALUE(pwr_cfg_cmd)));
if ((GET_PWR_CFG_FAB_MASK(pwr_cfg_cmd)&fab_version) &&
(GET_PWR_CFG_CUT_MASK(pwr_cfg_cmd)&cut_version) &&
(GET_PWR_CFG_INTF_MASK(pwr_cfg_cmd)&interface_type)) {
switch (GET_PWR_CFG_CMD(pwr_cfg_cmd)) {
case PWR_CMD_READ:
RT_TRACE(COMP_INIT, DBG_TRACE,
("rtl_hal_pwrseqcmdparsing(): PWR_CMD_READ\n"));
break;
case PWR_CMD_WRITE: {
RT_TRACE(COMP_INIT, DBG_TRACE,
("rtl_hal_pwrseqcmdparsing(): PWR_CMD_WRITE\n"));
offset = GET_PWR_CFG_OFFSET(pwr_cfg_cmd);
/*Read the value from system register*/
value = rtl_read_byte(rtlpriv, offset);
value = value & (~(GET_PWR_CFG_MASK(pwr_cfg_cmd)));
value = value | (GET_PWR_CFG_VALUE(pwr_cfg_cmd)
& GET_PWR_CFG_MASK(pwr_cfg_cmd));
/*Write the value back to sytem register*/
rtl_write_byte(rtlpriv, offset, value);
}
break;
case PWR_CMD_POLLING:
RT_TRACE(COMP_INIT, DBG_TRACE,
("rtl_hal_pwrseqcmdparsing(): PWR_CMD_POLLING\n"));
polling_bit = false;
offset = GET_PWR_CFG_OFFSET(pwr_cfg_cmd);
do {
value = rtl_read_byte(rtlpriv, offset);
value = value & GET_PWR_CFG_MASK(pwr_cfg_cmd);
if (value == (GET_PWR_CFG_VALUE(pwr_cfg_cmd)
& GET_PWR_CFG_MASK(pwr_cfg_cmd)))
polling_bit=true;
else
udelay(10);
if (polling_count++ > max_polling_cnt) {
return false;
}
} while (!polling_bit);
break;
case PWR_CMD_DELAY:
RT_TRACE(COMP_INIT, DBG_TRACE,
("rtl_hal_pwrseqcmdparsing(): PWR_CMD_DELAY\n"));
if (GET_PWR_CFG_VALUE(pwr_cfg_cmd) == PWRSEQ_DELAY_US)
udelay(GET_PWR_CFG_OFFSET(pwr_cfg_cmd));
else
mdelay(GET_PWR_CFG_OFFSET(pwr_cfg_cmd));
break;
case PWR_CMD_END:
RT_TRACE(COMP_INIT, DBG_TRACE,
("rtl_hal_pwrseqcmdparsing(): PWR_CMD_END\n"));
return true;
break;
default:
RT_ASSERT(false,
("rtl_hal_pwrseqcmdparsing(): Unknown CMD!!\n"));
break;
}
}
ary_idx++;
} while (1);
return true;
}

71
drivers/staging/rtl8821ae/rtl8821ae/pwrseqcmd.h Normal file
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#ifndef __RTL8821AE_PWRSEQCMD_H__
#define __RTL8821AE_PWRSEQCMD_H__
#include "../wifi.h"
/*---------------------------------------------*/
/*The value of cmd: 4 bits */
/*---------------------------------------------*/
#define PWR_CMD_READ 0x00
#define PWR_CMD_WRITE 0x01
#define PWR_CMD_POLLING 0x02
#define PWR_CMD_DELAY 0x03
#define PWR_CMD_END 0x04
/* define the base address of each block */
#define PWR_BASEADDR_MAC 0x00
#define PWR_BASEADDR_USB 0x01
#define PWR_BASEADDR_PCIE 0x02
#define PWR_BASEADDR_SDIO 0x03
#define PWR_INTF_SDIO_MSK BIT(0)
#define PWR_INTF_USB_MSK BIT(1)
#define PWR_INTF_PCI_MSK BIT(2)
#define PWR_INTF_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3))
#define PWR_FAB_TSMC_MSK BIT(0)
#define PWR_FAB_UMC_MSK BIT(1)
#define PWR_FAB_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3))
#define PWR_CUT_TESTCHIP_MSK BIT(0)
#define PWR_CUT_A_MSK BIT(1)
#define PWR_CUT_B_MSK BIT(2)
#define PWR_CUT_C_MSK BIT(3)
#define PWR_CUT_D_MSK BIT(4)
#define PWR_CUT_E_MSK BIT(5)
#define PWR_CUT_F_MSK BIT(6)
#define PWR_CUT_G_MSK BIT(7)
#define PWR_CUT_ALL_MSK 0xFF
enum pwrseq_delay_unit {
PWRSEQ_DELAY_US,
PWRSEQ_DELAY_MS,
};
struct wlan_pwr_cfg {
u16 offset;
u8 cut_msk;
u8 fab_msk:4;
u8 interface_msk:4;
u8 base:4;
u8 cmd:4;
u8 msk;
u8 value;
};
#define GET_PWR_CFG_OFFSET(__PWR_CMD) __PWR_CMD.offset
#define GET_PWR_CFG_CUT_MASK(__PWR_CMD) __PWR_CMD.cut_msk
#define GET_PWR_CFG_FAB_MASK(__PWR_CMD) __PWR_CMD.fab_msk
#define GET_PWR_CFG_INTF_MASK(__PWR_CMD) __PWR_CMD.interface_msk
#define GET_PWR_CFG_BASE(__PWR_CMD) __PWR_CMD.base
#define GET_PWR_CFG_CMD(__PWR_CMD) __PWR_CMD.cmd
#define GET_PWR_CFG_MASK(__PWR_CMD) __PWR_CMD.msk
#define GET_PWR_CFG_VALUE(__PWR_CMD) __PWR_CMD.value
bool rtl_hal_pwrseqcmdparsing(struct rtl_priv * rtlpriv, u8 cut_version,
u8 fab_version, u8 interface_type,
struct wlan_pwr_cfg pwrcfgcmd[]);
#endif

2427
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464
drivers/staging/rtl8821ae/rtl8821ae/rf.c Normal file
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/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "../wifi.h"
#include "reg.h"
#include "def.h"
#include "phy.h"
#include "rf.h"
#include "dm.h"
static bool _rtl8821ae_phy_rf6052_config_parafile(struct ieee80211_hw *hw);
void rtl8821ae_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw, u8 bandwidth)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
switch (bandwidth) {
case HT_CHANNEL_WIDTH_20:
rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, BIT(11)|BIT(10), 3);
rtl_set_rfreg(hw, RF90_PATH_B, RF_CHNLBW, BIT(11)|BIT(10), 3);
break;
case HT_CHANNEL_WIDTH_20_40:
rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, BIT(11)|BIT(10), 1);
rtl_set_rfreg(hw, RF90_PATH_B, RF_CHNLBW, BIT(11)|BIT(10), 1);
break;
case HT_CHANNEL_WIDTH_80:
rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, BIT(11)|BIT(10), 0);
rtl_set_rfreg(hw, RF90_PATH_B, RF_CHNLBW, BIT(11)|BIT(10), 0);
break;
default:
RT_TRACE(COMP_ERR, DBG_EMERG,
("unknown bandwidth: %#X\n", bandwidth));
break;
}
}
void rtl8821ae_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
u8 *ppowerlevel)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_phy *rtlphy = &(rtlpriv->phy);
struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
u32 tx_agc[2] = {0, 0}, tmpval;
bool turbo_scanoff = false;
u8 idx1, idx2;
u8 *ptr;
u8 direction;
u32 pwrtrac_value;
if (rtlefuse->eeprom_regulatory != 0)
turbo_scanoff = true;
if (mac->act_scanning == true) {
tx_agc[RF90_PATH_A] = 0x3f3f3f3f;
tx_agc[RF90_PATH_B] = 0x3f3f3f3f;
if (turbo_scanoff) {
for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
tx_agc[idx1] = ppowerlevel[idx1] |
(ppowerlevel[idx1] << 8) |
(ppowerlevel[idx1] << 16) |
(ppowerlevel[idx1] << 24);
}
}
} else {
for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
tx_agc[idx1] = ppowerlevel[idx1] |
(ppowerlevel[idx1] << 8) |
(ppowerlevel[idx1] << 16) |
(ppowerlevel[idx1] << 24);
}
if (rtlefuse->eeprom_regulatory == 0) {
tmpval =
(rtlphy->mcs_txpwrlevel_origoffset[0][6]) +
(rtlphy->mcs_txpwrlevel_origoffset[0][7] <<
8);
tx_agc[RF90_PATH_A] += tmpval;
tmpval = (rtlphy->mcs_txpwrlevel_origoffset[0][14]) +
(rtlphy->mcs_txpwrlevel_origoffset[0][15] <<
24);
tx_agc[RF90_PATH_B] += tmpval;
}
}
for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
ptr = (u8 *) (&(tx_agc[idx1]));
for (idx2 = 0; idx2 < 4; idx2++) {
if (*ptr > RF6052_MAX_TX_PWR)
*ptr = RF6052_MAX_TX_PWR;
ptr++;
}
}
rtl8821ae_dm_txpower_track_adjust(hw,1,&direction,&pwrtrac_value);
if (direction ==1){
tx_agc[0] += pwrtrac_value;
tx_agc[1] += pwrtrac_value;
} else if (direction == 2){
tx_agc[0] -= pwrtrac_value;
tx_agc[1] -= pwrtrac_value;
}
tmpval = tx_agc[RF90_PATH_A] ;
rtl_set_bbreg(hw, RTXAGC_A_CCK11_CCK1, MASKDWORD, tmpval);
RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
("CCK PWR 1~11M (rf-A) = 0x%x (reg 0x%x)\n", tmpval,
RTXAGC_A_CCK11_CCK1));
tmpval = tx_agc[RF90_PATH_B] ;
rtl_set_bbreg(hw, RTXAGC_B_CCK11_CCK1, MASKDWORD, tmpval);
RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
("CCK PWR 11M (rf-B) = 0x%x (reg 0x%x)\n", tmpval,
RTXAGC_B_CCK11_CCK1));
}
static void rtl8821ae_phy_get_power_base(struct ieee80211_hw *hw,
u8 *ppowerlevel_ofdm, u8 *ppowerlevel_bw20, u8 *ppowerlevel_bw40, u8 channel,
u32 *ofdmbase, u32 *mcsbase)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_phy *rtlphy = &(rtlpriv->phy);
u32 powerBase0, powerBase1;
u8 i, powerlevel[2];
for (i = 0; i < 2; i++) {
powerBase0 = ppowerlevel_ofdm[i];
powerBase0 = (powerBase0 << 24) | (powerBase0 << 16) |
(powerBase0 << 8) | powerBase0;
*(ofdmbase + i) = powerBase0;
RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
(" [OFDM power base index rf(%c) = 0x%x]\n",
((i == 0) ? 'A' : 'B'), *(ofdmbase + i)));
}
for (i = 0; i < 2; i++) {
if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20) {
powerlevel[i] = ppowerlevel_bw20[i];
}else{
powerlevel[i] = ppowerlevel_bw40[i];
}
powerBase1 = powerlevel[i];
powerBase1 = (powerBase1 << 24) |
(powerBase1 << 16) | (powerBase1 << 8) | powerBase1;
*(mcsbase + i) = powerBase1;
RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
(" [MCS power base index rf(%c) = 0x%x]\n",
((i == 0) ? 'A' : 'B'), *(mcsbase + i)));
}
}
static void _rtl8821ae_get_txpower_writeval_by_regulatory(struct ieee80211_hw *hw,
u8 channel, u8 index,
u32 *powerBase0,
u32 *powerBase1,
u32 *p_outwriteval)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_phy *rtlphy = &(rtlpriv->phy);
struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
u8 i, chnlgroup = 0, pwr_diff_limit[4],pwr_diff = 0,customer_pwr_diff;
u32 writeVal, customer_limit, rf;
for (rf = 0; rf < 2; rf++) {
switch (rtlefuse->eeprom_regulatory) {
case 0:
chnlgroup = 0;
writeVal =
rtlphy->mcs_txpwrlevel_origoffset[chnlgroup][index +
(rf ? 8 : 0)]
+ ((index < 2) ? powerBase0[rf] : powerBase1[rf]);
RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
("RTK better performance, "
"writeVal(%c) = 0x%x\n",
((rf == 0) ? 'A' : 'B'), writeVal));
break;
case 1:
if (rtlphy->pwrgroup_cnt == 1)
chnlgroup = 0;
else {
if(channel<3)
chnlgroup = 0;
else if (channel <6)
chnlgroup = 1;
else if (channel <9)
chnlgroup = 2;
else if (channel <12)
chnlgroup = 3;
else if (channel < 14)
chnlgroup = 4;
else if (channel == 14)
chnlgroup = 5;
}
writeVal =
rtlphy->mcs_txpwrlevel_origoffset[chnlgroup]
[index + (rf ? 8 : 0)] + ((index < 2) ?
powerBase0[rf] :
powerBase1[rf]);
RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
("Realtek regulatory, 20MHz, "
"writeVal(%c) = 0x%x\n",
((rf == 0) ? 'A' : 'B'), writeVal));
break;
case 2:
writeVal =
((index < 2) ? powerBase0[rf] : powerBase1[rf]);
RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
("Better regulatory, "
"writeVal(%c) = 0x%x\n",
((rf == 0) ? 'A' : 'B'), writeVal));
break;
case 3:
chnlgroup = 0;
if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) {
RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
("customer's limit, 40MHz "
"rf(%c) = 0x%x\n",
((rf == 0) ? 'A' : 'B'),
rtlefuse->pwrgroup_ht40[rf][channel -
1]));
} else {
RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
("customer's limit, 20MHz "
"rf(%c) = 0x%x\n",
((rf == 0) ? 'A' : 'B'),
rtlefuse->pwrgroup_ht20[rf][channel -
1]));
}
if (index < 2)
pwr_diff = rtlefuse->txpwr_legacyhtdiff[rf][channel-1];
else if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20)
pwr_diff = rtlefuse->txpwr_ht20diff[rf][channel-1];
if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40)
customer_pwr_diff = rtlefuse->pwrgroup_ht40[rf][channel-1];
else
customer_pwr_diff = rtlefuse->pwrgroup_ht20[rf][channel-1];
if (pwr_diff > customer_pwr_diff)
pwr_diff = 0;
else
pwr_diff = customer_pwr_diff - pwr_diff;
for (i = 0; i < 4; i++) {
pwr_diff_limit[i] =
(u8) ((rtlphy->mcs_txpwrlevel_origoffset
[chnlgroup][index + (rf ? 8 : 0)] & (0x7f <<
(i * 8))) >> (i * 8));
if(pwr_diff_limit[i] > pwr_diff)
pwr_diff_limit[i] = pwr_diff;
}
customer_limit = (pwr_diff_limit[3] << 24) |
(pwr_diff_limit[2] << 16) |
(pwr_diff_limit[1] << 8) | (pwr_diff_limit[0]);
RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
("Customer's limit rf(%c) = 0x%x\n",
((rf == 0) ? 'A' : 'B'), customer_limit));
writeVal = customer_limit +
((index < 2) ? powerBase0[rf] : powerBase1[rf]);
RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
("Customer, writeVal rf(%c)= 0x%x\n",
((rf == 0) ? 'A' : 'B'), writeVal));
break;
default:
chnlgroup = 0;
writeVal =
rtlphy->mcs_txpwrlevel_origoffset[chnlgroup]
[index + (rf ? 8 : 0)]
+ ((index < 2) ? powerBase0[rf] : powerBase1[rf]);
RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
("RTK better performance, writeVal "
"rf(%c) = 0x%x\n",
((rf == 0) ? 'A' : 'B'), writeVal));
break;
}
if (rtlpriv->dm.dynamic_txhighpower_lvl == TXHIGHPWRLEVEL_BT1)
writeVal = writeVal - 0x06060606;
else if (rtlpriv->dm.dynamic_txhighpower_lvl ==
TXHIGHPWRLEVEL_BT2)
writeVal = writeVal - 0x0c0c0c0c;
*(p_outwriteval + rf) = writeVal;
}
}
static void _rtl8821ae_write_ofdm_power_reg(struct ieee80211_hw *hw,
u8 index, u32 *pValue)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
u16 regoffset_a[6] = {
RTXAGC_A_OFDM18_OFDM6, RTXAGC_A_OFDM54_OFDM24,
RTXAGC_A_MCS03_MCS00, RTXAGC_A_MCS07_MCS04,
RTXAGC_A_MCS11_MCS08, RTXAGC_A_MCS15_MCS12
};
u16 regoffset_b[6] = {
RTXAGC_B_OFDM18_OFDM6, RTXAGC_B_OFDM54_OFDM24,
RTXAGC_B_MCS03_MCS00, RTXAGC_B_MCS07_MCS04,
RTXAGC_B_MCS11_MCS08, RTXAGC_B_MCS15_MCS12
};
u8 i, rf, pwr_val[4];
u32 writeVal;
u16 regoffset;
for (rf = 0; rf < 2; rf++) {
writeVal = pValue[rf];
for (i = 0; i < 4; i++) {
pwr_val[i] = (u8) ((writeVal & (0x7f <<
(i * 8))) >> (i * 8));
if (pwr_val[i] > RF6052_MAX_TX_PWR)
pwr_val[i] = RF6052_MAX_TX_PWR;
}
writeVal = (pwr_val[3] << 24) | (pwr_val[2] << 16) |
(pwr_val[1] << 8) | pwr_val[0];
if (rf == 0)
regoffset = regoffset_a[index];
else
regoffset = regoffset_b[index];
rtl_set_bbreg(hw, regoffset, MASKDWORD, writeVal);
RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
("Set 0x%x = %08x\n", regoffset, writeVal));
}
}
void rtl8821ae_phy_rf6052_set_ofdm_txpower(struct ieee80211_hw *hw,
u8 *ppowerlevel_ofdm, u8 *ppowerlevel_bw20, u8 *ppowerlevel_bw40, u8 channel)
{
u32 writeVal[2], powerBase0[2], powerBase1[2];
u8 index;
u8 direction;
u32 pwrtrac_value;
rtl8821ae_phy_get_power_base(hw, ppowerlevel_ofdm, ppowerlevel_bw20, ppowerlevel_bw40,
channel, &powerBase0[0], &powerBase1[0]);
rtl8821ae_dm_txpower_track_adjust(hw,1,&direction,&pwrtrac_value);
for (index = 0; index < 6; index++) {
_rtl8821ae_get_txpower_writeval_by_regulatory(hw,
channel, index,
&powerBase0[0],
&powerBase1[0],
&writeVal[0]);
if (direction ==1){
writeVal[0] += pwrtrac_value;
writeVal[1] += pwrtrac_value;
} else if (direction == 2){
writeVal[0] -= pwrtrac_value;
writeVal[1] -= pwrtrac_value;
}
_rtl8821ae_write_ofdm_power_reg(hw, index, &writeVal[0]);
}
}
bool rtl8821ae_phy_rf6052_config(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_phy *rtlphy = &(rtlpriv->phy);
if (rtlphy->rf_type == RF_1T1R)
rtlphy->num_total_rfpath = 1;
else
rtlphy->num_total_rfpath = 2;
return _rtl8821ae_phy_rf6052_config_parafile(hw);
}
static bool _rtl8821ae_phy_rf6052_config_parafile(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_phy *rtlphy = &(rtlpriv->phy);
struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
//u32 u4_regvalue = 0;
u8 rfpath;
bool rtstatus = true;
//struct bb_reg_def *pphyreg;
for (rfpath = 0; rfpath < rtlphy->num_total_rfpath; rfpath++) {
switch (rfpath) {
case RF90_PATH_A: {
if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
rtstatus = rtl8812ae_phy_config_rf_with_headerfile(hw,
(enum radio_path)rfpath);
else
rtstatus = rtl8821ae_phy_config_rf_with_headerfile(hw,
(enum radio_path)rfpath);
break;
}
case RF90_PATH_B: {
if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
rtstatus = rtl8812ae_phy_config_rf_with_headerfile(hw,
(enum radio_path)rfpath);
else
rtstatus = rtl8821ae_phy_config_rf_with_headerfile(hw,
(enum radio_path)rfpath);
break;
}
case RF90_PATH_C:
break;
case RF90_PATH_D:
break;
}
if (rtstatus != true) {
RT_TRACE(COMP_INIT, DBG_TRACE,
("Radio[%d] Fail!!", rfpath));
return false;
}
}
/*put arrays in dm.c*/
/*_rtl8821ae_config_rf_txpwr_track_headerfile(hw);*/
RT_TRACE(COMP_INIT, DBG_TRACE, ("\n"));
return rtstatus;
}

46
drivers/staging/rtl8821ae/rtl8821ae/rf.h Normal file
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@ -0,0 +1,46 @@
/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __RTL8821AE_RF_H__
#define __RTL8821AE_RF_H__
#define RF6052_MAX_TX_PWR 0x3F
#define RF6052_MAX_REG 0x3F
extern void rtl8821ae_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw,
u8 bandwidth);
extern void rtl8821ae_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
u8 *ppowerlevel);
extern void rtl8821ae_phy_rf6052_set_ofdm_txpower(struct ieee80211_hw *hw,
u8 *ppowerlevel_ofdm,
u8 *ppowerlevel_bw20,
u8 *ppowerlevel_bw40,
u8 channel);
extern bool rtl8821ae_phy_rf6052_config(struct ieee80211_hw *hw);
#endif

499
drivers/staging/rtl8821ae/rtl8821ae/sw.c Normal file
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/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include <linux/vmalloc.h>
#include <linux/module.h>
#include "../wifi.h"
#include "../core.h"
#include "../pci.h"
#include "reg.h"
#include "def.h"
#include "phy.h"
#include "dm.h"
#include "hw.h"
#include "sw.h"
#include "trx.h"
#include "led.h"
#include "table.h"
#include "hal_btc.h"
#include "../btcoexist/rtl_btc.h"
void rtl8821ae_init_aspm_vars(struct ieee80211_hw *hw)
{
struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
/*close ASPM for AMD defaultly */
rtlpci->const_amdpci_aspm = 0;
/*
* ASPM PS mode.
* 0 - Disable ASPM,
* 1 - Enable ASPM without Clock Req,
* 2 - Enable ASPM with Clock Req,
* 3 - Alwyas Enable ASPM with Clock Req,
* 4 - Always Enable ASPM without Clock Req.
* set defult to RTL8192CE:3 RTL8192E:2
* */
rtlpci->const_pci_aspm = 3;
/*Setting for PCI-E device */
rtlpci->const_devicepci_aspm_setting = 0x03;
/*Setting for PCI-E bridge */
rtlpci->const_hostpci_aspm_setting = 0x02;
/*
* In Hw/Sw Radio Off situation.
* 0 - Default,
* 1 - From ASPM setting without low Mac Pwr,
* 2 - From ASPM setting with low Mac Pwr,
* 3 - Bus D3
* set default to RTL8192CE:0 RTL8192SE:2
*/
rtlpci->const_hwsw_rfoff_d3 = 0;
/*
* This setting works for those device with
* backdoor ASPM setting such as EPHY setting.
* 0 - Not support ASPM,
* 1 - Support ASPM,
* 2 - According to chipset.
*/
rtlpci->const_support_pciaspm = 1;
}
/*InitializeVariables8812E*/
int rtl8821ae_init_sw_vars(struct ieee80211_hw *hw)
{
int err = 0;
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
const struct firmware *firmware;
struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
char *fw_name = NULL;
rtl8821ae_bt_reg_init(hw);
rtlpriv->btcoexist.btc_ops = rtl_btc_get_ops_pointer();
rtlpriv->dm.b_dm_initialgain_enable = 1;
rtlpriv->dm.dm_flag = 0;
rtlpriv->dm.b_disable_framebursting = 0;;
rtlpriv->dm.thermalvalue = 0;
rtlpci->transmit_config = CFENDFORM | BIT(15) | BIT(24) | BIT(25);
mac->ht_enable = true;
rtlpriv->rtlhal.current_bandtype = BAND_ON_2_4G;
/*following 2 is for register 5G band, refer to _rtl_init_mac80211()*/
rtlpriv->rtlhal.bandset = BAND_ON_BOTH;
rtlpriv->rtlhal.macphymode = SINGLEMAC_SINGLEPHY;
rtlpci->receive_config = (RCR_APPFCS |
RCR_APP_MIC |
RCR_APP_ICV |
RCR_APP_PHYST_RXFF |
RCR_NONQOS_VHT |
RCR_HTC_LOC_CTRL |
RCR_AMF |
RCR_ACF |
RCR_ADF | /*This bit controls the PS-Poll packet filter.*/
RCR_AICV |
RCR_ACRC32 |
RCR_AB |
RCR_AM |
RCR_APM |
0);
rtlpci->irq_mask[0] =
(u32) (IMR_PSTIMEOUT |
IMR_GTINT3 |
/*IMR_TBDER |
IMR_TBDOK |
IMR_BCNDMAINT0 |*/
IMR_HSISR_IND_ON_INT |
IMR_C2HCMD |
IMR_HIGHDOK |
IMR_MGNTDOK |
IMR_BKDOK |
IMR_BEDOK |
IMR_VIDOK |
IMR_VODOK |
IMR_RDU |
IMR_ROK |
0);
rtlpci->irq_mask[1] =
(u32)( IMR_RXFOVW |
IMR_TXFOVW |
0);
/* for LPS & IPS */
rtlpriv->psc.b_inactiveps = rtlpriv->cfg->mod_params->b_inactiveps;
rtlpriv->psc.b_swctrl_lps = rtlpriv->cfg->mod_params->b_swctrl_lps;
rtlpriv->psc.b_fwctrl_lps = rtlpriv->cfg->mod_params->b_fwctrl_lps;
rtlpriv->psc.b_reg_fwctrl_lps = 3;
rtlpriv->psc.reg_max_lps_awakeintvl = 5;
/* for ASPM, you can close aspm through
* set const_support_pciaspm = 0 */
rtl8821ae_init_aspm_vars(hw);
if (rtlpriv->psc.b_reg_fwctrl_lps == 1)
rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE;
else if (rtlpriv->psc.b_reg_fwctrl_lps == 2)
rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE;
else if (rtlpriv->psc.b_reg_fwctrl_lps == 3)
rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE;
/* for firmware buf */
rtlpriv->rtlhal.pfirmware = (u8 *) vmalloc(0x8000);
if (!rtlpriv->rtlhal.pfirmware) {
RT_TRACE(COMP_ERR, DBG_EMERG,
("Can't alloc buffer for fw.\n"));
return 1;
}
fw_name = "rtlwifi/rtl8821aefw.bin";
err = request_firmware(&firmware, fw_name, rtlpriv->io.dev);
if (err) {
RT_TRACE(COMP_ERR, DBG_EMERG,
("Failed to request firmware!\n"));
return 1;
}
if (firmware->size > 0x8000) {
RT_TRACE(COMP_ERR, DBG_EMERG,
("Firmware is too big!\n"));
release_firmware(firmware);
return 1;
}
memcpy(rtlpriv->rtlhal.pfirmware, firmware->data, firmware->size);
rtlpriv->rtlhal.fwsize = firmware->size;
release_firmware(firmware);
if (rtlpriv->cfg->ops->get_btc_status()){
rtlpriv->btcoexist.btc_ops->btc_init_variables(rtlpriv);
rtlpriv->btcoexist.btc_ops->btc_init_hal_vars(rtlpriv);
}
RT_TRACE(COMP_INIT, DBG_LOUD, (" FirmwareDownload OK\n"));
return err;
}
void rtl8821ae_deinit_sw_vars(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
//printk("=========>rtl8821ae_deinit_sw_vars().\n");
if (rtlpriv->cfg->ops->get_btc_status()){
//printk("=========>rtl8821ae_deinit_sw_vars().get_btc_status\n");
rtlpriv->btcoexist.btc_ops->btc_halt_notify();
}
if (rtlpriv->rtlhal.pfirmware) {
//printk("=========>rtl8821ae_deinit_sw_vars().rtlpriv->rtlhal.pfirmware\n");
vfree(rtlpriv->rtlhal.pfirmware);
rtlpriv->rtlhal.pfirmware = NULL;
}
//printk("<=========rtl8821ae_deinit_sw_vars().\n");
}
u32 rtl8812ae_rx_command_packet_handler(
struct ieee80211_hw *hw,
struct rtl_stats status,
struct sk_buff *skb
)
{
u32 result = 0;
struct rtl_priv *rtlpriv = rtl_priv(hw);
switch (status.packet_report_type) {
case NORMAL_RX:
result = 0;
break;
case C2H_PACKET:
rtl8812ae_c2h_packet_handler(hw, skb->data, (u8) skb->len);
result = 1;
RT_TRACE(COMP_RECV, DBG_LOUD,
("===>rtl8821ae_rx_command_packet_handler(): (u8) skb->len=%d\n\n", skb->len));
break;
default:
RT_TRACE(COMP_RECV, DBG_LOUD,
("===>rtl8821ae_rx_command_packet_handler(): No this packet type!!\n"));
break;
}
return result;
}
/* get bt coexist status */
bool rtl8821ae_get_btc_status(void)
{
return true;
}
struct rtl_hal_ops rtl8821ae_hal_ops = {
.init_sw_vars = rtl8821ae_init_sw_vars,
.deinit_sw_vars = rtl8821ae_deinit_sw_vars,
.read_eeprom_info = rtl8821ae_read_eeprom_info,
.interrupt_recognized = rtl8821ae_interrupt_recognized,
.hw_init = rtl8821ae_hw_init,
.hw_disable = rtl8821ae_card_disable,
.hw_suspend = rtl8821ae_suspend,
.hw_resume = rtl8821ae_resume,
.enable_interrupt = rtl8821ae_enable_interrupt,
.disable_interrupt = rtl8821ae_disable_interrupt,
.set_network_type = rtl8821ae_set_network_type,
.set_chk_bssid = rtl8821ae_set_check_bssid,
.set_qos = rtl8821ae_set_qos,
.set_bcn_reg = rtl8821ae_set_beacon_related_registers,
.set_bcn_intv = rtl8821ae_set_beacon_interval,
.update_interrupt_mask = rtl8821ae_update_interrupt_mask,
.get_hw_reg = rtl8821ae_get_hw_reg,
.set_hw_reg = rtl8821ae_set_hw_reg,
.update_rate_tbl = rtl8821ae_update_hal_rate_tbl,
.fill_tx_desc = rtl8821ae_tx_fill_desc,
.fill_tx_cmddesc = rtl8821ae_tx_fill_cmddesc,
.query_rx_desc = rtl8821ae_rx_query_desc,
.set_channel_access = rtl8821ae_update_channel_access_setting,
.radio_onoff_checking = rtl8821ae_gpio_radio_on_off_checking,
.set_bw_mode = rtl8821ae_phy_set_bw_mode,
.switch_channel = rtl8821ae_phy_sw_chnl,
.dm_watchdog = rtl8821ae_dm_watchdog,
.scan_operation_backup = rtl8821ae_phy_scan_operation_backup,
.set_rf_power_state = rtl8821ae_phy_set_rf_power_state,
.led_control = rtl8821ae_led_control,
.set_desc = rtl8821ae_set_desc,
.get_desc = rtl8821ae_get_desc,
.is_tx_desc_closed = rtl8821ae_is_tx_desc_closed,
.tx_polling = rtl8821ae_tx_polling,
.enable_hw_sec = rtl8821ae_enable_hw_security_config,
.set_key = rtl8821ae_set_key,
.init_sw_leds = rtl8821ae_init_sw_leds,
.allow_all_destaddr = rtl8821ae_allow_all_destaddr,
.get_bbreg = rtl8821ae_phy_query_bb_reg,
.set_bbreg = rtl8821ae_phy_set_bb_reg,
.get_rfreg = rtl8821ae_phy_query_rf_reg,
.set_rfreg = rtl8821ae_phy_set_rf_reg,
.c2h_command_handle = rtl_8821ae_c2h_command_handle,
.bt_wifi_media_status_notify = rtl_8821ae_bt_wifi_media_status_notify,
.bt_turn_off_bt_coexist_before_enter_lps = rtl8821ae_dm_bt_turn_off_bt_coexist_before_enter_lps,
.fill_h2c_cmd = rtl8821ae_fill_h2c_cmd,
.get_btc_status = rtl8821ae_get_btc_status,
.rx_command_packet_handler = rtl8812ae_rx_command_packet_handler,
};
struct rtl_mod_params rtl8821ae_mod_params = {
.sw_crypto = false,
.b_inactiveps = false,//true,
.b_swctrl_lps = false,
.b_fwctrl_lps = false, //true,
};
struct rtl_hal_cfg rtl8821ae_hal_cfg = {
.bar_id = 2,
.write_readback = true,
.name = "rtl8821ae_pci",
.fw_name = "rtlwifi/rtl8821aefw.bin",
.ops = &rtl8821ae_hal_ops,
.mod_params = &rtl8821ae_mod_params,
.maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL,
.maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN,
.maps[SYS_CLK] = REG_SYS_CLKR,
.maps[MAC_RCR_AM] = AM,
.maps[MAC_RCR_AB] = AB,
.maps[MAC_RCR_ACRC32] = ACRC32,
.maps[MAC_RCR_ACF] = ACF,
.maps[MAC_RCR_AAP] = AAP,
.maps[MAC_HIMR] = REG_HIMR,
.maps[MAC_HIMRE] = REG_HIMRE,
.maps[EFUSE_ACCESS] = REG_EFUSE_ACCESS,
.maps[EFUSE_TEST] = REG_EFUSE_TEST,
.maps[EFUSE_CTRL] = REG_EFUSE_CTRL,
.maps[EFUSE_CLK] = 0,
.maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL,
.maps[EFUSE_PWC_EV12V] = PWC_EV12V,
.maps[EFUSE_FEN_ELDR] = FEN_ELDR,
.maps[EFUSE_LOADER_CLK_EN] = LOADER_CLK_EN,
.maps[EFUSE_ANA8M] = ANA8M,
.maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE,
.maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION,
.maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN,
.maps[EFUSE_OOB_PROTECT_BYTES_LEN] = EFUSE_OOB_PROTECT_BYTES,
.maps[RWCAM] = REG_CAMCMD,
.maps[WCAMI] = REG_CAMWRITE,
.maps[RCAMO] = REG_CAMREAD,
.maps[CAMDBG] = REG_CAMDBG,
.maps[SECR] = REG_SECCFG,
.maps[SEC_CAM_NONE] = CAM_NONE,
.maps[SEC_CAM_WEP40] = CAM_WEP40,
.maps[SEC_CAM_TKIP] = CAM_TKIP,
.maps[SEC_CAM_AES] = CAM_AES,
.maps[SEC_CAM_WEP104] = CAM_WEP104,
.maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6,
.maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5,
.maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4,
.maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3,
.maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2,
.maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1,
/* .maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8, */ /*need check*/
.maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7,
.maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6,
.maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5,
.maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4,
.maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3,
.maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2,
.maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1,
/* .maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2,*/
/* .maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1,*/
.maps[RTL_IMR_TXFOVW] = IMR_TXFOVW,
.maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT,
.maps[RTL_IMR_BcnInt] = IMR_BCNDMAINT0,
.maps[RTL_IMR_RXFOVW] = IMR_RXFOVW,
.maps[RTL_IMR_RDU] = IMR_RDU,
.maps[RTL_IMR_ATIMEND] = IMR_ATIMEND,
.maps[RTL_IMR_BDOK] = IMR_BCNDOK0,
.maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK,
.maps[RTL_IMR_TBDER] = IMR_TBDER,
.maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK,
.maps[RTL_IMR_TBDOK] = IMR_TBDOK,
.maps[RTL_IMR_BKDOK] = IMR_BKDOK,
.maps[RTL_IMR_BEDOK] = IMR_BEDOK,
.maps[RTL_IMR_VIDOK] = IMR_VIDOK,
.maps[RTL_IMR_VODOK] = IMR_VODOK,
.maps[RTL_IMR_ROK] = IMR_ROK,
.maps[RTL_IBSS_INT_MASKS] = (IMR_BCNDMAINT0 | IMR_TBDOK | IMR_TBDER),
.maps[RTL_RC_CCK_RATE1M] = DESC_RATE1M,
.maps[RTL_RC_CCK_RATE2M] = DESC_RATE2M,
.maps[RTL_RC_CCK_RATE5_5M] = DESC_RATE5_5M,
.maps[RTL_RC_CCK_RATE11M] = DESC_RATE11M,
.maps[RTL_RC_OFDM_RATE6M] = DESC_RATE6M,
.maps[RTL_RC_OFDM_RATE9M] = DESC_RATE9M,
.maps[RTL_RC_OFDM_RATE12M] = DESC_RATE12M,
.maps[RTL_RC_OFDM_RATE18M] = DESC_RATE18M,
.maps[RTL_RC_OFDM_RATE24M] = DESC_RATE24M,
.maps[RTL_RC_OFDM_RATE36M] = DESC_RATE36M,
.maps[RTL_RC_OFDM_RATE48M] = DESC_RATE48M,
.maps[RTL_RC_OFDM_RATE54M] = DESC_RATE54M,
.maps[RTL_RC_HT_RATEMCS7] = DESC_RATEMCS7,
.maps[RTL_RC_HT_RATEMCS15] = DESC_RATEMCS15,
};
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,8,0))
static struct pci_device_id rtl8821ae_pci_ids[] = {
{RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8812, rtl8821ae_hal_cfg)},
{RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8821, rtl8821ae_hal_cfg)},
{},
};
#else
static struct pci_device_id rtl8821ae_pci_ids[] __devinitdata = {
{RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8812, rtl8821ae_hal_cfg)},
{RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8821, rtl8821ae_hal_cfg)},
{},
};
#endif
MODULE_DEVICE_TABLE(pci, rtl8821ae_pci_ids);
MODULE_AUTHOR("Ping Yan<ping_yan@realsil.com.cn>");
MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>");
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Realtek 8821ae 802.11ac PCI wireless");
MODULE_FIRMWARE("rtlwifi/rtl8821aefw.bin");
module_param_named(swenc, rtl8821ae_mod_params.sw_crypto, bool, 0444);
module_param_named(ips, rtl8821ae_mod_params.b_inactiveps, bool, 0444);
module_param_named(swlps, rtl8821ae_mod_params.b_swctrl_lps, bool, 0444);
module_param_named(fwlps, rtl8821ae_mod_params.b_fwctrl_lps, bool, 0444);
MODULE_PARM_DESC(swenc, "using hardware crypto (default 0 [hardware])\n");
MODULE_PARM_DESC(ips, "using no link power save (default 1 is open)\n");
MODULE_PARM_DESC(fwlps, "using linked fw control power save (default 1 is open)\n");
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29))
static const SIMPLE_DEV_PM_OPS(rtlwifi_pm_ops, rtl_pci_suspend, rtl_pci_resume);
#endif
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,29))
compat_pci_suspend(rtl_pci_suspend)
compat_pci_resume(rtl_pci_resume)
#endif
static struct pci_driver rtl8821ae_driver = {
.name = KBUILD_MODNAME,
.id_table = rtl8821ae_pci_ids,
.probe = rtl_pci_probe,
.remove = rtl_pci_disconnect,
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29))
.driver.pm = &rtlwifi_pm_ops,
#elif defined(CONFIG_PM)
.suspend = rtl_pci_suspend_compat,
.resume = rtl_pci_resume_compat,
#endif
};
extern int rtl_core_module_init(void);
extern void rtl_core_module_exit(void);
static int __init rtl8821ae_module_init(void)
{
int ret;
ret = rtl_core_module_init();
if (ret)
return ret;
//printk("==========>rtl8821ae_module_init().\n");
ret = pci_register_driver(&rtl8821ae_driver);
if (ret)
RT_ASSERT(false, (": No device found\n"));
return ret;
}
static void __exit rtl8821ae_module_exit(void)
{
pci_unregister_driver(&rtl8821ae_driver);
rtl_core_module_exit();
}
module_init(rtl8821ae_module_init);
module_exit(rtl8821ae_module_exit);

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/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __RTL8821AE_SW_H__
#define __RTL8821AE_SW_H__
int rtl8821ae_init_sw_vars(struct ieee80211_hw *hw);
void rtl8821ae_deinit_sw_vars(struct ieee80211_hw *hw);
void rtl8821ae_init_var_map(struct ieee80211_hw *hw);
bool rtl8821ae_get_btc_status(void);
#endif

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/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Created on 2010/ 5/18, 1:41
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __RTL8821AE_TABLE__H_
#define __RTL8821AE_TABLE__H_
#include <linux/types.h>
#define RTL8821AEPHY_REG_1TARRAYLEN 344
extern u32 RTL8821AE_PHY_REG_ARRAY[];
#define RTL8812AEPHY_REG_1TARRAYLEN 490
extern u32 RTL8812AE_PHY_REG_ARRAY[];
#define RTL8821AEPHY_REG_ARRAY_PGLEN 90
extern u32 RTL8821AE_PHY_REG_ARRAY_PG[];
#define RTL8812AEPHY_REG_ARRAY_PGLEN 276
extern u32 RTL8812AE_PHY_REG_ARRAY_PG[];
//#define RTL8723BE_RADIOA_1TARRAYLEN 206
//extern u8 *RTL8821AE_TXPWR_LMT_ARRAY[];
#define RTL8812AE_RADIOA_1TARRAYLEN 1264
extern u32 RTL8812AE_RADIOA_ARRAY[];
#define RTL8812AE_RADIOB_1TARRAYLEN 1240
extern u32 RTL8812AE_RADIOB_ARRAY[];
#define RTL8821AE_RADIOA_1TARRAYLEN 1176
extern u32 RTL8821AE_RADIOA_ARRAY[];
#define RTL8821AEMAC_1T_ARRAYLEN 194
extern u32 RTL8821AE_MAC_REG_ARRAY[];
#define RTL8812AEMAC_1T_ARRAYLEN 214
extern u32 RTL8812AE_MAC_REG_ARRAY[];
#define RTL8821AEAGCTAB_1TARRAYLEN 382
extern u32 RTL8821AE_AGC_TAB_ARRAY[];
#define RTL8812AEAGCTAB_1TARRAYLEN 1312
extern u32 RTL8812AE_AGC_TAB_ARRAY[];
#endif

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/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __RTL8821AE_TRX_H__
#define __RTL8821AE_TRX_H__
#define TX_DESC_SIZE 40
#define TX_DESC_AGGR_SUBFRAME_SIZE 32
#define RX_DESC_SIZE 32
#define RX_DRV_INFO_SIZE_UNIT 8
#define TX_DESC_NEXT_DESC_OFFSET 40
#define USB_HWDESC_HEADER_LEN 40
#define CRCLENGTH 4
#define SET_TX_DESC_PKT_SIZE(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc, 0, 16, __val)
#define SET_TX_DESC_OFFSET(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc, 16, 8, __val)
#define SET_TX_DESC_BMC(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc, 24, 1, __val)
#define SET_TX_DESC_HTC(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc, 25, 1, __val)
#define SET_TX_DESC_LAST_SEG(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc, 26, 1, __val)
#define SET_TX_DESC_FIRST_SEG(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc, 27, 1, __val)
#define SET_TX_DESC_LINIP(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc, 28, 1, __val)
#define SET_TX_DESC_NO_ACM(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc, 29, 1, __val)
#define SET_TX_DESC_GF(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc, 30, 1, __val)
#define SET_TX_DESC_OWN(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc, 31, 1, __val)
#define GET_TX_DESC_PKT_SIZE(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc, 0, 16)
#define GET_TX_DESC_OFFSET(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc, 16, 8)
#define GET_TX_DESC_BMC(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc, 24, 1)
#define GET_TX_DESC_HTC(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc, 25, 1)
#define GET_TX_DESC_LAST_SEG(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc, 26, 1)
#define GET_TX_DESC_FIRST_SEG(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc, 27, 1)
#define GET_TX_DESC_LINIP(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc, 28, 1)
#define GET_TX_DESC_NO_ACM(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc, 29, 1)
#define GET_TX_DESC_GF(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc, 30, 1)
#define GET_TX_DESC_OWN(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc, 31, 1)
#define SET_TX_DESC_MACID(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+4, 0, 7, __val)
#define SET_TX_DESC_QUEUE_SEL(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+4, 8, 5, __val)
#define SET_TX_DESC_RDG_NAV_EXT(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+4, 13, 1, __val)
#define SET_TX_DESC_LSIG_TXOP_EN(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+4, 14, 1, __val)
#define SET_TX_DESC_PIFS(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+4, 15, 1, __val)
#define SET_TX_DESC_RATE_ID(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+4, 16, 5, __val)
#define SET_TX_DESC_EN_DESC_ID(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+4, 21, 1, __val)
#define SET_TX_DESC_SEC_TYPE(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+4, 22, 2, __val)
#define SET_TX_DESC_PKT_OFFSET(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+4, 24, 5, __val)
#define SET_TX_DESC_PAID(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+8, 0, 9, __val)
#define SET_TX_DESC_CCA_RTS(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+8, 10, 2, __val)
#define SET_TX_DESC_AGG_ENABLE(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+8, 12, 1, __val)
#define SET_TX_DESC_RDG_ENABLE(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+8, 13, 1, __val)
#define SET_TX_DESC_BAR_RTY_TH(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+8, 14, 2, __val)
#define SET_TX_DESC_AGG_BREAK(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+8, 16, 1, __val)
#define SET_TX_DESC_MORE_FRAG(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+8, 17, 1, __val)
#define SET_TX_DESC_RAW(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+8, 18, 1, __val)
#define SET_TX_DESC_SPE_RPT(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+8, 19, 1, __val)
#define SET_TX_DESC_AMPDU_DENSITY(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+8, 20, 3, __val)
#define SET_TX_DESC_BT_INT(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+8, 23, 1, __val)
#define SET_TX_DESC_GID(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+8, 24, 6, __val)
#define SET_TX_DESC_WHEADER_LEN(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+12, 0, 4, __val)
#define SET_TX_DESC_CHK_EN(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+12, 4, 1, __val)
#define SET_TX_DESC_EARLY_MODE(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+12, 5, 1, __val)
#define SET_TX_DESC_HWSEQ_SEL(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+12, 6, 2, __val)
#define SET_TX_DESC_USE_RATE(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+12, 8, 1, __val)
#define SET_TX_DESC_DISABLE_RTS_FB(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+12, 9, 1, __val)
#define SET_TX_DESC_DISABLE_FB(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+12, 10, 1, __val)
#define SET_TX_DESC_CTS2SELF(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+12, 11, 1, __val)
#define SET_TX_DESC_RTS_ENABLE(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+12, 12, 1, __val)
#define SET_TX_DESC_HW_RTS_ENABLE(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+12, 13, 1, __val)
#define SET_TX_DESC_NAV_USE_HDR(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+12, 15, 1, __val)
#define SET_TX_DESC_USE_MAX_LEN(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+12, 16, 1, __val)
#define SET_TX_DESC_MAX_AGG_NUM(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+12, 17, 5, __val)
#define SET_TX_DESC_NDPA(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+12, 22, 2, __val)
#define SET_TX_DESC_AMPDU_MAX_TIME(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+12, 24, 8, __val)
#define SET_TX_DESC_TX_ANT(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+20, 24, 4, __val)
#define SET_TX_DESC_TX_RATE(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+16, 0, 7, __val)
#define SET_TX_DESC_DATA_RATE_FB_LIMIT(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+16, 8, 5, __val)
#define SET_TX_DESC_RTS_RATE_FB_LIMIT(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+16, 13, 4, __val)
#define SET_TX_DESC_RETRY_LIMIT_ENABLE(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+16, 17, 1, __val)
#define SET_TX_DESC_DATA_RETRY_LIMIT(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+16, 18, 6, __val)
#define SET_TX_DESC_RTS_RATE(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+16, 24, 5, __val)
#define SET_TX_DESC_TX_SUB_CARRIER(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+20, 0, 4, __val)
#define SET_TX_DESC_DATA_SHORTGI(__pdesc, __val) \
SET_BITS_TO_LE_1BYTE(__pdesc+20, 6, 1, __val)
#define SET_TX_DESC_DATA_BW(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+20, 5, 2, __val)
#define SET_TX_DESC_DATA_LDPC(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+20, 7, 1, __val)
#define SET_TX_DESC_DATA_STBC(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+20, 8, 2, __val)
#define SET_TX_DESC_CTROL_STBC(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+20, 10, 2, __val)
#define SET_TX_DESC_RTS_SHORT(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+20, 12, 1, __val)
#define SET_TX_DESC_RTS_SC(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+20, 13, 4, __val)
#define SET_TX_DESC_TX_BUFFER_SIZE(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+28, 0, 16, __val)
#define GET_TX_DESC_TX_BUFFER_SIZE(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+28, 0, 16)
#define SET_TX_DESC_HWSEQ_EN(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+32, 15, 1, __val)
#define SET_TX_DESC_SEQ(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+36, 12, 12, __val)
#define SET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+40, 0, 32, __val)
#define GET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+40, 0, 32)
#define SET_TX_DESC_NEXT_DESC_ADDRESS(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+48, 0, 32, __val)
#define GET_TX_DESC_NEXT_DESC_ADDRESS(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+48, 0, 32)
#define GET_RX_DESC_PKT_LEN(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc, 0, 14)
#define GET_RX_DESC_CRC32(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc, 14, 1)
#define GET_RX_DESC_ICV(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc, 15, 1)
#define GET_RX_DESC_DRV_INFO_SIZE(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc, 16, 4)
#define GET_RX_DESC_SECURITY(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc, 20, 3)
#define GET_RX_DESC_QOS(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc, 23, 1)
#define GET_RX_DESC_SHIFT(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc, 24, 2)
#define GET_RX_DESC_PHYST(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc, 26, 1)
#define GET_RX_DESC_SWDEC(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc, 27, 1)
#define GET_RX_DESC_LS(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc, 28, 1)
#define GET_RX_DESC_FS(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc, 29, 1)
#define GET_RX_DESC_EOR(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc, 30, 1)
#define GET_RX_DESC_OWN(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc, 31, 1)
#define SET_RX_DESC_PKT_LEN(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc, 0, 14, __val)
#define SET_RX_DESC_EOR(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc, 30, 1, __val)
#define SET_RX_DESC_OWN(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc, 31, 1, __val)
#define GET_RX_DESC_MACID(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+4, 0, 7)
#define GET_RX_DESC_TID(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+4, 8, 4)
#define GET_RX_DESC_AMSDU(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+4, 13, 1)
#define GET_RX_STATUS_DESC_RXID_MATCH(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+4, 14, 1)
#define GET_RX_DESC_PAGGR(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+4, 15, 1)
#define GET_RX_DESC_A1_FIT(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+4, 16, 4)
#define GET_RX_DESC_CHKERR(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+4, 20, 1)
#define GET_RX_DESC_IPVER(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+4, 21, 1)
#define GET_RX_STATUS_DESC_IS_TCPUDP(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+4, 22, 1)
#define GET_RX_STATUS_DESC_CHK_VLD(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+4, 23, 1)
#define GET_RX_DESC_PAM(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+4, 24, 1)
#define GET_RX_DESC_PWR(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+4, 25, 1)
#define GET_RX_DESC_MD(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+4, 26, 1)
#define GET_RX_DESC_MF(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+4, 27, 1)
#define GET_RX_DESC_TYPE(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+4, 28, 2)
#define GET_RX_DESC_MC(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+4, 30, 1)
#define GET_RX_DESC_BC(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+4, 31, 1)
#define GET_RX_DESC_SEQ(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+8, 0, 12)
#define GET_RX_DESC_FRAG(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+8, 12, 4)
#define GET_RX_STATUS_DESC_RX_IS_QOS(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+8, 16, 1)
#define GET_RX_STATUS_DESC_WLANHD_IV_LEN(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+8, 18, 6)
#define GET_RX_STATUS_DESC_RPT_SEL(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+8, 28, 1)
#define GET_RX_DESC_RXMCS(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+12, 0, 7)
#define GET_RX_DESC_RXHT(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+12, 6, 1)
#define GET_RX_STATUS_DESC_RX_GF(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+12, 7, 1)
#define GET_RX_DESC_HTC(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+12, 10, 1)
#define GET_RX_STATUS_DESC_EOSP(__pdesc) \
LE_BITS_TO_4BYTE( __pdesc+12, 11, 1)
#define GET_RX_STATUS_DESC_BSSID_FIT(__pdesc) \
LE_BITS_TO_4BYTE( __pdesc+12, 12, 2)
#define GET_RX_STATUS_DESC_PATTERN_MATCH(__pdesc) \
LE_BITS_TO_4BYTE( __pdesc+12, 29, 1)
#define GET_RX_STATUS_DESC_UNICAST_MATCH(__pdesc) \
LE_BITS_TO_4BYTE( __pdesc+12, 30, 1)
#define GET_RX_STATUS_DESC_MAGIC_MATCH(__pdesc) \
LE_BITS_TO_4BYTE( __pdesc+12, 31, 1)
#define GET_RX_DESC_SPLCP(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+16, 0, 1)
#define GET_RX_STATUS_DESC_LDPC(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+16, 1, 1)
#define GET_RX_STATUS_DESC_STBC(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+16, 2, 1)
#define GET_RX_DESC_BW(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+16, 4, 2)
#define GET_RX_DESC_TSFL(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+20, 0, 32)
#define GET_RX_DESC_BUFF_ADDR(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+24, 0, 32)
#define GET_RX_DESC_BUFF_ADDR64(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+28, 0, 32)
#define SET_RX_DESC_BUFF_ADDR(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+24, 0, 32, __val)
#define SET_RX_DESC_BUFF_ADDR64(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+28, 0, 32, __val)
/* TX report 2 format in Rx desc*/
#define GET_RX_RPT2_DESC_PKT_LEN(__pRxStatusDesc) \
LE_BITS_TO_4BYTE( __pRxStatusDesc, 0, 9)
#define GET_RX_RPT2_DESC_MACID_VALID_1(__pRxStatusDesc) \
LE_BITS_TO_4BYTE( __pRxStatusDesc+16, 0, 32)
#define GET_RX_RPT2_DESC_MACID_VALID_2(__pRxStatusDesc) \
LE_BITS_TO_4BYTE( __pRxStatusDesc+20, 0, 32)
#define SET_EARLYMODE_PKTNUM(__paddr, __value) \
SET_BITS_TO_LE_4BYTE(__paddr, 0, 4, __value)
#define SET_EARLYMODE_LEN0(__paddr, __value) \
SET_BITS_TO_LE_4BYTE(__paddr, 4, 12, __value)
#define SET_EARLYMODE_LEN1(__paddr, __value) \
SET_BITS_TO_LE_4BYTE(__paddr, 16, 12, __value)
#define SET_EARLYMODE_LEN2_1(__paddr, __value) \
SET_BITS_TO_LE_4BYTE(__paddr, 28, 4, __value)
#define SET_EARLYMODE_LEN2_2(__paddr, __value) \
SET_BITS_TO_LE_4BYTE(__paddr+4, 0, 8, __value)
#define SET_EARLYMODE_LEN3(__paddr, __value) \
SET_BITS_TO_LE_4BYTE(__paddr+4, 8, 12, __value)
#define SET_EARLYMODE_LEN4(__paddr, __value) \
SET_BITS_TO_LE_4BYTE(__paddr+4, 20, 12, __value)
#define CLEAR_PCI_TX_DESC_CONTENT(__pdesc, _size) \
do { \
if(_size > TX_DESC_NEXT_DESC_OFFSET) \
memset(__pdesc, 0, TX_DESC_NEXT_DESC_OFFSET); \
else \
memset(__pdesc, 0, _size); \
} while (0);
#define RX_HAL_IS_CCK_RATE(rxmcs)\
(rxmcs == DESC_RATE1M ||\
rxmcs == DESC_RATE2M ||\
rxmcs == DESC_RATE5_5M ||\
rxmcs == DESC_RATE11M)
#define IS_LITTLE_ENDIAN 1
struct phy_rx_agc_info_t {
#if IS_LITTLE_ENDIAN
u8 gain:7,trsw:1;
#else
u8 trsw:1,gain:7;
#endif
};
struct phy_status_rpt{
struct phy_rx_agc_info_t path_agc[2];
u8 ch_corr[2];
u8 cck_sig_qual_ofdm_pwdb_all;
u8 cck_agc_rpt_ofdm_cfosho_a;
u8 cck_rpt_b_ofdm_cfosho_b;
u8 rsvd_1;//ch_corr_msb;
u8 noise_power_db_msb;
u8 path_cfotail[2];
u8 pcts_mask[2];
u8 stream_rxevm[2];
u8 path_rxsnr[2];
u8 noise_power_db_lsb;
u8 rsvd_2[3];
u8 stream_csi[2];
u8 stream_target_csi[2];
u8 sig_evm;
u8 rsvd_3;
#if IS_LITTLE_ENDIAN
u8 antsel_rx_keep_2:1; /*ex_intf_flg:1;*/
u8 sgi_en:1;
u8 rxsc:2;
u8 idle_long:1;
u8 r_ant_train_en:1;
u8 ant_sel_b:1;
u8 ant_sel:1;
#else /* _BIG_ENDIAN_ */
u8 ant_sel:1;
u8 ant_sel_b:1;
u8 r_ant_train_en:1;
u8 idle_long:1;
u8 rxsc:2;
u8 sgi_en:1;
u8 antsel_rx_keep_2:1; /*ex_intf_flg:1;*/
#endif
}__packed;
struct rx_fwinfo_8821ae {
u8 gain_trsw[4];
u8 pwdb_all;
u8 cfosho[4];
u8 cfotail[4];
char rxevm[2];
char rxsnr[4];
u8 pdsnr[2];
u8 csi_current[2];
u8 csi_target[2];
u8 sigevm;
u8 max_ex_pwr;
u8 ex_intf_flag:1;
u8 sgi_en:1;
u8 rxsc:2;
u8 reserve:4;
} __packed;
struct tx_desc_8821ae {
u32 pktsize:16;
u32 offset:8;
u32 bmc:1;
u32 htc:1;
u32 lastseg:1;
u32 firstseg:1;
u32 linip:1;
u32 noacm:1;
u32 gf:1;
u32 own:1;
u32 macid:6;
u32 rsvd0:2;
u32 queuesel:5;
u32 rd_nav_ext:1;
u32 lsig_txop_en:1;
u32 pifs:1;
u32 rateid:4;
u32 nav_usehdr:1;
u32 en_descid:1;
u32 sectype:2;
u32 pktoffset:8;
u32 rts_rc:6;
u32 data_rc:6;
u32 agg_en:1;
u32 rdg_en:1;
u32 bar_retryht:2;
u32 agg_break:1;
u32 morefrag:1;
u32 raw:1;
u32 ccx:1;
u32 ampdudensity:3;
u32 bt_int:1;
u32 ant_sela:1;
u32 ant_selb:1;
u32 txant_cck:2;
u32 txant_l:2;
u32 txant_ht:2;
u32 nextheadpage:8;
u32 tailpage:8;
u32 seq:12;
u32 cpu_handle:1;
u32 tag1:1;
u32 trigger_int:1;
u32 hwseq_en:1;
u32 rtsrate:5;
u32 apdcfe:1;
u32 qos:1;
u32 hwseq_ssn:1;
u32 userrate:1;
u32 dis_rtsfb:1;
u32 dis_datafb:1;
u32 cts2self:1;
u32 rts_en:1;
u32 hwrts_en:1;
u32 portid:1;
u32 pwr_status:3;
u32 waitdcts:1;
u32 cts2ap_en:1;
u32 txsc:2;
u32 stbc:2;
u32 txshort:1;
u32 txbw:1;
u32 rtsshort:1;
u32 rtsbw:1;
u32 rtssc:2;
u32 rtsstbc:2;
u32 txrate:6;
u32 shortgi:1;
u32 ccxt:1;
u32 txrate_fb_lmt:5;
u32 rtsrate_fb_lmt:4;
u32 retrylmt_en:1;
u32 txretrylmt:6;
u32 usb_txaggnum:8;
u32 txagca:5;
u32 txagcb:5;
u32 usemaxlen:1;
u32 maxaggnum:5;
u32 mcsg1maxlen:4;
u32 mcsg2maxlen:4;
u32 mcsg3maxlen:4;
u32 mcs7sgimaxlen:4;
u32 txbuffersize:16;
u32 sw_offset30:8;
u32 sw_offset31:4;
u32 rsvd1:1;
u32 antsel_c:1;
u32 null_0:1;
u32 null_1:1;
u32 txbuffaddr;
u32 txbufferaddr64;
u32 nextdescaddress;
u32 nextdescaddress64;
u32 reserve_pass_pcie_mm_limit[4];
} __packed;
struct rx_desc_8821ae {
u32 length:14;
u32 crc32:1;
u32 icverror:1;
u32 drv_infosize:4;
u32 security:3;
u32 qos:1;
u32 shift:2;
u32 phystatus:1;
u32 swdec:1;
u32 lastseg:1;
u32 firstseg:1;
u32 eor:1;
u32 own:1;
u32 macid:6;
u32 tid:4;
u32 hwrsvd:5;
u32 paggr:1;
u32 faggr:1;
u32 a1_fit:4;
u32 a2_fit:4;
u32 pam:1;
u32 pwr:1;
u32 moredata:1;
u32 morefrag:1;
u32 type:2;
u32 mc:1;
u32 bc:1;
u32 seq:12;
u32 frag:4;
u32 nextpktlen:14;
u32 nextind:1;
u32 rsvd:1;
u32 rxmcs:6;
u32 rxht:1;
u32 amsdu:1;
u32 splcp:1;
u32 bandwidth:1;
u32 htc:1;
u32 tcpchk_rpt:1;
u32 ipcchk_rpt:1;
u32 tcpchk_valid:1;
u32 hwpcerr:1;
u32 hwpcind:1;
u32 iv0:16;
u32 iv1;
u32 tsfl;
u32 bufferaddress;
u32 bufferaddress64;
} __packed;
/*<delete in kernel start>*/
#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,7,0))
void rtl8821ae_tx_fill_desc(struct ieee80211_hw *hw,
struct ieee80211_hdr *hdr, u8 *pdesc_tx, u8 *txbd,
struct ieee80211_tx_info *info, struct sk_buff *skb,
u8 hw_queue, struct rtl_tcb_desc *ptcb_desc);
#else
/*<delete in kernel end>*/
void rtl8821ae_tx_fill_desc(struct ieee80211_hw *hw,
struct ieee80211_hdr *hdr, u8 *pdesc_tx, u8 *txbd,
struct ieee80211_tx_info *info,
struct ieee80211_sta *sta,
struct sk_buff *skb,
u8 hw_queue, struct rtl_tcb_desc *ptcb_desc);
/*<delete in kernel start>*/
#endif
/*<delete in kernel end>*/
bool rtl8821ae_rx_query_desc(struct ieee80211_hw *hw,
struct rtl_stats *status,
struct ieee80211_rx_status *rx_status,
u8 *pdesc, struct sk_buff *skb);
void rtl8821ae_set_desc(struct ieee80211_hw * hw, u8 *pdesc, bool istx, u8 desc_name, u8 *val);
u32 rtl8821ae_get_desc(u8 *pdesc, bool istx, u8 desc_name);
bool rtl8821ae_is_tx_desc_closed(struct ieee80211_hw *hw,
u8 hw_queue, u16 index);
void rtl8821ae_tx_polling(struct ieee80211_hw *hw, u8 hw_queue);
void rtl8821ae_tx_fill_cmddesc(struct ieee80211_hw *hw, u8 *pdesc,
bool b_firstseg, bool b_lastseg,
struct sk_buff *skb);
#endif

283
drivers/staging/rtl8821ae/stats.c Normal file
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@ -0,0 +1,283 @@
/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#include "wifi.h"
#include "stats.h"
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,0))
#include <linux/export.h>
#endif
u8 rtl_query_rxpwrpercentage(char antpower)
{
if ((antpower <= -100) || (antpower >= 20))
return 0;
else if (antpower >= 0)
return 100;
else
return (100 + antpower);
}
//EXPORT_SYMBOL(rtl_query_rxpwrpercentage);
u8 rtl_evm_db_to_percentage(char value)
{
char ret_val;
ret_val = value;
if (ret_val >= 0)
ret_val = 0;
if (ret_val <= -33)
ret_val = -33;
ret_val = 0 - ret_val;
ret_val *= 3;
if (ret_val == 99)
ret_val = 100;
return ret_val;
}
//EXPORT_SYMBOL(rtl_evm_db_to_percentage);
long rtl_translate_todbm(struct ieee80211_hw *hw,
u8 signal_strength_index)
{
long signal_power;
signal_power = (long)((signal_strength_index + 1) >> 1);
signal_power -= 95;
return signal_power;
}
long rtl_signal_scale_mapping(struct ieee80211_hw *hw, long currsig)
{
long retsig;
if (currsig >= 61 && currsig <= 100)
retsig = 90 + ((currsig - 60) / 4);
else if (currsig >= 41 && currsig <= 60)
retsig = 78 + ((currsig - 40) / 2);
else if (currsig >= 31 && currsig <= 40)
retsig = 66 + (currsig - 30);
else if (currsig >= 21 && currsig <= 30)
retsig = 54 + (currsig - 20);
else if (currsig >= 5 && currsig <= 20)
retsig = 42 + (((currsig - 5) * 2) / 3);
else if (currsig == 4)
retsig = 36;
else if (currsig == 3)
retsig = 27;
else if (currsig == 2)
retsig = 18;
else if (currsig == 1)
retsig = 9;
else
retsig = currsig;
return retsig;
}
//EXPORT_SYMBOL(rtl_signal_scale_mapping);
void rtl_process_ui_rssi(struct ieee80211_hw *hw, struct rtl_stats *pstatus)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_phy *rtlphy = &(rtlpriv->phy);
u8 rfpath;
u32 last_rssi, tmpval;
if (!pstatus->b_packet_toself && !pstatus->b_packet_beacon)
return;
rtlpriv->stats.pwdb_all_cnt += pstatus->rx_pwdb_all;
rtlpriv->stats.rssi_calculate_cnt++;
if (rtlpriv->stats.ui_rssi.total_num++ >= PHY_RSSI_SLID_WIN_MAX) {
rtlpriv->stats.ui_rssi.total_num = PHY_RSSI_SLID_WIN_MAX;
last_rssi = rtlpriv->stats.ui_rssi.elements[
rtlpriv->stats.ui_rssi.index];
rtlpriv->stats.ui_rssi.total_val -= last_rssi;
}
rtlpriv->stats.ui_rssi.total_val += pstatus->signalstrength;
rtlpriv->stats.ui_rssi.elements[rtlpriv->stats.ui_rssi.index++] =
pstatus->signalstrength;
if (rtlpriv->stats.ui_rssi.index >= PHY_RSSI_SLID_WIN_MAX)
rtlpriv->stats.ui_rssi.index = 0;
tmpval = rtlpriv->stats.ui_rssi.total_val /
rtlpriv->stats.ui_rssi.total_num;
rtlpriv->stats.signal_strength = rtl_translate_todbm(hw,
(u8) tmpval);
pstatus->rssi = rtlpriv->stats.signal_strength;
if (pstatus->b_is_cck)
return;
for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath;
rfpath++) {
if (rtlpriv->stats.rx_rssi_percentage[rfpath] == 0) {
rtlpriv->stats.rx_rssi_percentage[rfpath] =
pstatus->rx_mimo_signalstrength[rfpath];
}
if (pstatus->rx_mimo_signalstrength[rfpath] >
rtlpriv->stats.rx_rssi_percentage[rfpath]) {
rtlpriv->stats.rx_rssi_percentage[rfpath] =
((rtlpriv->stats.rx_rssi_percentage[rfpath] *
(RX_SMOOTH_FACTOR - 1)) +
(pstatus->rx_mimo_signalstrength[rfpath])) /
(RX_SMOOTH_FACTOR);
rtlpriv->stats.rx_rssi_percentage[rfpath] =
rtlpriv->stats.rx_rssi_percentage[rfpath] + 1;
} else {
rtlpriv->stats.rx_rssi_percentage[rfpath] =
((rtlpriv->stats.rx_rssi_percentage[rfpath] *
(RX_SMOOTH_FACTOR - 1)) +
(pstatus->rx_mimo_signalstrength[rfpath])) /
(RX_SMOOTH_FACTOR);
}
rtlpriv->stats.rx_snr_db[rfpath] = pstatus->rx_snr[rfpath];
rtlpriv->stats.rx_evm_dbm[rfpath] =
pstatus->rx_mimo_evm_dbm[rfpath];
rtlpriv->stats.rx_cfo_short[rfpath] =
pstatus->cfo_short[rfpath];
rtlpriv->stats.rx_cfo_tail[rfpath] = pstatus->cfo_tail[rfpath];
}
}
static void rtl_update_rxsignalstatistics(struct ieee80211_hw *hw,
struct rtl_stats *pstatus)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
int weighting = 0;
if (rtlpriv->stats.recv_signal_power == 0)
rtlpriv->stats.recv_signal_power = pstatus->recvsignalpower;
if (pstatus->recvsignalpower > rtlpriv->stats.recv_signal_power)
weighting = 5;
else if (pstatus->recvsignalpower < rtlpriv->stats.recv_signal_power)
weighting = (-5);
rtlpriv->stats.recv_signal_power = (rtlpriv->stats.recv_signal_power *
5 + pstatus->recvsignalpower + weighting) / 6;
}
static void rtl_process_pwdb(struct ieee80211_hw *hw, struct rtl_stats *pstatus)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_sta_info *drv_priv = NULL;
struct ieee80211_sta *sta = NULL;
long undecorated_smoothed_pwdb;
rcu_read_lock();
if (rtlpriv->mac80211.opmode != NL80211_IFTYPE_STATION)
sta = rtl_find_sta(hw, pstatus->psaddr);
/* adhoc or ap mode */
if (sta) {
drv_priv = (struct rtl_sta_info *) sta->drv_priv;
undecorated_smoothed_pwdb =
drv_priv->rssi_stat.undecorated_smoothed_pwdb;
} else {
undecorated_smoothed_pwdb =
rtlpriv->dm.undecorated_smoothed_pwdb;
}
if (undecorated_smoothed_pwdb < 0)
undecorated_smoothed_pwdb = pstatus->rx_pwdb_all;
if (pstatus->rx_pwdb_all > (u32) undecorated_smoothed_pwdb) {
undecorated_smoothed_pwdb = (((undecorated_smoothed_pwdb) *
(RX_SMOOTH_FACTOR - 1)) +
(pstatus->rx_pwdb_all)) / (RX_SMOOTH_FACTOR);
undecorated_smoothed_pwdb = undecorated_smoothed_pwdb + 1;
} else {
undecorated_smoothed_pwdb = (((undecorated_smoothed_pwdb) *
(RX_SMOOTH_FACTOR - 1)) +
(pstatus->rx_pwdb_all)) / (RX_SMOOTH_FACTOR);
}
if(sta) {
drv_priv->rssi_stat.undecorated_smoothed_pwdb =
undecorated_smoothed_pwdb;
} else {
rtlpriv->dm.undecorated_smoothed_pwdb = undecorated_smoothed_pwdb;
}
rcu_read_unlock();
rtl_update_rxsignalstatistics(hw, pstatus);
}
static void rtl_process_ui_link_quality(struct ieee80211_hw *hw,
struct rtl_stats *pstatus)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
u32 last_evm, n_stream, tmpval;
if (pstatus->signalquality == 0)
return;
if (rtlpriv->stats.ui_link_quality.total_num++ >=
PHY_LINKQUALITY_SLID_WIN_MAX) {
rtlpriv->stats.ui_link_quality.total_num =
PHY_LINKQUALITY_SLID_WIN_MAX;
last_evm = rtlpriv->stats.ui_link_quality.elements[
rtlpriv->stats.ui_link_quality.index];
rtlpriv->stats.ui_link_quality.total_val -= last_evm;
}
rtlpriv->stats.ui_link_quality.total_val += pstatus->signalquality;
rtlpriv->stats.ui_link_quality.elements[
rtlpriv->stats.ui_link_quality.index++] =
pstatus->signalquality;
if (rtlpriv->stats.ui_link_quality.index >=
PHY_LINKQUALITY_SLID_WIN_MAX)
rtlpriv->stats.ui_link_quality.index = 0;
tmpval = rtlpriv->stats.ui_link_quality.total_val /
rtlpriv->stats.ui_link_quality.total_num;
rtlpriv->stats.signal_quality = tmpval;
rtlpriv->stats.last_sigstrength_inpercent = tmpval;
for (n_stream = 0; n_stream < 2; n_stream++) {
if (pstatus->rx_mimo_signalquality[n_stream] != -1) {
if (rtlpriv->stats.rx_evm_percentage[n_stream] == 0) {
rtlpriv->stats.rx_evm_percentage[n_stream] =
pstatus->rx_mimo_signalquality[n_stream];
}
rtlpriv->stats.rx_evm_percentage[n_stream] =
((rtlpriv->stats.rx_evm_percentage[n_stream]
* (RX_SMOOTH_FACTOR - 1)) +
(pstatus->rx_mimo_signalquality[n_stream] * 1)) /
(RX_SMOOTH_FACTOR);
}
}
}
void rtl_process_phyinfo(struct ieee80211_hw *hw, u8 *buffer,
struct rtl_stats *pstatus)
{
if (!pstatus->b_packet_matchbssid)
return;
rtl_process_ui_rssi(hw, pstatus);
rtl_process_pwdb(hw, pstatus);
rtl_process_ui_link_quality(hw, pstatus);
}
//EXPORT_SYMBOL(rtl_process_phyinfo);

46
drivers/staging/rtl8821ae/stats.h Normal file
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@ -0,0 +1,46 @@
/******************************************************************************
*
* Copyright(c) 2009-2010 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* wlanfae <wlanfae@realtek.com>
* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
* Hsinchu 300, Taiwan.
*
* Larry Finger <Larry.Finger@lwfinger.net>
*
*****************************************************************************/
#ifndef __RTL_STATS_H__
#define __RTL_STATS_H__
#define PHY_RSSI_SLID_WIN_MAX 100
#define PHY_LINKQUALITY_SLID_WIN_MAX 20
#define PHY_BEACON_RSSI_SLID_WIN_MAX 10
/* Rx smooth factor */
#define RX_SMOOTH_FACTOR 20
u8 rtl_query_rxpwrpercentage(char antpower);
u8 rtl_evm_db_to_percentage(char value);
long rtl_signal_scale_mapping(struct ieee80211_hw *hw, long currsig);
void rtl_process_phyinfo(struct ieee80211_hw *hw, u8 *buffer,
struct rtl_stats *pstatus);
#endif

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