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Merge tag 'imx-dt-newclk-4.17' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt 

Pull "i.MX device tree update with new clock for 4.17" from Shawn Guo:

 - Add CAAM and Keypad device node for i.MX7S/D SoC device tree.
 - Add clock support for i.MX7 SNVS RTC device.

* tag 'imx-dt-newclk-4.17' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  ARM: dts: imx7s: add Keypad Port module
  ARM: dts: imx7s: add CAAM device node
  ARM: dts: imx7s: add snvs rtc clock
  clk: imx: imx7d: add the Keypad Port module clock
  clk: imx7d: add CAAM clock
  clk: imx: imx7d: add the snvs clock
This commit is contained in:
Arnd Bergmann 2018-03-15 16:01:18 +01:00
parent f3ccc2b445 303aa1bf07
commit fed925ea70
4 changed files with 64 additions and 1 deletions
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17
Documentation/devicetree/bindings/crypto/fsl-sec4.txt
View File

@ -415,12 +415,27 @@ Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node
value type: <u32>
Definition: LP register offset. default it is 0x34.
- clocks
Usage: optional, required if SNVS LP RTC requires explicit
enablement of clocks
Value type: <prop_encoded-array>
Definition: a clock specifier describing the clock required for
enabling and disabling SNVS LP RTC.
- clock-names
Usage: optional, required if SNVS LP RTC requires explicit
enablement of clocks
Value type: <string>
Definition: clock name string should be "snvs-rtc".
EXAMPLE
sec_mon_rtc_lp@1 {
compatible = "fsl,sec-v4.0-mon-rtc-lp";
interrupts = <93 2>;
regmap = <&snvs>;
offset = <0x34>;
clocks = <&clks IMX7D_SNVS_CLK>;
clock-names = "snvs-rtc";
};
=====================================================================
@ -543,6 +558,8 @@ FULL EXAMPLE
regmap = <&sec_mon>;
offset = <0x34>;
interrupts = <93 2>;
clocks = <&clks IMX7D_SNVS_CLK>;
clock-names = "snvs-rtc";
};
snvs-pwrkey@020cc000 {

40
arch/arm/boot/dts/imx7s.dtsi
View File

@ -499,6 +499,14 @@ gpt4: gpt@30300000 {
status = "disabled";
};
kpp: kpp@30320000 {
compatible = "fsl,imx7d-kpp", "fsl,imx21-kpp";
reg = <0x30320000 0x10000>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_KPP_ROOT_CLK>;
status = "disabled";
};
iomuxc: iomuxc@30330000 {
compatible = "fsl,imx7d-iomuxc";
reg = <0x30330000 0x10000>;
@ -551,6 +559,8 @@ snvs_rtc: snvs-rtc-lp {
offset = <0x34>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_SNVS_CLK>;
clock-names = "snvs-rtc";
};
snvs_poweroff: snvs-poweroff {
@ -822,6 +832,36 @@ sai3: sai@308c0000 {
status = "disabled";
};
crypto: caam@30900000 {
compatible = "fsl,sec-v4.0";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x30900000 0x40000>;
ranges = <0 0x30900000 0x40000>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_CAAM_CLK>,
<&clks IMX7D_AHB_CHANNEL_ROOT_CLK>;
clock-names = "ipg", "aclk";
sec_jr0: jr0@1000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x1000 0x1000>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
};
sec_jr1: jr1@2000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x2000 0x1000>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
};
sec_jr2: jr1@3000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x3000 0x1000>;
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
};
};
flexcan1: can@30a00000 {
compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
reg = <0x30a00000 0x10000>;

3
drivers/clk/imx/clk-imx7d.c
View File

@ -795,6 +795,8 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
clks[IMX7D_DRAM_PHYM_ALT_ROOT_CLK] = imx_clk_gate4("dram_phym_alt_root_clk", "dram_phym_alt_post_div", base + 0x4130, 0);
clks[IMX7D_DRAM_ALT_ROOT_CLK] = imx_clk_gate4("dram_alt_root_clk", "dram_alt_post_div", base + 0x4130, 0);
clks[IMX7D_OCOTP_CLK] = imx_clk_gate4("ocotp_clk", "ipg_root_clk", base + 0x4230, 0);
clks[IMX7D_SNVS_CLK] = imx_clk_gate4("snvs_clk", "ipg_root_clk", base + 0x4250, 0);
clks[IMX7D_CAAM_CLK] = imx_clk_gate4("caam_clk", "ipg_root_clk", base + 0x4240, 0);
clks[IMX7D_USB_HSIC_ROOT_CLK] = imx_clk_gate4("usb_hsic_root_clk", "usb_hsic_post_div", base + 0x4420, 0);
clks[IMX7D_SDMA_CORE_CLK] = imx_clk_gate4("sdma_root_clk", "ahb_root_clk", base + 0x4480, 0);
clks[IMX7D_PCIE_CTRL_ROOT_CLK] = imx_clk_gate4("pcie_ctrl_root_clk", "pcie_ctrl_post_div", base + 0x4600, 0);
@ -857,6 +859,7 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
clks[IMX7D_WDOG2_ROOT_CLK] = imx_clk_gate4("wdog2_root_clk", "wdog_post_div", base + 0x49d0, 0);
clks[IMX7D_WDOG3_ROOT_CLK] = imx_clk_gate4("wdog3_root_clk", "wdog_post_div", base + 0x49e0, 0);
clks[IMX7D_WDOG4_ROOT_CLK] = imx_clk_gate4("wdog4_root_clk", "wdog_post_div", base + 0x49f0, 0);
clks[IMX7D_KPP_ROOT_CLK] = imx_clk_gate4("kpp_root_clk", "ipg_root_clk", base + 0x4aa0, 0);
clks[IMX7D_CSI_MCLK_ROOT_CLK] = imx_clk_gate4("csi_mclk_root_clk", "csi_mclk_post_div", base + 0x4490, 0);
clks[IMX7D_AUDIO_MCLK_ROOT_CLK] = imx_clk_gate4("audio_mclk_root_clk", "audio_mclk_post_div", base + 0x4790, 0);
clks[IMX7D_WRCLK_ROOT_CLK] = imx_clk_gate4("wrclk_root_clk", "wrclk_post_div", base + 0x47a0, 0);

5
include/dt-bindings/clock/imx7d-clock.h
View File

@ -452,5 +452,8 @@
#define IMX7D_OCOTP_CLK 439
#define IMX7D_NAND_RAWNAND_CLK 440
#define IMX7D_NAND_USDHC_BUS_RAWNAND_CLK 441
#define IMX7D_CLK_END 442
#define IMX7D_SNVS_CLK 442
#define IMX7D_CAAM_CLK 443
#define IMX7D_KPP_ROOT_CLK 444
#define IMX7D_CLK_END 445
#endif /* __DT_BINDINGS_CLOCK_IMX7D_H */