mirror of https://gitee.com/openkylin/linux.git
ARM: dts: keystone: Add clock tree data to devicetree
Add clock tree for Keystone 2 based SOCs. Cc: Mike Turquette <mturquette@linaro.org> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
This commit is contained in:
Santosh Shilimkar
parent
d0e639c9e0
commit
feeea8f34c
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@ -0,0 +1,821 @@
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/*
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* Device Tree Source for Keystone 2 clock tree
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*
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* Copyright (C) 2013 Texas Instruments, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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clocks {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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refclkmain: refclkmain {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <122880000>;
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clock-output-names = "refclk-main";
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};
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mainpllclk: mainpllclk@2310110 {
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#clock-cells = <0>;
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compatible = "ti,keystone,main-pll-clock";
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clocks = <&refclkmain>;
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reg = <0x02620350 4>, <0x02310110 4>;
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reg-names = "control", "multiplier";
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fixed-postdiv = <2>;
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};
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papllclk: papllclk@2620358 {
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#clock-cells = <0>;
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compatible = "ti,keystone,pll-clock";
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clocks = <&refclkmain>;
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clock-output-names = "pa-pll-clk";
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reg = <0x02620358 4>;
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reg-names = "control";
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fixed-postdiv = <6>;
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};
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ddr3allclk: ddr3apllclk@2620360 {
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#clock-cells = <0>;
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compatible = "ti,keystone,pll-clock";
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clocks = <&refclkmain>;
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clock-output-names = "ddr-3a-pll-clk";
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reg = <0x02620360 4>;
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reg-names = "control";
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fixed-postdiv = <6>;
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};
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ddr3bllclk: ddr3bpllclk@2620368 {
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#clock-cells = <0>;
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compatible = "ti,keystone,pll-clock";
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clocks = <&refclkmain>;
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clock-output-names = "ddr-3b-pll-clk";
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reg = <0x02620368 4>;
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reg-names = "control";
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fixed-postdiv = <6>;
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};
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armpllclk: armpllclk@2620370 {
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#clock-cells = <0>;
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compatible = "ti,keystone,pll-clock";
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clocks = <&refclkmain>;
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clock-output-names = "arm-pll-clk";
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reg = <0x02620370 4>;
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reg-names = "control";
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fixed-postdiv = <6>;
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};
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mainmuxclk: mainmuxclk@2310108 {
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#clock-cells = <0>;
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compatible = "ti,keystone,pll-mux-clock";
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clocks = <&mainpllclk>, <&refclkmain>;
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reg = <0x02310108 4>;
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bit-shift = <23>;
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bit-mask = <1>;
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clock-output-names = "mainmuxclk";
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};
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chipclk1: chipclk1 {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&mainmuxclk>;
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clock-div = <1>;
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clock-mult = <1>;
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clock-output-names = "chipclk1";
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};
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chipclk1rstiso: chipclk1rstiso {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&mainmuxclk>;
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clock-div = <1>;
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clock-mult = <1>;
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clock-output-names = "chipclk1rstiso";
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};
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gemtraceclk: gemtraceclk@2310120 {
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#clock-cells = <0>;
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compatible = "ti,keystone,pll-divider-clock";
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clocks = <&mainmuxclk>;
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reg = <0x02310120 4>;
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bit-shift = <0>;
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bit-mask = <8>;
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clock-output-names = "gemtraceclk";
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};
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chipstmxptclk: chipstmxptclk {
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#clock-cells = <0>;
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compatible = "ti,keystone,pll-divider-clock";
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clocks = <&mainmuxclk>;
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reg = <0x02310164 4>;
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bit-shift = <0>;
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bit-mask = <8>;
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clock-output-names = "chipstmxptclk";
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};
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chipclk12: chipclk12 {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&chipclk1>;
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clock-div = <2>;
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clock-mult = <1>;
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clock-output-names = "chipclk12";
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};
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chipclk13: chipclk13 {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&chipclk1>;
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clock-div = <3>;
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clock-mult = <1>;
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clock-output-names = "chipclk13";
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};
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chipclk14: chipclk14 {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&chipclk1>;
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clock-div = <4>;
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clock-mult = <1>;
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clock-output-names = "chipclk14";
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};
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chipclk16: chipclk16 {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&chipclk1>;
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clock-div = <6>;
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clock-mult = <1>;
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clock-output-names = "chipclk16";
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};
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chipclk112: chipclk112 {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&chipclk1>;
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clock-div = <12>;
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clock-mult = <1>;
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clock-output-names = "chipclk112";
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};
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chipclk124: chipclk124 {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&chipclk1>;
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clock-div = <24>;
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clock-mult = <1>;
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clock-output-names = "chipclk114";
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};
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chipclk1rstiso13: chipclk1rstiso13 {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&chipclk1rstiso>;
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clock-div = <3>;
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clock-mult = <1>;
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clock-output-names = "chipclk1rstiso13";
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};
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chipclk1rstiso14: chipclk1rstiso14 {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&chipclk1rstiso>;
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clock-div = <4>;
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clock-mult = <1>;
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clock-output-names = "chipclk1rstiso14";
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};
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chipclk1rstiso16: chipclk1rstiso16 {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&chipclk1rstiso>;
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clock-div = <6>;
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clock-mult = <1>;
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clock-output-names = "chipclk1rstiso16";
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};
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chipclk1rstiso112: chipclk1rstiso112 {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&chipclk1rstiso>;
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clock-div = <12>;
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clock-mult = <1>;
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clock-output-names = "chipclk1rstiso112";
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};
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clkmodrst0: clkmodrst0 {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk16>;
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clock-output-names = "modrst0";
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reg = <0x02350000 0xb00>, <0x02350000 0x400>;
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reg-names = "control", "domain";
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domain-id = <0>;
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};
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clkusb: clkusb {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk16>;
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clock-output-names = "usb";
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reg = <0x02350008 0xb00>, <0x02350000 0x400>;
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reg-names = "control", "domain";
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domain-id = <0>;
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};
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clkaemifspi: clkaemifspi {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk16>;
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clock-output-names = "aemif-spi";
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reg = <0x0235000c 0xb00>, <0x02350000 0x400>;
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reg-names = "control", "domain";
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domain-id = <0>;
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};
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clkdebugsstrc: clkdebugsstrc {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk13>;
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clock-output-names = "debugss-trc";
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reg = <0x02350014 0xb00>, <0x02350000 0x400>;
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reg-names = "control", "domain";
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domain-id = <0>;
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};
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clktetbtrc: clktetbtrc {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk13>;
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clock-output-names = "tetb-trc";
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reg = <0x02350018 0xb00>, <0x02350004 0x400>;
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reg-names = "control", "domain";
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domain-id = <1>;
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};
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clkpa: clkpa {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk16>;
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clock-output-names = "pa";
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reg = <0x0235001c 0xb00>, <0x02350008 0x400>;
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reg-names = "control", "domain";
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domain-id = <2>;
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};
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clkcpgmac: clkcpgmac {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&clkpa>;
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clock-output-names = "cpgmac";
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reg = <0x02350020 0xb00>, <0x02350008 0x400>;
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reg-names = "control", "domain";
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domain-id = <2>;
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};
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clksa: clksa {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&clkpa>;
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clock-output-names = "sa";
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reg = <0x02350024 0xb00>, <0x02350008 0x400>;
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reg-names = "control", "domain";
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domain-id = <2>;
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};
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clkpcie: clkpcie {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk12>;
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clock-output-names = "pcie";
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reg = <0x02350028 0xb00>, <0x0235000c 0x400>;
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reg-names = "control", "domain";
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domain-id = <3>;
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};
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clksrio: clksrio {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk1rstiso13>;
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clock-output-names = "srio";
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reg = <0x0235002c 0xb00>, <0x02350010 0x400>;
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reg-names = "control", "domain";
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domain-id = <4>;
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};
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clkhyperlink0: clkhyperlink0 {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk12>;
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clock-output-names = "hyperlink-0";
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reg = <0x02350030 0xb00>, <0x02350014 0x400>;
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reg-names = "control", "domain";
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domain-id = <5>;
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};
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clksr: clksr {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk1rstiso112>;
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clock-output-names = "sr";
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reg = <0x02350034 0xb00>, <0x02350018 0x400>;
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reg-names = "control", "domain";
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domain-id = <6>;
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};
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clkmsmcsram: clkmsmcsram {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk1>;
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clock-output-names = "msmcsram";
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reg = <0x02350038 0xb00>, <0x0235001c 0x400>;
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reg-names = "control", "domain";
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domain-id = <7>;
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};
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clkgem0: clkgem0 {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk1>;
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clock-output-names = "gem0";
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reg = <0x0235003c 0xb00>, <0x02350020 0x400>;
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reg-names = "control", "domain";
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domain-id = <8>;
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};
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clkgem1: clkgem1 {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk1>;
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clock-output-names = "gem1";
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reg = <0x02350040 0xb00>, <0x02350024 0x400>;
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reg-names = "control", "domain";
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domain-id = <9>;
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};
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clkgem2: clkgem2 {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk1>;
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clock-output-names = "gem2";
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reg = <0x02350044 0xb00>, <0x02350028 0x400>;
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reg-names = "control", "domain";
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domain-id = <10>;
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};
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clkgem3: clkgem3 {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk1>;
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clock-output-names = "gem3";
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reg = <0x02350048 0xb00>, <0x0235002c 0x400>;
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reg-names = "control", "domain";
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domain-id = <11>;
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};
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clkgem4: clkgem4 {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk1>;
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clock-output-names = "gem4";
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reg = <0x0235004c 0xb00>, <0x02350030 0x400>;
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reg-names = "control", "domain";
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domain-id = <12>;
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};
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clkgem5: clkgem5 {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk1>;
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clock-output-names = "gem5";
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reg = <0x02350050 0xb00>, <0x02350034 0x400>;
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reg-names = "control", "domain";
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domain-id = <13>;
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};
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clkgem6: clkgem6 {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk1>;
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clock-output-names = "gem6";
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reg = <0x02350054 0xb00>, <0x02350038 0x400>;
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reg-names = "control", "domain";
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domain-id = <14>;
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};
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clkgem7: clkgem7 {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk1>;
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clock-output-names = "gem7";
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reg = <0x02350058 0xb00>, <0x0235003c 0x400>;
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reg-names = "control", "domain";
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domain-id = <15>;
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};
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clkddr30: clkddr30 {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk12>;
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clock-output-names = "ddr3-0";
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reg = <0x0235005c 0xb00>, <0x02350040 0x400>;
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reg-names = "control", "domain";
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domain-id = <16>;
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};
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clkddr31: clkddr31 {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk13>;
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clock-output-names = "ddr3-1";
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reg = <0x02350060 0xb00>, <0x02350040 0x400>;
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reg-names = "control", "domain";
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domain-id = <16>;
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};
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clktac: clktac {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk13>;
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clock-output-names = "tac";
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reg = <0x02350064 0xb00>, <0x02350044 0x400>;
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reg-names = "control", "domain";
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domain-id = <17>;
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};
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clkrac01: clktac01 {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk13>;
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clock-output-names = "rac-01";
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reg = <0x02350068 0xb00>, <0x02350044 0x400>;
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reg-names = "control", "domain";
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domain-id = <17>;
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};
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clkrac23: clktac23 {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk13>;
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clock-output-names = "rac-23";
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reg = <0x0235006c 0xb00>, <0x02350048 0x400>;
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||||
reg-names = "control", "domain";
|
||||
domain-id = <18>;
|
||||
};
|
||||
|
||||
clkfftc0: clkfftc0 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk13>;
|
||||
clock-output-names = "fftc-0";
|
||||
reg = <0x02350070 0xb00>, <0x0235004c 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <19>;
|
||||
};
|
||||
|
||||
clkfftc1: clkfftc1 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk13>;
|
||||
clock-output-names = "fftc-1";
|
||||
reg = <0x02350074 0xb00>, <0x023504c0 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <19>;
|
||||
};
|
||||
|
||||
clkfftc2: clkfftc2 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk13>;
|
||||
clock-output-names = "fftc-2";
|
||||
reg = <0x02350078 0xb00>, <0x02350050 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <20>;
|
||||
};
|
||||
|
||||
clkfftc3: clkfftc3 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk13>;
|
||||
clock-output-names = "fftc-3";
|
||||
reg = <0x0235007c 0xb00>, <0x02350050 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <20>;
|
||||
};
|
||||
|
||||
clkfftc4: clkfftc4 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk13>;
|
||||
clock-output-names = "fftc-4";
|
||||
reg = <0x02350080 0xb00>, <0x02350050 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <20>;
|
||||
};
|
||||
|
||||
clkfftc5: clkfftc5 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk13>;
|
||||
clock-output-names = "fftc-5";
|
||||
reg = <0x02350084 0xb00>, <0x02350050 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <20>;
|
||||
};
|
||||
|
||||
clkaif: clkaif {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk13>;
|
||||
clock-output-names = "aif";
|
||||
reg = <0x02350088 0xb00>, <0x02350054 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <21>;
|
||||
};
|
||||
|
||||
clktcp3d0: clktcp3d0 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk13>;
|
||||
clock-output-names = "tcp3d-0";
|
||||
reg = <0x0235008c 0xb00>, <0x02350058 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <22>;
|
||||
};
|
||||
|
||||
clktcp3d1: clktcp3d1 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk13>;
|
||||
clock-output-names = "tcp3d-1";
|
||||
reg = <0x02350090 0xb00>, <0x02350058 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <22>;
|
||||
};
|
||||
|
||||
clktcp3d2: clktcp3d2 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk13>;
|
||||
clock-output-names = "tcp3d-2";
|
||||
reg = <0x02350094 0xb00>, <0x0235005c 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <23>;
|
||||
};
|
||||
|
||||
clktcp3d3: clktcp3d3 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk13>;
|
||||
clock-output-names = "tcp3d-3";
|
||||
reg = <0x02350098 0xb00>, <0x0235005c 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <23>;
|
||||
};
|
||||
|
||||
clkvcp0: clkvcp0 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk13>;
|
||||
clock-output-names = "vcp-0";
|
||||
reg = <0x0235009c 0xb00>, <0x02350060 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <24>;
|
||||
};
|
||||
|
||||
clkvcp1: clkvcp1 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk13>;
|
||||
clock-output-names = "vcp-1";
|
||||
reg = <0x023500a0 0xb00>, <0x02350060 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <24>;
|
||||
};
|
||||
|
||||
clkvcp2: clkvcp2 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk13>;
|
||||
clock-output-names = "vcp-2";
|
||||
reg = <0x023500a4 0xb00>, <0x02350060 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <24>;
|
||||
};
|
||||
|
||||
clkvcp3: clkvcp3 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk13>;
|
||||
clock-output-names = "vcp-3";
|
||||
reg = <0x0235000a8 0xb00>, <0x02350060 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <24>;
|
||||
};
|
||||
|
||||
clkvcp4: clkvcp4 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk13>;
|
||||
clock-output-names = "vcp-4";
|
||||
reg = <0x023500ac 0xb00>, <0x02350064 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <25>;
|
||||
};
|
||||
|
||||
clkvcp5: clkvcp5 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk13>;
|
||||
clock-output-names = "vcp-5";
|
||||
reg = <0x023500b0 0xb00>, <0x02350064 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <25>;
|
||||
};
|
||||
|
||||
clkvcp6: clkvcp6 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk13>;
|
||||
clock-output-names = "vcp-6";
|
||||
reg = <0x023500b4 0xb00>, <0x02350064 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <25>;
|
||||
};
|
||||
|
||||
clkvcp7: clkvcp7 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk13>;
|
||||
clock-output-names = "vcp-7";
|
||||
reg = <0x023500b8 0xb00>, <0x02350064 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <25>;
|
||||
};
|
||||
|
||||
clkbcp: clkbcp {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk13>;
|
||||
clock-output-names = "bcp";
|
||||
reg = <0x023500bc 0xb00>, <0x02350068 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <26>;
|
||||
};
|
||||
|
||||
clkdxb: clkdxb {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk13>;
|
||||
clock-output-names = "dxb";
|
||||
reg = <0x023500c0 0xb00>, <0x0235006c 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <27>;
|
||||
};
|
||||
|
||||
clkhyperlink1: clkhyperlink1 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk12>;
|
||||
clock-output-names = "hyperlink-1";
|
||||
reg = <0x023500c4 0xb00>, <0x02350070 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <28>;
|
||||
};
|
||||
|
||||
clkxge: clkxge {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&chipclk13>;
|
||||
clock-output-names = "xge";
|
||||
reg = <0x023500c8 0xb00>, <0x02350074 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <29>;
|
||||
};
|
||||
|
||||
clkwdtimer0: clkwdtimer0 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&clkmodrst0>;
|
||||
clock-output-names = "timer0";
|
||||
reg = <0x02350000 0xb00>, <0x02350000 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <0>;
|
||||
};
|
||||
|
||||
clkwdtimer1: clkwdtimer1 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&clkmodrst0>;
|
||||
clock-output-names = "timer1";
|
||||
reg = <0x02350000 0xb00>, <0x02350000 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <0>;
|
||||
};
|
||||
|
||||
clkwdtimer2: clkwdtimer2 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&clkmodrst0>;
|
||||
clock-output-names = "timer2";
|
||||
reg = <0x02350000 0xb00>, <0x02350000 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <0>;
|
||||
};
|
||||
|
||||
clkwdtimer3: clkwdtimer3 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&clkmodrst0>;
|
||||
clock-output-names = "timer3";
|
||||
reg = <0x02350000 0xb00>, <0x02350000 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <0>;
|
||||
};
|
||||
|
||||
clkuart0: clkuart0 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&clkmodrst0>;
|
||||
clock-output-names = "uart0";
|
||||
reg = <0x02350000 0xb00>, <0x02350000 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <0>;
|
||||
};
|
||||
|
||||
clkuart1: clkuart1 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&clkmodrst0>;
|
||||
clock-output-names = "uart1";
|
||||
reg = <0x02350000 0xb00>, <0x02350000 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <0>;
|
||||
};
|
||||
|
||||
clkaemif: clkaemif {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&clkaemifspi>;
|
||||
clock-output-names = "aemif";
|
||||
reg = <0x02350000 0xb00>, <0x02350000 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <0>;
|
||||
};
|
||||
|
||||
clkusim: clkusim {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&clkmodrst0>;
|
||||
clock-output-names = "usim";
|
||||
reg = <0x02350000 0xb00>, <0x02350000 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <0>;
|
||||
};
|
||||
|
||||
clki2c: clki2c {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&clkmodrst0>;
|
||||
clock-output-names = "i2c";
|
||||
reg = <0x02350000 0xb00>, <0x02350000 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <0>;
|
||||
};
|
||||
|
||||
clkspi: clkspi {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&clkaemifspi>;
|
||||
clock-output-names = "spi";
|
||||
reg = <0x02350000 0xb00>, <0x02350000 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <0>;
|
||||
};
|
||||
|
||||
clkgpio: clkgpio {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&clkmodrst0>;
|
||||
clock-output-names = "gpio";
|
||||
reg = <0x02350000 0xb00>, <0x02350000 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <0>;
|
||||
};
|
||||
|
||||
clkkeymgr: clkkeymgr {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,keystone,psc-clock";
|
||||
clocks = <&clkmodrst0>;
|
||||
clock-output-names = "keymgr";
|
||||
reg = <0x02350000 0xb00>, <0x02350000 0x400>;
|
||||
reg-names = "control", "domain";
|
||||
domain-id = <0>;
|
||||
};
|
||||
};
|
||||
|
|
@ -100,6 +100,8 @@ rstctrl: reset-controller {
|
|||
reg = <0x023100e8 4>; /* pll reset control reg */
|
||||
};
|
||||
|
||||
/include/ "keystone-clocks.dtsi"
|
||||
|
||||
uart0: serial@02530c00 {
|
||||
compatible = "ns16550a";
|
||||
current-speed = <115200>;
|
||||
|
|
|
|||
Loading…
Reference in New Issue