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drm/amdgpu: add initial support for sdma v5.0 (v6) 

SDMA (System DMA) is a general purpose DMA engine usable
by UMDs for transfers or the kernel for paging or GPUVM
updates.

v1: support basic funcitonalites includes rb, ib, vm,
    copy buffer and trap irq
v2: convert to use new get_vm_pde in emit_vm_flush
v3: retire amdgpu_ttm_set_active_vram_size from sdma v5
v4: retire the redundant hdp_invalidate implementation
v5: squash in updates
v6: some golden regs moved to vbios

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Hawking Zhang 2019-03-31 22:13:57 +08:00 committed by Alex Deucher
parent be9250fb96
commit fef6e24c8b
3 changed files with 1732 additions and 1 deletions
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3
drivers/gpu/drm/amd/amdgpu/Makefile
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@ -117,7 +117,8 @@ amdgpu-y += \
amdgpu_sdma.o \
sdma_v2_4.o \
sdma_v3_0.o \
sdma_v4_0.o
sdma_v4_0.o \
sdma_v5_0.o
# add UVD block
amdgpu-y += \

1685
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c Normal file
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File diff suppressed because it is too large Load Diff

45
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.h Normal file
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@ -0,0 +1,45 @@
/*
* Copyright 2019 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef __SDMA_V5_0_H__
#define __SDMA_V5_0_H__
enum sdma_v5_0_utcl2_cache_read_policy {
CACHE_READ_POLICY_L2__LRU = 0x00000000,
CACHE_READ_POLICY_L2__STREAM = 0x00000001,
CACHE_READ_POLICY_L2__NOA = 0x00000002,
CACHE_READ_POLICY_L2__DEFAULT = CACHE_READ_POLICY_L2__NOA,
};
enum sdma_v5_0_utcl2_cache_write_policy {
CACHE_WRITE_POLICY_L2__LRU = 0x00000000,
CACHE_WRITE_POLICY_L2__STREAM = 0x00000001,
CACHE_WRITE_POLICY_L2__NOA = 0x00000002,
CACHE_WRITE_POLICY_L2__BYPASS = 0x00000003,
CACHE_WRITE_POLICY_L2__DEFAULT = CACHE_WRITE_POLICY_L2__BYPASS,
};
extern const struct amd_ip_funcs sdma_v5_0_ip_funcs;
extern const struct amdgpu_ip_block_version sdma_v5_0_ip_block;
#endif /* __SDMA_V5_0_H__ */