mirror of https://gitee.com/openkylin/linux.git
MMC core:
- mmc: core: Avoid hang when claiming host MMC host: - dw_mmc: Avoid hang when accessing registers - dw_mmc: Fix out-of-bounds access for slot's caps - dw_mmc-k3: Fix out-of-bounds access through DT alias - sdhci-pci: Fix S0i3 for Intel BYT-based controllers -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJamTk2AAoJEP4mhCVzWIwp108P/RcicjtOpcvTKMYnt7l6hAQ6 1Qr4tjAtj75FSVZooEKo1B13GTJOqgGh3O5x1nEcCGI2iA8ZV2XclN1QZhJeVJcF 5B1/hAXMjRaUkXzUrD9pOi+m+s3IBK82hJ40ac4JHYUpRT7fRLkB1PdU0gV3V9yZ Uy967pL9spHMbgDDbGut2gnBt9MyTysRfvCnEUKPKvPPqL6QaOGNEEIlXQedrSoi vUvvQjpAAUMd3kDWhnxNileLyHUFatpaJOYtxfTWiXNgP9LHv1o1X2QbbagnXaqY AybOjvWinbKoaX6+5G+ZZJMrW14D6gG9AZ/vi57U7ta8NiKRWmn0KjzTk0VVKsbo 5oKqjRT3Hu/SCqyqhVvo8dY+HSqhv0v1EtXVjfI1D8mxBt4v4fwnQrzNr9dBCouD Lb+l6hnZJq/xq3BDF+pZk0HiErGdXrXeq/pEKZXRL4EvX6TF0YZhc4VIyShDmRa5 5ZNgCndkUQ9Y/LYYnuwDvqkqlysR49FTCw5fGZDxtJzud6rupgF+/0QGwyGjGCZk 4Add0EcTKgWsSBcVwkyRJbDTmQB4tSVwAGMjAnlMJW3YX8chuzg2//DuW3DZLRao TH0PMPYTQeWclsz3ySBE/FU9IQhSQ44s0VUO+G+XxtfffaqOcMVs5D2ZKTjk8jWD lvdznNBylRrleG9K5zcA =pILk -----END PGP SIGNATURE----- Merge tag 'mmc-v4.16-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc Pull MMC fixes from Ulf Hansson: "MMC core: - mmc: core: Avoid hang when claiming host MMC host: - dw_mmc: Avoid hang when accessing registers - dw_mmc: Fix out-of-bounds access for slot's caps - dw_mmc-k3: Fix out-of-bounds access through DT alias - sdhci-pci: Fix S0i3 for Intel BYT-based controllers" * tag 'mmc-v4.16-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc: mmc: core: Avoid hanging to claim host for mmc via some nested calls mmc: dw_mmc: Avoid accessing registers in runtime suspended state mmc: dw_mmc: Fix out-of-bounds access for slot's caps mmc: dw_mmc: Factor out dw_mci_init_slot_caps mmc: dw_mmc-k3: Fix out-of-bounds access through DT alias mmc: sdhci-pci: Fix S0i3 for Intel BYT-based controllers
This commit is contained in:
commit
ff06b55ec4
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@ -848,7 +848,6 @@ int mmc_interrupt_hpi(struct mmc_card *card)
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return 1;
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}
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mmc_claim_host(card->host);
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err = mmc_send_status(card, &status);
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if (err) {
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pr_err("%s: Get card status fail\n", mmc_hostname(card->host));
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@ -890,7 +889,6 @@ int mmc_interrupt_hpi(struct mmc_card *card)
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} while (!err);
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out:
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mmc_release_host(card->host);
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return err;
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}
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@ -932,9 +930,7 @@ static int mmc_read_bkops_status(struct mmc_card *card)
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int err;
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u8 *ext_csd;
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mmc_claim_host(card->host);
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err = mmc_get_ext_csd(card, &ext_csd);
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mmc_release_host(card->host);
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if (err)
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return err;
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@ -487,6 +487,7 @@ static unsigned long exynos_dwmmc_caps[4] = {
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static const struct dw_mci_drv_data exynos_drv_data = {
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.caps = exynos_dwmmc_caps,
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.num_caps = ARRAY_SIZE(exynos_dwmmc_caps),
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.init = dw_mci_exynos_priv_init,
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.set_ios = dw_mci_exynos_set_ios,
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.parse_dt = dw_mci_exynos_parse_dt,
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@ -135,6 +135,9 @@ static int dw_mci_hi6220_parse_dt(struct dw_mci *host)
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if (priv->ctrl_id < 0)
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priv->ctrl_id = 0;
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if (priv->ctrl_id >= TIMING_MODE)
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return -EINVAL;
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host->priv = priv;
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return 0;
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}
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@ -207,6 +210,7 @@ static int dw_mci_hi6220_execute_tuning(struct dw_mci_slot *slot, u32 opcode)
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static const struct dw_mci_drv_data hi6220_data = {
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.caps = dw_mci_hi6220_caps,
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.num_caps = ARRAY_SIZE(dw_mci_hi6220_caps),
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.switch_voltage = dw_mci_hi6220_switch_voltage,
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.set_ios = dw_mci_hi6220_set_ios,
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.parse_dt = dw_mci_hi6220_parse_dt,
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@ -319,6 +319,7 @@ static const struct dw_mci_drv_data rk2928_drv_data = {
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static const struct dw_mci_drv_data rk3288_drv_data = {
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.caps = dw_mci_rk3288_dwmmc_caps,
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.num_caps = ARRAY_SIZE(dw_mci_rk3288_dwmmc_caps),
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.set_ios = dw_mci_rk3288_set_ios,
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.execute_tuning = dw_mci_rk3288_execute_tuning,
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.parse_dt = dw_mci_rk3288_parse_dt,
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@ -195,6 +195,7 @@ static unsigned long zx_dwmmc_caps[3] = {
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static const struct dw_mci_drv_data zx_drv_data = {
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.caps = zx_dwmmc_caps,
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.num_caps = ARRAY_SIZE(zx_dwmmc_caps),
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.execute_tuning = dw_mci_zx_execute_tuning,
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.prepare_hs400_tuning = dw_mci_zx_prepare_hs400_tuning,
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.parse_dt = dw_mci_zx_parse_dt,
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@ -165,6 +165,8 @@ static int dw_mci_regs_show(struct seq_file *s, void *v)
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{
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struct dw_mci *host = s->private;
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pm_runtime_get_sync(host->dev);
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seq_printf(s, "STATUS:\t0x%08x\n", mci_readl(host, STATUS));
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seq_printf(s, "RINTSTS:\t0x%08x\n", mci_readl(host, RINTSTS));
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seq_printf(s, "CMD:\t0x%08x\n", mci_readl(host, CMD));
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@ -172,6 +174,8 @@ static int dw_mci_regs_show(struct seq_file *s, void *v)
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seq_printf(s, "INTMASK:\t0x%08x\n", mci_readl(host, INTMASK));
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seq_printf(s, "CLKENA:\t0x%08x\n", mci_readl(host, CLKENA));
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pm_runtime_put_autosuspend(host->dev);
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return 0;
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}
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@ -2778,12 +2782,57 @@ static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
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return IRQ_HANDLED;
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}
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static int dw_mci_init_slot_caps(struct dw_mci_slot *slot)
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{
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struct dw_mci *host = slot->host;
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const struct dw_mci_drv_data *drv_data = host->drv_data;
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struct mmc_host *mmc = slot->mmc;
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int ctrl_id;
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if (host->pdata->caps)
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mmc->caps = host->pdata->caps;
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/*
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* Support MMC_CAP_ERASE by default.
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* It needs to use trim/discard/erase commands.
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*/
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mmc->caps |= MMC_CAP_ERASE;
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if (host->pdata->pm_caps)
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mmc->pm_caps = host->pdata->pm_caps;
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if (host->dev->of_node) {
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ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
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if (ctrl_id < 0)
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ctrl_id = 0;
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} else {
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ctrl_id = to_platform_device(host->dev)->id;
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}
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if (drv_data && drv_data->caps) {
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if (ctrl_id >= drv_data->num_caps) {
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dev_err(host->dev, "invalid controller id %d\n",
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ctrl_id);
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return -EINVAL;
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}
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mmc->caps |= drv_data->caps[ctrl_id];
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}
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if (host->pdata->caps2)
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mmc->caps2 = host->pdata->caps2;
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/* Process SDIO IRQs through the sdio_irq_work. */
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if (mmc->caps & MMC_CAP_SDIO_IRQ)
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mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
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return 0;
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}
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static int dw_mci_init_slot(struct dw_mci *host)
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{
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struct mmc_host *mmc;
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struct dw_mci_slot *slot;
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const struct dw_mci_drv_data *drv_data = host->drv_data;
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int ctrl_id, ret;
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int ret;
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u32 freq[2];
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mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
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@ -2817,38 +2866,13 @@ static int dw_mci_init_slot(struct dw_mci *host)
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if (!mmc->ocr_avail)
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mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
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if (host->pdata->caps)
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mmc->caps = host->pdata->caps;
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/*
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* Support MMC_CAP_ERASE by default.
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* It needs to use trim/discard/erase commands.
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*/
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mmc->caps |= MMC_CAP_ERASE;
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if (host->pdata->pm_caps)
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mmc->pm_caps = host->pdata->pm_caps;
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if (host->dev->of_node) {
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ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
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if (ctrl_id < 0)
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ctrl_id = 0;
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} else {
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ctrl_id = to_platform_device(host->dev)->id;
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}
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if (drv_data && drv_data->caps)
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mmc->caps |= drv_data->caps[ctrl_id];
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if (host->pdata->caps2)
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mmc->caps2 = host->pdata->caps2;
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ret = mmc_of_parse(mmc);
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if (ret)
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goto err_host_allocated;
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/* Process SDIO IRQs through the sdio_irq_work. */
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if (mmc->caps & MMC_CAP_SDIO_IRQ)
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mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
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ret = dw_mci_init_slot_caps(slot);
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if (ret)
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goto err_host_allocated;
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/* Useful defaults if platform data is unset. */
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if (host->use_dma == TRANS_MODE_IDMAC) {
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@ -543,6 +543,7 @@ struct dw_mci_slot {
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/**
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* dw_mci driver data - dw-mshc implementation specific driver data.
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* @caps: mmc subsystem specified capabilities of the controller(s).
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* @num_caps: number of capabilities specified by @caps.
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* @init: early implementation specific initialization.
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* @set_ios: handle bus specific extensions.
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* @parse_dt: parse implementation specific device tree properties.
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*/
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struct dw_mci_drv_data {
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unsigned long *caps;
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u32 num_caps;
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int (*init)(struct dw_mci *host);
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void (*set_ios)(struct dw_mci *host, struct mmc_ios *ios);
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int (*parse_dt)(struct dw_mci *host);
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@ -654,9 +654,36 @@ static void byt_read_dsm(struct sdhci_pci_slot *slot)
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slot->chip->rpm_retune = intel_host->d3_retune;
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}
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static int intel_execute_tuning(struct mmc_host *mmc, u32 opcode)
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{
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int err = sdhci_execute_tuning(mmc, opcode);
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struct sdhci_host *host = mmc_priv(mmc);
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if (err)
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return err;
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/*
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* Tuning can leave the IP in an active state (Buffer Read Enable bit
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* set) which prevents the entry to low power states (i.e. S0i3). Data
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* reset will clear it.
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*/
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sdhci_reset(host, SDHCI_RESET_DATA);
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return 0;
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}
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static void byt_probe_slot(struct sdhci_pci_slot *slot)
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{
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struct mmc_host_ops *ops = &slot->host->mmc_host_ops;
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byt_read_dsm(slot);
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ops->execute_tuning = intel_execute_tuning;
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}
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static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot)
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{
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byt_read_dsm(slot);
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byt_probe_slot(slot);
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slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
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MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR |
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MMC_CAP_CMD_DURING_TFR |
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{
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int err;
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byt_read_dsm(slot);
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byt_probe_slot(slot);
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err = ni_set_max_freq(slot);
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if (err)
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@ -792,7 +819,7 @@ static int ni_byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
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static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
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{
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byt_read_dsm(slot);
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byt_probe_slot(slot);
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slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE |
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MMC_CAP_WAIT_WHILE_BUSY;
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return 0;
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@ -800,7 +827,7 @@ static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
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static int byt_sd_probe_slot(struct sdhci_pci_slot *slot)
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{
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byt_read_dsm(slot);
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byt_probe_slot(slot);
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slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY |
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MMC_CAP_AGGRESSIVE_PM | MMC_CAP_CD_WAKE;
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slot->cd_idx = 0;
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