mirror of https://gitee.com/openkylin/linux.git
Renesas ARM Based SoC Marzen Board Removal for v4.3
* Remove legacy r8a7779 SoC code * Remove legacy marzen board code -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJVvwN/AAoJENfPZGlqN0++xRUP/1lVK2q2ixR2B/7jqPyvcrai 6RwXT99cwGSpUe7X7AcpWRW39EhRmt89ZPlQvkLF/Ylx9+XUBG3lsyIoaa40YW6x mNvbiKTJCFILh7K4YshibFtJPzj7sL+Vhy8xV6zVIBn5oA9rSBfEteTUt5JWik0b 2QZYZix8STU52k/djQ4vUbAwJfFNwmO4PDqY9B/XXE5a9ETUeEPecBB94xaJCyv+ ULFmPEHxfvdUug2tLJUTazdtDgQlxRczZ7vYMKpmUeQTPTvx/2L3scz36JpjTFx9 +U1KSPUzUKwonhS9/TEAeqbU1hDkOvIx7d9lJgd2zxnMrwCyTuJuvmaFV8dZlftu 8v5cTbdr8InLVdqDM4GzjrL5RhPl1F3MYtfUdT50duzcRTiwyOkKCbjQakV2rgKZ aQp4RdDxl1DBlqxyYW16o9Q5figecfqsxzNvAmveM+GOA19a2h9hLNTotZUvDGCC AXFrdXMCwzxpIy/LeWcIDs5ycHE0hrD1y68vH4vJp3pWr+dJ0p+QUgjtK5poXvLe 9RJnYtqJ0cXaYZj0DR64X3TUB2VpCbnK2pNv1/O1TJysiRUGlffRohaGv/UC5am2 y/kRYOX3qay0a60wWkGQzm/cMB4Zg8fa0ktXj5W/PIhGBLYXTPIQHkSfdFjpkyR6 WVXodsZdANGIlwQSCeLa =VPyl -----END PGP SIGNATURE----- Merge tag 'renesas-marzen-board-removal-for-v4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/cleanup Renesas ARM Based SoC Marzen Board Removal for v4.3 * Remove legacy r8a7779 SoC code * Remove legacy marzen board code * tag 'renesas-marzen-board-removal-for-v4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: r8a7779: Remove legacy SoC code ARM: shmobile: marzen: Remove legacy board code ARM: shmobile: r8a7779: Cleanup header file ARM: shmobile: marzen-reference: Remove C board code ARM: shmobile: r8a7779: Generic SMP ops ARM: shmobile: r8a7779: Generic CCF and timer support Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
ff20775d18
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@ -503,7 +503,8 @@ dtb-$(CONFIG_ARCH_S5PV210) += \
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dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += \
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r8a7778-bockw.dtb \
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r8a7778-bockw-reference.dtb \
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r8a7779-marzen.dtb
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r8a7779-marzen.dtb \
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sh73a0-kzm9g.dtb
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dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \
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emev2-kzm9d.dtb \
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r7s72100-genmai.dtb \
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@ -89,13 +89,6 @@ config ARCH_SH73A0
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select ARCH_RMOBILE
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select RENESAS_INTC_IRQPIN
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comment "Renesas ARM SoCs Board Type"
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config MACH_MARZEN
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bool "MARZEN board"
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depends on ARCH_R8A7779
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select REGULATOR_FIXED_VOLTAGE if REGULATOR
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comment "Renesas ARM SoCs System Configuration"
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endif
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@ -139,13 +132,6 @@ config MACH_BOCKW_REFERENCE
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This is intended to aid developers
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config MACH_MARZEN
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bool "MARZEN board"
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depends on ARCH_R8A7779
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select ARCH_REQUIRE_GPIOLIB
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select REGULATOR_FIXED_VOLTAGE if REGULATOR
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select USE_OF
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comment "Renesas ARM SoCs System Configuration"
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config CPU_HAS_INTEVT
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@ -21,7 +21,6 @@ obj-$(CONFIG_ARCH_R7S72100) += setup-r7s72100.o
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ifndef CONFIG_COMMON_CLK
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obj-y += clock.o
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obj-$(CONFIG_ARCH_R8A7778) += clock-r8a7778.o
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obj-$(CONFIG_ARCH_R8A7779) += clock-r8a7779.o
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endif
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# CPU reset vector handling objects
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@ -49,13 +48,9 @@ obj-$(CONFIG_PM_RMOBILE) += pm-rmobile.o
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obj-$(CONFIG_ARCH_RCAR_GEN2) += pm-rcar-gen2.o
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# Board objects
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ifdef CONFIG_ARCH_SHMOBILE_MULTI
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obj-$(CONFIG_MACH_MARZEN) += board-marzen-reference.o
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else
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ifndef CONFIG_ARCH_SHMOBILE_MULTI
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obj-$(CONFIG_MACH_BOCKW) += board-bockw.o
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obj-$(CONFIG_MACH_BOCKW_REFERENCE) += board-bockw-reference.o
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obj-$(CONFIG_MACH_MARZEN) += board-marzen.o
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endif
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# Framework support
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obj-$(CONFIG_SMP) += $(smp-y)
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@ -2,7 +2,6 @@
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loadaddr-y :=
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loadaddr-$(CONFIG_MACH_BOCKW) += 0x60008000
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loadaddr-$(CONFIG_MACH_BOCKW_REFERENCE) += 0x60008000
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loadaddr-$(CONFIG_MACH_MARZEN) += 0x60008000
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__ZRELADDR := $(sort $(loadaddr-y))
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zreladdr-y += $(__ZRELADDR)
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@ -1,56 +0,0 @@
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/*
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* marzen board support - Reference DT implementation
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*
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* Copyright (C) 2011 Renesas Solutions Corp.
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* Copyright (C) 2011 Magnus Damm
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* Copyright (C) 2013 Simon Horman
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk/shmobile.h>
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#include <linux/clocksource.h>
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#include <linux/of_platform.h>
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#include <asm/irq.h>
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#include <asm/mach/arch.h>
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#include "common.h"
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#include "irqs.h"
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#include "r8a7779.h"
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static void __init marzen_init_timer(void)
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{
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r8a7779_clocks_init(r8a7779_read_mode_pins());
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clocksource_of_init();
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}
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static void __init marzen_init(void)
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{
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of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
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r8a7779_init_irq_extpin_dt(1); /* IRQ1 as individual interrupt */
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}
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static const char *const marzen_boards_compat_dt[] __initconst = {
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"renesas,marzen",
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"renesas,marzen-reference",
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NULL,
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};
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DT_MACHINE_START(MARZEN, "marzen")
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.smp = smp_ops(r8a7779_smp_ops),
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.map_io = r8a7779_map_io,
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.init_early = shmobile_init_delay,
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.init_time = marzen_init_timer,
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.init_irq = r8a7779_init_irq_dt,
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.init_machine = marzen_init,
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.init_late = shmobile_init_late,
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.dt_compat = marzen_boards_compat_dt,
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MACHINE_END
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@ -1,347 +0,0 @@
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/*
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* marzen board support
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*
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* Copyright (C) 2011, 2013 Renesas Solutions Corp.
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* Copyright (C) 2011 Magnus Damm
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* Copyright (C) 2013 Cogent Embedded, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/platform_device.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/leds.h>
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#include <linux/dma-mapping.h>
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#include <linux/pinctrl/machine.h>
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#include <linux/platform_data/camera-rcar.h>
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#include <linux/platform_data/gpio-rcar.h>
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#include <linux/platform_data/usb-rcar-phy.h>
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#include <linux/regulator/fixed.h>
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#include <linux/regulator/machine.h>
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#include <linux/smsc911x.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/sh_hspi.h>
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#include <linux/mmc/host.h>
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#include <linux/mmc/sh_mobile_sdhi.h>
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#include <linux/mfd/tmio.h>
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#include <media/soc_camera.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#include <asm/traps.h>
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#include "common.h"
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#include "irqs.h"
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#include "r8a7779.h"
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/* Fixed 3.3V regulator to be used by SDHI0 */
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static struct regulator_consumer_supply fixed3v3_power_consumers[] = {
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REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
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REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
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};
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/* Dummy supplies, where voltage doesn't matter */
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static struct regulator_consumer_supply dummy_supplies[] = {
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REGULATOR_SUPPLY("vddvario", "smsc911x"),
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REGULATOR_SUPPLY("vdd33a", "smsc911x"),
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};
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/* USB PHY */
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static struct resource usb_phy_resources[] = {
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[0] = {
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.start = 0xffe70800,
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.end = 0xffe70900 - 1,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct rcar_phy_platform_data usb_phy_platform_data;
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static struct platform_device usb_phy = {
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.name = "rcar_usb_phy",
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.id = -1,
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.dev = {
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.platform_data = &usb_phy_platform_data,
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},
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.resource = usb_phy_resources,
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.num_resources = ARRAY_SIZE(usb_phy_resources),
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};
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/* SMSC LAN89218 */
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static struct resource smsc911x_resources[] = {
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[0] = {
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.start = 0x18000000, /* ExCS0 */
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.end = 0x180000ff, /* A1->A7 */
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = irq_pin(1), /* IRQ 1 */
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct smsc911x_platform_config smsc911x_platdata = {
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.flags = SMSC911X_USE_32BIT, /* 32-bit SW on 16-bit HW bus */
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.phy_interface = PHY_INTERFACE_MODE_MII,
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.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
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.irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
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};
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static struct platform_device eth_device = {
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.name = "smsc911x",
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.id = -1,
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.dev = {
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.platform_data = &smsc911x_platdata,
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},
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.resource = smsc911x_resources,
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.num_resources = ARRAY_SIZE(smsc911x_resources),
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};
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static struct resource sdhi0_resources[] = {
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[0] = {
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.name = "sdhi0",
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.start = 0xffe4c000,
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.end = 0xffe4c0ff,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = gic_iid(0x88),
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct tmio_mmc_data sdhi0_platform_data = {
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.chan_priv_tx = (void *)HPBDMA_SLAVE_SDHI0_TX,
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.chan_priv_rx = (void *)HPBDMA_SLAVE_SDHI0_RX,
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.flags = TMIO_MMC_WRPROTECT_DISABLE | TMIO_MMC_HAS_IDLE_WAIT,
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.capabilities = MMC_CAP_SD_HIGHSPEED,
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};
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static struct platform_device sdhi0_device = {
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.name = "sh_mobile_sdhi",
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.num_resources = ARRAY_SIZE(sdhi0_resources),
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.resource = sdhi0_resources,
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.id = 0,
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.dev = {
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.platform_data = &sdhi0_platform_data,
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}
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};
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/* Thermal */
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static struct resource thermal_resources[] = {
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[0] = {
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.start = 0xFFC48000,
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.end = 0xFFC48038 - 1,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct platform_device thermal_device = {
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.name = "rcar_thermal",
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.resource = thermal_resources,
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.num_resources = ARRAY_SIZE(thermal_resources),
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};
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/* HSPI */
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static struct resource hspi_resources[] = {
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[0] = {
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.start = 0xFFFC7000,
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.end = 0xFFFC7018 - 1,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct platform_device hspi_device = {
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.name = "sh-hspi",
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.id = 0,
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.resource = hspi_resources,
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.num_resources = ARRAY_SIZE(hspi_resources),
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};
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/* LEDS */
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static struct gpio_led marzen_leds[] = {
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{
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.name = "led2",
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.gpio = RCAR_GP_PIN(4, 29),
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.default_state = LEDS_GPIO_DEFSTATE_ON,
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}, {
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.name = "led3",
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.gpio = RCAR_GP_PIN(4, 30),
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.default_state = LEDS_GPIO_DEFSTATE_ON,
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}, {
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.name = "led4",
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.gpio = RCAR_GP_PIN(4, 31),
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.default_state = LEDS_GPIO_DEFSTATE_ON,
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},
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};
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static struct gpio_led_platform_data marzen_leds_pdata = {
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.leds = marzen_leds,
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.num_leds = ARRAY_SIZE(marzen_leds),
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};
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static struct platform_device leds_device = {
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.name = "leds-gpio",
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.id = 0,
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.dev = {
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.platform_data = &marzen_leds_pdata,
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},
|
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};
|
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|
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/* VIN */
|
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static struct rcar_vin_platform_data vin_platform_data __initdata = {
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.flags = RCAR_VIN_BT656,
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};
|
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#define MARZEN_VIN(idx) \
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static struct resource vin##idx##_resources[] __initdata = { \
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DEFINE_RES_MEM(0xffc50000 + 0x1000 * (idx), 0x1000), \
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DEFINE_RES_IRQ(gic_iid(0x5f + (idx))), \
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}; \
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\
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static struct platform_device_info vin##idx##_info __initdata = { \
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.name = "r8a7779-vin", \
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.id = idx, \
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.res = vin##idx##_resources, \
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.num_res = ARRAY_SIZE(vin##idx##_resources), \
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.dma_mask = DMA_BIT_MASK(32), \
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.data = &vin_platform_data, \
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.size_data = sizeof(vin_platform_data), \
|
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}
|
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MARZEN_VIN(1);
|
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MARZEN_VIN(3);
|
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|
||||
#define MARZEN_CAMERA(idx) \
|
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static struct i2c_board_info camera##idx##_info = { \
|
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I2C_BOARD_INFO("adv7180", 0x20 + (idx)), \
|
||||
}; \
|
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\
|
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static struct soc_camera_link iclink##idx##_adv7180 = { \
|
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.bus_id = 1 + 2 * (idx), \
|
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.i2c_adapter_id = 0, \
|
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.board_info = &camera##idx##_info, \
|
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}; \
|
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\
|
||||
static struct platform_device camera##idx##_device = { \
|
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.name = "soc-camera-pdrv", \
|
||||
.id = idx, \
|
||||
.dev = { \
|
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.platform_data = &iclink##idx##_adv7180, \
|
||||
}, \
|
||||
};
|
||||
|
||||
MARZEN_CAMERA(0);
|
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MARZEN_CAMERA(1);
|
||||
|
||||
static struct platform_device *marzen_devices[] __initdata = {
|
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ð_device,
|
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&sdhi0_device,
|
||||
&thermal_device,
|
||||
&hspi_device,
|
||||
&leds_device,
|
||||
&usb_phy,
|
||||
&camera0_device,
|
||||
&camera1_device,
|
||||
};
|
||||
|
||||
static const struct pinctrl_map marzen_pinctrl_map[] = {
|
||||
/* DU (CN10: ARGB0, CN13: LVDS) */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7779", "pfc-r8a7779",
|
||||
"du0_rgb888", "du0"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7779", "pfc-r8a7779",
|
||||
"du0_sync_1", "du0"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7779", "pfc-r8a7779",
|
||||
"du0_clk_out_0", "du0"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7779", "pfc-r8a7779",
|
||||
"du1_rgb666", "du1"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7779", "pfc-r8a7779",
|
||||
"du1_sync_1", "du1"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("rcar-du-r8a7779", "pfc-r8a7779",
|
||||
"du1_clk_out", "du1"),
|
||||
/* HSPI0 */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh-hspi.0", "pfc-r8a7779",
|
||||
"hspi0", "hspi0"),
|
||||
/* SCIF2 (CN18: DEBUG0) */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-r8a7779",
|
||||
"scif2_data_c", "scif2"),
|
||||
/* SCIF4 (CN19: DEBUG1) */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-r8a7779",
|
||||
"scif4_data", "scif4"),
|
||||
/* SDHI0 */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
|
||||
"sdhi0_data4", "sdhi0"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
|
||||
"sdhi0_ctrl", "sdhi0"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
|
||||
"sdhi0_cd", "sdhi0"),
|
||||
/* SMSC */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-r8a7779",
|
||||
"intc_irq1_b", "intc"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-r8a7779",
|
||||
"lbsc_ex_cs0", "lbsc"),
|
||||
/* USB0 */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform.0", "pfc-r8a7779",
|
||||
"usb0", "usb0"),
|
||||
/* USB1 */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform.0", "pfc-r8a7779",
|
||||
"usb1", "usb1"),
|
||||
/* USB2 */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform.1", "pfc-r8a7779",
|
||||
"usb2", "usb2"),
|
||||
/* VIN1 */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("r8a7779-vin.1", "pfc-r8a7779",
|
||||
"vin1_clk", "vin1"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("r8a7779-vin.1", "pfc-r8a7779",
|
||||
"vin1_data8", "vin1"),
|
||||
/* VIN3 */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("r8a7779-vin.3", "pfc-r8a7779",
|
||||
"vin3_clk", "vin3"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("r8a7779-vin.3", "pfc-r8a7779",
|
||||
"vin3_data8", "vin3"),
|
||||
};
|
||||
|
||||
static void __init marzen_init(void)
|
||||
{
|
||||
regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
|
||||
ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
|
||||
regulator_register_fixed(1, dummy_supplies,
|
||||
ARRAY_SIZE(dummy_supplies));
|
||||
|
||||
pinctrl_register_mappings(marzen_pinctrl_map,
|
||||
ARRAY_SIZE(marzen_pinctrl_map));
|
||||
r8a7779_pinmux_init();
|
||||
r8a7779_init_irq_extpin(1); /* IRQ1 as individual interrupt */
|
||||
|
||||
r8a7779_add_standard_devices();
|
||||
platform_device_register_full(&vin1_info);
|
||||
platform_device_register_full(&vin3_info);
|
||||
platform_add_devices(marzen_devices, ARRAY_SIZE(marzen_devices));
|
||||
}
|
||||
|
||||
static const char *const marzen_boards_compat_dt[] __initconst = {
|
||||
"renesas,marzen",
|
||||
NULL,
|
||||
};
|
||||
|
||||
DT_MACHINE_START(MARZEN, "marzen")
|
||||
.smp = smp_ops(r8a7779_smp_ops),
|
||||
.map_io = r8a7779_map_io,
|
||||
.init_early = r8a7779_add_early_devices,
|
||||
.init_irq = r8a7779_init_irq_dt,
|
||||
.init_machine = marzen_init,
|
||||
.init_late = r8a7779_init_late,
|
||||
.dt_compat = marzen_boards_compat_dt,
|
||||
.init_time = r8a7779_earlytimer_init,
|
||||
MACHINE_END
|
||||
|
|
@ -1,271 +0,0 @@
|
|||
/*
|
||||
* r8a7779 clock framework support
|
||||
*
|
||||
* Copyright (C) 2011 Renesas Solutions Corp.
|
||||
* Copyright (C) 2011 Magnus Damm
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/sh_clk.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/sh_timer.h>
|
||||
|
||||
#include "clock.h"
|
||||
#include "common.h"
|
||||
#include "r8a7779.h"
|
||||
|
||||
/*
|
||||
* MD1 = 1 MD1 = 0
|
||||
* (PLLA = 1500) (PLLA = 1600)
|
||||
* (MHz) (MHz)
|
||||
*------------------------------------------------+--------------------
|
||||
* clkz 1000 (2/3) 800 (1/2)
|
||||
* clkzs 250 (1/6) 200 (1/8)
|
||||
* clki 750 (1/2) 800 (1/2)
|
||||
* clks 250 (1/6) 200 (1/8)
|
||||
* clks1 125 (1/12) 100 (1/16)
|
||||
* clks3 187.5 (1/8) 200 (1/8)
|
||||
* clks4 93.7 (1/16) 100 (1/16)
|
||||
* clkp 62.5 (1/24) 50 (1/32)
|
||||
* clkg 62.5 (1/24) 66.6 (1/24)
|
||||
* clkb, CLKOUT
|
||||
* (MD2 = 0) 62.5 (1/24) 66.6 (1/24)
|
||||
* (MD2 = 1) 41.6 (1/36) 50 (1/32)
|
||||
*/
|
||||
|
||||
#define MD(nr) BIT(nr)
|
||||
|
||||
#define MSTPCR0 IOMEM(0xffc80030)
|
||||
#define MSTPCR1 IOMEM(0xffc80034)
|
||||
#define MSTPCR3 IOMEM(0xffc8003c)
|
||||
#define MSTPSR1 IOMEM(0xffc80044)
|
||||
|
||||
/* ioremap() through clock mapping mandatory to avoid
|
||||
* collision with ARM coherent DMA virtual memory range.
|
||||
*/
|
||||
|
||||
static struct clk_mapping cpg_mapping = {
|
||||
.phys = 0xffc80000,
|
||||
.len = 0x80,
|
||||
};
|
||||
|
||||
/*
|
||||
* Default rate for the root input clock, reset this with clk_set_rate()
|
||||
* from the platform code.
|
||||
*/
|
||||
static struct clk plla_clk = {
|
||||
/* .rate will be updated on r8a7779_clock_init() */
|
||||
.mapping = &cpg_mapping,
|
||||
};
|
||||
|
||||
/*
|
||||
* clock ratio of these clock will be updated
|
||||
* on r8a7779_clock_init()
|
||||
*/
|
||||
SH_FIXED_RATIO_CLK_SET(clkz_clk, plla_clk, 1, 1);
|
||||
SH_FIXED_RATIO_CLK_SET(clkzs_clk, plla_clk, 1, 1);
|
||||
SH_FIXED_RATIO_CLK_SET(clki_clk, plla_clk, 1, 1);
|
||||
SH_FIXED_RATIO_CLK_SET(clks_clk, plla_clk, 1, 1);
|
||||
SH_FIXED_RATIO_CLK_SET(clks1_clk, plla_clk, 1, 1);
|
||||
SH_FIXED_RATIO_CLK_SET(clks3_clk, plla_clk, 1, 1);
|
||||
SH_FIXED_RATIO_CLK_SET(clks4_clk, plla_clk, 1, 1);
|
||||
SH_FIXED_RATIO_CLK_SET(clkb_clk, plla_clk, 1, 1);
|
||||
SH_FIXED_RATIO_CLK_SET(clkout_clk, plla_clk, 1, 1);
|
||||
SH_FIXED_RATIO_CLK_SET(clkp_clk, plla_clk, 1, 1);
|
||||
SH_FIXED_RATIO_CLK_SET(clkg_clk, plla_clk, 1, 1);
|
||||
|
||||
static struct clk *main_clks[] = {
|
||||
&plla_clk,
|
||||
&clkz_clk,
|
||||
&clkzs_clk,
|
||||
&clki_clk,
|
||||
&clks_clk,
|
||||
&clks1_clk,
|
||||
&clks3_clk,
|
||||
&clks4_clk,
|
||||
&clkb_clk,
|
||||
&clkout_clk,
|
||||
&clkp_clk,
|
||||
&clkg_clk,
|
||||
};
|
||||
|
||||
enum { MSTP323, MSTP322, MSTP321, MSTP320,
|
||||
MSTP120,
|
||||
MSTP116, MSTP115, MSTP114,
|
||||
MSTP110, MSTP109, MSTP108,
|
||||
MSTP103, MSTP101, MSTP100,
|
||||
MSTP030,
|
||||
MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
|
||||
MSTP016, MSTP015, MSTP014,
|
||||
MSTP007,
|
||||
MSTP_NR };
|
||||
|
||||
static struct clk mstp_clks[MSTP_NR] = {
|
||||
[MSTP323] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 23, 0), /* SDHI0 */
|
||||
[MSTP322] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 22, 0), /* SDHI1 */
|
||||
[MSTP321] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 21, 0), /* SDHI2 */
|
||||
[MSTP320] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 20, 0), /* SDHI3 */
|
||||
[MSTP120] = SH_CLK_MSTP32_STS(&clks_clk, MSTPCR1, 20, MSTPSR1, 0), /* VIN3 */
|
||||
[MSTP116] = SH_CLK_MSTP32_STS(&clkp_clk, MSTPCR1, 16, MSTPSR1, 0), /* PCIe */
|
||||
[MSTP115] = SH_CLK_MSTP32_STS(&clkp_clk, MSTPCR1, 15, MSTPSR1, 0), /* SATA */
|
||||
[MSTP114] = SH_CLK_MSTP32_STS(&clkp_clk, MSTPCR1, 14, MSTPSR1, 0), /* Ether */
|
||||
[MSTP110] = SH_CLK_MSTP32_STS(&clks_clk, MSTPCR1, 10, MSTPSR1, 0), /* VIN0 */
|
||||
[MSTP109] = SH_CLK_MSTP32_STS(&clks_clk, MSTPCR1, 9, MSTPSR1, 0), /* VIN1 */
|
||||
[MSTP108] = SH_CLK_MSTP32_STS(&clks_clk, MSTPCR1, 8, MSTPSR1, 0), /* VIN2 */
|
||||
[MSTP103] = SH_CLK_MSTP32_STS(&clks_clk, MSTPCR1, 3, MSTPSR1, 0), /* DU */
|
||||
[MSTP101] = SH_CLK_MSTP32_STS(&clkp_clk, MSTPCR1, 1, MSTPSR1, 0), /* USB2 */
|
||||
[MSTP100] = SH_CLK_MSTP32_STS(&clkp_clk, MSTPCR1, 0, MSTPSR1, 0), /* USB0/1 */
|
||||
[MSTP030] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 30, 0), /* I2C0 */
|
||||
[MSTP029] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 29, 0), /* I2C1 */
|
||||
[MSTP028] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 28, 0), /* I2C2 */
|
||||
[MSTP027] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 27, 0), /* I2C3 */
|
||||
[MSTP026] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 26, 0), /* SCIF0 */
|
||||
[MSTP025] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 25, 0), /* SCIF1 */
|
||||
[MSTP024] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 24, 0), /* SCIF2 */
|
||||
[MSTP023] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 23, 0), /* SCIF3 */
|
||||
[MSTP022] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 22, 0), /* SCIF4 */
|
||||
[MSTP021] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 21, 0), /* SCIF5 */
|
||||
[MSTP016] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 16, 0), /* TMU0 */
|
||||
[MSTP015] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 15, 0), /* TMU1 */
|
||||
[MSTP014] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 14, 0), /* TMU2 */
|
||||
[MSTP007] = SH_CLK_MSTP32(&clks_clk, MSTPCR0, 7, 0), /* HSPI */
|
||||
};
|
||||
|
||||
static struct clk_lookup lookups[] = {
|
||||
/* main clocks */
|
||||
CLKDEV_CON_ID("plla_clk", &plla_clk),
|
||||
CLKDEV_CON_ID("clkz_clk", &clkz_clk),
|
||||
CLKDEV_CON_ID("clkzs_clk", &clkzs_clk),
|
||||
|
||||
/* DIV4 clocks */
|
||||
CLKDEV_CON_ID("shyway_clk", &clks_clk),
|
||||
CLKDEV_CON_ID("bus_clk", &clkout_clk),
|
||||
CLKDEV_CON_ID("shyway4_clk", &clks4_clk),
|
||||
CLKDEV_CON_ID("shyway3_clk", &clks3_clk),
|
||||
CLKDEV_CON_ID("shyway1_clk", &clks1_clk),
|
||||
CLKDEV_CON_ID("peripheral_clk", &clkp_clk),
|
||||
|
||||
/* MSTP32 clocks */
|
||||
CLKDEV_DEV_ID("r8a7779-vin.3", &mstp_clks[MSTP120]), /* VIN3 */
|
||||
CLKDEV_DEV_ID("rcar-pcie", &mstp_clks[MSTP116]), /* PCIe */
|
||||
CLKDEV_DEV_ID("sata_rcar", &mstp_clks[MSTP115]), /* SATA */
|
||||
CLKDEV_DEV_ID("fc600000.sata", &mstp_clks[MSTP115]), /* SATA w/DT */
|
||||
CLKDEV_DEV_ID("r8a777x-ether", &mstp_clks[MSTP114]), /* Ether */
|
||||
CLKDEV_DEV_ID("r8a7779-vin.0", &mstp_clks[MSTP110]), /* VIN0 */
|
||||
CLKDEV_DEV_ID("r8a7779-vin.1", &mstp_clks[MSTP109]), /* VIN1 */
|
||||
CLKDEV_DEV_ID("r8a7779-vin.2", &mstp_clks[MSTP108]), /* VIN2 */
|
||||
CLKDEV_DEV_ID("ehci-platform.1", &mstp_clks[MSTP101]), /* USB EHCI port2 */
|
||||
CLKDEV_DEV_ID("ohci-platform.1", &mstp_clks[MSTP101]), /* USB OHCI port2 */
|
||||
CLKDEV_DEV_ID("ehci-platform.0", &mstp_clks[MSTP100]), /* USB EHCI port0/1 */
|
||||
CLKDEV_DEV_ID("ohci-platform.0", &mstp_clks[MSTP100]), /* USB OHCI port0/1 */
|
||||
CLKDEV_ICK_ID("fck", "sh-tmu.0", &mstp_clks[MSTP016]), /* TMU0 */
|
||||
CLKDEV_DEV_ID("i2c-rcar.0", &mstp_clks[MSTP030]), /* I2C0 */
|
||||
CLKDEV_DEV_ID("ffc70000.i2c", &mstp_clks[MSTP030]), /* I2C0 */
|
||||
CLKDEV_DEV_ID("i2c-rcar.1", &mstp_clks[MSTP029]), /* I2C1 */
|
||||
CLKDEV_DEV_ID("ffc71000.i2c", &mstp_clks[MSTP029]), /* I2C1 */
|
||||
CLKDEV_DEV_ID("i2c-rcar.2", &mstp_clks[MSTP028]), /* I2C2 */
|
||||
CLKDEV_DEV_ID("ffc72000.i2c", &mstp_clks[MSTP028]), /* I2C2 */
|
||||
CLKDEV_DEV_ID("i2c-rcar.3", &mstp_clks[MSTP027]), /* I2C3 */
|
||||
CLKDEV_DEV_ID("ffc73000.i2c", &mstp_clks[MSTP027]), /* I2C3 */
|
||||
CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */
|
||||
CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */
|
||||
CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP024]), /* SCIF2 */
|
||||
CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP023]), /* SCIF3 */
|
||||
CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP022]), /* SCIF4 */
|
||||
CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP021]), /* SCIF6 */
|
||||
CLKDEV_DEV_ID("sh-hspi.0", &mstp_clks[MSTP007]), /* HSPI0 */
|
||||
CLKDEV_DEV_ID("fffc7000.spi", &mstp_clks[MSTP007]), /* HSPI0 */
|
||||
CLKDEV_DEV_ID("sh-hspi.1", &mstp_clks[MSTP007]), /* HSPI1 */
|
||||
CLKDEV_DEV_ID("fffc8000.spi", &mstp_clks[MSTP007]), /* HSPI1 */
|
||||
CLKDEV_DEV_ID("sh-hspi.2", &mstp_clks[MSTP007]), /* HSPI2 */
|
||||
CLKDEV_DEV_ID("fffc6000.spi", &mstp_clks[MSTP007]), /* HSPI2 */
|
||||
CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP323]), /* SDHI0 */
|
||||
CLKDEV_DEV_ID("ffe4c000.sd", &mstp_clks[MSTP323]), /* SDHI0 */
|
||||
CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */
|
||||
CLKDEV_DEV_ID("ffe4d000.sd", &mstp_clks[MSTP322]), /* SDHI1 */
|
||||
CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */
|
||||
CLKDEV_DEV_ID("ffe4e000.sd", &mstp_clks[MSTP321]), /* SDHI2 */
|
||||
CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP320]), /* SDHI3 */
|
||||
CLKDEV_DEV_ID("ffe4f000.sd", &mstp_clks[MSTP320]), /* SDHI3 */
|
||||
CLKDEV_DEV_ID("rcar-du-r8a7779", &mstp_clks[MSTP103]), /* DU */
|
||||
};
|
||||
|
||||
void __init r8a7779_clock_init(void)
|
||||
{
|
||||
u32 mode = r8a7779_read_mode_pins();
|
||||
int k, ret = 0;
|
||||
|
||||
if (mode & MD(1)) {
|
||||
plla_clk.rate = 1500000000;
|
||||
|
||||
SH_CLK_SET_RATIO(&clkz_clk_ratio, 2, 3);
|
||||
SH_CLK_SET_RATIO(&clkzs_clk_ratio, 1, 6);
|
||||
SH_CLK_SET_RATIO(&clki_clk_ratio, 1, 2);
|
||||
SH_CLK_SET_RATIO(&clks_clk_ratio, 1, 6);
|
||||
SH_CLK_SET_RATIO(&clks1_clk_ratio, 1, 12);
|
||||
SH_CLK_SET_RATIO(&clks3_clk_ratio, 1, 8);
|
||||
SH_CLK_SET_RATIO(&clks4_clk_ratio, 1, 16);
|
||||
SH_CLK_SET_RATIO(&clkp_clk_ratio, 1, 24);
|
||||
SH_CLK_SET_RATIO(&clkg_clk_ratio, 1, 24);
|
||||
if (mode & MD(2)) {
|
||||
SH_CLK_SET_RATIO(&clkb_clk_ratio, 1, 36);
|
||||
SH_CLK_SET_RATIO(&clkout_clk_ratio, 1, 36);
|
||||
} else {
|
||||
SH_CLK_SET_RATIO(&clkb_clk_ratio, 1, 24);
|
||||
SH_CLK_SET_RATIO(&clkout_clk_ratio, 1, 24);
|
||||
}
|
||||
} else {
|
||||
plla_clk.rate = 1600000000;
|
||||
|
||||
SH_CLK_SET_RATIO(&clkz_clk_ratio, 1, 2);
|
||||
SH_CLK_SET_RATIO(&clkzs_clk_ratio, 1, 8);
|
||||
SH_CLK_SET_RATIO(&clki_clk_ratio, 1, 2);
|
||||
SH_CLK_SET_RATIO(&clks_clk_ratio, 1, 8);
|
||||
SH_CLK_SET_RATIO(&clks1_clk_ratio, 1, 16);
|
||||
SH_CLK_SET_RATIO(&clks3_clk_ratio, 1, 8);
|
||||
SH_CLK_SET_RATIO(&clks4_clk_ratio, 1, 16);
|
||||
SH_CLK_SET_RATIO(&clkp_clk_ratio, 1, 32);
|
||||
SH_CLK_SET_RATIO(&clkg_clk_ratio, 1, 24);
|
||||
if (mode & MD(2)) {
|
||||
SH_CLK_SET_RATIO(&clkb_clk_ratio, 1, 32);
|
||||
SH_CLK_SET_RATIO(&clkout_clk_ratio, 1, 32);
|
||||
} else {
|
||||
SH_CLK_SET_RATIO(&clkb_clk_ratio, 1, 24);
|
||||
SH_CLK_SET_RATIO(&clkout_clk_ratio, 1, 24);
|
||||
}
|
||||
}
|
||||
|
||||
for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
|
||||
ret = clk_register(main_clks[k]);
|
||||
|
||||
if (!ret)
|
||||
ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
|
||||
|
||||
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
|
||||
|
||||
if (!ret)
|
||||
shmobile_clk_init();
|
||||
else
|
||||
panic("failed to setup r8a7779 clocks\n");
|
||||
}
|
||||
|
||||
/* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
|
||||
void __init __weak r8a7779_register_twd(void) { }
|
||||
|
||||
void __init r8a7779_earlytimer_init(void)
|
||||
{
|
||||
r8a7779_clock_init();
|
||||
r8a7779_register_twd();
|
||||
shmobile_earlytimer_init();
|
||||
}
|
||||
|
|
@ -3,26 +3,7 @@
|
|||
|
||||
#include <linux/sh_clk.h>
|
||||
|
||||
/* HPB-DMA slave IDs */
|
||||
enum {
|
||||
HPBDMA_SLAVE_DUMMY,
|
||||
HPBDMA_SLAVE_SDHI0_TX,
|
||||
HPBDMA_SLAVE_SDHI0_RX,
|
||||
};
|
||||
|
||||
extern void r8a7779_init_irq_extpin(int irlm);
|
||||
extern void r8a7779_init_irq_extpin_dt(int irlm);
|
||||
extern void r8a7779_init_irq_dt(void);
|
||||
extern void r8a7779_map_io(void);
|
||||
extern void r8a7779_earlytimer_init(void);
|
||||
extern void r8a7779_add_early_devices(void);
|
||||
extern void r8a7779_add_standard_devices(void);
|
||||
extern void r8a7779_init_late(void);
|
||||
extern u32 r8a7779_read_mode_pins(void);
|
||||
extern void r8a7779_clock_init(void);
|
||||
extern void r8a7779_pinmux_init(void);
|
||||
extern void r8a7779_pm_init(void);
|
||||
extern void r8a7779_register_twd(void);
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
extern void __init r8a7779_init_pm_domains(void);
|
||||
|
|
|
|||
|
|
@ -14,37 +14,17 @@
|
|||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/clk/shmobile.h>
|
||||
#include <linux/clocksource.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/irqchip.h>
|
||||
#include <linux/irqchip/arm-gic.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/platform_data/dma-rcar-hpbdma.h>
|
||||
#include <linux/platform_data/gpio-rcar.h>
|
||||
#include <linux/platform_data/irq-renesas-intc-irqpin.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/input.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/serial_sci.h>
|
||||
#include <linux/sh_timer.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/usb/otg.h>
|
||||
#include <linux/usb/hcd.h>
|
||||
#include <linux/usb/ehci_pdriver.h>
|
||||
#include <linux/usb/ohci_pdriver.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/time.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/hardware/cache-l2x0.h>
|
||||
|
||||
#include "common.h"
|
||||
#include "irqs.h"
|
||||
#include "r8a7779.h"
|
||||
|
||||
static struct map_desc r8a7779_io_desc[] __initdata = {
|
||||
|
|
@ -64,7 +44,7 @@ static struct map_desc r8a7779_io_desc[] __initdata = {
|
|||
},
|
||||
};
|
||||
|
||||
void __init r8a7779_map_io(void)
|
||||
static void __init r8a7779_map_io(void)
|
||||
{
|
||||
debug_ll_io_init();
|
||||
iotable_init(r8a7779_io_desc, ARRAY_SIZE(r8a7779_io_desc));
|
||||
|
|
@ -80,652 +60,12 @@ void __init r8a7779_map_io(void)
|
|||
#define INT2NTSR0 IOMEM(0xfe700060)
|
||||
#define INT2NTSR1 IOMEM(0xfe700064)
|
||||
|
||||
static struct renesas_intc_irqpin_config irqpin0_platform_data __initdata = {
|
||||
.irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
|
||||
.sense_bitfield_width = 2,
|
||||
};
|
||||
|
||||
static struct resource irqpin0_resources[] __initdata = {
|
||||
DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */
|
||||
DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */
|
||||
DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */
|
||||
DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */
|
||||
DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */
|
||||
DEFINE_RES_IRQ(gic_spi(27)), /* IRQ0 */
|
||||
DEFINE_RES_IRQ(gic_spi(28)), /* IRQ1 */
|
||||
DEFINE_RES_IRQ(gic_spi(29)), /* IRQ2 */
|
||||
DEFINE_RES_IRQ(gic_spi(30)), /* IRQ3 */
|
||||
};
|
||||
|
||||
void __init r8a7779_init_irq_extpin_dt(int irlm)
|
||||
static void __init r8a7779_init_irq_dt(void)
|
||||
{
|
||||
void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE);
|
||||
u32 tmp;
|
||||
|
||||
if (!icr0) {
|
||||
pr_warn("r8a7779: unable to setup external irq pin mode\n");
|
||||
return;
|
||||
}
|
||||
|
||||
tmp = ioread32(icr0);
|
||||
if (irlm)
|
||||
tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */
|
||||
else
|
||||
tmp &= ~(1 << 23); /* IRL mode - not supported */
|
||||
tmp |= (1 << 21); /* LVLMODE = 1 */
|
||||
iowrite32(tmp, icr0);
|
||||
iounmap(icr0);
|
||||
}
|
||||
|
||||
void __init r8a7779_init_irq_extpin(int irlm)
|
||||
{
|
||||
r8a7779_init_irq_extpin_dt(irlm);
|
||||
if (irlm)
|
||||
platform_device_register_resndata(
|
||||
NULL, "renesas_intc_irqpin", -1,
|
||||
irqpin0_resources, ARRAY_SIZE(irqpin0_resources),
|
||||
&irqpin0_platform_data, sizeof(irqpin0_platform_data));
|
||||
}
|
||||
|
||||
/* PFC/GPIO */
|
||||
static struct resource r8a7779_pfc_resources[] = {
|
||||
DEFINE_RES_MEM(0xfffc0000, 0x023c),
|
||||
};
|
||||
|
||||
static struct platform_device r8a7779_pfc_device = {
|
||||
.name = "pfc-r8a7779",
|
||||
.id = -1,
|
||||
.resource = r8a7779_pfc_resources,
|
||||
.num_resources = ARRAY_SIZE(r8a7779_pfc_resources),
|
||||
};
|
||||
|
||||
#define R8A7779_GPIO(idx, npins) \
|
||||
static struct resource r8a7779_gpio##idx##_resources[] = { \
|
||||
DEFINE_RES_MEM(0xffc40000 + (0x1000 * (idx)), 0x002c), \
|
||||
DEFINE_RES_IRQ(gic_iid(0xad + (idx))), \
|
||||
}; \
|
||||
\
|
||||
static struct gpio_rcar_config r8a7779_gpio##idx##_platform_data = { \
|
||||
.gpio_base = 32 * (idx), \
|
||||
.irq_base = 0, \
|
||||
.number_of_pins = npins, \
|
||||
.pctl_name = "pfc-r8a7779", \
|
||||
}; \
|
||||
\
|
||||
static struct platform_device r8a7779_gpio##idx##_device = { \
|
||||
.name = "gpio_rcar", \
|
||||
.id = idx, \
|
||||
.resource = r8a7779_gpio##idx##_resources, \
|
||||
.num_resources = ARRAY_SIZE(r8a7779_gpio##idx##_resources), \
|
||||
.dev = { \
|
||||
.platform_data = &r8a7779_gpio##idx##_platform_data, \
|
||||
}, \
|
||||
}
|
||||
|
||||
R8A7779_GPIO(0, 32);
|
||||
R8A7779_GPIO(1, 32);
|
||||
R8A7779_GPIO(2, 32);
|
||||
R8A7779_GPIO(3, 32);
|
||||
R8A7779_GPIO(4, 32);
|
||||
R8A7779_GPIO(5, 32);
|
||||
R8A7779_GPIO(6, 9);
|
||||
|
||||
static struct platform_device *r8a7779_pinctrl_devices[] __initdata = {
|
||||
&r8a7779_pfc_device,
|
||||
&r8a7779_gpio0_device,
|
||||
&r8a7779_gpio1_device,
|
||||
&r8a7779_gpio2_device,
|
||||
&r8a7779_gpio3_device,
|
||||
&r8a7779_gpio4_device,
|
||||
&r8a7779_gpio5_device,
|
||||
&r8a7779_gpio6_device,
|
||||
};
|
||||
|
||||
void __init r8a7779_pinmux_init(void)
|
||||
{
|
||||
platform_add_devices(r8a7779_pinctrl_devices,
|
||||
ARRAY_SIZE(r8a7779_pinctrl_devices));
|
||||
}
|
||||
|
||||
/* SCIF */
|
||||
#define R8A7779_SCIF(index, baseaddr, irq) \
|
||||
static struct plat_sci_port scif##index##_platform_data = { \
|
||||
.type = PORT_SCIF, \
|
||||
.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
|
||||
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \
|
||||
}; \
|
||||
\
|
||||
static struct resource scif##index##_resources[] = { \
|
||||
DEFINE_RES_MEM(baseaddr, 0x100), \
|
||||
DEFINE_RES_IRQ(irq), \
|
||||
}; \
|
||||
\
|
||||
static struct platform_device scif##index##_device = { \
|
||||
.name = "sh-sci", \
|
||||
.id = index, \
|
||||
.resource = scif##index##_resources, \
|
||||
.num_resources = ARRAY_SIZE(scif##index##_resources), \
|
||||
.dev = { \
|
||||
.platform_data = &scif##index##_platform_data, \
|
||||
}, \
|
||||
}
|
||||
|
||||
R8A7779_SCIF(0, 0xffe40000, gic_iid(0x78));
|
||||
R8A7779_SCIF(1, 0xffe41000, gic_iid(0x79));
|
||||
R8A7779_SCIF(2, 0xffe42000, gic_iid(0x7a));
|
||||
R8A7779_SCIF(3, 0xffe43000, gic_iid(0x7b));
|
||||
R8A7779_SCIF(4, 0xffe44000, gic_iid(0x7c));
|
||||
R8A7779_SCIF(5, 0xffe45000, gic_iid(0x7d));
|
||||
|
||||
/* TMU */
|
||||
static struct sh_timer_config tmu0_platform_data = {
|
||||
.channels_mask = 7,
|
||||
};
|
||||
|
||||
static struct resource tmu0_resources[] = {
|
||||
DEFINE_RES_MEM(0xffd80000, 0x30),
|
||||
DEFINE_RES_IRQ(gic_iid(0x40)),
|
||||
DEFINE_RES_IRQ(gic_iid(0x41)),
|
||||
DEFINE_RES_IRQ(gic_iid(0x42)),
|
||||
};
|
||||
|
||||
static struct platform_device tmu0_device = {
|
||||
.name = "sh-tmu",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &tmu0_platform_data,
|
||||
},
|
||||
.resource = tmu0_resources,
|
||||
.num_resources = ARRAY_SIZE(tmu0_resources),
|
||||
};
|
||||
|
||||
/* I2C */
|
||||
static struct resource rcar_i2c0_res[] = {
|
||||
{
|
||||
.start = 0xffc70000,
|
||||
.end = 0xffc70fff,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.start = gic_iid(0x6f),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device i2c0_device = {
|
||||
.name = "i2c-rcar",
|
||||
.id = 0,
|
||||
.resource = rcar_i2c0_res,
|
||||
.num_resources = ARRAY_SIZE(rcar_i2c0_res),
|
||||
};
|
||||
|
||||
static struct resource rcar_i2c1_res[] = {
|
||||
{
|
||||
.start = 0xffc71000,
|
||||
.end = 0xffc71fff,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.start = gic_iid(0x72),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device i2c1_device = {
|
||||
.name = "i2c-rcar",
|
||||
.id = 1,
|
||||
.resource = rcar_i2c1_res,
|
||||
.num_resources = ARRAY_SIZE(rcar_i2c1_res),
|
||||
};
|
||||
|
||||
static struct resource rcar_i2c2_res[] = {
|
||||
{
|
||||
.start = 0xffc72000,
|
||||
.end = 0xffc72fff,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.start = gic_iid(0x70),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device i2c2_device = {
|
||||
.name = "i2c-rcar",
|
||||
.id = 2,
|
||||
.resource = rcar_i2c2_res,
|
||||
.num_resources = ARRAY_SIZE(rcar_i2c2_res),
|
||||
};
|
||||
|
||||
static struct resource rcar_i2c3_res[] = {
|
||||
{
|
||||
.start = 0xffc73000,
|
||||
.end = 0xffc73fff,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}, {
|
||||
.start = gic_iid(0x71),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device i2c3_device = {
|
||||
.name = "i2c-rcar",
|
||||
.id = 3,
|
||||
.resource = rcar_i2c3_res,
|
||||
.num_resources = ARRAY_SIZE(rcar_i2c3_res),
|
||||
};
|
||||
|
||||
static struct resource sata_resources[] = {
|
||||
[0] = {
|
||||
.name = "rcar-sata",
|
||||
.start = 0xfc600000,
|
||||
.end = 0xfc601fff,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = gic_iid(0x84),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device sata_device = {
|
||||
.name = "sata_rcar",
|
||||
.id = -1,
|
||||
.resource = sata_resources,
|
||||
.num_resources = ARRAY_SIZE(sata_resources),
|
||||
.dev = {
|
||||
.dma_mask = &sata_device.dev.coherent_dma_mask,
|
||||
.coherent_dma_mask = DMA_BIT_MASK(32),
|
||||
},
|
||||
};
|
||||
|
||||
/* USB */
|
||||
static struct usb_phy *phy;
|
||||
|
||||
static int usb_power_on(struct platform_device *pdev)
|
||||
{
|
||||
if (IS_ERR(phy))
|
||||
return PTR_ERR(phy);
|
||||
|
||||
pm_runtime_enable(&pdev->dev);
|
||||
pm_runtime_get_sync(&pdev->dev);
|
||||
|
||||
usb_phy_init(phy);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void usb_power_off(struct platform_device *pdev)
|
||||
{
|
||||
if (IS_ERR(phy))
|
||||
return;
|
||||
|
||||
usb_phy_shutdown(phy);
|
||||
|
||||
pm_runtime_put_sync(&pdev->dev);
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
}
|
||||
|
||||
static int ehci_init_internal_buffer(struct usb_hcd *hcd)
|
||||
{
|
||||
/*
|
||||
* Below are recommended values from the datasheet;
|
||||
* see [USB :: Setting of EHCI Internal Buffer].
|
||||
*/
|
||||
/* EHCI IP internal buffer setting */
|
||||
iowrite32(0x00ff0040, hcd->regs + 0x0094);
|
||||
/* EHCI IP internal buffer enable */
|
||||
iowrite32(0x00000001, hcd->regs + 0x009C);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct usb_ehci_pdata ehcix_pdata = {
|
||||
.power_on = usb_power_on,
|
||||
.power_off = usb_power_off,
|
||||
.power_suspend = usb_power_off,
|
||||
.pre_setup = ehci_init_internal_buffer,
|
||||
};
|
||||
|
||||
static struct resource ehci0_resources[] = {
|
||||
[0] = {
|
||||
.start = 0xffe70000,
|
||||
.end = 0xffe70400 - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = gic_iid(0x4c),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device ehci0_device = {
|
||||
.name = "ehci-platform",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.dma_mask = &ehci0_device.dev.coherent_dma_mask,
|
||||
.coherent_dma_mask = 0xffffffff,
|
||||
.platform_data = &ehcix_pdata,
|
||||
},
|
||||
.num_resources = ARRAY_SIZE(ehci0_resources),
|
||||
.resource = ehci0_resources,
|
||||
};
|
||||
|
||||
static struct resource ehci1_resources[] = {
|
||||
[0] = {
|
||||
.start = 0xfff70000,
|
||||
.end = 0xfff70400 - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = gic_iid(0x4d),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device ehci1_device = {
|
||||
.name = "ehci-platform",
|
||||
.id = 1,
|
||||
.dev = {
|
||||
.dma_mask = &ehci1_device.dev.coherent_dma_mask,
|
||||
.coherent_dma_mask = 0xffffffff,
|
||||
.platform_data = &ehcix_pdata,
|
||||
},
|
||||
.num_resources = ARRAY_SIZE(ehci1_resources),
|
||||
.resource = ehci1_resources,
|
||||
};
|
||||
|
||||
static struct usb_ohci_pdata ohcix_pdata = {
|
||||
.power_on = usb_power_on,
|
||||
.power_off = usb_power_off,
|
||||
.power_suspend = usb_power_off,
|
||||
};
|
||||
|
||||
static struct resource ohci0_resources[] = {
|
||||
[0] = {
|
||||
.start = 0xffe70400,
|
||||
.end = 0xffe70800 - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = gic_iid(0x4c),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device ohci0_device = {
|
||||
.name = "ohci-platform",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.dma_mask = &ohci0_device.dev.coherent_dma_mask,
|
||||
.coherent_dma_mask = 0xffffffff,
|
||||
.platform_data = &ohcix_pdata,
|
||||
},
|
||||
.num_resources = ARRAY_SIZE(ohci0_resources),
|
||||
.resource = ohci0_resources,
|
||||
};
|
||||
|
||||
static struct resource ohci1_resources[] = {
|
||||
[0] = {
|
||||
.start = 0xfff70400,
|
||||
.end = 0xfff70800 - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = gic_iid(0x4d),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device ohci1_device = {
|
||||
.name = "ohci-platform",
|
||||
.id = 1,
|
||||
.dev = {
|
||||
.dma_mask = &ohci1_device.dev.coherent_dma_mask,
|
||||
.coherent_dma_mask = 0xffffffff,
|
||||
.platform_data = &ohcix_pdata,
|
||||
},
|
||||
.num_resources = ARRAY_SIZE(ohci1_resources),
|
||||
.resource = ohci1_resources,
|
||||
};
|
||||
|
||||
/* HPB-DMA */
|
||||
|
||||
/* Asynchronous mode register bits */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD43_MASK BIT(23) /* MMC1 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD43_SINGLE BIT(23) /* MMC1 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD43_MULTI 0 /* MMC1 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASBTMD43_MASK BIT(22) /* MMC1 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASBTMD43_BURST BIT(22) /* MMC1 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASBTMD43_NBURST 0 /* MMC1 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD24_MASK BIT(21) /* MMC0 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD24_SINGLE BIT(21) /* MMC0 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD24_MULTI 0 /* MMC0 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASBTMD24_MASK BIT(20) /* MMC0 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASBTMD24_BURST BIT(20) /* MMC0 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASBTMD24_NBURST 0 /* MMC0 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD41_MASK BIT(19) /* SDHI3 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD41_SINGLE BIT(19) /* SDHI3 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD41_MULTI 0 /* SDHI3 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASBTMD41_MASK BIT(18) /* SDHI3 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASBTMD41_BURST BIT(18) /* SDHI3 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASBTMD41_NBURST 0 /* SDHI3 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD40_MASK BIT(17) /* SDHI3 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD40_SINGLE BIT(17) /* SDHI3 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD40_MULTI 0 /* SDHI3 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASBTMD40_MASK BIT(16) /* SDHI3 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASBTMD40_BURST BIT(16) /* SDHI3 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASBTMD40_NBURST 0 /* SDHI3 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD39_MASK BIT(15) /* SDHI3 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD39_SINGLE BIT(15) /* SDHI3 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD39_MULTI 0 /* SDHI3 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASBTMD39_MASK BIT(14) /* SDHI3 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASBTMD39_BURST BIT(14) /* SDHI3 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASBTMD39_NBURST 0 /* SDHI3 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD27_MASK BIT(13) /* SDHI2 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD27_SINGLE BIT(13) /* SDHI2 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD27_MULTI 0 /* SDHI2 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASBTMD27_MASK BIT(12) /* SDHI2 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASBTMD27_BURST BIT(12) /* SDHI2 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASBTMD27_NBURST 0 /* SDHI2 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD26_MASK BIT(11) /* SDHI2 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD26_SINGLE BIT(11) /* SDHI2 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD26_MULTI 0 /* SDHI2 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASBTMD26_MASK BIT(10) /* SDHI2 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASBTMD26_BURST BIT(10) /* SDHI2 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASBTMD26_NBURST 0 /* SDHI2 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD25_MASK BIT(9) /* SDHI2 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD25_SINGLE BIT(9) /* SDHI2 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD25_MULTI 0 /* SDHI2 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASBTMD25_MASK BIT(8) /* SDHI2 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASBTMD25_BURST BIT(8) /* SDHI2 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASBTMD25_NBURST 0 /* SDHI2 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD23_MASK BIT(7) /* SDHI0 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD23_SINGLE BIT(7) /* SDHI0 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD23_MULTI 0 /* SDHI0 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASBTMD23_MASK BIT(6) /* SDHI0 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASBTMD23_BURST BIT(6) /* SDHI0 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASBTMD23_NBURST 0 /* SDHI0 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD22_MASK BIT(5) /* SDHI0 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD22_SINGLE BIT(5) /* SDHI0 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD22_MULTI 0 /* SDHI0 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASBTMD22_MASK BIT(4) /* SDHI0 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASBTMD22_BURST BIT(4) /* SDHI0 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASBTMD22_NBURST 0 /* SDHI0 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD21_MASK BIT(3) /* SDHI0 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD21_SINGLE BIT(3) /* SDHI0 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD21_MULTI 0 /* SDHI0 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASBTMD21_MASK BIT(2) /* SDHI0 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASBTMD21_BURST BIT(2) /* SDHI0 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASBTMD21_NBURST 0 /* SDHI0 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD20_MASK BIT(1) /* SDHI1 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD20_SINGLE BIT(1) /* SDHI1 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASMD20_MULTI 0 /* SDHI1 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASBTMD20_MASK BIT(0) /* SDHI1 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASBTMD20_BURST BIT(0) /* SDHI1 */
|
||||
#define HPB_DMAE_ASYNCMDR_ASBTMD20_NBURST 0 /* SDHI1 */
|
||||
|
||||
static const struct hpb_dmae_slave_config hpb_dmae_slaves[] = {
|
||||
{
|
||||
.id = HPBDMA_SLAVE_SDHI0_TX,
|
||||
.addr = 0xffe4c000 + 0x30,
|
||||
.dcr = HPB_DMAE_DCR_SPDS_16BIT |
|
||||
HPB_DMAE_DCR_DMDL |
|
||||
HPB_DMAE_DCR_DPDS_16BIT,
|
||||
.rstr = HPB_DMAE_ASYNCRSTR_ASRST21 |
|
||||
HPB_DMAE_ASYNCRSTR_ASRST22 |
|
||||
HPB_DMAE_ASYNCRSTR_ASRST23,
|
||||
.mdr = HPB_DMAE_ASYNCMDR_ASMD21_SINGLE |
|
||||
HPB_DMAE_ASYNCMDR_ASBTMD21_NBURST,
|
||||
.mdm = HPB_DMAE_ASYNCMDR_ASMD21_MASK |
|
||||
HPB_DMAE_ASYNCMDR_ASBTMD21_MASK,
|
||||
.port = 0x0D0C,
|
||||
.flags = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE,
|
||||
.dma_ch = 21,
|
||||
}, {
|
||||
.id = HPBDMA_SLAVE_SDHI0_RX,
|
||||
.addr = 0xffe4c000 + 0x30,
|
||||
.dcr = HPB_DMAE_DCR_SMDL |
|
||||
HPB_DMAE_DCR_SPDS_16BIT |
|
||||
HPB_DMAE_DCR_DPDS_16BIT,
|
||||
.rstr = HPB_DMAE_ASYNCRSTR_ASRST21 |
|
||||
HPB_DMAE_ASYNCRSTR_ASRST22 |
|
||||
HPB_DMAE_ASYNCRSTR_ASRST23,
|
||||
.mdr = HPB_DMAE_ASYNCMDR_ASMD22_SINGLE |
|
||||
HPB_DMAE_ASYNCMDR_ASBTMD22_NBURST,
|
||||
.mdm = HPB_DMAE_ASYNCMDR_ASMD22_MASK |
|
||||
HPB_DMAE_ASYNCMDR_ASBTMD22_MASK,
|
||||
.port = 0x0D0C,
|
||||
.flags = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE,
|
||||
.dma_ch = 22,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct hpb_dmae_channel hpb_dmae_channels[] = {
|
||||
HPB_DMAE_CHANNEL(0x93, HPBDMA_SLAVE_SDHI0_TX), /* ch. 21 */
|
||||
HPB_DMAE_CHANNEL(0x93, HPBDMA_SLAVE_SDHI0_RX), /* ch. 22 */
|
||||
};
|
||||
|
||||
static struct hpb_dmae_pdata dma_platform_data __initdata = {
|
||||
.slaves = hpb_dmae_slaves,
|
||||
.num_slaves = ARRAY_SIZE(hpb_dmae_slaves),
|
||||
.channels = hpb_dmae_channels,
|
||||
.num_channels = ARRAY_SIZE(hpb_dmae_channels),
|
||||
.ts_shift = {
|
||||
[XMIT_SZ_8BIT] = 0,
|
||||
[XMIT_SZ_16BIT] = 1,
|
||||
[XMIT_SZ_32BIT] = 2,
|
||||
},
|
||||
.num_hw_channels = 44,
|
||||
};
|
||||
|
||||
static struct resource hpb_dmae_resources[] __initdata = {
|
||||
/* Channel registers */
|
||||
DEFINE_RES_MEM(0xffc08000, 0x1000),
|
||||
/* Common registers */
|
||||
DEFINE_RES_MEM(0xffc09000, 0x170),
|
||||
/* Asynchronous reset registers */
|
||||
DEFINE_RES_MEM(0xffc00300, 4),
|
||||
/* Asynchronous mode registers */
|
||||
DEFINE_RES_MEM(0xffc00400, 4),
|
||||
/* IRQ for DMA channels */
|
||||
DEFINE_RES_NAMED(gic_iid(0x8e), 12, NULL, IORESOURCE_IRQ),
|
||||
};
|
||||
|
||||
static void __init r8a7779_register_hpb_dmae(void)
|
||||
{
|
||||
platform_device_register_resndata(NULL, "hpb-dma-engine",
|
||||
-1, hpb_dmae_resources,
|
||||
ARRAY_SIZE(hpb_dmae_resources),
|
||||
&dma_platform_data,
|
||||
sizeof(dma_platform_data));
|
||||
}
|
||||
|
||||
static struct platform_device *r8a7779_early_devices[] __initdata = {
|
||||
&tmu0_device,
|
||||
};
|
||||
|
||||
static struct platform_device *r8a7779_standard_devices[] __initdata = {
|
||||
&scif0_device,
|
||||
&scif1_device,
|
||||
&scif2_device,
|
||||
&scif3_device,
|
||||
&scif4_device,
|
||||
&scif5_device,
|
||||
&i2c0_device,
|
||||
&i2c1_device,
|
||||
&i2c2_device,
|
||||
&i2c3_device,
|
||||
&sata_device,
|
||||
};
|
||||
|
||||
void __init r8a7779_add_standard_devices(void)
|
||||
{
|
||||
#ifdef CONFIG_CACHE_L2X0
|
||||
/* Shared attribute override enable, 64K*16way */
|
||||
l2x0_init(IOMEM(0xf0100000), 0x00400000, 0xc20f0fff);
|
||||
#endif
|
||||
r8a7779_pm_init();
|
||||
|
||||
r8a7779_init_pm_domains();
|
||||
|
||||
platform_add_devices(r8a7779_early_devices,
|
||||
ARRAY_SIZE(r8a7779_early_devices));
|
||||
platform_add_devices(r8a7779_standard_devices,
|
||||
ARRAY_SIZE(r8a7779_standard_devices));
|
||||
r8a7779_register_hpb_dmae();
|
||||
}
|
||||
|
||||
void __init r8a7779_add_early_devices(void)
|
||||
{
|
||||
early_platform_add_devices(r8a7779_early_devices,
|
||||
ARRAY_SIZE(r8a7779_early_devices));
|
||||
|
||||
/* Early serial console setup is not included here due to
|
||||
* memory map collisions. The SCIF serial ports in r8a7779
|
||||
* are difficult to identity map 1:1 due to collision with the
|
||||
* virtual memory range used by the coherent DMA code on ARM.
|
||||
*
|
||||
* Anyone wanting to debug early can remove UPF_IOREMAP from
|
||||
* the sh-sci serial console platform data, adjust mapbase
|
||||
* to a static M:N virt:phys mapping that needs to be added to
|
||||
* the mappings passed with iotable_init() above.
|
||||
*
|
||||
* Then add a call to shmobile_setup_console() from this function.
|
||||
*
|
||||
* As a final step pass earlyprint=sh-sci.2,115200 on the kernel
|
||||
* command line in case of the marzen board.
|
||||
*/
|
||||
}
|
||||
|
||||
static struct platform_device *r8a7779_late_devices[] __initdata = {
|
||||
&ehci0_device,
|
||||
&ehci1_device,
|
||||
&ohci0_device,
|
||||
&ohci1_device,
|
||||
};
|
||||
|
||||
void __init r8a7779_init_late(void)
|
||||
{
|
||||
/* get USB PHY */
|
||||
phy = usb_get_phy(USB_PHY_TYPE_USB2);
|
||||
|
||||
shmobile_init_late();
|
||||
platform_add_devices(r8a7779_late_devices,
|
||||
ARRAY_SIZE(r8a7779_late_devices));
|
||||
}
|
||||
|
||||
#ifdef CONFIG_USE_OF
|
||||
void __init r8a7779_init_irq_dt(void)
|
||||
{
|
||||
#ifdef CONFIG_ARCH_SHMOBILE_LEGACY
|
||||
void __iomem *gic_dist_base = ioremap_nocache(0xf0001000, 0x1000);
|
||||
void __iomem *gic_cpu_base = ioremap_nocache(0xf0000100, 0x1000);
|
||||
#endif
|
||||
gic_set_irqchip_flags(IRQCHIP_SKIP_SET_WAKE);
|
||||
|
||||
#ifdef CONFIG_ARCH_SHMOBILE_LEGACY
|
||||
gic_init(0, 29, gic_dist_base, gic_cpu_base);
|
||||
#else
|
||||
irqchip_init();
|
||||
#endif
|
||||
|
||||
/* route all interrupts to ARM */
|
||||
__raw_writel(0xffffffff, INT2NTSR0);
|
||||
__raw_writel(0x3fffffff, INT2NTSR1);
|
||||
|
|
@ -740,7 +80,7 @@ void __init r8a7779_init_irq_dt(void)
|
|||
|
||||
#define MODEMR 0xffcc0020
|
||||
|
||||
u32 __init r8a7779_read_mode_pins(void)
|
||||
static u32 __init r8a7779_read_mode_pins(void)
|
||||
{
|
||||
static u32 mode;
|
||||
static bool mode_valid;
|
||||
|
|
@ -756,16 +96,23 @@ u32 __init r8a7779_read_mode_pins(void)
|
|||
return mode;
|
||||
}
|
||||
|
||||
static void __init r8a7779_init_time(void)
|
||||
{
|
||||
r8a7779_clocks_init(r8a7779_read_mode_pins());
|
||||
clocksource_of_init();
|
||||
}
|
||||
|
||||
static const char *const r8a7779_compat_dt[] __initconst = {
|
||||
"renesas,r8a7779",
|
||||
NULL,
|
||||
};
|
||||
|
||||
DT_MACHINE_START(R8A7779_DT, "Generic R8A7779 (Flattened Device Tree)")
|
||||
.smp = smp_ops(r8a7779_smp_ops),
|
||||
.map_io = r8a7779_map_io,
|
||||
.init_early = shmobile_init_delay,
|
||||
.init_time = r8a7779_init_time,
|
||||
.init_irq = r8a7779_init_irq_dt,
|
||||
.init_late = shmobile_init_late,
|
||||
.dt_compat = r8a7779_compat_dt,
|
||||
MACHINE_END
|
||||
#endif /* CONFIG_USE_OF */
|
||||
|
|
|
|||
|
|
@ -23,7 +23,6 @@
|
|||
#include <asm/cacheflush.h>
|
||||
#include <asm/smp_plat.h>
|
||||
#include <asm/smp_scu.h>
|
||||
#include <asm/smp_twd.h>
|
||||
|
||||
#include "common.h"
|
||||
#include "pm-rcar.h"
|
||||
|
|
@ -56,14 +55,6 @@ static const struct rcar_sysc_ch * const r8a7779_ch_cpu[4] = {
|
|||
[3] = &r8a7779_ch_cpu3,
|
||||
};
|
||||
|
||||
#if defined(CONFIG_HAVE_ARM_TWD) && !defined(CONFIG_ARCH_MULTIPLATFORM)
|
||||
static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, R8A7779_SCU_BASE + 0x600, 29);
|
||||
void __init r8a7779_register_twd(void)
|
||||
{
|
||||
twd_local_timer_register(&twd_local_timer);
|
||||
}
|
||||
#endif
|
||||
|
||||
static int r8a7779_platform_cpu_kill(unsigned int cpu)
|
||||
{
|
||||
const struct rcar_sysc_ch *ch = NULL;
|
||||
|
|
|
|||
Loading…
Reference in New Issue