Commit Graph

612 Commits

Author SHA1 Message Date
Chris Wilson 995073072c drm/i915: Fix unintended recursion in ironlake_disable_rc6
After disabling, we're meant to teardown the bo used for the contexts,
not recurse into ourselves again and preventing module unload.

Reported-and-tested-by: Ben Widawsky <bwidawsk@gmail.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-24 17:16:43 +00:00
Chris Wilson ce453d81cb drm/i915: Use a device flag for non-interruptible phases
The code paths for modesetting are growing in complexity as we may need
to move the buffers around in order to fit the scanout in the aperture.
Therefore we face a choice as to whether to thread the interruptible status
through the entire pinning and unbinding code paths or to add a flag to
the device when we may not be interrupted by a signal. This does the
latter and so fixes a few instances of modesetting failures under stress.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-22 15:56:25 +00:00
Chris Wilson c872522663 drm/i915: Protect against drm_gem_object not being the first member
Dave Airlie spotted that we had a potential bug should we ever rearrange
the drm_i915_gem_object so not the base drm_gem_object was not its first
member. He noticed that we often convert the return of
drm_gem_object_lookup() immediately into drm_i915_gem_object and then
check the result for nullity. This is only valid when the base object is
the first member and so the superobject has the same address. Play safe
instead and use the compiler to convert back to the original return
address for sanity testing.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-22 15:55:57 +00:00
Jesse Barnes 548f245ba6 drm/i915: fix per-pipe reads after "cleanup"
In a few places I replaced reads of per-pipe registers with the actual
register offsets themselves (converting I915_READ(reg) to _PIPE(reg)).
Alexey caught this on his 9xx machine because the cursor control write
was affected.  A quick audit showed a few more places where I'd borked
a read, so here's a patch to fix things up.

Reported-by: Alexey Fisher <bug-track@fisher-privat.net>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
[ickle: compilation fix]
Tested-by: Alexey Fisher <bug-track@fisher-privat.net>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-22 15:55:49 +00:00
Chris Wilson fc9a2228ac Revert "drm/i915: Disable SSC for outputs other than LVDS or DP"
This reverts commit 633f2ea266 and the
attempted fix dcbe6f2b3d.

There is a single clock source used for both SSC (some LVDS and DP) and
non-SSC (VGA, DVI) outputs. So we need to be careful to only enable SSC
as necessary. However, fiddling with DREFCLK was causing DP links to be
dropped and we do not have a fix ready, so revert.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-22 15:55:28 +00:00
Jesse Barnes 011b9910bd drm/i915: skip FDI & PCH enabling for DP_A
eDP on the CPU doesn't need the PCH set up at all, it can in fact cause
problems.  So avoid FDI training and PCH PLL enabling in that case.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Tested-by: Andy Whitcroft <apw@canonical.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-22 15:52:41 +00:00
Chris Wilson 86b27d8050 drm/i915: Ignore a hung GPU when flushing the framebuffer prior to a switch
If the gpu is hung, then whatever was inside the render cache is lost
and there is little point waiting for it. Or complaining if we see an
EIO or EAGAIN instead. So, if the GPU is indeed in its death throes when
we need to rewrite the registers for a new framebuffer, just ignore the
error and proceed with the update.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-22 15:52:40 +00:00
Chris Wilson 9035a97a32 Merge branch 'drm-intel-fixes' into drm-intel-next
Grab the latest stabilisation bits from -fixes and some suspend and
resume fixes from linus.

Conflicts:
	drivers/gpu/drm/i915/i915_drv.h
	drivers/gpu/drm/i915/i915_irq.c
2011-02-16 09:44:30 +00:00
Chris Wilson 01eec727d9 drm/i915: Ignore a hung GPU when flushing the framebuffer prior to a switch
If the gpu is hung, then whatever was inside the render cache is lost
and there is little point waiting for it. Or complaining if we see an
EIO or EAGAIN instead. So, if the GPU is indeed in its death throes when
we need to rewrite the registers for a new framebuffer, just ignore the
error and proceed with the update.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-16 09:25:17 +00:00
Jesse Barnes 47a05eca72 drm/i915: disable PCH ports if needed when disabling a CRTC
Disable any PCH ports associated with a pipe when disabling it.  This
should prevent transcoder disable failures due to ports still being on.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
[ickle: introduce *_PIPE_ENABLED() macro]
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-11 20:32:44 +00:00
Chris Wilson 04dbff5260 drm/i915: Fix resume regression from 5d1d0cc
The irony of the patch to fix the resume regression on PineView causing
a further regression on Ironlake is not lost on me.

Reported-by: Jeff Chua <jeff.chua.linux@gmail.com>
Reported-by: Björn Schließmann <chronoss@gmx.de>
Tested-by: Björn Schließmann <chronoss@gmx.de>
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=28802
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-11 09:20:51 +00:00
Chris Wilson ac66808814 drm/i915: Disable RC6 on Ironlake
The automatic powersaving feature is once again causing havoc, with 100%
reliable hangs on boot and resume on affected machines.

Reported-by: Francesco Allertsen <fallertsen@gmail.com>
Reported-by: Gui Rui <chaos.proton@gmail.com>
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=28582
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-09 17:04:54 +00:00
Jesse Barnes 9db4a9c7b2 drm/i915: cleanup per-pipe reg usage
We had some conversions over to the _PIPE macros, but didn't get
everything.  So hide the per-pipe regs with an _ (still used in a few
places for legacy) and add a few _PIPE based macros, then make sure
everyone uses them.

[update: remove usage of non-existent no-op macro]
[update 2: keep modesetting suspend/resume code, update to new reg names]
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
[ickle: stylistic cleanups for checkpatch and taste]
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-07 21:17:15 +00:00
Jesse Barnes dcbe6f2b3d drm/i915: the PCH reference clocks are global, so don't clobber unconditionally
The PCH can drive several reference clocks simultaneously, and needs to
with multiple display configurations.  So we can't just clobber the
existing state everytime we set a mode, we need to take into account
what the other CRTCs are doing at the time.

Doing so fixes an issue where you'd lose the LVDS display at boot if you
had an LVDS+DP config.

[updated: init bools and check CRTC status correctly]
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-07 12:06:14 +00:00
Jesse Barnes 291906f11c drm/i915: add port assertion check when disabling transcoders
When a transcoder is disabled, any ports pointing at it should also be
disabled.  If they're not, we may fail to disable the transcoder,
leading to blank displays.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-07 12:06:13 +00:00
Jesse Barnes 19ec135838 drm/i915: don't check plane vs pipe enable on ILK+
These bits have a different meaning on ILK+, where planes are hardwired
to pipes.  Fixing this avoid some spurious assertion failures.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-07 12:06:13 +00:00
Eric Anholt cb3543c6b1 drm/i915: Set the transcoder port to none when disabling DP.
The specs say to do so.

Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-07 12:06:12 +00:00
Chris Wilson 308977ac03 drm/i915: Use DEBUG_KMS for the self-refresh watermarks
For consistency and segregation from the noisy DRM_DEBUG().

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-07 12:04:52 +00:00
Chris Wilson 4a1dc3ff68 Merge branch 'drm-intel-fixes' into drm-intel-next
Merge resume fixes from -fixes and an important fix for SDVO GMBUS.
2011-02-01 08:49:14 +00:00
Chris Wilson 72557b4f32 drm/i915: Remove unreachable condition
Fortunately unreachable. For Crestline, the watermarks must always be
programmed to 8...

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-01 08:48:37 +00:00
Chris Wilson 309cfea822 drm/i915: Trivial spelling mistake 'assertiing'
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-01 08:48:36 +00:00
Chris Wilson 5d1d0cc87f drm/i915: Reset crtc after resume
Based on a patch by Takashi Iwai.

Reported-by: Matthias Hopf <mat@mshopf.de>
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=27272
Tested-by: Takashi Iwai <tiwai@suse.de>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-25 19:23:29 +00:00
Chris Wilson d210246ab1 drm/i915: Refactor self-refresh watermark calculations
Move the plane->mode config to the point of use rather than repeatedly
querying the same information.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-25 11:22:10 +00:00
Chris Wilson 29ee399131 drm/i915: Silence a few -Wunused-but-set-variable
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-25 10:33:11 +00:00
Chris Wilson fe4402931e Merge branch 'drm-intel-fixes' into drm-intel-next
Apply the SandyBridge stability fixes from -fixes.
2011-01-20 09:41:07 +00:00
Chris Wilson 417ae1476d drm/i915: Include TLB miss latency in g4x watermark computations
Reports of FIFO underruns are still persisting on gm45.

References: https://bugs.freedesktop.org/show_bug.cgi?id=27589
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-19 15:04:42 +00:00
Chris Wilson 633f2ea266 drm/i915: Disable SSC for outputs other than LVDS or DP
For CRT and SDVO/HDMI, we need to use a normal, non-SSC, clock and so we
must clear any enabling bits left-over from earlier outputs. And also
seems to correct the LVDS panel on the Lenovo U160.

However, at one point, it did cause an "ERROR failed to disable
trancoder". So prolonged testing on top of Jesse's refactored and
error-checking CRTC logic is desired.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-19 13:33:27 +00:00
Bryan Freed aa9b500ddf drm/i915: Honour LVDS sync polarity from EDID
The i915 driver normally assumes the video bios has configured several
of the LVDS panel registers, and it just inherits the values. If the
vbios has not run, several of these will need to be setup. So we need to
check that the LVDS sync polarity is correctly configured per any
available modelines (e.g. EDID) and adjust if not, issuing a warning as
we do.

Signed-off-by: Mark Hayter <mdhayter@chromium.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-19 13:12:16 +00:00
Jesse Barnes ccab5c8275 drm/i915: tune Sandy Bridge DRPS constants
These make us increase our frequency much more readily, and decrease
them only after significant idle time, resulting in a 20% performance
increase for nexuiz.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-19 12:57:56 +00:00
Chris Wilson 311bd68e02 drm/i915: Trivial sparse fixes
Move code around and invoke iomem annotation in a few more places in
order to silence sparse. Still a few more iomem annotations to go...

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-19 12:39:38 +00:00
Alexander Lam 18b2190ca5 drm/i915: allow 945 to control self refresh (CxSR) automatically
I changed 945's self refresh to work without the need for the driver to
enable/disable self refresh manually based on the idle state of the gpu.
This is much better than enabling/disabling self refresh for various
reasons, including staying in a lower power state for more time and
avoiding the need for cpu cycles.

This was originally done manually to workaround issues with the hardware
hanging. However, since 944001201: drm/i915: enable low power render
writes on GEN3 hardware, automatic CxSR seems stable.

Signed-off-by: Alexander Lam <lambchop468@gmail.com>
Acked-by : Li Peng <peng.li@linux.intel.com>
[ickle: play safe with the ordering and disable CxSR before tweaking any
watermark and enable afterwards.]
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-19 12:38:48 +00:00
Jesse Barnes f67a559daa drm/i915: skip FDI & PCH enabling for DP_A
eDP on the CPU doesn't need the PCH set up at all, it can in fact cause
problems.  So avoid FDI training and PCH PLL enabling in that case.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Tested-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-19 12:38:11 +00:00
Jesse Barnes 6f06ce184c drm/i915: set phase sync pointer override enable before setting phase sync pointer
We need to unlock the phase sync pointer enable bit before we can
actually enable the phase sync pointer workaround on Ironlake.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-19 12:37:48 +00:00
Jesse Barnes 0fc932b8ec drm/i915: factor out FDI disable and add FDI assertions
Factor out the FDI disable function (make it a mirror of
ironlake_fdi_enable) and add some FDI related assertions to the FDI
training code (we need an active pipe & plane before we start
transmitting bits).

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-19 12:37:33 +00:00
Jesse Barnes 040484af3a drm/i915: add transcoder enable/disable functions
Along with assertion checks for the FDI transmitters and receivers
(including PLLs).  Modify the pipe enable function to check for FDI PLL
status as well, when driving PCH ports.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-19 12:37:18 +00:00
Jesse Barnes d9b6cb568b drm/i915: assert panel is unlocked before writing transcoder timing regs
Otherwise our writes will be silently ignored.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-19 12:37:03 +00:00
Jesse Barnes 92f2584a08 drm/i915: add PCH DPLL enable/disable functions
With assertions to check transcoder and reference clock state.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-19 12:36:41 +00:00
Jesse Barnes 63d7bbe9de drm/i915: add PLL enable/disable functions
For pre-ILK only.  Saves some code in the CRTC enable/disable functions
and allows us to check for pipe and panel status at enable/disable time.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-19 12:36:26 +00:00
Jesse Barnes ea0760cfc0 drm/i915: add panel lock assertion function
When PLLs or timing regs are changed, we need to make sure the panel
lock will allow it.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-19 12:36:11 +00:00
Jesse Barnes b24e717988 drm/i915: add pipe/plane enable/disable functions
Add plane enable/disable functions to prevent duplicated code and allow
us to easily check for plane enable/disable requirements (such as pipe
enable, plane status, pll status etc).

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-19 12:35:49 +00:00
Jesse Barnes 65993d64a3 drm/i915: don't enable plane, pipe and PLL prematurely
On Ironlake+ we need to enable these in a specific order.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-19 12:35:27 +00:00
Jesse Barnes 4efe070896 drm/i915: make the blitter report buffer modifications to the FBC unit
Without this change, blits to the front buffer won't invalidate FBC
state, causing us to scan out stale data.  Make sure we update these
bits on every FBC enable, since they may get clobbered if we shut off
the display.

References: https://bugzilla.kernel.org/show_bug.cgi?id=26932
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-18 19:30:24 +00:00
Jesse Barnes 1ffa325bac drm/i915: set more FBC chicken bits
Add a couple of missing workaround bits for ILK & SNB.  These disable
clock gating on a couple of units that would otherwise prevent FBC from
working.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-18 09:50:08 +00:00
Chris Wilson a76150302d drm/i915: Add a module option to override the use of SSC
In order to workaround the issue with LVDS not working on the Lenovo
U160 apparently due to using the wrong SSC frequency, add an option to
disable SSC.

Suggested-by: Lukács, Árpád <lukacs.arpad@gmail.com>
Bugzillla: https://bugs.freedesktop.org/show_bug.cgi?id=32748
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: stable@kernel.org
2011-01-13 16:05:58 +00:00
Chris Wilson db66e37d23 drm/i915: Include TLB miss overhead for computing WM
The docs recommend that if 8 display lines fit inside the FIFO buffer,
then the number of watermark entries should be increased to hide the
latency of filling the rest of the FIFO buffer.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-11 20:44:54 +00:00
Jesse Barnes d5bb081b02 drm/i915: cleanup rc6 code
Cleanup several aspects of the rc6 code:
  - misnamed intel_disable_clock_gating function (was only about rc6)
  - remove commented call to intel_disable_clock_gating
  - rc6 enabling code belongs in its own function (allows us to move the
    actual clock gating enable call back into restore_state)
  - allocate power & render contexts up front, only free on unload
    (avoids ugly lazy init at rc6 enable time)

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
[ickle: checkpatch cleanup]
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-11 20:43:59 +00:00
Jesse Barnes 88271da3f3 drm/i915: re-enable rc6 support for Ironlake+
Re-enable rc6 support on Ironlake for power savings.  Adds a debugfs
file to check current RC state, adds a missing workaround for Ironlake
MI_SET_CONTEXT instructions, and renames MCHBAR_RENDER_STANDBY to
RSTDBYCTL to match the docs.

Keep RC6 and the power context disabled on pre-ILK.  It only seems to
hang and doesn't save any power.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-11 20:43:58 +00:00
Jesse Barnes dbdc647927 drm/i915: avoid reading non-existent PLL reg on Ironlake+
These functions need to be reworked for Ironlake and above, but until
then at least avoid reading non-existent registers.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
[ickle: combine with a gratuitous tidy]
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-11 20:37:05 +00:00
Yuanhan Liu a0fa62d3b6 drm/i915: fix the wrong latency value while computing wm0
On Ironlake, the LP0 latency is hardcoded and in ns unit, while on
Sandybridge, it comes from a register and with unit 0.1 us. So, fix
the wrong latency value while computing wm0 on Ironlake and Sandybridge.

Signed-off-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-11 20:36:15 +00:00
Jesse Barnes b79d499022 drm/i915: support low power watermarks on Ironlake
This patch actually makes the watermark code even uglier (if that's
possible), but has the advantage of sharing code between SNB and ILK at
least.  Longer term we should refactor the watermark stuff into its own
file and clean it up now that we know how it's supposed to work.

Supporting WM2 on my Vaio reduced power consumption by around 0.5W, so
this patch is definitely worthwhile (though it also needs lots of test
coverage).

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
[ickle: pass the watermark structs arounds]
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-11 20:36:14 +00:00
Chris Wilson 35c3047ad1 drm/i915: Use the mappable sizes determined by GTT for consistency.
There should be no difference, but we can eliminate redundant code.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-11 20:35:40 +00:00
Jesse Barnes a6044e23b7 drm/i915: support overclocking on Sandy Bridge
In some configuration, the PCU may allow us to overclock the GPU.
Check for this case and adjust the max frequency as appropriate.  Also
initialize the min/max frequencies to default values as indicated by
hardware.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-11 20:35:40 +00:00
Chris Wilson 47356eb672 drm/i915/panel: Only record the backlight level when it is enabled
By tracking the current status of the backlight we can prevent recording
the value of the current backlight when we have disabled it. And so
prevent restoring it to 'off' after an unbalanced sequence of
intel_lvds_disable/enable.

Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=22672
Tested-by: Alex Riesen <raa.lkml@gmail.com>
Tested-by: Larry Finger <Larry.Finger@lwfinger.net>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: stable@kernel.org
2011-01-11 20:27:04 +00:00
Jesse Barnes 858bc21f06 drm/i915: check eDP encoder correctly when setting modes
We were using a stale pointer in the check which caused us to use CPU
attached DP params when we should have been using PCH attached params.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=31988
Tested-by: Jan-Hendrik Zab <jan@jhz.name>
Tested-by: Christoph Lukas <christoph.lukas@gmx.net>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: stable@kernel.org
2011-01-11 20:21:55 +00:00
Dave Airlie 4f125010d2 Merge branch 'master' of /home/airlied/kernel/linux-2.6 into drm-core-next 2011-01-05 08:31:08 +10:00
Chris Wilson 4d3024428f drm/i915: Verify Ironlake eDP presence on DP_A using the capability fuse
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-23 09:51:37 +00:00
Eric Anholt 06f37751af drm/i915: Set the required VFMUNIT clock gating disable on Ironlake.
It's required by the specs, but we don't know why.  Let's not find out
why.

Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-23 09:49:40 +00:00
Jesse Barnes 3b8d8d91d5 drm/i915: dynamic render p-state support for Sandy Bridge
Add an interrupt handler for switching graphics frequencies and handling
PM interrupts.  This should allow for increased performance when busy
and lower power consumption when idle.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-18 11:07:02 +00:00
Chris Wilson 9c3d2f7ffa drm/i915: Enable EI mode for RCx decision making on Sandybridge
And no I have no idea what the difference is either, just that is the
recommendation.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-17 10:54:26 +00:00
Mario Kleiner 49b14a5ca2 drm/i915: Add Guess-o-matic for pageflip timestamping.
This patch changes the strategy for pageflip completion
timestamping. It detects if the pageflip completion
routine gets executed before or after drm_handle_vblank,
and thereby decides if the returned vblank count and
timestamp must be incremented by 1 frame(duration) or
not. It compares the current system time at invocation
against the current vblank timestamp. If the difference
is more than 0.9 video refresh interval durations then
it assumes the vblank timestamp and count are outdated
and need to be incremented and does so. Otherwise it
assumes a delayed pageflip irq and doesn't correct
the timestamp and count.

Advantage of this patch: Pageflip timestamping becomes
more robust against implementation errors and is
maintenance free for future GPU's.

Disadvantage: A few dozen (hundred?) nsecs extra
time spent in pageflip irq handler for each flip,
compared to hard-coded per-gpu settings?

Signed-off-by: Mario Kleiner <mario.kleiner@tuebingen.mpg.de>
Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-16 21:02:26 +00:00
Mario Kleiner 0af7e4dff5 drm/i915: Add support for precise vblank timestamping (v2)
v2: Change IS_IRONLAKE to IS_GEN5 to adapt to 2.6.37

This patch adds new functions for use by the drm core:

.get_vblank_timestamp() provides a precise timestamp
for the end of the most recent (or current) vblank
interval of a given crtc, as needed for the DRI2
implementation of the OML_sync_control extension.
It is a thin wrapper around the drm function
drm_calc_vbltimestamp_from_scanoutpos() which does
almost all the work.

.get_scanout_position() provides the current horizontal
and vertical video scanout position and "in vblank"
status of a given crtc, as needed by the drm for use by
drm_calc_vbltimestamp_from_scanoutpos().

The patch modifies the pageflip completion routine
to use these precise vblank timestamps as the timestamps
for pageflip completion events.

This code has been only tested on a HP-Mini Netbook with
Atom processor and Intel 945GME gpu. The codepath for
(IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev)) gpu's
has not been tested so far due to lack of hardware.

Signed-off-by: Mario Kleiner <mario.kleiner@tuebingen.mpg.de>
Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-16 21:02:24 +00:00
Yuanhan Liu 9c04f015eb drm/i915: Add frame buffer compression on Sandybridge
Add frame buffer compression on Sandybridge. The method is similar to
Ironlake, except that two new registers of type GTTMMADR must be written
with the right fence info.

Signed-off-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-15 11:22:27 +00:00
Yuanhan Liu 1398261a2e drm/i915: Add self-refresh support on Sandybridge
Add the support of memory self-refresh on Sandybridge, which is now
support 3 levels of watermarks and the source of the latency values
for watermarks has changed.

On Sandybridge, the LP0 WM value is not hardcoded any more. All the
latency value is now should be extracted from MCHBAR SSKPD register.
And the MCHBAR base address is changed, too.

For the WM values, if any calculated watermark values is larger than
the maximum value that can be programmed into the associated watermark
register, that watermark must be disabled.

Signed-off-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
[ickle: remove duplicate compute routines and fixup for checkpatch]
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-15 11:16:57 +00:00
Chris Wilson b7f1de289c drm/i915: Wait for vblank before unpinning old fb
Be paranoid and ensure that the vblank has passed and the scanout has
switched to the new fb, before unpinning the old one and possibly
tearing down its PTEs.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-15 10:33:23 +00:00
Chris Wilson 1b894b5924 drm/i915: Pass clock limits down to PLL matcher
As we already know the limits for the hardware clock, pass it down
rather than recomputing them for each match.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-14 20:09:04 +00:00
Chris Wilson 8fd2685911 drm/i915: Enable RC6 autodownclocking on Sandybridge
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-09 19:46:24 +00:00
Chris Wilson ff7ea4c040 drm/i915: Re-arm the idle timers if the device is still busy
Don't post a downclocking task if the device is still active when the
idle timer fires. A pathological process could queue up several seconds
worth of processing and then go to sleep, during which time the idle
timer would kick in and downclock the GPU.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-09 19:13:52 +00:00
Chris Wilson c57802706a drm/i915: Disable renderctx powersaving support for Ironlake
... still causes a failure during suspend.

Reported-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-07 23:05:32 +00:00
Chris Wilson 0cdab21f9a drm/i915: Uncouple render/power ctx before suspending
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-05 23:19:37 +00:00
Chris Wilson 3c8cdf9b60 drm/i915: Power Context register is only available for gen4 mobiles
The ability to save the hardware context upon powering down the render
clock through PWRCTXA is only available on a couple of gen4 chipsets.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-05 23:18:31 +00:00
Chris Wilson 382ab78c0e Merge branch 'drm-intel-fixes' into drm-intel-next 2010-12-05 00:37:43 +00:00
Chris Wilson f7746f0e1f drm/i915: Enable self-refresh for Ironlake
We disabled this a while ago as it was inexplicably broken. However, it
now appears to work...

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-05 00:37:39 +00:00
Chris Wilson 1ec14ad313 drm/i915: Implement GPU semaphores for inter-ring synchronisation on SNB
The bulk of the change is to convert the growing list of rings into an
array so that the relationship between the rings and the semaphore sync
registers can be easily computed.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-05 00:37:38 +00:00
Chris Wilson f684f5b48c drm/i915: Re-enable RC6 for power-savings.
Let's see if we've successfully cleared up all the bugs from last
time...

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-05 00:37:37 +00:00
Chris Wilson c1858123db drm/i915: Enable CB tuning of the Display PLL
Magic numbers from the specs. This is supposed to allow the PLL some
variance to improve jitter performance and VCO headroom across
manufacturing and environmental variations.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-05 00:37:36 +00:00
Chris Wilson a589b9f429 drm/i915: Explain why we need to write DPLL twice
... it's because setting the Pixel Multiply bits only takes effect once
the PLL is enabled and stable.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-05 00:37:35 +00:00
Chris Wilson 49078f7d10 drm/i915: Factor in pixel-repeat in FDI M/N calculation
Fixes the modesetting on the secondary panel of the Libretto W100 and
presumably many more Ironlake laptops with SDVO LVDS displays.

Reported-and-tested-by: Matthew Willoughby <mattfredwill@gmail.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: stable@kernel.org
2010-12-04 13:41:04 +00:00
Chris Wilson 22ed1113a9 drm/i915: Death to the unnecessary 64bit divide
Use the hardware DDA to calculate the ratio with as much accuracy as is
possible.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: stable@kernel.org
2010-12-03 23:51:02 +00:00
Chris Wilson 47f1c6c9ff drm/i915: Clean conflicting modesetting registers upon init
If we leave the registers in a conflicting state then when we attempt
to teardown the active mode, we will not disable the pipes and planes
in the correct order -- leaving a plane reading from a disabled pipe and
possibly leading to undefined behaviour.

Reported-and-tested-by: Andy Whitcroft <apw@canonical.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=32078
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: stable@kernel.org
2010-12-03 17:50:55 +00:00
Chris Wilson b9e68670cc Merge branch 'drm-intel-fixes' into drm-intel-next
Conflicts:
	drivers/gpu/drm/i915/intel_drv.h
2010-12-02 23:50:36 +00:00
Eric Anholt 220cad3cbf drm/i915: Always set the DP transcoder config to 8BPC.
The pipe is always set to 8BPC, but here we were leaving whatever
previous bits were set by the BIOS in place.

Signed-off-by: Eric Anholt <eric@anholt.net>
Tested-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: stable@kernel.org
2010-12-02 22:31:20 +00:00
Chris Wilson d9e86c0ee6 drm/i915: Pipelined fencing [infrastructure]
With this change, every batchbuffer can use all available fences (save
pinned and scanout, of course) without ever stalling the gpu!

In theory. Currently the actual pipelined update of the register is
disabled due to some stability issues. However, just the deferred update
is a significant win.

Based on a series of patches by Daniel Vetter.

The premise is that before every access to a buffer through the GTT we
have to declare whether we need a register or not. If the access is by
the GPU, a pipelined update to the register is made via the ringbuffer,
and we track the last seqno of the batches that access it. If by the
CPU we wait for the last GPU access and update the register (either
to clear or to set it for the current buffer).

One advantage of being able to pipeline changes is that we can defer the
actual updating of the fence register until we first need to access the
object through the GTT, i.e. we can eliminate the stall on set_tiling.
This is important as the userspace bo cache does not track the tiling
status of active buffers which generate frequent stalls on gen3 when
enabling tiling for an already bound buffer.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2010-12-02 10:07:05 +00:00
Chris Wilson c5d1b51d35 drm/i915: Clear pfit registers when not used by any outputs
... otherwise the panel-fitter may be left enabled with random settings
and cause unintended filtering (i.e. blurring of native modes on external
panels).

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=31942
Reported-and-tested-by: Ben Kohler <bkohler@gmail.com>
Tested-by: Ciprian Docan <docan@eden.rutgers.edu>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-29 18:45:01 +00:00
Chris Wilson 919926aeb3 drm/i915: Thread the pipelining ring through the callers.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23 20:19:16 +00:00
Chris Wilson 05394f3975 drm/i915: Use drm_i915_gem_object as the preferred type
A glorified s/obj_priv/obj/ with a net reduction of over a 100 lines and
many characters!

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23 20:19:10 +00:00
Chris Wilson c4a1d9e4dc drm/i915: Capture interesting display registers on error
When trying to diagnose mysterious errors on resume, capture the
display register contents as well.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-22 08:08:19 +00:00
Chris Wilson c94f28c383 Merge branch 'drm-intel-fixes' into drm-intel-next
Conflicts:
	drivers/gpu/drm/i915/i915_gem.c
	drivers/gpu/drm/i915/intel_ringbuffer.c
2010-11-15 06:49:30 +00:00
Chris Wilson 85345517fe drm/i915: Retire any pending operations on the old scanout when switching
An old and oft reported bug, is that of the GPU hanging on a
MI_WAIT_FOR_EVENT following a mode switch. The cause is that the GPU is
waiting on a scanline counter on an inactive pipe, and so waits for a
very long time until eventually the user reboots his machine.

We can prevent this either by moving the WAIT into the kernel and
thereby incurring considerable cost on every swapbuffers, or by waiting
for the GPU to retire the last batch that accesses the framebuffer
before installing a new one. As mode switches are much rarer than swap
buffers, this looks like an easy choice.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=28964
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=29252
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: stable@kernel.org
2010-11-13 09:49:11 +00:00
Chris Wilson 8168bd48bb drm/i915: Remove the definitions for Primary Ring Buffer
We only ever used the PRB0, neglecting the secondary ring buffers, and
now with the advent of multiple engines with separate ring buffers we
need to excise the anachronisms from our code (and be explicit about
which ring we mean where). This is doubly important in light of the
FORCEWAKE required to read ring buffer registers on SandyBridge.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-11 17:54:52 +00:00
Chris Wilson 33d2323711 drm/i915: Unconditionally get the fence reg when pinning scanout
We use i915_gem_object_get_fence_reg() to do LRU tracking of the fence
registers, so stop trying to be too clever when pinning the fb->obj.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-10 13:59:09 +00:00
Eric Anholt 67e92af01c drm/i915: Apply display workaround required according to the B-Spec.
Not known to fix any current bugs.

Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-08 09:20:12 +00:00
Eric Anholt de6e2eaf2c drm/i915: Apply B-spec mandated workaround for read flushes on Ironlake.
This is not known to fix any particular bugs we have, but the spec
says to do it, and the BIOS hadn't already set it up on my system.

Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-08 09:20:08 +00:00
Daniel Vetter 75e9e9158f drm/i915: kill mappable/fenceable disdinction
a00b10c360 "Only enforce fence limits inside the GTT" also
added a fenceable/mappable disdinction when binding/pinning buffers.
This only complicates the code with no pratical gain:

- In execbuffer this matters on for g33/pineview, as this is the only
  chip that needs fences and has an unmappable gtt area. But fences
  are only possible in the mappable part of the gtt, so need_fence
  implies need_mappable. And need_mappable is only set independantly
  with relocations which implies (for sane userspace) that the buffer
  is untiled.

- The overlay code is only really used on i8xx, which doesn't have
  unmappable gtt. And it doesn't support tiled buffers, currently.

- For all other buffers it's a bug to pass in a tiled bo.

In short, this disdinction doesn't have any practical gain.

I've also reverted mapping the overlay and context pages as possibly
unmappable. It's not worth being overtly clever here, all the big
gains from unmappable are for execbuf bos.

Also add a comment for a clever optimization that confused me
while reading the original patch by Chris Wilson.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-04 19:02:03 +00:00
Daniel Vetter 818f2a3cc3 drm/i915: revert pageflip/mappable related abi breakage
In a00b10c360 "Only enforce fence limits inside the GTT"
Chris Wilson implemented an optimization to only pin framebuffers
as mappable for crtc_set_base (but not for pageflips). This breaks
the abi, eg: A double buffering mesa client might leave the last
framebuffer in unmappable space on close. A subsequent glReadPix
by a frontbuffer rendering client then goes boom. My pretty anal
mappable/unmappable consistency checking detected this, see

https://bugs.freedesktop.org/show_bug.cgi?id=31286

Chris Wilson tried to fix this in 085ce26437 by pinning
tiled framebuffers into mappable space. This
a) renders the original optimization of not forcing framebuffers
   for pageflipping clients into mappable pointless because all our
   scanout buffers are tiled by default.
b) doesn't solve the problem for untiled framebuffers.

So kill this. Emperically it's no gain anyway because framebuffers are
being reused by the ddx and hence there's no chance for them to get
constanly bounced between mappable and unmappable.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-04 18:55:59 +00:00
Chris Wilson 46168f3936 Merge branch 'drm-intel-fixes' into drm-intel-next 2010-11-04 09:40:36 +00:00
Zhenyu Wang e07ac3a0b1 drm/i915; Don't apply Ironlake FDI clock workaround to Sandybridge
Signed-off-by: Zhenyu Wang <zhenyu.z.wang@intel.com>
Cc: stable@kernel.org
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-04 09:39:15 +00:00
Zhenyu Wang 5e84e1a487 drm/i915: Fix KMS regression on Sandybridge/CPT
We should enable FDI normal training on Sandybridge/CPT system
as well.

Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
[ickle: removed unrelated chunks]
Cc: stable@kernel.org
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-04 09:39:08 +00:00
Chris Wilson 085ce26437 drm/i915: Ensure that if we ever try to pin+fence it is mappable.
When merging Daniel's full-gtt patches I had a set of tweaks which I
thought I had undone. I was half right...

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=31286
Reported-by: jinjin.wang@intel.com
Reported-by: Alexey Fisher <bug-track@fisher-privat.net>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-03 09:31:57 +00:00
Chris Wilson 8c1812ad48 Merge branch 'drm-intel-fixes' into drm-intel-next
Immediate merge to resolve conflicts from applying a stability fix to
both branches.

Conflicts:
	drivers/gpu/drm/i915/intel_ringbuffer.c
	drivers/gpu/drm/i915/intel_ringbuffer.h
2010-11-02 10:53:29 +00:00
Jesse Barnes 80dbf4b72b drm/i915: Fix the graphics frequency clamping at init and when IPS is active.
Part of the issue here was that Eric slipped in a debug hack for
testing the i915 IPS code before the intel_ips.c driver had landed.
This caused the driver to always use the full range of frequencies,
which is only legal when IPS tells us we have the headroom.  Once that
hack was removed, there was confusion about the driver's frequency
clamping variables: max_delay is the driver's current limit on the
highest frequency the IPS driver wants us to use, while dev_priv->fmax
is the hardware-reported limit that the IPS driver can increase up to.

Tested with IPS driver loaded or not.  Note that on Ironlake systems
without the IPS driver loaded this will result in a performance
reduction, and the inital warmup of frequency limits can impact
benchmarking on systems with IPS loaded.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
[ickle: demoted a debugging printk]
Cc: stable@kernel.org
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-02 09:34:52 +00:00
Chris Wilson a00b10c360 drm/i915: Only enforce fence limits inside the GTT.
So long as we adhere to the fence registers rules for alignment and no
overlaps (including with unfenced accesses to linear memory) and account
for the tiled access in our size allocation, we do not have to allocate
the full fenced region for the object. This allows us to fight the bloat
tiling imposed on pre-i965 chipsets and frees up RAM for real use. [Inside
the GTT we still suffer the additional alignment constraints, so it doesn't
magic allow us to render larger scenes without stalls -- we need the
expanded GTT and fence pipelining to overcome those...]

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-29 11:15:07 +01:00
Daniel Vetter 920afa77ce drm/i915: range-restricted bind_to_gtt
Like before add a parameter mappable (also to gem_object_pin) and
set it depending upon the context. Only bos that are brought into
the gtt due to an execbuffer call can be put into the unmappable
part of the gtt, everything else (especially pinned objects) need
to be put into the mappable part of the gtt.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-27 23:31:05 +01:00
Chris Wilson e1f99ce6ca drm/i915: Propagate errors from writing to ringbuffer
Preparing the ringbuffer for adding new commands can fail (a timeout
whilst waiting for the GPU to catch up and free some space). So check
for any potential error before overwriting HEAD with new commands, and
propagate that error back to the user where possible.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-27 23:26:34 +01:00
Chia-I Wu dc3f82c2e5 drm/i915: Fix current fb blocking for page flip
Block execbuffer for the fb to be flipped away, not the one that is to
be flipped in.

[ickle: rewritten for -next]
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Acked-by: Kristian Høgsberg <krh@bitplanet.net>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-21 19:38:25 +01:00
Chris Wilson f00a3ddf91 drm/i915: IS_IRONLAKE is synonymous with gen == 5
So remove the redundant bit in the capabilities block and
s/IS_IRONLAKE/IS_GEN5/.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-21 19:08:39 +01:00
Chris Wilson 8b99e68c0a drm/i915: restore fixed FDI link rate on Sandybridge
FDI_PLL_BIOS_0 register is for Ironlake only, don't apply to
Sandybridge.

Original-patch-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-19 09:16:52 +01:00
Chris Wilson fb9a90f7c6 Merge remote branch 'airlied/drm-core-next' into tmp 2010-10-19 09:14:50 +01:00
Jason Wessel 21c74a8ea8 drm, kdb, kms: Change mode_set_base_atomic() enter argument to be an enum
The enter argument as implemented by commit 413d45d362 (drm, kdb, kms:
Add an enter argument to mode_set_base_atomic() API) should be more
descriptive as to what it does vs just passing 1 and 0 around.

There is no runtime behavior change as a result of this patch.

Reported-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Jason Wessel <jason.wessel@windriver.com>
CC: David Airlie <airlied@linux.ie>
CC: dri-devel@lists.freedesktop.org
Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-10-19 14:13:33 +10:00
Jesse Barnes 382b093627 drm/i915: diasable clock gating for the panel power sequencer
Needed on Ibex Peak and Cougar Point or the panel won't always come on.

Cc: stable@kernel.org
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-08 10:28:28 +01:00
Jesse Barnes 8088699f02 drm/i915: don't program FDI RX/TX in mode_set
We do this later (and more properly) when we enable FDI, so we don't
need to do it here.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-08 10:28:25 +01:00
Jesse Barnes 17f6766c62 drm/i915: fix ironlake CRTC enable/disable
Wait for vblank after enabling a pipe, make the error messages more
informative, and wait for the pipe to turn off when we disable it.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-08 10:28:24 +01:00
Jesse Barnes 8324012087 drm/i915: use DPLL_DVO_HIGH_SPEED for PCH eDP
As with other PCH DP connections.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-08 10:28:23 +01:00
Jesse Barnes 1cb1b75e5e drm/i915: use 120MHz refclk in PCH eDP case too
CPU eDP needs a different reference clock than PCH eDP, which uses the
standard PCH refclk of 120MHz.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-08 10:28:23 +01:00
Jesse Barnes 7f82328268 drm/i915: fix PCH eDP SSC support
Enable SSC on PCH eDP if possible.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
[ickle: added a posting read of PCH_DREF_CONTROL before the udelay]
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-08 10:28:22 +01:00
Jesse Barnes 5b2adf8971 drm/i915: add Ironlake clock gating workaround for FDI link training
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-08 10:28:21 +01:00
Jesse Barnes 723bfd707a drm/i915: add _DSM support
The _DSM method on the integrated graphics device can tell us which
connectors are muxable, so add support for making the call and parsing
out the connector info.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
[ickle: fix compiler warnings for using uninitialized 'result' and
downgrade error message for non-switchable devices]
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-08 10:27:43 +01:00
Jesse Barnes 5c5313c8db drm/i915: fix CPU vs PCH eDP confusion
FDI training needs to done and idle for PCH eDP and before we turn the
pipes on, and various eDP checks need to account for PCH attached eDP.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-08 09:24:19 +01:00
Jesse Barnes 1d85036278 drm/i915: remove broken intel_pch_has_edp function
Since we set the output type of PCH attached eDP panels to
INTEL_OUTPUT_eDP this function would never return true when it should.
It's been replaced by working functions.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-08 09:23:18 +01:00
Chris Wilson e59f2bac15 drm/i915: Wait for pending flips on the GPU
Currently, if a batch buffer refers to an object with a pending flip,
then we sleep until that pending flip is completed (unpinned and
signalled). This is so that a flip can be queued and the user can
continue rendering to the backbuffer oblivious to whether the buffer is
still pinned as the scan out. (The kernel arbitrating at the last moment
to stall the batch and wait until the buffer is unpinned and replaced as
the front buffer.)

As we only have a queue depth of 1, we can simply wait for the current
pending flip to complete and continue rendering. We can achieve this
with a single WAIT_FOR_EVENT command inserted into the ring buffer prior
to executing the batch, *without* stalling the client.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-07 19:10:09 +01:00
Jason Wessel 413d45d362 drm, kdb, kms: Add an enter argument to mode_set_base_atomic() API
Some devices such as the radeon chips receive information from user
space which needs to be saved when executing an atomic mode set
operation, else the user space would have to be queried again for the
information.

This patch extends the mode_set_base_atomic() call to pass an argument
to indicate if this is an entry or an exit from an atomic kernel mode
set change.  Individual drm drivers can properly save and restore
state accordingly.

Signed-off-by: Jason Wessel <jason.wessel@windriver.com>
CC: Jesse Barnes <jbarnes@virtuousgeek.org>
CC: David Airlie <airlied@linux.ie>
CC: dri-devel@lists.freedesktop.org
Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-10-06 11:50:31 +10:00
Chris Wilson 7b4f3990a2 drm/i915: Avoid circular locking from intel_fbdev_fini()
lockdep spots that the fb_info->lock takes the dev->struct_mutex during
init (due to the device probing) and so we can not hold
dev->struct_mutex when unregistering the framebuffer. Simply reverse the
order of initialisation during cleanup and so do the intel_fbdev_fini()
before the intel_modeset_cleanup.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-04 16:11:54 +01:00
Keith Packard f87ea76131 drm/i915: avoid struct mutex output_poll mutex lock loop on unload
Cancel the output polling work proc before acquiring the struct mutex
to avoid acquiring the work proc mutex with the struct mutex
held. This avoids inverting the lock order seen when the work proc
runs.

Signed-off-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-04 09:43:16 +01:00
Chris Wilson 58e10eb92d Merge branch 'drm-intel-fixes' into drm-intel-next
Conflicts:
	drivers/gpu/drm/i915/i915_gem_evict.c
	drivers/gpu/drm/i915/intel_display.c
	drivers/gpu/drm/i915/intel_dp.c
2010-10-03 10:56:11 +01:00
Keith Packard ab7ad7f645 drm/i915: Use pipe state to tell when pipe is off
Instead of waiting for the display line value to settle, we can simply
wait for the pipe configuration register 'state' bit to turn off.

Contrarywise, disabling the plane will not cause the display line
value to stop changing, so instead we wait for the vblank interrupt
bit to get set. And, we only do this when we're not about to wait for
the pipe to turn off.

Signed-off-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-03 10:23:26 +01:00
Chris Wilson f787a5f59e drm/i915: Only hold a process-local lock whilst throttling.
Avoid cause latencies in other clients by not taking the global struct
mutex and moving the per-client request manipulation a local per-client
mutex. For example, this allows a compositor to schedule a page-flip
(through X) whilst an OpenGL application is monopolising the GPU.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-24 21:03:00 +01:00
Chris Wilson 5ceb0f9bb7 drm/i915: Parse the eDP link configuration from the vBIOS
First step, lets have a look at the values for troublesome panels and
see if they may be used to improve our link training.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-24 14:22:11 +01:00
Chris Wilson e6c3a2a6d3 drm/i915: Use an uninterruptible wait for page-flips during modeset
We need to drain the pending flips prior to disabling the pipe during
modeset, and these need to be done in an uninterruptible fashion.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-24 14:19:57 +01:00
Chris Wilson 3eee1794ac drm/i915: Remove idle timer debugging messages
These have served their purpose and are now just noise in the debug
stream.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-24 14:19:54 +01:00
Chris Wilson 20f0cd55f6 drm/i915: Remove the broken flush_ring from page-flip
This is already performed with the pipelined flush, so by the time we
schedule the flush in the page-flip, the ring is NULL and we OOPs
instead.

Reported-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-23 11:02:55 +01:00
Chris Wilson a5cad620b3 drm/i915: Disable "disabled FBC" message when a no-op
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-22 13:15:10 +01:00
Chris Wilson cdd5998311 drm/i915: Drop crtc->fb pin on disable.
In order to handle disable_functions() where the framebuffer is
decoupled from the crtc we need to unpin the fb in order to prevent a
leak.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=29857
Reported-by: Sitsofe Wheeler <sitsofe@yahoo.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-21 11:59:21 +01:00
Chris Wilson 265db9585e drm/i915: Drain any pending flips on the fb prior to unpinning
If we have queued a page flip on the current fb and then request a mode
change, wait until the page flip completes before performing the new
request.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-21 11:24:17 +01:00
Chris Wilson c78ec30bba drm/i915: Merge ring flushing and lazy requests
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-21 11:24:16 +01:00
Chris Wilson c7f9f9a8b8 drm/i915: Use ring->flush() instead of MI_FLUSH
Use the ring abstraction to hide the details of having choose the
appropriate flushing method.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-21 11:19:59 +01:00
Chris Wilson a6c45cf013 drm/i915: INTEL_INFO->gen supercedes i8xx, i9xx, i965g
Avoid confusion between i965g meaning broadwater and the gen4+ chipset
families.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-21 11:19:45 +01:00
Chris Wilson e9e5f8e8d3 Merge branch 'drm-intel-fixes' into HEAD
Conflicts:
	drivers/char/agp/intel-agp.c
	drivers/gpu/drm/i915/intel_crt.c
2010-09-21 11:19:32 +01:00
Chris Wilson f899fc64cd drm/i915: use GMBUS to manage i2c links
Use the GMBUS interface rather than direct bit banging to grab the EDID
over DDC (and for other forms of auxiliary communication with external
display controllers). The hope is that this method will be much faster
and more reliable than bit banging for fetching EDIDs from buggy monitors
or through switches, though we still preserve the bit banging as a
fallback in case GMBUS fails.

Based on an original patch by Jesse Barnes.

Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-18 15:46:19 +01:00
Chris Wilson 2cf34d7b7e drm/i915: Allow get_fence_reg() to be uninterruptible
As we currently may need to acquire a fence register during a modeset,
we need to be able to do so in an uninterruptible manner. So expose that
parameter to the callers of the fence management code.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-14 21:08:36 +01:00
Chris Wilson 48b956c5a8 drm/i915: Push pipelining of display plane flushes to the caller
This ensures that we do wait upon the flushes to complete if necessary
and avoid the visual tears, whilst enabling pipelined page-flips.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-14 21:08:35 +01:00
Chris Wilson 7213342db5 drm/i915: Consolidate flushing the display plane
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-14 10:34:27 +01:00
Chris Wilson e2e767abd8 drm/i915: Remove redundant initialisation of crtc->pipe
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-13 17:04:15 +01:00
Chris Wilson e65d9305f5 drm/i915: Initialize intel_crtc->active
Fix a regression in the previous regression fix...

In order to turn off the pipes entirely upon the first modeset, we
pretend that BIOS (or earlier module incarnation) left them active.
The first task performed by setup_initial_configuration() is to disable
all pipes and so to avoid skipping that step and so to ensure a known
configuration we need to mark all the crtcs as active.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-13 17:04:14 +01:00
Chris Wilson f7abfe8b28 drm/i915: Fix an overlay regression from 7e7d76c
When separating out the prepare/commit into its own separate functions
we overlooked that the intel_crtc->dpms_mode was being used elsewhere to
check on the actual status of the pipe.

Track that bit of logic separately from the actual dpms mode, so there
is no confusion should we be able to handle multiple dpms modes, nor
any semantic conflict between prepare/commit and dpms.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-13 14:32:18 +01:00
Chris Wilson 6b383a7f63 drm/i915: Share crtc setup and teardown between dpms and disable/enable
This closes a couple of corner cases where we introduced and forgot
about a couple of routines that need to be called when disabling the
crtc and then re-enabling it. The code needs to be moved again so that
the common bits are shared across generations.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-13 14:26:55 +01:00
Chris Wilson e9e331a8ab drm/i915/lvds: Ensure panel is unlocked for Ironlake or the panel fitter
Commit 77d07fd9d7 introduced a regression
where by not waiting for the panel to be turned off, left the panel and
PLL registers locked across the modeset. Thus the panel remaining blank.

As pointed out by Daniel Vetter, when testing LVDS it helps to open the
laptop and look at the actual panel you are purporting to test.

A second issue with the patch was that in order to modify the panel
fitter before gen5, the pipe and the panel must have be completely
powered down. So we wait.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-13 10:25:26 +01:00
Chris Wilson 897493504a drm/i915: Ensure that the crtcinfo is populated during mode_fixup()
This should fix the mysterious mode setting failures reported during
boot up and after resume, generally for i8xx class machines.

Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=16478
Reported-and-tested-by: Xavier Chantry <chantry.xavier@gmail.com>
Buzilla: https://bugs.freedesktop.org/show_bug.cgi?id=29413
Tested-by: Daniel Vetter <daniel@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: stable@kernel.org
2010-09-12 21:20:41 +01:00
Chris Wilson ec5da01e23 drm/i915: Use msleep instead of mdelay during wait_vblank_off
Avoid a potentially long busy-wait if we not in the process of
atomically switching to the kdb console.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-12 13:34:08 +01:00
Chris Wilson 5eddb70ba2 drm/i915: Use macros to switch between equivalent pipe registers
The purpose is to make the code much easier to read and therefore reduce
the possibility for bugs.

A side effect is that it also makes it much easier for the compiler,
reducing the object size by 4k -- from just a few functions!

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-11 19:27:12 +01:00
Chris Wilson 4ed765f966 drm/i915: Tidy Ironlake watermark computation
Refactor the common code into seperate functions and use the MIN(large,
small) buffer calculation for self-refresh watermarks.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-11 10:59:57 +01:00
Chris Wilson bed4a6734b drm/i915: Fix updating FBC
We need to track different state on each generation in order to detect
when we need to refresh the FBC registers.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-11 10:50:55 +01:00
Jesse Barnes ea056c14a2 drm/i915: enable thermal reporting for IPS
Thermal reporting may not be enabled by default on some machines, so
enable the appropriate bits to allow IPS to get the data it needs from
the CPU thermal device.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-11 10:49:34 +01:00
Chris Wilson 8b3016c4f4 Merge branch 'drm-intel-fixes' into drm-intel-next 2010-09-11 09:49:58 +01:00
Chris Wilson 021357acc8 drm/i915: Use the real FDI frequency for determining b/w
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-10 23:13:51 +01:00
Chris Wilson 8c4223bee9 drm/i915: Only call udelay() when waiting for clocks to stabilise
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-10 23:13:51 +01:00
Chris Wilson d5e0d2f519 drm/i915: Ensure all PLL registers are flushed before a udelay()
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-10 23:13:50 +01:00
Jesse Barnes c64e311e65 drm/i915: set FDI RX TU size to match transmit size
This allows FDI error checking to work.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-10 23:13:49 +01:00
Jesse Barnes de9c27bf70 drm/i915: don't write TU size to N1 reg
TU size is only part of the M1 and M2 regs, not the N regs.  This keeps
us from overwriting a reserved field.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-10 23:13:48 +01:00
Jesse Barnes 0e23b99d25 drm/i915: split Ironlake FDI enable function
Easier to read, and will pair up with a disable function.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-10 23:13:48 +01:00
Jesse Barnes c98e9dcf90 drm/i915: enable PCH PLL, FDI training and transcoder even for eDP
eDP panels require these to be set up prior to panel power sequencing,
or they'll fail to power on due to an "asset not ready" check.  And of
course, eDP panels attached to anything other than DP_A need them
enabled regardless, since they'll be driven from the CPU through FDI out
to the PCH.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-10 23:13:47 +01:00
Jesse Barnes 7e7d76c306 drm/i915: use i915 and Ironlake CRTC enable/disable functions in prepare/commit
This will allow us to optimize our prepare/commit paths a bit better.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
[ickle: minor tweak to handle the cursor across pipe resizing]
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-10 23:12:55 +01:00
Jesse Barnes 0b8765c6e7 drm/i915: split i9xx CRTC enable/disable code
So we can use it for CRTC prepare/commit.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-10 22:23:45 +01:00
Jesse Barnes 6be4a6078e drm/i915: split Ironlake CRTC enable/disable code
This way we can also use it in CRTC prepare/commit.  Also makes it
easier to split out FDI and other code.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-10 22:23:44 +01:00
Jesse Barnes dd8849c8f5 drm/i915: don't enable self-refresh on Ironlake
We don't know how to enable it safely, especially as outputs turn on and
off.  When disabling LP1 we also need to make sure LP2 and 3 are already
disabled.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=29173
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=29082
Reported-by: Chris Lord <chris@linux.intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Tested-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: stable@kernel.org
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-10 15:11:43 +01:00
Chris Wilson df0e924883 drm/i915: Make the connector->encoder relationship explicit
Currently we have a exact mapping of a connector onto an encoder for its
whole lifetime. Make this an explicit property of the structure and so
simplify the code.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2010-09-09 17:00:43 +01:00
Chris Wilson f875c15a4f drm/i915: Use the direct mapping of pipe->crtc
Why iterate all the crtcs to find the pipe, when we already know which
crtc is attached to which pipe?

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2010-09-09 17:00:36 +01:00
Chris Wilson 4ef69c7a64 drm/i915: Rename intel_encoder->enc to base for consistency
[Patch is slightly larger than is strictly necessary to fixup
surrounding checkpatch.pl errors.]

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2010-09-09 17:00:13 +01:00
Jesse Barnes 434ed09724 drm/i915: set dither bits on eDP panels too
We really need a macro to test whether a given connector has a panel
attached rather than sprinkling HAS_PCH_SPLIT/IS_eDP/has_edp_encoder
etc all over. In the meantime, fix the bug...

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
[ickle: tidy up the duplicity in the conditionals]
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-08 12:44:12 +01:00
Jesse Barnes 4f0d1aff79 drm/i915: fix pipeconf dither bit definitions
Make them match the others and add BPP definitions.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-08 12:38:17 +01:00
Chris Wilson 4b60e5cb70 drm/i915: Clear scanline waits after disabling the pipe.
If we disable the pipe and the GPU is currently waiting on a scanline
WAIT_FOR_EVENT, the GPU will hang. Fortunately, there is a magic bit
which we can write on i915+ to break this wait after disabling the
pipe.

References:

  Bug 29252 - [Arrandale] Hung WAIT_FOR_EVENT when running rss-glx-skyrocket
  https://bugs.freedesktop.org/show_bug.cgi?id=29252

  Bug 28964 - [i965gm] GPU infinite MI_WAIT_FOR_EVENT while watching video in Totem
  https://bugs.freedesktop.org/show_bug.cgi?id=28964

and many others.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
2010-09-08 11:29:58 +01:00
Chris Wilson 23f09ce31c drm/i915/overlay: Make the overlay control struct opaque.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2010-09-08 10:23:53 +01:00
Chris Wilson 5dcdbcb06b drm/i915/overlay: Pass interruptible to switch_off()
During DPMS we currently do not want the overlay code to be
interruptible, so pass that information down and only take the
uninterrruptible paths.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2010-09-08 10:23:52 +01:00
Chris Wilson 6c9547ff35 drm/i915/sdvo: Preserve pixel-multiplier
Store the pixel-multiplier on the adjusted mode and avoid modifying the
requested mode.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-08 10:23:27 +01:00
Chris Wilson 57cd6508da drm/i915: Sanity check user framebuffer parameters on creation
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-08 10:13:37 +01:00
Sitsofe Wheeler efe8c25680 drm/i915: Revert extra intel_wait_for_vblank to prevent stalls.
With the extra intel_wait_for_vblank added in commit
9d0498a2bf periodic stalls were being
triggered (which were detected by i915_hangcheck_elapsed). Partially
revert this change for now.

Signed-off-by: Sitsofe Wheeler <sitsofe@yahoo.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-08 10:13:34 +01:00
Chris Wilson 481b6af3d1 drm/i915: Drop the msleep parameter to wait_for()
Jesse's feedback from using the wait_for() macro was that the msleep
argument was that it was superfluous and made the macro more difficult
to use and to read. As the actually amount of time to sleep is not
critical, the crucial part is to sleep and let the processor schedule
something else whilst we wait for the event, replace the argument with a
hardcoded value.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
2010-09-08 10:13:29 +01:00
Daniel Vetter 67e77c5ae8 drm/i915: unload: fix unpin_work related races
Kill any outstanding unpin_work when destroying the corresponding
crtc. Then flush the workqueue before the gem teardown, in case
any unpin work is still outstanding.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-08 10:13:27 +01:00
Daniel Vetter 3dec0095f7 drm/i915: unload: fix idle_timer/idle_work races
idle_work wasn't cleaned up at all. It takes &dev->struct_mutex, but
accesss the mode_config crtc list (without any other locking!). Hence
this work needs to be canceled before calling drm_mode_config_cleanup.

As evidenced by the kernel's object debuggin code, the current code
also cleans up the timer to early (it gets rearmed). So move it right
before the final cleanup (it seems to work).

Also unconditionally set up the idle_timer in intel_increase_pllclock.
If we're unlucky the timer might fire right away, rendering the call
in the modesetting teardown pointless.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-08 10:13:26 +01:00
Daniel Vetter 6c0d93500e drm/i915: unload: fix hotplug_work races
hotplug_work is queued by the hotplug interrupt and only either emits
a hotplug uevent or queues a crt poll slow-work. No other locking.  So
it's safe to cancel this work _after_ irq's have been turned off.  But
before the modesetting objects are destroyed because the hotplug
function accesses them (without locking).

The current code (for kms) only switches irqs off after modesetting
teardown, hence move the irq teardown into the modeset cleanup right
before the crtc cleanup.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-08 10:13:24 +01:00
Chris Wilson c3add4b634 Revert "drm/i915: Warn if we run out of FIFO space for a mode"
This reverts commit b9421ae8f3.

This warning was so prelevant, even for apparently working machines,
that it was just causing fear, anxiety and panic.

The root cause still remains, so we will add some better debugging when
we focus on fixing it.

Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=17021
Reported-by: Maciej Rutecki <maciej.rutecki@gmail.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-08 09:22:52 +01:00
Chris Wilson bc41606aef Revert "drm/i915: Enable RC6 on Ironlake."
This reverts commit ce17178094.

This commit has been independently bisected a few times as being the cause
of a s2ram failure.

Reported-and-tested-by: Kyle McMartin <kyle@mcmartin.ca>
Reported-and-tested-by: Andy Isaacson <adi@hexapodia.org>
Cc: Zou Nan hai <nanhai.zou@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-07 21:55:52 +01:00
Chris Wilson 032d2a0d06 drm/i915: Prevent double dpms on
Arguably this is a bug in drm-core in that we should not be called twice
in succession with DPMS_ON, however this is still occuring and we see
FDI link training failures on the second call leading to the occassional
blank display. For the time being ignore the repeated call.

Original patch by Dave Airlie <airlied@redhat.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: stable@kernel.org
2010-09-07 11:16:41 +01:00
Chris Wilson 52be119648 drm/i915: Avoid use of uninitialised values when disabling panel-fitter
We were passing garbage values into the panel-fitter control register
when disabling it on Ironlake - those values (filter modes and reserved
MBZ bits) would have then be re-used the next time panel-fitting was
enabled.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-07 11:16:40 +01:00
Simon Farnsworth 4e5359cd05 drm/i915: Avoid pageflipping freeze when we miss the flip prepare interrupt
When we miss the flip prepare interrupt, we never get into the
software state needed to restart userspace, resulting in a freeze of a
full-screen OpenGL application (such as a compositor).

Work around this by checking DSPxSURF/DSPxBASE to see if the page flip
has actually happened. If it has, do the work we would have done when
the flip prepare interrupt comes in.

Also, add debugfs information to tell us what's going on (based on the
patch from Chris Wilson attached to bugs.fdo bug #29798).

Signed-off-by: Simon Farnsworth <simon.farnsworth@onelan.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-07 11:16:35 +01:00
Chris Wilson 8e647a279c drm/i915: Tightly scope intel_encoder to prevent invalid use
We reset intel_encoder for every matching encoder whilst iterating over
the encoders attached to this crtc when changing mode. As such in a
cloned configuration intel_encoder may not correspond to the correct
is_edp encoder.

By scoping intel_encoder to the loop, not only is the compiler able to
spot this mistake, we also improve readiability for ourselves.
[It might not be a mistake, within this function it is unclear as to
whether it is permissable for eDP to be cloned...]

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-07 11:14:19 +01:00
Chris Wilson 0ad6ef2c58 drm/i915/dp: Boost timeout for enabling transcoder to 100ms
Adam Hill reported that his Arrandale system required a much longer, up
to 200x500us, wait for the panel to initialise or else modesetting would
fail.

References:

  https://bugs.freedesktop.org/show_bug.cgi?id=29141

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reported-and-tested-by: Adam Hill <sidepipeuk@yahoo.co.uk>
2010-09-07 11:14:16 +01:00
Chris Wilson 4e6cfefc72 drm/i915: Re-use set_base_atomic to share setting of the display registers
Lets try to avoid repeating old bugs.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2010-09-07 11:14:10 +01:00
Chris Wilson 52e68630d1 drm/i915: Fix offset page-flips on i965+
i965 uses the Display Registers to compute the offset from the display
base so the new base does not need adjusting when flipping. The older
chipsets use a fence to access the display and so do perceive the
surface as linear and have a single base register which is reprogrammed
using the flip.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
Reported-by: Marty Jack <martyj19@comcast.net>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2010-09-07 11:13:00 +01:00
Chris Wilson 300387c0b5 drm/i915: Clear the vblank status bit before polling for the next vblank
The vblank status bit is a sticky bit that must be cleared with a write
of '1' prior to polling for the next vblank.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Tested-by: Sitsofe Wheeler <sitsofe@yahoo.com>

jbarnes: I'd still rather see a lock, but I think you're right that
we don't generally wait in code that needs not to miss an interrupt.
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2010-09-06 23:09:51 +01:00
Jesse Barnes 9559fcdbff drm/i915: fix vblank wait test condition
When converting this to the new wait_for macro I inverted the wait
condition, which causes all sorts of problems.  So correct it to fix
several failures caused by the bad wait (flickering, bad output
detection, tearing, etc.).

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Tested-by: Sitsofe Wheeler <sitsofe@yahoo.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2010-08-24 11:41:08 -07:00
Linus Torvalds 4238a417a9 Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel: (58 commits)
  drm/i915,intel_agp: Add support for Sandybridge D0
  drm/i915: fix render pipe control notify on sandybridge
  agp/intel: set 40-bit dma mask on Sandybridge
  drm/i915: Remove the conflicting BUG_ON()
  drm/i915/suspend: s/IS_IRONLAKE/HAS_PCH_SPLIT/
  drm/i915/suspend: Flush register writes before busy-waiting.
  i915: disable DAC on Ironlake also when doing CRT load detection.
  drm/i915: wait for actual vblank, not just 20ms
  drm/i915: make sure eDP PLL is enabled at the right time
  drm/i915: fix VGA plane disable for Ironlake+
  drm/i915: eDP mode set sequence corrections
  drm/i915: add panel reset workaround
  drm/i915: Enable RC6 on Ironlake.
  drm/i915/sdvo: Only set is_lvds if we have a valid fixed mode.
  drm/i915: Set up a render context on Ironlake
  drm/i915 invalidate indirect state pointers at end of ring exec
  drm/i915: Wake-up wait_request() from elapsed hang-check (v2)
  drm/i915: Apply i830 errata for cursor alignment
  drm/i915: Only update i845/i865 CURBASE when disabled (v2)
  drm/i915: FBC is updated within set_base() so remove second call in mode_set()
  ...
2010-08-22 11:03:27 -07:00
Jesse Barnes 9d0498a2bf drm/i915: wait for actual vblank, not just 20ms
Waiting for a hard coded 20ms isn't always enough to make sure a vblank
period has actually occurred, so add code to make sure we really have
passed through a vblank period (or that the pipe is off when disabling).

This prevents problems with mode setting and link training, and seems to
fix a bug like https://bugs.freedesktop.org/show_bug.cgi?id=29278, but
on an HP 8440p instead.  Hopefully also fixes
https://bugs.freedesktop.org/show_bug.cgi?id=29141.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
2010-08-21 22:59:23 -07:00
Jesse Barnes d240f20f54 drm/i915: make sure eDP PLL is enabled at the right time
We need to make sure the eDP PLL is enabled before the pipes or planes,
so do it as part of the DP prepare mode set function.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2010-08-18 13:21:50 -07:00
Jesse Barnes 9cce37f485 drm/i915: fix VGA plane disable for Ironlake+
We need to use I/O port instructions to access VGA registers on
Ironlake+, and it doesn't hurt on other platforms, so switch the VGA
plane disable function over to using them.  Move it to init time as well
while we're at it, no need to repeatedly disable the VGA plane with
every mode set and DPMS event.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2010-08-18 13:21:45 -07:00
Linus Torvalds aa9f56b66d Merge branch 'drm-core-next' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6
* 'drm-core-next' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: (55 commits)
  io-mapping: move asm include inside the config option
  vgaarb: drop vga.h include
  drm/radeon: Add probing of clocks from device-tree
  drm/radeon: drop old and broken mesa warning
  drm/radeon: Fix pci_map_page() error checking
  drm: Remove count_lock for calling lastclose() after 58474713 (v2)
  drm/radeon/kms: allow FG_ALPHA_VALUE on r5xx
  drm/radeon/kms: another r6xx/r7xx CS checker fix
  DRM: Replace kmalloc/memset combos with kzalloc
  drm: expand gamma_set
  drm/edid: Split mode lists out to their own header for readability
  drm/edid: Rewrite mode parse to use the generic detailed block walk
  drm/edid: Add detailed block walk for VTB extensions
  drm/edid: Add detailed block walk for CEA extensions
  drm: Remove unused fields from drm_display_info
  drm: Use ENOENT consistently for the error return for an unmatched handle.
  drm/radeon/kms: mark 3D power states as performance
  drm: Only set DPMS once on the CRTC not after every encoder.
  drm/radeon/kms: add additional quirk for Acer rv620 laptop
  drm: Propagate error code from fb_create()
  ...

Fix up trivial conflicts in drivers/gpu/drm/drm_edid.c
2010-08-12 09:21:39 -07:00
James Simmons 7203425a94 drm: expand gamma_set
Expand the crtc_gamma_set function to accept a starting offset. The
reason for this is to eventually use this function for setcolreg from
drm_fb_helper.c. The fbdev colormap function can start at any offset in
the color map.

Signed-by: James Simmons <jsimmons@infradead.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-08-10 10:47:00 +10:00
Chris Wilson cce13ff759 drm: Propagate error code from fb_create()
Change the interface to expect a PTR_ERR specifing the real error code
as opposed to assuming a NULL return => -EINVAL. Just once the user may
not be at fault!

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-08-10 10:46:51 +10:00
Zou Nan hai ce17178094 drm/i915: Enable RC6 on Ironlake.
RC6 allows the GPU to enter a lower power state when the GPU is idle.

Signed-off-by: Zou Nan hai <nanhai.zou@intel.com>
[anholt: Fixed the !renderctx error path to actually not enable RC6.]
Signed-off-by: Eric Anholt <eric@anholt.net>
2010-08-09 14:13:39 -07:00
Zou Nan hai aa40d6bbb9 drm/i915: Set up a render context on Ironlake
RC6 power state requires a logical render context in place for saving
render context.

Signed-off-by: Zou Nan hai <nanhai.zou@intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
2010-08-09 11:34:12 -07:00
Chris Wilson 6eeefaf3c8 drm/i915: Apply i830 errata for cursor alignment
i830 requires 32bpp cursors to be aligned to 16KB, so we have to expose
the alignment parameter to i915_gem_attach_phys_object().

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Eric Anholt <eric@anholt.net>
2010-08-09 11:24:36 -07:00
Chris Wilson 560b85bb75 drm/i915: Only update i845/i865 CURBASE when disabled (v2)
The i845 and i865 have a peculiarlity in that CURBASE is not the trigger
for the vsync update of the cursor registers but instead the
modification of that register is prohibited whilst the cursor is
enabled. Reorder the write sequence for CURPOS, CURCNTR and CURBASE on
i845 to i865 to match.

v2: Remove the checks for i845/i865 from within i9xx_cursor_update()

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Eric Anholt <eric@anholt.net>
2010-08-09 11:24:36 -07:00