This patch fixes the following DTC warnings for am3517-craneboard.dtb:
"fixedregulator@0 has a unit name, but no reg property"
Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This patch fixes the following DTC warnings for omap2430-sdp.dtb:
"func_96m_ck has a reg or ranges property, but no unit name"
Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Fix pll3x2 and pll7x2 not having a parent clock, specifically this
fixes the kernel turning of pll3 while simplefb is using it when
uboot has configured things to use pll3x2 as lcd ch clk parent.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Add support for the Broadcom BCM953012 Enterprise Router reference
board, enable the following peripherals:
- UART0 (UART1 is not populated)
- WPS and restart GPIO buttons
- Ethernet switch w/ only two facing ports
- NAND flash
- SPI-NOR flash
Acked-by: Jon Mason <jon.mason@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Add "ti,cpsw-mdio" for am335x/am437x/dra7 SoCs where MDIO is
implemented as part of TI CPSW and, this way, enable PM runtime auto
suspend for Davinci MDIO driver on these paltforms.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Add support for the Computer on Module Colibri iMX7S/iMX7D along
with the development/evaluation carrier board device trees. Follow
the usual hierarchic include model, maintaining shared configuration
in imx7-colibri.dtsi and imx7-colibri-eval-v3.dtsi respectively.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The base device tree uses KEY_POWER in the snvs-powerkey node,
hence include the input.h header file in the base device tree.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The i.MX 7Solo implements a subset of features available on
i.MX 7Dual. Recreate imx7s.dtsi as the base device tree for
i.MX 7Dual boards. The i.MX 7Dual's additional features over
i.MX 7Solo are:
- Second Cortex-A7 core
- Second Gigabit Ethernet controller
- EPD (Electronc Paper Display, not yet part of the device tree)
- PCIe (not yet part of the device tree)
- Additional USB2.0 OTG controller
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The i.MX 7 series currently consists of two SoCs: i.MX 7Solo and
7Dual. The former has a subset of features of the latter, hence
use imx7s.dtsi as the new base device tree. To keep diffstat nice,
just move imx7d.dtsi to imx7s.dtsi temporarily and recreate
imx7d.dtsi in a second commit.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
bx50v3 boards can be powered off via GPIO, this patch specifies the GPIO to
be used with the gpio-poweroff driver.
Signed-off-by: Ken Lin <ken.lin@advantech.com.tw>
Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add support for cortex-a7-pmu present on ipq4019 SoCs.
Signed-off-by: Thomas Pedersen <twp@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This is the first Dragonboard based on APQ8060 and PM8058. It
was produced in 2011 in cooperation between Qualcomm and
BSQUARE.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
There is currently a fixed regulator in the .dtsi file for
the MSM8660 chipset, used by the SURF board. We want to define
real regulators for a board using this chipset, so push the fixed
regulator down to the SURF board which is the only user.
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
The RTC was defined on 0x11d but on the MSM8660/APQ8060 it is
actually on 0x1e8. We were saved by the fact that the driver does
not use the reg parameter: instead it uses the compatible string
to figure out where the RTC is.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
The I2C block on the GSBI12 is used on the APQ8060 Dragonboard for
sensors. Make it available in the chipset file.
Take this opportunity to fix the IRQ flag "0" to "NONE" using the
IRQ DT include.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This adds the L2CC IPC resource and RPM devices plus the nodes
for the PM8901 and PM8058 regulators to the MSM8660 device tree.
This was tested on the APQ8060 Dragonboard.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
The SDCC5 SD/MMC controller is used for a second uSD slot
on the APQ8060 Dragonboard. On most other systems it is just
dark silicon so define it and leave it as "disabled" in the core
SoC file.
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This adds the 8660 PMIC GPIO and MPP blocks to the MSM8660
DTSI. Verified against the vendor tree to be in these locations
with these interrupts, tested on the APQ8060 Dragonboard.
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Since the pmic8xxx-pwrkey driver is already supported in the
qcom-apq8064.dtsi, and the pmic8xxx-pwrkey supports logic to
configure proper device shutdown when ps_hold goes low, it is
better to use that driver then a generic gpio button.
Thus this patch remove the gpio power key entry here, so we
don't get double input events from having two drivers enabled.
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Andy Gross <agross@codeaurora.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Stephen Boyd <stephen.boyd@linaro.org>
Cc: linux-arm-msm@vger.kernel.org
Cc: devicetree@vger.kernel.org
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: John Stultz <john.stultz@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch updates the qcom,state-cells to qcom,smem-state-cells to
match recent changes to the binding.
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch adds the qcom,controlled-remotely property for the blsp2_bam
controller node. This board requires this, otherwise the board fails to
boot due to access of protected registers during BAM initialization.
Fixes: 62bc817922 dts: msm8974: Add blsp2_bam dma node
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
This board locks up if we stress test the eMMC, as the regulator s4 is
unable to supply enough current for all the peripherials attached to it.
As this supply is wired up to most of the peripherials including DDR,
it resulted in such lockup.
This patch fixes this issue by setting s4 regulator correctly with
Auto power mode.
Reported-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
[Srinivas Kandagatla: rewrote the change log]
Tested-by: Girish Sharma <girish.sharma@einfochips.com>
Signed-off-by: Parth Pancholi <parth.pancholi@einfochips.com>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This board has been renamed recently and announced at
https://eragon.einfochips.com/products/sd-600eval.html
So rename this board files so that it reflects actual product in market.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch move sdcc3 pinctrl nodes out of board file, so that
other boards do not duplicate the same thing.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch moves out the sdcc1 pinctrl nodes out of board files to soc file,
so that it will be duplicated in other board files.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Initial release for rk3229 evb board, and turn the GMAC on.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
We have the brother chipset that RK3228 and RK3229, they share most
of dts configuration, but there are a number of different features.
In order to develop the future when they are easy to distinguish,
we need them to be independent.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add the DT node for the random number generator peripheral.
Acked-by: Scott Branden <scott.branden@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
- dts: rename 'ide-disk' to 'disk-activity'
- platform: rename 'ide-disk' to 'disk-activity'
- defconfig: rename 'LEDS_TRIGGER_IDE_DISK' to 'LEDS_TRIGGER_DISK'
Signed-off-by: Stephan Linz <linz@li-pro.net>
Acked-by: Sekhar Nori <nsekhar@ti.com>
Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Jacek Anaszewski <j.anaszewski@samsung.com>
Various I/O memory fix for Cortex A9 based SoCs
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iEYEABECAAYFAldo+JYACgkQCwYYjhRyO9XI5QCglOxAOJSamD5IgIpMklk/5ZpG
/MEAn0j80ClwN+YB+/eii/iUMwHwMDQe
=iyoH
-----END PGP SIGNATURE-----
Merge tag 'mvebu-fixes-4.7-1' of git://git.infradead.org/linux-mvebu into fixes
mvebu fixes for 4.7 (part 1)
Various I/O memory fix for Cortex A9 based SoCs
* tag 'mvebu-fixes-4.7-1' of git://git.infradead.org/linux-mvebu:
ARM: dts: armada-38x: fix MBUS_ID for crypto SRAM on Armada 385 Linksys
ARM: mvebu: map PCI I/O regions strongly ordered
ARM: mvebu: fix HW I/O coherency related deadlocks
Signed-off-by: Olof Johansson <olof@lixom.net>
Describe JPEG Processing Unit (JPU) in the R8A7792 device tree.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add JPU clock and its parent, M2 clock to the R8A7792 device tree.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add the (previously omitted) DU pin data to the SILK board's device tree.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Commit 3939f33450 ("ARM: 8418/1: add boot image dependencies to
not generate invalid images") fixed bad image generation for the
parallel building, but as its side effect, Kbuild now descends into
arch/arm/boot/ again and again, duplicating the log messages.
It looks clumsy, so let's display the same message only once.
This commit moves the log rules from arch/arm/boot/Makefile to
arch/arm/Makefile. I did not delete them completely because *Image
are the final targets that users are interested in.
Without this commit, the log of incremental build is like follows:
$ make ARCH=arm UIMAGE_LOADADDR=0x80208000 uImage
CHK include/config/kernel.release
CHK include/generated/uapi/linux/version.h
CHK include/generated/utsrelease.h
CHK include/generated/bounds.h
CHK include/generated/timeconst.h
CHK include/generated/asm-offsets.h
CALL scripts/checksyscalls.sh
CHK include/generated/compile.h
Kernel: arch/arm/boot/Image is ready
Kernel: arch/arm/boot/Image is ready
Kernel: arch/arm/boot/zImage is ready
Kernel: arch/arm/boot/Image is ready
Kernel: arch/arm/boot/zImage is ready
Image arch/arm/boot/uImage is ready
With this commit, it will look like follows:
$ make ARCH=arm UIMAGE_LOADADDR=0x80208000 uImage
CHK include/config/kernel.release
CHK include/generated/uapi/linux/version.h
CHK include/generated/utsrelease.h
CHK include/generated/bounds.h
CHK include/generated/timeconst.h
CHK include/generated/asm-offsets.h
CALL scripts/checksyscalls.sh
CHK include/generated/compile.h
Kernel: arch/arm/boot/Image is ready
Kernel: arch/arm/boot/zImage is ready
Kernel: arch/arm/boot/uImage is ready
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Now that we've a clock node describing pll3 we must add it to the
simplefb nodes clocks lists to avoid it getting turned off when
simplefb is used.
This fixes the screen going black when using simplefb.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Adding dt node for hardware random number generator IP.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
DRA7 SoC has the same SHA IP as OMAP5. Add DT entry for the same.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
[t-kristo@ti.com: changed SHA to use EDMA instead of SDMA]
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
DRA7 SoC has the same AES IP as OMAP4. Add DT entries for both AES cores.
Signed-off-by: Joel Fernandes <joelf@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
[t-kristo@ti.com: squashed in the change to use EDMA, squashed in
support for two AES cores]
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit adds the stdout-path propety in /chosen for all Beaglebone
boards.
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
- Chris provides documentation and DTS fixes for the bcm11351 CPU enable-method in preparation
for adding support for the BCM23550 SoC and its corresponding documentation, SoC dtsi
and the Sparrow board DTS file
- Jon adds MSI support to the PCI nodes, updates the secondary cores boot address for the B0
production revision of the Northstar Plus SoC, adds a DTS for the BCM958625HR board, another
one for the BCM958525XMC board, and finally adds the PL330 DMA controller to the NSP DTS
- Rafal enables the SPI NOR flash on dual flash systems (NAND + SPI) on the BCM5301x SoCs
and devices
- Florian adds support for the BCM5301x built-in Ethernet switch by adding nodes for the
Gigabit MAC controllers and the Switch Register Access block, and finally updates the
SmartRG SR-400AC board with its switch port layout
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJXY1hBAAoJEIfQlpxEBwcEY6gQAKRAF/CK920lh6BeW0JKgzix
L1J2TBirqYv/yRB0hiBY9myh61yV31SgCksgJbJrOREWTJMxx8lLve3jnCqVdzd+
ODfgb2QLGgQJZfLFaK2JHxY8NkgrrABkNEb7kIv+MCes3FrtBJHtH02y661w5goB
t5zJyvz9FeIQJULFv9jNyVpa+A7Hy8jg1Wvin62mF7uXewFEr9kcddbeXsmRw/EB
j491pFNDw4lkYecyMWyb5c4QqJEtVWIFWxCFRDf4OvG3JhzvMWfyNfhSm9t4nPUU
pxadZsnVrPPYBQq5QC0zC5bSBCZHRgTt+JsXAl557rAGePuPSKTennri3ubxwQbi
9w8PevstBXKq0J6Ynl0lrqLAUrLbnt57bq49hxMM7ur0CXGL5CdzRKRkiUme4ZsB
G5shPXsYlfpCwjAvthshb1npreUxTyxQkO6D6y3Zojb/tlNrwBvV3QmqC8Lpe4wm
7J/hznwOUyhgm+IR92tSL+nyFd8gqOBAHOipUNDTQGix2BuYveAngh0I7lysVvQt
E47UAc6+y6IHt7iNbubZVfJ6HQnu5EZPoPwoev0/2Xbr0Bd7wBYshAYnVynkj0lf
9v47CYKNvaYDzXSacpxodA+iZMVgkGrRzoyMskaqzPgcBCnMiQeVLuivrUerx1in
yYxPjRCv+QMd1qbv3K4+
=0GWx
-----END PGP SIGNATURE-----
Merge tag 'arm-soc/for-4.8/devicetree' of http://github.com/Broadcom/stblinux into next/dt
This pull request contains Device Tree changes for Broadcom ARM-based SoCs:
- Chris provides documentation and DTS fixes for the bcm11351 CPU enable-method in preparation
for adding support for the BCM23550 SoC and its corresponding documentation, SoC dtsi
and the Sparrow board DTS file
- Jon adds MSI support to the PCI nodes, updates the secondary cores boot address for the B0
production revision of the Northstar Plus SoC, adds a DTS for the BCM958625HR board, another
one for the BCM958525XMC board, and finally adds the PL330 DMA controller to the NSP DTS
- Rafal enables the SPI NOR flash on dual flash systems (NAND + SPI) on the BCM5301x SoCs
and devices
- Florian adds support for the BCM5301x built-in Ethernet switch by adding nodes for the
Gigabit MAC controllers and the Switch Register Access block, and finally updates the
SmartRG SR-400AC board with its switch port layout
* tag 'arm-soc/for-4.8/devicetree' of http://github.com/Broadcom/stblinux:
ARM: dts: BCM5310x: Enable switch ports on SmartRG SR400AC
ARM: dts: BCM5301X: Add SRAB interrupts
ARM: dts: Enable SRAB switch and GMACs on 5301x DTS
ARM: dts: NSP: Add PL330 support
ARM: dts: NSP: Add XMC board support
ARM: dts: bcm23550: Add device tree files
Documentation: devicetree: Document BCM23550 bindings
ARM: BCM5301X: Enable SPI-NOR on dual flash devices
ARM: dts: NSP: Add new DT file for bcm958625hr
ARM: dts: NSP: modify second CPU address
ARM: dts: NSP: Add MSI support on PCI
ARM: BCM: modify Broadcom CPU enable method
ARM: dts: fix use of bcm11351 enable method
Documentation: Binding docs for bcm11351 enable method
Signed-off-by: Olof Johansson <olof@lixom.net>
- Fix dra7 for hardware issues limiting L4Per and L3init power domains
to on state. Without this the devices may not work correctly after
some time of use because of asymmetric aging. And related to this,
let's also remove the unusable states.
- Always select omap interconnect for am43x as otherwise the am43x
only configurations will not boot properly. This can happen easily
for any product kernels that leave out other SoCs to save memory.
- Fix DSS PLL2 addresses that have gone unused for now
- Select erratum 430973 for omap3, this is now safe to do and can
save quite a bit of debugging time for people who may have left
it out.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJXXm6cAAoJEBvUPslcq6VzgiAP/3j+Zvaks93gLf0Hc1sQ5ow+
UxQ3Gb3/gVGEh1OSb/c4MI800UBK1B0f6CqLK7zDFAuDHyUwmqJ27nrARfazoMPD
DxRYZoEs897peB0/SWwDtHR+yje5UmIB0P31kRJ+t5nYwXBKvmvkWPFrOISxgI1Z
yLc62tFoVy37IYfeH6pRNwMyJz9scl4qXjiBCHTmBQvgo4I3IPpvhFAWN5YMBZlz
VwXDtmR9B/WlcRYel+RplYQrQrXVvaaT01wTPfejKHI9dyNQmbJQDWFMuuvdQKjE
O7yjcgR6DdWjdDwCmIHLuc2FyrwW+wt1AY/5UXKGroxfW6Ct3JKuhUPPxsHfRMKX
2NnQtgUcUxiIAGrsEZFadUAIEedd+DBVK+aztn1reaaHR1R/pBnMcEnch9WRuAOQ
srOaaL2Had/NG+QRE0psgck9ayzpDHw+LMd18BckCN+1mIiFBnXYZrCVUPrutgPP
5RbDWIeSVeAwbdaxPRqkXOcMGZ1MDRGoS+UBlTms+gWuSLjFj6sye0+Dao+68Ehz
im/xhh0YCHgN0TvuvTla5BgLgOunlCNtXMNWyg801lDIvzOj/ngEQlasng9uzuri
mfGf5w8ctub0Ileq4eU+rYb+bRDiDagjmiVBjbRmLWtgOUcsrNr+FX9sp5NDELmS
oEa/VB8jNmI3aSv6OrNi
=mQyc
-----END PGP SIGNATURE-----
Merge tag 'omap-for-v4.7/fixes-powedomain' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into fixes
Fixes for omaps for v4.7-rc cycle:
- Fix dra7 for hardware issues limiting L4Per and L3init power domains
to on state. Without this the devices may not work correctly after
some time of use because of asymmetric aging. And related to this,
let's also remove the unusable states.
- Always select omap interconnect for am43x as otherwise the am43x
only configurations will not boot properly. This can happen easily
for any product kernels that leave out other SoCs to save memory.
- Fix DSS PLL2 addresses that have gone unused for now
- Select erratum 430973 for omap3, this is now safe to do and can
save quite a bit of debugging time for people who may have left
it out.
* tag 'omap-for-v4.7/fixes-powedomain' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP: DRA7: powerdomain data: Remove unused pwrsts_mem_ret
ARM: OMAP: DRA7: powerdomain data: Remove unused pwrsts_logic_ret
ARM: OMAP: DRA7: powerdomain data: Set L3init and L4per to ON
ARM: OMAP2+: Select OMAP_INTERCONNECT for SOC_AM43XX
ARM: dts: DRA74x: fix DSS PLL2 addresses
ARM: OMAP2: Enable Errata 430973 for OMAP3
+ Linux 4.7-rc2
Signed-off-by: Olof Johansson <olof@lixom.net>
- Two boot warning fixes from the RCU tree that should have gotten
merged several weeks ago already but did not because of issues
with who merges them. Paul has now split the RCU warning fixes into
sets for various maintainers.
- Fix ams-delta FIQ regression caused by omap1 sparse IRQ changes
- Fix PM for omap3 boards using timer12 and gptimer, like the
original beagleboard
- Fix hangs on am437x-sk-evm by lowering the I2C bus speed
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJXY8wuAAoJEBvUPslcq6VzGBQQAJ6OIH0Gws19Wyi8IqnjMLJN
npu+JXU0xP5bBZ+HbCVjyN8k32drhXdwDMQ+u1DvBYwUuyLIIRZPZF4aHb8fDfOC
v1VqUzQRzj1FCh9MlkdqTedA180WCo5PCGlFOon0BmaZlv9WevEaTOYrEgyZPrmk
quBnaE+baZfGxWBbDSN+OrGYobQRs7Eu8bel0gh628CDiajrbwlIyAcNdEn5C/Uu
GHiEuIQcxb4b62mwAwh/t7el9ureirsS1b6mFB41puPmF/lYawI6YaCWIL48lbMd
XsgKGnFDU6dgSO5QRx5PhP/7YP9FetS0U+g7iFhgjmArNCraNQYBY0ltMweOG0qe
M8BPxDuCnhm1Q+PcjBORteN/PF47kcnBMpiJVVTmq5JRlXUqXecKpoScCt9HfPgy
EJq+esLQNIuRw9cEwVPQBj80GyxFUVqL/Rzo7xjEwTDPYRQERGCB7V68iV25on3w
07dOVl/lSwe902ik580wnlGUq+J09wk+9hIKV2XwQAV/8mKaWMc3pA8rE/efLJoC
buAsccxVcEsR3+uLSsU/P+fFm8nfBRmiOO9yIR4gez0BhbiDMc1zpwwhLkI+vTT4
D3PnuUdVeBvoGTNnpwqSURxajhaK0DSKTwhWnWGubYfXd3B48sW76rvKLO1FThgL
qyaed06QFeWj8gV+VZLb
=P0Vi
-----END PGP SIGNATURE-----
Merge tag 'fixes-rcu-fiq-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into fixes
Fixes for omaps for v4.7-rc cycle:
- Two boot warning fixes from the RCU tree that should have gotten
merged several weeks ago already but did not because of issues
with who merges them. Paul has now split the RCU warning fixes into
sets for various maintainers.
- Fix ams-delta FIQ regression caused by omap1 sparse IRQ changes
- Fix PM for omap3 boards using timer12 and gptimer, like the
original beagleboard
- Fix hangs on am437x-sk-evm by lowering the I2C bus speed
* tag 'fixes-rcu-fiq-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: dts: am437x-sk-evm: Reduce i2c0 bus speed for tps65218
ARM: OMAP2+: timer: add probe for clocksources
ARM: OMAP1: fix ams-delta FIQ handler to work with sparse IRQ
arm: Use _rcuidle for smp_cross_call() tracepoints
arm: Use _rcuidle tracepoint to allow use from idle
Signed-off-by: Olof Johansson <olof@lixom.net>
This patch fixes a non-booting issue in Mainline.
When booting with a compressed kernel, we need to be careful how we
populate memory close to DDR start. AUTO_ZRELADDR is enabled by default
in multi-arch enabled configurations, which place some restrictions on
where the kernel is placed and where it will be uncompressed to on boot.
AUTO_ZRELADDR takes the decompressor code's start address and masks out
the bottom 28 bits to obtain an address to uncompress the kernel to
(thus a load address of 0x42000000 means that the kernel will be
uncompressed to 0x40000000 i.e. DDR START on this platform).
Even changing the load address to after the co-processor's shared memory
won't render a booting platform, since the AUTO_ZRELADDR algorithm still
ensures the kernel is uncompressed into memory shared with the first
co-processor (0x40000000).
Another option would be to move loading to 0x4A000000, since this will
mean the decompressor will decompress the kernel to 0x48000000. However,
this would mean a large chunk (0x44000000 => 0x48000000 (64MB)) of
memory would essentially be wasted for no good reason.
Until we can work with ST to find a suitable memory location to
relocate co-processor shared memory, let's disable the shared memory
nodes. This will ensure a working platform in the mean time.
NB: The more observant of you will notice that we're leaving the DMU
shared memory node enabled; this is because a) it is the only one in
active use at the time of this writing and b) it is not affected by
the current default behaviour which is causing issues.
Fixes: fe135c6 (ARM: dts: STiH407: Move over to using the 'reserved-memory' API for obtaining DMA memory)
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Reviewed-by Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
There is no reason to hold s/w dependent parameter in device tree.
Even more, there is no reason in this parameter because davinici_cpdma
driver splits pool of descriptors equally between tx and rx channels
anyway.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@linaro.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
Based on the latest timing specifications for the TPS65218 from the data
sheet, http://www.ti.com/lit/ds/symlink/tps65218.pdf, document SLDS206
from November 2014, we must change the i2c bus speed to better fit within
the minimum high SCL time required for proper i2c transfer.
When running at 400khz, measurements show that SCL spends
0.8125 uS/1.666 uS high/low which violates the requirement for minimum
high period of SCL provided in datasheet Table 7.6 which is 1 uS.
Switching to 100khz gives us 5 uS/5 uS high/low which both fall above
the minimum given values for 100 khz, 4.0 uS/4.7 uS high/low.
Without this patch occasionally a voltage set operation from the kernel
will appear to have worked but the actual voltage reflected on the PMIC
will not have updated, causing problems especially with cpufreq that may
update to a higher OPP without actually raising the voltage on DCDC2,
leading to a hang.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Signed-off-by: Aparna Balasubramanian <aparnab@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
In order to use Wake-on-Lan on RK3288 integrated MAC, we need to wake-up
the CPU on the PMT interrupt when the MAC and the PHY are in low power mode.
Adding the interrupt declaration.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
Add sata support to the Northstar Plus SoC device tree.
Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Tejun Heo <tj@kernel.org>
When the support for the Marvell crypto engine was added in the Device
Tree of the various Armada 385 Device Tree files in commit
d716f2e837 ("ARM: mvebu: define crypto SRAM ranges for all armada-38x
boards"), a typo was made in the MBus window attributes for the Armada
385 Linksys board: 0x09/0x05 are used instead of 0x19/0x15. This commit
fixes this typo, which makes the CESA engines operational on Armada 385
Linksys boards.
Reported-by: Terry Stockert <stockert@inkblotadmirer.me>
Cc: Terry Stockert <stockert@inkblotadmirer.me>
Cc: Imre Kaloz <kaloz@openwrt.org>
Cc: Boris Brezillon <boris.brezillon@free-electrons.com>
Cc: <stable@vger.kernel.org>
Fixes: d716f2e837 ("ARM: mvebu: define crypto SRAM ranges for all armada-38x boards")
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
The sun4i-timer driver registers its sched_clock only if the machine is
compatible with "allwinner,sun5i-a13", "allwinner,sun5i-a10s" or
"allwinner,sun4i-a10".
Add the missing "allwinner,sun5i-a13" string to the machine compatible.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Fixes: 465a225fb2 ("ARM: sun5i: Add C.H.I.P DTS")
Cc: <stable@vger.kernel.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
According to the imx6ul-pico-hobbit schematics the Ethernet PHY reset GPIO
is GPIO1_28, so fix it accordingly.
Also adjust the reset duration to 1ms, because the KSZ8081 datasheet
requires 500μs.
Signed-off-by: Diego Dorta <diego.dorta@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
According to Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt the
polarity of "reset-gpio" is assumed to be active-low unless a separate
property "reset-gpio-active-high" is available. So replace the inconsistent
polarity description to make the correct active-low reset behavior more
obvious.
Signed-off-by: Soeren Moch <smoch@web.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
imx6sx-sdb has WDOG1_B pin connected to the PMIC.
Pass the 'fsl,ext-reset-output' property so that the watchdog
can trigger a system POR reset via the PMIC.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
imx6ul-evk has WDOG1_B pin connected to the PMIC.
Pass the 'fsl,ext-reset-output' property so that the watchdog
can trigger a system POR reset via the PMIC.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
imx7d-sdb has WDOG1_B pin connected to the PMIC.
Pass the 'fsl,ext-reset-output' property so that the watchdog
can trigger a system POR reset via the PMIC.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
imx6qdl-sabresd has WDOG2_B pin connected to the PMIC.
Pass the 'fsl,ext-reset-output' property so that the watchdog
can trigger a system POR reset via the PMIC.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The Utilite Pro has a mmc card slot connected to the usdhc3
controller. There is no card detection until hardware revision 1.3.
Add support for it and signal the controller with the broken-cd
property that polling has to be used to detect a card.
Signed-off-by: Christopher Spinrath <christopher.spinrath@rwth-aachen.de>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The current ldo settings of the cm-fx6 do not allow 1.2GHz cpu
frequency. At this frequency the module behaves unstable.
But the imx6q fuse indicates that 1.2GHz operation is possible.
Hence, remove the 1.2GHz operation point in the device tree.
Signed-off-by: Valentin Raevsky <valentin@compulab.co.il>
[christopher.spinrath@rwth-aachen.de: enhance commit message, adjust
remaining operation points to match the ones in imx6q.dtsi and add
a comment in the device tree]
Signed-off-by: Christopher Spinrath <christopher.spinrath@rwth-aachen.de>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The imx6 SMP system has the same DMA memory coherency issue [1] with
pl310 L2 controller. With this shared override bit set, the customer
reports the DMA coherency issue is gone. Besides, I have tested
the performance using USB ethernet with/without this bit, it shows
no difference.
[1] http://patchwork.ozlabs.org/patch/469362/
Signed-off-by: Peter Chen <peter.chen@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
R8A7792 SoC doesn't have the EtherMAC core, so SMSC LAN89218 Ethernet
chip was used instead on the Blanche board; this chip is compatible with
SMSC LAN9115 for which there's a (device tree aware) driver. Describe
the chip in the Blanche device tree; enable DHCP and NFS root in the
kernel command line for the kernel booting.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add the initial device tree for the R8A7792 SoC based Blanche board.
The board has 2 debug serial ports: SCIF0 and SCIF3; include support for
them, so that the serial console can work.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Describe the IRQC interrupt controller in the R8A7792 device tree.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Describe [H]SCIFs in the R8A7792 device tree.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Describe SYS-DMAC0/1 in the R8A7792 device tree.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The initial R8A7792 SoC device tree including CPU cores, GIC, timer, SYSC,
and the required clock descriptions.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
With the SION bit set a pin can be read as GPIO even though it's not muxed
as GPIO. This is useful at times. The downside however is that the signal
is not only routed to the GPIO IP but also all other IPs that can make use
of the pin. This resulted in more than one issue for me in the past. Things
like spi transfers that result in usb reenumeration or setting a GPIO to a
value that triggers an RTS irq for an UART.
This convinces me that the SION bit does more harm than good and so all
SION bits are removed that are not known to be needed.
Note that this has no influence on GPIOs under Linux as the gpio-mxc
driver just reports the level the pin is driven to for outputs and not
the level as seen on the pin.
If this commit introduces a regression for you, please report which SION
bit is essential for your setup.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Update DTSI file to add the reset controller node.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
On these two boards, the serial0 is used for inter-chip connection,
so cannot be used for login console. The serial2 is used instead
for them, but it is tedious to use because upper level deployment
projects must switch login console per board.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
This node consists of various system-level configuration registers.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
This pin-muxing is needed to get access to the UniPhier System Bus.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Name the Pin Function Controller subnode for SCIFA4 after its device
name, instead of after the serial port alias.
This avoids conflicts when adding support for more serial ports later,
either here or in a DT overlay.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Name the Pin Function Controller subnode for QSPI after its device name,
instead of after the spi interface alias.
This avoids conflicts when enabling support for more spi interfaces
later, either here or in a DT overlay.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Name the Pin Function Controller subnode for SCIF2 after its device
name, instead of using some arbitrary name that looks like a serial port
alias, but differs from the actual alias.
This avoids conflicts when enabling support for more serial ports later,
either here or in a DT overlay.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Name the Pin Function Controller subnode for QSPI after its device name,
instead of after the spi interface alias.
This avoids conflicts when enabling support for more spi interfaces later,
either here or in a DT overlay.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Name the Pin Function Controller subnode for SCIF2 after its device
name, instead of using some arbitrary name that looks like a serial port
alias, but differs from the actual alias.
This avoids conflicts when enabling support for more serial ports later,
either here or in a DT overlay.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Name the Pin Function Controller subnode for QSPI after its device name,
instead of after the spi interface alias.
This avoids conflicts when enabling support for more spi interfaces later,
either here or in a DT overlay.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Name the Pin Function Controller subnodes for SCIF0 and SCIF1 after
their device names, instead of after the serial port aliases.
This avoids conflicts when enabling support for more serial ports later,
either here or in a DT overlay.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Name the Pin Function Controller subnode for QSPI after its device name,
instead of after the spi interface alias.
This avoids conflicts when enabling support for more spi interfaces
later, either here or in a DT overlay.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Name the Pin Function Controller subnode for SCIF0 after its device
name, instead of after the serial port alias.
This avoids conflicts when enabling support for more serial ports later,
either here or in a DT overlay.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Name the Pin Function Controller subnodes for QSPI and MSIOF0 after
their device names, instead of after the spi interface aliases.
This avoids conflicts when enabling support for more spi interfaces
later, either here or in a DT overlay.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Name the Pin Function Controller subnodes for SCIF0 and SCIF1 after
their device names, instead of after the serial port aliases.
This avoids conflicts when enabling support for more serial ports later,
either here or in a DT overlay.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Name the Pin Function Controller subnode for VIN1 after its device name,
instead of using the generic and indexless "vin".
This avoids conflicts when enabling support for more video inputs later,
either here or in a DT overlay.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Name the Pin Function Controller subnodes for QSPI and MSIOF1 after
their device names, instead of after the spi interface aliases.
This avoids conflicts when enabling support for more spi interfaces
later, either here or in a DT overlay.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Name the Pin Function Controller subnodes for SCIF0 and SCIFA1 after
their device names, instead of after the serial port aliases.
This avoids conflicts when enabling support for more serial ports later,
either here or in a DT overlay.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Name the Pin Function Controller subnodes for SCIF2 and SCIF4 after
their device names, instead of using some arbitrary names that look like
serial port aliases, but differ from the actual aliases.
This avoids conflicts when enabling support for more serial ports later,
either here or in a DT overlay.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Name the Pin Function Controller subnode for SCIF0 after its device
name, instead of after the serial port alias.
This avoids conflicts when enabling support for more serial ports later,
either here or in a DT overlay.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Name the Pin Function Controller subnode for SCIFA1 after its device
name, instead of after the serial port alias.
This avoids conflicts when enabling support for more serial ports later,
either here or in a DT overlay.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Name the Pin Function Controller subnode for MMC0 after its device name,
instead of using the generic and indexless "mmc".
This avoids conflicts when enabling support for more MMC interfaces
later, either here or in a DT overlay.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Name the Pin Function Controller subnode for SCIFA0 after its device
name, instead of after the serial port alias.
This avoids conflicts when enabling support for more serial ports later,
either here or in a DT overlay.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
4.7-rc1 because OF graph logic expects specific names of child nodes.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJXXssHAAoJEME3ZuaGi4PXGNwQAIuZyLfPaJpqOlhIACwQsaXj
/X6/sg1dy92QooW1r5VHeYYVBjcY3xfOqpFuJhQbxXbsDuhgrKFLIZh0hyUd1uoY
hWJAlwmTjF85IxhbNtPMoysxDxRpKs/nuR/GiDI+5cR50YNZC8tCiyODurRGCLm2
QQ7Y4DcmuWfLqTR8o65xCGv8AuVEhp4S+b4uLT3Cx5BSZd7cQVlHpcMyI4Ynkm1K
nQ/yWF7SA8q6bQtb4ApofQszUZiC5R5V5xi1iCz9ukktEs1f7F+HkFaCTw9QtlbU
Ej258jvnDxDAHwcAzFWxFHlk6zJV/SIFHH4lxvyPNVnRs6mRoCmBnyWrsKiHOCo3
lCSaAwDluyBFRK+cfa0gZsBco69BBniRBkapqbQeu+GdnOli726XA/vBST+qpQ0C
+2js6i6wpokR3YHqXhaf6HNqM1Q5ORYPQMxz76u2Okdnucha0/q7cBjJPekpIwE0
TyoXUWP8tWWxdDoAVwyHp+0Ai34pof2pyMFFkV2PdIheVYlGYVust5uEhTWGp+ty
4m0ukaMffq5Xp4xOlRraaVgSvZo7/BGxiBRFud8ve9sYEx6uu7a0R365kDsnScVW
gpnUoDTuf0FsH/OAj6ZSraf2oqfOvrJ+TEybMdTD4M9MeZqcxtc8x6bWb2Ilwox3
JFXyCQR4Y+GtpQFEwAfL
=ro/B
-----END PGP SIGNATURE-----
Merge tag 'samsung-fixes-4.7-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into fixes
Fixes for Exynos-based Snow and Peach Pit boards for regressions introduced in
4.7-rc1 because OF graph logic expects specific names of child nodes.
* tag 'samsung-fixes-4.7-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
ARM: dts: exynos: Fix port nodes names for Exynos5420 Peach Pit board
ARM: dts: exynos: Fix port nodes names for Exynos5250 Snow board
Signed-off-by: Olof Johansson <olof@lixom.net>
- Update Arria10 ECC manager
- Add ethernet alias for Arria10
- Update serial alias for Arria10
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJXWHESAAoJEBmUBAuBoyj0VV0QALgtV3avO4/bTuAOjkhvUy9Q
KX4Hbene+bK2zkd82ChMfaFErPD8AYttdy6pLKUHp+F6AssTRH2RTyezwv/dlIBH
+Q/qFvs6SRvc+0Jto11hVe/Dx5adV7aeBLjzWwLkNJ/BpqRCyM4hKw228i0JwuMl
/PM3LdZw8V1956rbwcjLCNWV4HaDhOB0hTmfO+nZIGHaj6Qut27BYa4tGLWDKRPs
QE7RwY3FBNMCXcpRGQBhjFzBGJrFEAT5/tkr3UA2vJnUhSKQa99QQon/L/REhPdY
EWkrvLOTa86sof51jsm9bSM2TJvbJs+rQkHsp8qgWfgz2TI0S9kvFq72ttDJtII1
HWxAJqAiJgP6X95RVU/aLPVZ4uyKg3MjPT4mYhIj9H1yex440kPHG9dOx99DKoxA
1UGDh68J4c0UIL9Uvt+QLeTY2PfaunfDxjcsDVxKfw++sXE4OeazhJCJlceq8P+o
z5r5hl2CzWeKLnrWP7oNQhfjuRce8G4NzBKAoL+11JVi1xwv8C1ggX2TqAhfY+kz
WH45OmG2djzuY96sLb3tabatl7i6h3UALFCZTJ6D9XXB3zKbqgwSrq7IlVvkFkf9
ivDNp8TQ1rczho/ue5GLgrqBN3l1El1KX4Kj3K9ZW3Fj60FzVvP+V5tsNBVq+nBb
ntn4eP0ZTeozDIm/XvtK
=WdVs
-----END PGP SIGNATURE-----
Merge tag 'socfpga_updates_v4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into next/dt
SoCFPGA DTS updates for v4.8
- Update Arria10 ECC manager
- Add ethernet alias for Arria10
- Update serial alias for Arria10
* tag 'socfpga_updates_v4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
ARM: dts: socfpga: fix definitions of serial console
ARM: dts: socfpga: add ethernet alias on Arria10
ARM: dts: Move Arria10 SDRAM as child of ECC Manager
ARM: dts: Arria10 ECC Manager IRQ controller changes
Signed-off-by: Olof Johansson <olof@lixom.net>
- Move the ab8500 compatible string from the board to the
chipset.
- Define GPIO line names for the boards.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJXV8y4AAoJEEEQszewGV1zXRUP/RitlC4vtzEXCfhTHdg3BQI1
uNkHl96N3sgQaj/67ImT46E078JlIz9uNFhxj3jXxIk5BOaJoBBG6Giz8NzFpEl/
Jh7YFzUW4L5v8O4vp5Fl1vEUvXoZn8MZClihcREihcjecm6FAD0CHujmu6dn2cpx
sC7L1mbmS8IWvGeLxohfCoeAJFnSsNwJ2BUqgdnM/dxRFa33fr45XTGIVeV5XkI6
JPYyM7jsGnbg9YqWX+RdLLMLD1DcriSpXjVbmHdfW6avqAjWT6USIe7gjcG6YUwR
6Pqh0HLGVH6PNVRlkIlV1hVizPPb3At4ouMT9I09kmoAD1mpg1AsiadunA4F2EPa
oDgajYRI4Teuj171jCjWyCnJIcluqhXK+QgYFs/ubT1BklKBxBwOHFgz0yIhpSEq
VBMEjfyXko+wYpCfG+ZZEPyqOhBFQfhlQnS8TzL4nMI1oma7XnY7s/Ph0oSuZOlx
L+FeQQ21SV2gBnO1oTTUk+D9D8V0Vwq9WvQWNt6kEt5E8AwGPX0N1FCGCFAyrwa+
+YmCIBpMZj5TtYHhf6frRx+dEe5e3or3NdR0a43jXhPYxPkWhXVcBVKzMuPFfA0z
5/3JDx37bFNmvSXW7ysw5dZeimvYtZfitw/9EOnxk9vS5ASiEOA2VtCTx9h3OZLs
1ZDvxa/0XAOHTp5gbmv8
=sOoX
-----END PGP SIGNATURE-----
Merge tag 'ux500-dt-asoc-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson into next/dt
Ux500 devicetree patches:
- Move the ab8500 compatible string from the board to the
chipset.
- Define GPIO line names for the boards.
* tag 'ux500-dt-asoc-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson:
ARM: dts: UX500: name the GPIO lines on HREFv60plus
ARM: dts: Ux500: name the GPIO lines on Snowball
ARM: dts: Ux500: move compatible string to chipset
Signed-off-by: Olof Johansson <olof@lixom.net>
This brings support for Hardkernel's Odroid XU board. It was the first
design with big.LITTLE SoC from Samsung: Exynos5410. The board is not
very popular. Newer XU3 and XU4 got more attention.
Board details:
1. Exynos5410 octa-core (A15+A7, however as of now only one cluster is
enabled),
2. 2 GB DDR3 RAM,
3. PowerVR SGX544MP3 GPU (not enabled in DTS),
4. USB 3.0 Host x 1, USB 3.0 OTG x 1, USB 2.0 Host x 4,
5. HDMI 1.4a, MIPI DSI and Display Port (Display Port not on all of
revisions though),
6. eMMC 4.5 and microSD slots.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJXVWVcAAoJEME3ZuaGi4PXFVQP/3JyYEYpBw+6tu0PasYz2cYr
D2fprLkHlfFOY+wGdHoTuBsjsOj1nwTXyVAA/zhIqudgJFXH67vR+BABoCDVT7J0
/pYfMT4rm9Wa4ddKJnE6bv78IbAI52S1tzKsHRi+YlceVbKFUWJAqSsaJYVDOaci
Sxg4/sbD2VcU7xlDNw2lSux6du3MEkdbarOd3l58eKMwvqSRCmvx7YultrrFwDhV
JByy1VG+WXAWyaE59VRZ+kAGHMDTz7KK8YNjkUGmgJK0Ryd6C8kETw1ZC8fiA/tZ
+QlnDehngSZ15x79RI7JUj/F+UY2QrMDzLk6qIa2E3sgWv4aJ0csFymk1+mUDhJF
vO8EwqF+YnbwNG1mmzmqBgeQxb3EdKdM/onanpazIlQAlpaJIJpBbKR8x2Doa6TZ
g/f37FQW3l1DEBT3H2IXd6Yx1FgCnlFjPb0fwnS5sG05YyOEKdKTss+5LKShG5J4
VeN8/EmaocRvQx0GE0pRr0nhuaWt9E59jXrAmBe8OUVIjQYTvxRoH2mWEQ0iuOEZ
+VRD/WwtkdqeUBOSFYckVWDanJPqh3qLZ+eCEqoguMKtqCTC3eJp2euIBsawA4DW
Nxl6Zy5iIMfc7j4VtoDy7qDtBJ1hzeX8gzRE+tVXrtpiMs2gd1+Jkofr2nTIihU9
h/Hg9dc34pSV9by8hutW
=7u0/
-----END PGP SIGNATURE-----
Merge tag 'samsung-dt-odroid-xu-4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/dt
Topic branch for adding Exynos 5410 Odroid XU board for v4.8.
This brings support for Hardkernel's Odroid XU board. It was the first
design with big.LITTLE SoC from Samsung: Exynos5410. The board is not
very popular. Newer XU3 and XU4 got more attention.
Board details:
1. Exynos5410 octa-core (A15+A7, however as of now only one cluster is
enabled),
2. 2 GB DDR3 RAM,
3. PowerVR SGX544MP3 GPU (not enabled in DTS),
4. USB 3.0 Host x 1, USB 3.0 OTG x 1, USB 2.0 Host x 4,
5. HDMI 1.4a, MIPI DSI and Display Port (Display Port not on all of
revisions though),
6. eMMC 4.5 and microSD slots.
* tag 'samsung-dt-odroid-xu-4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: (28 commits)
ARM: dts: exynos: Add watchdog and Security SubSystem to Exynos5410
ARM: dts: exynos: Configure PWM, usb3503, PMIC and thermal on Odroid XU board
ARM: dts: exynos: Add Thermal Management Unit to Exynos5410
ARM: dts: exynos: Interrupt for USB DWC3-1 differs between Exynos5420 and 5410
dt-bindings: clock: Add watchdog and SSS clock IDs to Exynos5410
dt-bindings: clock: Add TMU clock ID to Exynos5410
ARM: dts: exynos: Add RTC and I2C to Exynos5410
ARM: dts: exynos: Add I2C, PWM and UART pinctrl to Exynos5410
ARM: dts: exynos: Move HSI2C nodes to exynos54xx.dtsi
ARM: dts: exynos: Add initial support for Odroid XU board
ARM: dts: exynos: Add USB to Exynos5410
ARM: dts: exynos: Move common Exynos5410/542x/5800 nodes to new DTSI
ARM: dts: exynos: MCT is not an interrupt controller and extend length of iomap
ARM: dts: exynos: Enable UART3 on Exynos5410
ARM: dts: exynos: Include common exynos5 in exynos5410.dtsi
ARM: dts: exynos: Move Exynos5250 and Exynos5420 nodes under soc
ARM: dts: exynos: Use phandle to get parent node in exynos5250-snow
ARM: dts: exynos: Prepare for inclusion of exynos5.dtsi in exynos5410.dtsi
ARM: dts: exynos: Move common nodes to exynos5.dtsi
ARM: dts: exynos: Split Odroid XU3 LEDs to separate DTSI
...
Signed-off-by: Olof Johansson <olof@lixom.net>
Define the port mapping for the SmartRG SR400ACE device.
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Add interrupt mapping for the Switch Register Access Block. Only 12
interrupts are usable at the moment even though up to 32 are dedicated
to the SRAB.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Add the Switch Register Access Block which is a special piece of
hardware allowing us to perform indirect read/writes towards the
integrated BCM5301X Ethernet switch.
We also add the 4 Gigabit MAC Device Tree nodes within the brcm,bus-axi
bus node to get proper binding between the BCMA instantiated core and
the Device Tree nodes. We will need that to be able to reference
Ethernet Device Tree nodes in a future patch adding the switch ports
layout.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
This patch adds the firmware node for the SCM
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
This patch adds the power key device tree node.
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
The #size-cells for the pmics are 0, but we specify a size in the
reg property so that MPP and GPIO modules can figure out how many
pins there are. Now that we've done that by counting irqs, we can
remove the size elements in the reg properties and be DT
compliant.
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Enable the sdcard slot and wire up the regulators for the two
storage controllers found on the apq8074 dragonboard.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Add the appropriate min/max voltages for the regulators on the
apq8074 dragonboard so that they can be used by clients properly.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Add "dis_rxdet_inp3_quirk" boolean property to USB3 node. This property
is used to disable rx detection in P3 PHY mode.
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The PCI reset GPIO is active low, so represent it with the
GPIO_ACTIVE_LOW flag.
Even though the imx6 PCI driver will not take the polarity into account
in this case, it is better to provide a correct description in device-tree.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
GPLv2-only devicetrees make reuse difficult for software components
licensed under a different license. In particular, the Utilite Pro
devicetree file (which includes imx6q-cm-fx6.dts) is already dual
licensed under GPLv2/X11.
Hence, relicense imx6q-cm-fx6.dts under GPLv2/X11 dual license.
Signed-off-by: Christopher Spinrath <christopher.spinrath@rwth-aachen.de>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The CompuLab Utilite Pro is a miniature fanless desktop pc based on
the i.MX6 Quad powered cm-fx6 module. It features two serial ports,
USB OTG, 4x USB, analog audio and S/PDIF, 2x Gb Ethernet, HDMI and
DVI ports, an on-board 32GB SSD, a mmc slot, and on-board wifi/bt.
Add initial support for it including USB, Ethernet (both ports), sata
and HDMI support.
Signed-off-by: Christopher Spinrath <christopher.spinrath@rwth-aachen.de>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The cm-fx6 module has an on-board spi-flash chip for its firmware, an
eeprom (containing e.g. the mac address of the on-board Ethernet),
a sata port, a pcie controller, an USB hub, and an USB otg port.
Enable support for them. In addition, enable syscon poweroff support.
Signed-off-by: Christopher Spinrath <christopher.spinrath@rwth-aachen.de>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The imx6q-cm-fx6 iomuxc container node is not required. Remove it.
Signed-off-by: Christopher Spinrath <christopher.spinrath@rwth-aachen.de>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This fixes the following dtc warning by removing the unnecessary unit:
Warning (unit_address_vs_reg): Node /matrix-keypad@0 has a unit name,
but no reg property
Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
Acked-By: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This fixes the following dtc warning by removing the unnecessary unit:
Warning (unit_address_vs_reg): Node /onewire@0 has a unit name,
but no reg property
Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This patch adds the missing reg properties for the regulator nodes
in order to fix the dtc warnings.
Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This patch adds the missing reg properties for the MXS GPIO banks
in order to fix the dtc warnings.
Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The Auvidea H100 is a baseboard for the SolidRun MicroSOM.
Its primary feature is a Toshiba TC358743 HDMI to CSI decoder,
allowing the board to work as HDMI passthrough and framegrabber.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add the DT property to all boards that have the hardware workaround
for erratum ERR006687 present. This allows the CPUidle driver to use
the deep idle states, even if the FEC is active.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This node describes the DI1 port of IPU, fix the node name to reflect this.
There's currently no user of this node in mainline, so this change should
not break any supported platforms.
Signed-off-by: Juergen Borleis <jbe@pengutronix.de>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add support for the LCD8000-43T display and for the backlight
controlled via PWM1.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
As of commit 1006ed7e1b ("serial: imx: Use generic uart-has-rtscts
DT property"), the Freescale IMX UART driver recognizes the generic
"uart-has-rtscts" DT property, deprecating the vendor-specific
"fsl,uart-has-rtscts" DT property. Hence replace the latter by the
former in all DTS files.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
As of commit 182cdcb8bb ("serial: mxs-auart: Use generic
uart-has-rtscts DT property"), the Freescale MXS AUART driver recognizes
the generic "uart-has-rtscts" DT property, deprecating the
vendor-specific "fsl,uart-has-rtscts" DT property. Hence replace the
latter by the former in all DTS files.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This adds back the dma channels for the i2c1 node. This is safe now
that the qcom,controlled-remotely changes are in place and will be used
on the boards that require it.
This reverts commit 10c0f0e92f.
This puts back in place the blsp2_bam node. This can be safely added
due to the addition of the special qcom,controlled-remotely flag that
will be used on specific boards that require it.
This reverts commit 338d518898.
Add PL330 support to the the Broadcom Northstar Plus device tree.
Signed-off-by: Jon Mason <jonmason@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
The BCM958525XMC board is a smaller form factor typically used as
controller boards for switches. This smaller board has less devices
pinned out, so only a few need be populated in the device tree.
Signed-off-by: Jon Mason <jonmason@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
The clocks group properties and the clock@0 node have been obsolete for two
years, remove them.
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
The clocks group properties and the clock@0 node have been obsolete for two
years, remove them.
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
The clocks group properties and the clock@0 node have been obsolete for two
years, remove them.
Cc: Joachim Eastwood <manabian@gmail.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
The clocks group properties and the clock@0 node have been obsolete for two
years, remove them.
Cc: Fabio Porcedda <fabio.porcedda@gmail.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
The clocks group properties and the clock@0 node have been obsolete for two
years, remove them.
Cc: Sergio Tanzilli <tanzilli@acmesystems.it>
Cc: Douglas Gilbert <dgilbert@interlog.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
The clocks group properties and the clock@0 node have been obsolete for two
years, remove them.
Cc: Rodolfo Giometti <giometti@linux.it>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
The clocks group properties and the clock@0 node have been obsolete for two
years, remove them.
Cc: Sergio Tanzilli <tanzilli@acmesystems.it>
Cc: Douglas Gilbert <dgilbert@interlog.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
The clocks group properties and the clock@0 node have been obsolete for two
years, remove them.
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
The Denx MA5D4 dts doesn't properly define the slow_xtal and main_xtal
frequencies, the PMC then has to fallback to using the RC oscillators whose
precision is not really good.
As both crystals are populated, define their frequencies, see p17 of
http://www.denx-cs.de/sites/all/files/MA5D4.HWM_.002.pdf
Also, remove the obsolete main_clock definition.
Acked-by: Marek Vasut <marex@denx.de>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Use stdout-path to specify the console and remove the console argument from
the kernel command line.
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Add support for this small MP3 player based on STMP3780 (rev.3).
Currently supported are both external microSD and internal SD-NAND
bridge, PWM and USB gadget.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add support for this small MP3 player based on STMP3780 (rev.4).
Currently supported is both external microSD and internal SD-NAND
bridge, PWM and USB gadget.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add pinmux configuration for SSP2 port in SD mode, both for
the 4-bit and 8-bit case.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The unit address of the second PCIe instance
is set to be same as that of the first instance
(copy-paste error).
Fix it.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Define RFID eeprom node which is present on gta04
device.
Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
Signed-off-by: Marek Belisko <marek@goldelico.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The twl6040 codec is generating the pdmclk, which is used by the McPDM as
functional clock.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The twl6040 codec is generating the pdmclk, which is used by the McPDM as
functional clock.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The twl6040 codec is generating the pdmclk, which is used by the McPDM as
functional clock.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The twl6040 codec is generating the pdmclk, which is used by the McPDM as
functional clock.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The twl6040 codec is generating the pdmclk, which is used by the McPDM as
functional clock.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add clock properties to the McBSP nodes. McBSP2 and 3 need to have ick also
since the Sidetone block of these modules are operating using the McBSP
interface clock.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Currently am33xx.dtsi declares the MAC controller to have two
slave ports, on these boards we only use one, so set the slave
count to one. This eliminates a console error message when
the non-existent PHY is not detected.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Currently am4372.dtsi declares the MAC controller to have two
slave ports, on this board we only use one, so set the slave
count to one. This eliminates a console error message when
the non-existent PHY is not detected.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Correct misspelling, "emda3" -> "edma3".
Reported-by: Adam J Allison <adamj.allison@gmail.com>
Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Rename the tag of the 3.3 V regulator used in the DRA72 EVM in
order to have a consistent tag name with the DRA7 EVM. This
is useful when the regulator needs to be referenced in common
dtsi files (i.e. for common companion boards like JAMR3 [1]).
[1] http://www.ti.com.cn/cn/lit/ug/sprui52/sprui52.pdf
Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
AM335x ICE board has a TI PCA9536 chip connected to I2C0 at address
0x41. Add DT entry for the same.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Acked-by: Kristofer Martinez <Kristofer.S.Martinez@gmail.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add an operating-points-v2 table with all OPPs available for all silicon
revisions along with necessary data for use by ti-opp driver to selectively
enable the appropriate OPPs at runtime and handle voltage transitions
As we now need to define voltage ranges for each OPP, we define the
minimum and maximum voltage to match the ranges possible for AVS class0
voltage as defined by the DRA7/AM57 Data Manual, with the exception of
using a range for OPP_OD based on historical data to ensure that SoCs
from older lots still continue to boot, even though more optimal voltages
are now the standard. Once an AVS Class0 driver is in place it will be
possible for these OPP voltages to be adjusted to any voltage within the
provided range.
Information from SPRS953, Revised December 2015.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Nearly all of the information in the cpus node, especially for cpu0, is
the same between dra74x and dra72x so move the common information to
the parent dra7.dtsi to avoid duplication of data.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Create a system control module node for the control module portion that
resides under l4_wkup.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Hook dcdc2 as the cpu0-supply.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add an operating-points-v2 table with all OPPs available for all silicon
revisions along with necessary data for use by ti-cpufreq to selectively
enable the appropriate OPPs at runtime.
Information from AM437x Data Manual, SPRS851B, Revised April 2015,
Table 5-2.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Although all PG2.0 silicon may not support 1GHz OPP for the MPU, older
Beaglebone Blacks may have PG2.0 silicon populated and these particular
parts are guaranteed to support the OPP, so enable it for PG2.0 on
am335x-boneblack only.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Drop the operating-points table present in am33xx.dtsi and add an
operating-points-v2 table with all OPPs available for all silicon
revisions along with necessary data for use by ti-cpufreq to selectively
enable the appropriate OPPs at runtime. Also, drop the voltage-tolerance
value and provide voltages for each OPP using the <target min max>
format instead.
Information from AM335x Data Manual, SPRS717i, Revised December 2015,
Table 5-7.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Now that we are moving to OPPv2 bindings and able to add 1GHz OPP for
MPU, let's update the max MPU voltage range to align with the maximum
possible value allowed in the operating-points table, which is max
target voltage of 132500 uV + 2%.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Without that change wifi card isn't probed because pwrseq is necessary for
libertas chip.
Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Define pinmux and usage if irq pin + fix irq edge.
Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Define pwm backlight node which is using dmtimer pwm.
Signed-off-by: Marek Belisko <marek@goldelico.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add the needed DT data to enable IR TX driver
Signed-off-by: Ivaylo Dimitrov <ivo.g.dimitrov.75@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Secure variants of DRA7xx and AM57xx SoCs may need to reserve a region
of the SRAM for use by secure software. To account for this, add a child
node to the ocmcram1 node that will act as a placeholder at the start
of the SRAM for the reserved region of memory that may be required
by secure services. The node is added with size 0 so that by default
parts will have the full space available but the bootloader or board dts
file is able to resize the node as needed depending on how much reserved
space is needed, if any, so end users of the ocmcram1 region on HS parts
must be aware that a smaller amount of SRAM than expected may be available.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Reviewed-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add all ocmcram nodes to dra7.dtsi using the generic mmio-sram driver.
DRA7xx and AM57xx families of SoCs can contain three ocmcram regions of
SRAM, one of 512kb and also an optional two additional of 1Mb each. Mark
the two additional 1MB regions of SRAM as disabled as only ocmcmram1 is
on all variants of the SoCs, then depending on which specific variant
is in use the ocmcram2 and ocmcram3 nodes can be enabled in the board
dts file if the data manual for that part number indicates the ocmcram
region is available.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Reviewed-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add PWMSS device tree nodes for DRA7 SoC family and add documentation
for dt bindings.
Signed-off-by: Vignesh R <vigneshr@ti.com>
[fcooper@ti.com: Add eCAP and use updated bindings for PWMSS and ePWM]
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Previous patches switched the ECAP and EPWM to use the new bindings.
These bindings explicitly adds the various required clocks via DT rather
than depending on hwmod.
Therefore, it is safe to remove the hwmod entries since they are no longer
needed.
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Switch to a new ECAP and EPWM bindings that doesn't depend on hwmod to
provide the various required clocks.
For AM437 and AM335x, add the required clocks explicitly to DT. The
hwmod entries for ECAP and EPWM will be removed and this will prevent
anything from breaking.
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Avoid depending on the bootloader or the ROM for configuring the pinmux by
explicitly setting the pinmux here.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Santosh Shilimkar <ssantosh@kernel.org>
The pinctrl IP used in some of the Keystone 2 devices differ vs other
TI SoCs. Therefore, create a Keystone specific pinctrl header.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Santosh Shilimkar <ssantosh@kernel.org>
Add pinctrl support.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Santosh Shilimkar <ssantosh@kernel.org>
This enables support for the CAN controller located in the FPGA.
Signed-off-by: Damien Riegel <damien.riegel@savoirfairelinux.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Enable FPGA's IRQ controller. It is in charge of dispatching interrupts
generated by IPs in the FPGA. The SoC is notified that an interrupt
occurred through a GPIO.
Signed-off-by: Damien Riegel <damien.riegel@savoirfairelinux.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Commit 6c42db30d8 introduced audio support based on alsa ucm profiles
taken from the ChromeOS userspace. Both in the kernel as well as alsa
they were named (and matched against) ROCKCHIP-I2S. Audio profiles are
very much board-specific and hogging the ROCKCHIP-I2S name would make
it harder for future boards and also is misleading.
For Veyron boards the audio setup is similar over all variants, so
VEYRON-I2S is a more suitable name. This rename also was merged into
the alsa ucm profile so both userspace and kernel match and the old
naming was never released in any alsa or kernel release.
Fixes: 6c42db30d8 ("ARM: dts: rockchip: Add shared file for audio on rk3288-veyron boards")
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
DSS's 'pll2_clkctrl' and 'pll2' have wrong addresses in the dra74x.dtsi
file. Video PLL2 has not been used so wrong addresses went unnoticed.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add pinctrl node and populate the pinctrl registers with the default
values.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Santosh Shilimkar <ssantosh@kernel.org>
The PCI DT bindings contain a bogus entry for IO space which is not
supported on Keystone. The current bogus entry has an invalid size
and throws following error during boot.
[0.420713] keystone-pcie 21021000.pcie: error -22: failed to map
resource [io 0x0000-0x400000003fff]
So remove it from the dts. While at it also add a bus-range
value that eliminates following log at boot up.
[0.420659] No bus range found for /soc/pcie@21020000, using [bus 00-ff]
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Santosh Shilimkar <ssantosh@kernel.org>
The notion of which uart instance is serial0 or serial1
is board specific rather than generic to the chip. This
patch removes the serial aliases from generic chip dtsi
and adds an appropriate alias to the board specific dtsi.
By making the alias for serial0 point to uart1 for the arria10_socdk,
the linux boot command line supports specifying console=ttyS0,115200
for backwards compatibility, and it supports not specifying
the console at all.
Signed-off-by: Matthew Gerlach <mgerlach@opensource.altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Without having an ethernet alias, ethernet will have a random MAC address,
versus take an address that was provided from the bootloader.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
MFC device can be used without any external hardware dependencies (when
IOMMU is enabled), so it can be enabled by default (like it has been
already done for Exynos 542x platforms). This unifies handling of this
device for Exynos3250, Exynos4 and Exynos542x platforms. Board can still
include exynos-mfc-reserved-memory.dtsi to enable using this device
without IOMMU being enabled.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
This patch moves assigning reserved memory regions from each board dts
to common exynos-mfc-reserved-memory.dtsi file, where those regions are
defined.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Generic reserved memory regions bindings allow to automatically allocate
region of given parameters (alignment and size), so use this feature
instead of the hardcoded values, which had no dependency on the real
hardware. This patch also increases "left" region from 8MiB to 16MiB to
make the codec really usable with nowadays steams (with 8MiB reserved
region it was not even possible to decode 480p H264 video).
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Using the new line naming mechanism from the GPIO subsystem, name
the GPIO lines on the HREFv60plus board that are connected as
GPIO on this design.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Using the new line naming mechanism from the GPIO subsystem, name
the GPIO lines on the Snowball board that are connected as
GPIO on this design.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Move the compatible string "stericsson,ab8500" from the board
definitions into the main node in the chipset file where it
belongs.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Use compatible "atmel,sama5d2-ohci" to be capable of suspending
ports while sleep to save the power consumption.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
sam9-l9260 is a low cost board designed by Olimex.
More information is available at:
https://www.olimex.com/Products/ARM/Atmel/SAM9-L9260/
Signed-off-by: Raashid Muhammed <raashidmuhammed@zilogic.com>
Reviewed-by: Vijay Kumar B. <vijaykumar@bravegnu.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Remove leading zeros in OHCI node for at91sam9260 based boards.
Signed-off-by: Raashid Muhammed <raashidmuhammed@zilogic.com>
Reviewed-by: Vijay Kumar B. <vijaykumar@bravegnu.org>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Commit bea7eef694 ("ARM: dts: exynos: Fix DTC unit name warnings in
Peach Pit") fixed the DTC warnings about mismatches between unit names
and reg properties in the Exynos5420 Peach Pit DTS.
But unfortunately it also added a regression on the Peach Pit when
changing the port node names since the OF graph logic expects the port
nodes to be always named 'port'.
The Documentation/devicetree/bindings/graph.txt binding document says
that when there is more than one port, '#address-cells', '#size-cells'
and 'reg' properties should be used to number the port nodes.
Fixes: bea7eef694 ("ARM: dts: exynos: Fix DTC unit name warnings in Peach Pit")
Reported-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Commit 5c9cbade06 ("ARM: dts: exynos: Fix DTC unit name warnings in
Exynos5250") fixed all the DTC warnings about mismatchs between unit
names and reg properties in Exynos5250 boards DTS.
But unfortunately it also added a regression on the Exynos5250 Snow
Chromebook when changing the port node names since the OF graph logic
expects the port nodes to be always named 'port'.
The Documentation/devicetree/bindings/graph.txt binding document says
that when there is more than one port, '#address-cells', '#size-cells'
and 'reg' properties should be used to number the port nodes.
Fixes: 5c9cbade06 ("ARM: dts: exynos: Fix DTC unit name warnings in Exynos5250")
Reported-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com>
Tested-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Add device tree files for the Broadcom BCM23550 SoC and the
Broadcom Sparrow board.
Signed-off-by: Chris Brand <chris.brand@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
The thermal nodes are not disabled in exynos5420.dtsi so there is no
need to manually enable them on Odroid XU3/XU3-Lite/XU4 boards.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Move watchdog and Security SubSystem nodes from exynos5420.dtsi to file
shared with Exynos5410 and configure the clocks on the latter.
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Extend the DTS for Exynos5410-based Odroid XU board with:
1. Proper PWM outputs,
2. usb3503 USB HUB (with integrated LAN9730 ethernet adapter (smsc95xx)),
3. Maxim 77802 PMIC (regulators, 32 kHz clocks, RTC),
4. CPU thermal (trip points are the same as in Odroid XU3/XU4 but
cooling maps are different as there is no CPU freq and only one
cluster available for now),
5. Regulator supplies for USB 3.0.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Add nodes for Thermal Management Unit to exynos5410.dtsi. Use the same
compatible as for Exynos5420 however without second base for TRIMINFO
register and without TMU for GPU.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Add input mux for UART2 RX in DTE mode. This allows to use the pad
UART2_TX_DATA_ALT0 as UART2 RX. This particular input select seems
to be missing in current reference manuals (Rev. B), but when looking
at the tables and other UART input select registers (e.g. UART3) it
seems naturally that this input mux register also has a fourth pad
option for UART2_TX_DATA_ALT0. It has also been proven to be required
to use UART2 in DTE mode and the particular pads on the Colibri iMX7
platform.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Acked-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Pass "fsl,sai-mclk-direction-output" to the sai2 node, so that the
SAI2_MCLK can be an output.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add SAI alias entries, which makes it possibe for the SAI driver
to retrieve the port instance.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Building with W=1 option leads to several warnings like:
Warning (unit_address_vs_reg): Node /soc/aips-bus@02000000/anatop@020c8000/regulator-1p1@110 has a unit name, but no reg property
Fix them by removing the unneeded unit-addresses.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Enable support for Multimedia Codec (MFC) device for all Exynos4412-based
Odroid boards.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
This patch replaces custom properties for defining reserved memory
regions with generic reserved memory bindings for MFC video codec
device.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
[k.kozlowski: Add Samsung copyrights]
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
On Exynos5410 the SPI interrupt for second USB DWC3 (called DRD: Dual
Role Device) is different - 200 instead of 73.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Hang the three switches of the three MDIO busses using the new DSA
binding. Also, make use of the mdio-bus and explicitly list the phys
on one device. This is not required, but good for testing.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Reviewed-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This is the same issue fixed in commit dcf5341f01 ("ARM: dts:
sun8i-q8-common: Do not set constraints on dc1sw regulator").
Commit message copied:
dc1sw is an on/off only regulator and as such it cannot have constraints.
This is a limitation of the kernel regulator implementation which resolves
supplies on the first regulator_get(), which is done after applying
constraints, and applying the constrains will fail because it calls
_regulator_get_voltage() and _regulator_do_set_voltage() both of which
will fail on a switch regulator when there is no supply (yet).
This causes registering of all axp22x regulators to fail with the
following errors:
[ 1.395249] vcc-lcd: failed to get the current voltage(-22)
[ 1.405131] axp20x-regulator axp20x-regulator: Failed to register dc1sw
[ 1.412436] axp20x-regulator: probe of axp20x-regulator failed with error -22
This commit removes the constrains on dc1sw / vcc-lcd fixing this problem.
Note that dcdc1 itself is contrained to the exact same values, so this
does not change anything.
Cc: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Cc: <stable@vger.kernel.org> # 4.6
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
This is the same issue fixed in commit dcf5341f01 ("ARM: dts:
sun8i-q8-common: Do not set constraints on dc1sw regulator").
Commit message copied:
dc1sw is an on/off only regulator and as such it cannot have constraints.
This is a limitation of the kernel regulator implementation which resolves
supplies on the first regulator_get(), which is done after applying
constraints, and applying the constrains will fail because it calls
_regulator_get_voltage() and _regulator_do_set_voltage() both of which
will fail on a switch regulator when there is no supply (yet).
This causes registering of all axp22x regulators to fail with the
following errors:
[ 1.395249] vcc-lcd: failed to get the current voltage(-22)
[ 1.405131] axp20x-regulator axp20x-regulator: Failed to register dc1sw
[ 1.412436] axp20x-regulator: probe of axp20x-regulator failed with error -22
This commit removes the constrains on dc1sw / vcc-lcd fixing this problem.
Note that dcdc1 itself is contrained to the exact same values, so this
does not change anything.
Cc: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Cc: <stable@vger.kernel.org> # 4.6
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
with patches in Linux next:
- Fix omap5 and am57xx-idk input voltages to fix micro-sd
probing at least for some omap5-uevm configurations
- Fix unhandled fault for igepv5 audio
- Fix UART wakeirqs for omap5 by removing WAKUP_EN flags,
those are managed by the wakeirq and can currently confuse
the wakeirqs as there is no handler necessarily registered
- Fix LDO7 source for igepv5
Also included are few minor changes not strictly fixes
are good to have merged:
- Fix HP T410 boot time warnings for eMMC and disable the
unused MMC interfaces while at it
- Add dra7 gpmc dma channel
- Add igep00x0 SD card detect and write protect GPIOs
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJXNghoAAoJEBvUPslcq6Vzpj8P/jsKyMBQZZS/GXxLXouAIIx/
S/HK3Xd1VjW8FwB1cKDL2FcY9BF1q/sbc8r0499q1fYuoZoswv3fj8mssKSOPDPQ
1K5bjlgsw/eMaEkQh313ID7yLSK3jSBtt/USn/k+9DCg++JwnsMAi9n3GUmi1Itz
d7p/UBnIeMY3HNWau7svLL3iphAZy8CaD2jnsB+9ZhsaRx8+Am/Uwx+Y2CcwIgP+
lm3mzA6nnSuZkus6qW9zt5gurcA2hIyZZtdDmuEuv5D2e245z4MV/2pBbwfoAxB3
7aRej6L+tizPh3kqbaBFfMgd9mRSn6h4CoIJova/1U64KPAnF+hoUaKw4JNX6OQt
lnj/jqT2XwRzBejt7TVPyM9LOnF9HHP3TF0u/302tJS2OXEsfY0qt/zSAggr8pBR
kTIQofTH3VhfZa0qP8U1F7DWmFNDNvoKTf98yojGkDLDwvOkxH+SovRHTgQgg8+E
OVdU2PCfwzrP1/4RvvVxrgMTf5AidQCnvJbJP4Aa83WS9HEIZ3e+UXhLT+f5PFHc
AC5b8dYdHKO5IahBZUv9lg+GMDTTiwdPY9cN5OSvpLneYu8VkIa8RwjbuuzGf0mv
HA04E4LzIjHiHYam9NQVSlG+/hqsbgbmZOeGL7G4SxNTWQrrYeUA3ZXQwb5rlUjg
H6qshQYccawHebu9cwzv
=vMZg
-----END PGP SIGNATURE-----
Merge tag 'omap-for-v4.7-dts-fixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into fixes
DTS fixes for omaps for v4.7 merge window for issues noted
with patches in Linux next:
- Fix omap5 and am57xx-idk input voltages to fix micro-sd
probing at least for some omap5-uevm configurations
- Fix unhandled fault for igepv5 audio
- Fix UART wakeirqs for omap5 by removing WAKUP_EN flags,
those are managed by the wakeirq and can currently confuse
the wakeirqs as there is no handler necessarily registered
- Fix LDO7 source for igepv5
Also included are few minor changes not strictly fixes
are good to have merged:
- Fix HP T410 boot time warnings for eMMC and disable the
unused MMC interfaces while at it
- Add dra7 gpmc dma channel
- Add igep00x0 SD card detect and write protect GPIOs
* tag 'omap-for-v4.7-dts-fixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: dts: igep0020: Add SD card write-protect pin.
ARM: dts: igep00x0: Add SD card-detect.
ARM: dts: am57xx-idk-common: Fix input supply names
ARM: dts: dra7: Add gpmc dma channel
ARM: dts: disable mmc by default and enable when needed for dm814x
ARM: dts: Add non-removable to hsmmc on hp-t410
ARM: dts: Fix ldo7 source for HDMI on igepv5
ARM: dts: Fix uart wakeirq on omap5 by removing WAKEUP_EN for omaps
ARM: dts: Fix igepv5 audiopwon-gpio
ARM: dts: omap5-board-common: Describe the voltage supply mapping accurately
Signed-off-by: Olof Johansson <olof@lixom.net>
commit 27dd9af6bc ("ARM: dts: sunxi: Add a olinuxino-lime2-emmc")
added the new emmc equipped lime2 but forgot its Makefile.
This patch adds an entry to the Makefile.
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Changes to support IRQ controller implementation including adding
new property irq-controller to eccmgr and adding IRQ property
to children.
Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
The Exynos5800 Peach Pi and Exynos5420 Peach Pit Chromebooks have the
LDO10 1.8V output connected to the VDD18_TS{01,23,4} Exynos SoC pins.
Add this regulator as the input supply of the Thermal Management Unit
channels and also remove the always-on property since all the devices
using LDO10 as input supply are now defined.
Suggested-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Commit 1b47b98acc ("ARM: BCM5301X: Add DT entry for SPI controller and
NOR flash") enabled SPI-NOR device on routers using serial flash only.
However there are also devices with two flash memories:
1) Small SPI attached flash used mostly for booting
2) Bigger NAND used mostly for storing firmware
On such devices we still need SPI-NOR e.g. to access NVRAM data.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Create a new device tree file for the Broadcom Northstar Plus HR SVK.
This SVK is a smaller form factor, and thus only has 2 PCI slots and 1
UART. Also, it has the ability to reboot via GPIO (instead of the
processor reset).
Signed-off-by: Jon Mason <jonmason@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
NSP B0 has a different address for the second core. Since there should
not be any Ax versions in the field, it should be safe to universally
change this.
Signed-off-by: Jon Mason <jonmason@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Add MSI support to the PCI driver of the Northstar Plus SoC. This uses
the existing pcie-iproc driver. So, all that is needed is device tree
entries in the DTS.
Signed-off-by: Jon Mason <jonmason@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
bindings/arm/cpus.txt states that "enable-method" should be a
property of the "cpu" node rather than the "cpus" node.
Signed-off-by: Chris Brand <chris.brand@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
The hub and the ethernet in its port 1 are hardwired on the board.
Compared to the adapters that can be plugged into the USB ports, this
one has no serial EEPROM to store its MAC. Nevertheless, the Raspberry Pi
has the MAC address for this adapter in its ROM, accessible from its
firmware.
U-Boot can read out the address and set the local-mac-address property of the
node with "ethernet" alias. Let's add the node so that U-Boot can do its
business.
Model B rev2 and Model B+ entries were verified by me, the hierarchy and
pid/vid pair for the Version 2 was provided by Peter Chen. Original
Model B is a blind shot, though very likely correct.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Configure Exynos5410-specific properties of RTC, I2C and HSI2C nodes.
This still does not enable them on the board level though.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Add pincontrol groups for HSI2C (USI), I2C, PWM and UART to Exynos5410.
This allows configuring these pins to specific functions.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
The USI/HSI2C nodes can be mostly shared between Exynos5420 and
Exynos5410 so move them to common DTSI.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
The Hardkernel's Odroid XU board was first design with big.LITTLE SoC
from Samsung: the Exynos5410. Details:
1. Exynos5410 octa-core (A15+A7, however as of now only one cluster is
enabled),
2. 2 GB DDR3 RAM,
3. PowerVR SGX544MP3 GPU (not enabled in DTS),
4. USB 3.0 Host x 1, USB 3.0 OTG x 1, USB 2.0 Host x 4,
5. HDMI 1.4a, MIPI DSI and Display Port (Display Port not on all of
revisions though),
6. eMMC 4.5 and microSD slots.
Comparing this board to Odroid XU3 (more popular), the differences are:
1. Exynos5410 instead of 5422,
2. MIPI DSI LCD connector,
3. Main PMIC: Maxim 77802 instead of S2MPS11,
4. USB3503+LAN9730 instead of integrated LAN9514,
5. eMMC 4.5 instead of eMMC 5.0,
This patch adds initial support for the XU board with working basic
functions, eMMC/SD and USB (including attached ethernet adapter).
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Link: http://www.hardkernel.com/main/products/prdt_info.php?g_code=G137510300620
Move USB 3.0 DWC and 2.0 EHCI/OHCI nodes from exynos5420.dtsi to
exynos54xx.dtsi common for entire family. For Exynos542x/5800 this
should not have functional impact but for Exynos5410 this effectively
adds USB support.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
The Exynos5410/542x/5800 are very similar designs. Create a new
DTSI with common nodes to remove DTS duplication. Although currently
only MCT and SysRAM are shared but in future more nodes will be added to
the common file.
The patch should not have functional impact.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
Multi-Core Timer generates interrupts but it is not really an interrupt
controller so remove the "interrupt-controller" and "interrupt-cells"
properties. Additionally extend the length of mapped memory to cover all
registers (last SFR is at 0x0A40).
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
Just like other Exynos5 family SoCs, this one has four UARTs. Configure
clocks for UART3 and enable it.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
The exynos5.dtsi is used for common nodes shared between Exynos5250 and
Exynos542x. Since Exynos5410 is very similar to Exynos5420 it can
include the common file as well to remove duplication and make
everything more consistent.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
The conventions is to put SoC devices under 'soc' node. In fact other
our DTSes (like exynos3250.dtsi or exynos5410.dtsi) already follow it.
Adjust exynos5250 and exynos5420 DTSI to follow this convention. This is
also necessary for the upcoming change in exynos5410.dtsi to inherit
from common exynos5.dtsi.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
The i2c-arbitrator node in exynos5250-snow-common used absolute path to
reference other node (the i2c parent). Use phandle instead, because the
depth of the other node may be changed (like moving it under 'soc'
node).
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Add 'sromc' label to SROM memory controller in common exynos5.dtsi so it
can be referenced by inheriting DTSI.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
Exynos5420 and Exynos5250 share some nodes: the PWM, syscon
(sysreg_system_controller) and first four I2C controllers. Move them to
parent DTSI to avoid duplication.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
The LED nodes can be shared between Odroid XU3, XU3-Lite and XU (not yet
added) thus removing duplication.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
Configure the pinctrl for MMC0 (eMMC) and MMC2 (microSD card).
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Javier Martinez Canillas