Commit Graph

68 Commits

Author SHA1 Message Date
Ralf Baechle ae036b7908 [MIPS] SMTC: irq_{enter,leave} and kstats keeping for relayed timer ints.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-03-29 23:46:35 +01:00
Ralf Baechle c68644d330 [MIPS] Make SMTC_IDLE_HOOK_DEBUG a proper option in Kconfig.debug.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-02-26 23:06:06 +00:00
Ralf Baechle 5868756dcb [MIPS] SMTC: Make a bunch of functions and variables static.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-02-06 16:53:22 +00:00
Ralf Baechle e0daad449c [MIPS] Whitespace cleanups.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-02-06 16:53:19 +00:00
Ralf Baechle 418451c178 [MIPS] SMTC: remove unused atomic_postclear
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-02-06 16:53:16 +00:00
Atsushi Nemoto 97dcb82de6 [MIPS] Define MIPS_CPU_IRQ_BASE in generic header
The irq_base for {mips,rm7k,rm9k}_cpu_irq_init() are constant on all
platforms and are same value on most platforms (0 or 16, depends on
CONFIG_I8259).  Define them in asm-mips/mach-generic/irq.h and make
them customizable.  This will save a few cycle on each CPU interrupt.

A good side effect is removing some dependencies to MALTA in generic
SMTC code.

Although MIPS_CPU_IRQ_BASE is customizable, this patch changes irq
mappings on DDB5477, EMMA2RH and MIPS_SIM, since really customizing
them might cause some header dependency problem and there seems no
good reason to customize it.  So currently only VR41XX is using custom
MIPS_CPU_IRQ_BASE value, which is 0 regardless of CONFIG_I8259.

Testing this patch on those platforms is greatly appreciated.  Thank
you.

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-02-06 16:53:08 +00:00
Ralf Baechle ec43c01420 [MIPS] SMTC: Fix module build by exporting symbol
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-01-24 19:23:21 +00:00
Ralf Baechle a0b6218037 [MIPS] SMTC: Fix TLB sizing bug for TLB of 64 >= entries
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-01-24 19:23:21 +00:00
Ralf Baechle ac8be95504 [MIPS] SMTC: Instant IPI replay.
SMTC pseudo-interrupts between TCs are deferred and queued if the target
TC is interrupt-inhibited (IXMT). In the first SMTC prototypes, these
queued IPIs were serviced on return to user mode, or on entry into the
kernel idle loop. The INSTANT_REPLAY option dispatches them as part of
local_irq_restore() processing, which adds runtime overhead (hence the
option to turn it off), but ensures that IPIs are handled promptly even
under heavy I/O interrupt load.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-01-23 18:26:47 +00:00
Ralf Baechle c80697b3a0 [MIPS] SMTC: Fix cp0 hazard.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-01-19 01:08:26 +00:00
Atsushi Nemoto 1417836e81 [MIPS] use generic_handle_irq, handle_level_irq, handle_percpu_irq
Further incorporation of generic irq framework.  Replacing __do_IRQ()
by proper flow handler would make the irq handling path a bit simpler
and faster.

* use generic_handle_irq() instead of __do_IRQ().
* use handle_level_irq for obvious level-type irq chips.
* use handle_percpu_irq for irqs marked as IRQ_PER_CPU.
* setup .eoi routine for irq chips possibly used with handle_percpu_irq.

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-11-30 01:14:46 +00:00
Ralf Baechle 64c590b7a6 [MIPS] SMTC: Synchronize cp0 counters on bootup.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-11-01 17:46:09 +00:00
Ralf Baechle 937a801576 [MIPS] Complete fixes after removal of pt_regs argument to int handlers.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-10-08 02:38:28 +01:00
Ralf Baechle 54d0a216f4 [MIPS] Replace board_timer_setup function pointer by plat_timer_setup.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

---
2006-07-13 21:26:17 +01:00
Ralf Baechle 4bf42d4272 [MIPS] SMTC: Reformat to Linux style.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-07-13 21:26:15 +01:00
Thomas Gleixner f40298fddc [PATCH] irq-flags: MIPS: Use the new IRQF_ constants
Use the new IRQF_ constants and remove the SA_INTERRUPT define

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Ingo Molnar <mingo@elte.hu>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-07-02 13:58:47 -07:00
Ingo Molnar 34af946a22 [PATCH] spin/rwlock init cleanups
locking init cleanups:

 - convert " = SPIN_LOCK_UNLOCKED" to spin_lock_init() or DEFINE_SPINLOCK()
 - convert rwlocks in a similar manner

this patch was generated automatically.

Motivation:

 - cleanliness
 - lockdep needs control of lock initialization, which the open-coded
   variants do not give
 - it's also useful for -rt and for lock debugging in general

Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Arjan van de Ven <arjan@linux.intel.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-06-27 17:32:39 -07:00
Ralf Baechle 41c594ab65 [MIPS] MT: Improved multithreading support.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-04-19 04:14:28 +02:00