Commit Graph

9 Commits

Author SHA1 Message Date
Kuninori Morimoto 0207a2efb4 sh: Add support for SH7724 (SH-Mobile R2R) CPU subtype.
This implements initial support for the SH-Mobile R2R CPU.
Based on Rev 0.11 of the initial SH7724 hardware manual.

Signed-off-by: Kuninori Morimoto <morimoto.kuninori@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2009-04-16 14:40:56 +09:00
Kuninori Morimoto 1c58b0b1a1 sh: Tidy up sh7786 pinmux table.
Formatting and typo fix.

Signed-off-by: Kuninori Morimoto <morimoto.kuninori@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2009-03-31 07:39:51 +09:00
Paul Mundt 8263a67e16 sh: Support for extended ASIDs on PTEAEX-capable SH-X3 cores.
This adds support for extended ASIDs (up to 16-bits) on newer SH-X3 cores
that implement the PTAEX register and respective functionality. Presently
only the 65nm SH7786 (90nm only supports legacy 8-bit ASIDs).

The main change is in how the PTE is written out when loading the entry
in to the TLB, as well as in how the TLB entry is selectively flushed.

While SH-X2 extended mode splits out the memory-mapped U and I-TLB data
arrays for extra bits, extended ASID mode splits out the address arrays.
While we don't use the memory-mapped data array access, the address
array accesses are necessary for selective TLB flushes, so these are
implemented newly and replace the generic SH-4 implementation.

With this, TLB flushes in switch_mm() are almost non-existent on newer
parts.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2009-03-17 17:49:49 +09:00
Nobuhiro Iwamatsu 71b973a42c sh: dma-sh updates for multi IRQ and new SH-4A CPUs.
This adds DMA support for newer SH-4A CPUs, particularly SH7763/64/80/85.

This also enables multi IRQ support for platforms that have multiple
vectors bound to the same IRQ source.

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2009-03-10 17:26:49 +09:00
Kuninori Morimoto 55ba99eb21 sh: Add support for SH7786 CPU subtype.
This adds preliminary support for the SH7786 CPU subtype.

While this is a dual-core CPU, only UP is supported for now. L2 cache
support is likewise not yet implemented.

More information on this particular CPU subtype is available at:

	http://www.renesas.com/fmwk.jsp?cnt=sh7786_root.jsp&fp=/products/mpumcu/superh_family/sh7780_series/sh7786_group/

Signed-off-by: Kuninori Morimoto <morimoto.kuninori@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2009-03-03 15:40:25 +09:00
Paul Mundt b4d36a254f sh: Add on-chip RTC support for SH7722.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2008-10-28 18:40:19 +09:00
Magnus Damm 0835f127e5 sh: sh7785 pinmux support
This patch implements pinmux tables for the sh7785 processor.

Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2008-10-23 11:59:37 +09:00
Paul Mundt 40e24c403f sh: Move SH-4 CPU headers down one more level.
These accidentally got placed in to cpu-sh4 instead of cpu-sh4/cpu, push
them down one more level.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2008-10-20 14:30:17 +09:00
Paul Mundt f15cbe6f1a sh: migrate to arch/sh/include/
This follows the sparc changes a439fe51a1.

Most of the moving about was done with Sam's directions at:

http://marc.info/?l=linux-sh&m=121724823706062&w=2

with subsequent hacking and fixups entirely my fault.

Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2008-07-29 08:09:44 +09:00