Commit Graph

842 Commits

Author SHA1 Message Date
Ben Skeggs 6002525170 Revert "drm/nvc0: recognise 0xdX chipsets as NV_C0"
Oh boy.  That was a bad gamble.  PDISP has changed.

This reverts commit cdf81a235f.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-07-02 07:10:20 +10:00
Dave Airlie 4ee1c57fca drm/nouveau: drop leftover debugging
this printk isn't really useful, just drop it for now.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-06-20 15:27:18 +10:00
Ben Skeggs b16a5a18ff drm/nouveau: fix assumption that semaphore dmaobj is valid in x-chan sync
The DDX modifies DMA_SEMAPHORE on nv50 in order to implement sync-to-vblank,
things will go very wrong for cross-channel sync after this.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-06-18 14:56:24 +10:00
Ben Skeggs f66b3d5540 drm/nv50/disp: fix gamma with page flipping overlay turned on
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-06-18 14:38:45 +10:00
Emil Velikov 2905544073 drm/nouveau/pm: Prevent overflow in nouveau_perf_init()
While parsing the perf table, there is no check if
the num of entries read from the vbios is less than
the currently allocated number.

In case of a buggy vbios this will cause overwriting
of kernel memory, causing aditional problems.

Add a simple check in order to prevent the case

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-06-18 14:38:38 +10:00
Ben Skeggs 0897554cdd drm/nouveau: fix big-endian switch
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-06-18 14:38:27 +10:00
Ben Skeggs 4cff3ce5fe drm/nv40: fall back to paged dma object for the moment
PCI(E)GART isn't quite stable it seems, fall back to old method until I get
the time to sort it out properly.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-06-07 09:23:03 +10:00
Ben Skeggs 960bdba08e drm/nouveau: fix leak of gart mm node
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-06-07 09:22:51 +10:00
Ben Skeggs 73c337e70e drm/nouveau: fix vram page mapping when crossing page table boundaries
Hopefully the cause of nvc0 "page jumping" issue.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-06-07 09:22:48 +10:00
Francisco Jerez c1003d9c90 drm/nv17-nv40: Fix modesetting failure when pitch == 4096px (fdo bug 35901).
Reported-by: Mario Bachmann <grafgrimm77@gmx.de>
Tested-by: Greg Turner <gmturner007@ameritech.net>
Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-06-07 09:22:29 +10:00
Ben Skeggs 18b54c4d58 drm/nouveau: don't create accel engine objects when noaccel=1
Fixes various potential oopses.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-06-07 09:22:03 +10:00
Ben Skeggs cdf81a235f drm/nvc0: recognise 0xdX chipsets as NV_C0
Should hopefully get modesetting at least from this, it appears these are
GF119 chipsets.  Accel will come eventually, once I order a board.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-06-07 09:21:13 +10:00
Linus Torvalds 98b98d3163 Merge branch 'drm-core-next' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6
* 'drm-core-next' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: (169 commits)
  drivers/gpu/drm/radeon/atom.c: fix warning
  drm/radeon/kms: bump kms version number
  drm/radeon/kms: properly set num banks for fusion asics
  drm/radeon/kms/atom: move dig phy init out of modesetting
  drm/radeon/kms/cayman: fix typo in register mask
  drm/radeon/kms: fix typo in spread spectrum code
  drm/radeon/kms: fix tile_config value reported to userspace on cayman.
  drm/radeon/kms: fix incorrect comparison in cayman setup code.
  drm/radeon/kms: add wait idle ioctl for eg->cayman
  drm/radeon/cayman: setup hdp to invalidate and flush when asked
  drm/radeon/evergreen/btc/fusion: setup hdp to invalidate and flush when asked
  agp/uninorth: Fix lockups with radeon KMS and >1x.
  drm/radeon/kms: the SS_Id field in the LCD table if for LVDS only
  drm/radeon/kms: properly set the CLK_REF bit for DCE3 devices
  drm/radeon/kms: fixup eDP connector handling
  drm/radeon/kms: bail early for eDP in hotplug callback
  drm/radeon/kms: simplify hotplug handler logic
  drm/radeon/kms: rewrite DP handling
  drm/radeon/kms/atom: add support for setting DP panel mode
  drm/radeon/kms: atombios.h updates for DP panel mode
  ...
2011-05-24 12:06:40 -07:00
Randy Dunlap fb0b760605 drm: fix nouveau_acpi build
Fix build errors when CONFIG_ACPI is enabled but MXM_WMI is not enabled
by selecting both MXM_WMI and ACPI_WMI (the latter just for kconfig
dependencies):

nouveau_acpi.c:(.text+0x2400c8): undefined reference to `mxm_wmi_call_mxmx'
nouveau_acpi.c:(.text+0x2400cf): undefined reference to `mxm_wmi_call_mxds'
nouveau_acpi.c:(.text+0x2400fe): undefined reference to `mxm_wmi_call_mxmx'
nouveau_acpi.c:(.text+0x2402ba): undefined reference to `mxm_wmi_supported

Signed-off-by: Randy Dunlap <randy.dunlap@oracle.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-05-16 11:57:20 +10:00
Marcin Slusarz b4fa9d0f65 drm/nouveau: make cursor_set implementation consistent with other drivers
When xorg state tracker wants to hide the cursor it calls set_cursor
with NULL buffer_handle and size=0x0, but nouveau refuses to hide it
because size is not 64x64... which is a bit odd. Both radeon and intel
check buffer_handle before validating size of cursor, so make nouveau
implementation consistent with them.

Signed-off-by: Marcin Slusarz <marcin.slusarz@gmail.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16 10:51:05 +10:00
Ben Skeggs 52eba8dd5e drm/nva3/clk: better pll calculation when no fractional fb div available
The core/mem/shader clocks don't support the fractional feedback divider,
causing our calculated clocks to be off by quite a lot in some cases.  To
solve this we will switch to a search-based algorithm when fN is NULL.

For my NVA8 at PL3, this actually generates identical cooefficients to
the binary driver.  Hopefully that's a good sign, and that does not
break VPLL calculation for someone..

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16 10:50:59 +10:00
Ben Skeggs 96d1fcf8b5 drm/nouveau/pm: translate ramcfg strap through ram restrict table
Hopefully this is how we're supposed to correctly handle when the RAMCFG
strap is above the number of entries in timing-related tables.

It's rather difficult to confirm without finding a configuration where
the ram restrict table doesn't map 8-15 back onto 0-7 anyway.  There's
not a single vbios in the repo which is configured differently..

In any case, this is probably still better than potentially reading
outside of the bounds of various tables..

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16 10:50:57 +10:00
Ben Skeggs bfb61f43b3 drm/nva3/pm: allow use of divisor 16
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16 10:50:52 +10:00
Ben Skeggs 047d2df54c drm/nvc0/pm: parse clock for pll 0x0a (0x137020) from perf table
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16 10:50:47 +10:00
Ben Skeggs 40f6193b8f drm/nvc0/pm: correct core/mem/shader perflvl parsing
We need to parse some of these other entries still, but I've yet to
determine exactly which PLLs the rest map to.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16 10:50:42 +10:00
Ben Skeggs 730673b665 drm/nouveau/pm: remove memtiming support check when assigning to perflvl
Really not necessary here, we want to be able to see if/how we managed to
match a timingset to a performance level, even if we can't currently
program it.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16 10:50:38 +10:00
Ben Skeggs fcfc768806 drm/nva3: support for memory timing map table
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16 10:50:33 +10:00
Martin Peres e614b2e7ca drm/nouveau: Associate memtimings with performance levels on cards <= nv98
v2 (Ben Skeggs): fix ramcfg strap, and remove bogus handling of perf 0x40

Signed-off-by: Martin Peres <martin.peres@ensi-bourges.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16 10:50:30 +10:00
Ben Skeggs dac55b5825 drm/nva3/pm: initial pass at set_clock() hook
I still discourage anyone from actually doing this yet.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16 10:50:25 +10:00
Ben Skeggs aa58c40563 drm/nvc0/gr: calculate some more of our magic numbers
Again, doesn't quite match NVIDIA's, but not sure it really matters.  This
will however, match the same rules we use to calculate the other related
grctx magics.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16 10:50:22 +10:00
Ben Skeggs b23b9e7109 drm/nv50: respect LVDS link count from EDID on SPWG panels
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16 10:50:16 +10:00
Ben Skeggs 8c3f6bb970 drm/nouveau: recognise DCB connector type 0x41 as LVDS
After looking at a number of different logs, it appears 0x41 likely
indicates the presense of an LVDS panel following the SPWG spec
(http://www.spwg.org/)

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16 10:50:13 +10:00
Ben Skeggs eea55c89e5 drm/nouveau: fix uninitialised variable warning
Looks like a false positive to me, but, anyways!

Reported-by: Jimmy Rentz <jb17bsome@gmail.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16 10:50:07 +10:00
Jimmy Rentz 976661093d drm/nouveau: Fix a crash at card takedown for NV40 and older cards
NV40 and older cards (pre NV50) reserve a vram bo for the vga memory at
card init. This bo is then freed at card shutdown.  The problem is that
the ttm bo vram manager was already freed. So a crash occurs when the
vga bo is freed. The fix is to free the vga bo prior to freeing the ttm
bo vram manager. There might be other solutions but this seemed the
simplest to me.

Signed-off-by: Jimmy Rentz <jb17bsome@gmail.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16 10:50:04 +10:00
Jimmy Rentz 2abdb057e4 drm/nouveau: Free nv04 instmem ramin heap at card takedown
Add a missing nv04 instmem ramin heap shutdown call.

Signed-off-by: Jimmy Rentz <jb17bsome@gmail.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16 10:49:58 +10:00
Ben Skeggs 215f902e15 drm/nva3: somewhat improve clock reporting
Definitely not 100% correct, but, for the configurations I've seen used
it'll read back the correct clocks now.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16 10:49:54 +10:00
Ben Skeggs ce521846b9 drm/nouveau: pull refclk from vbios on limits 0x40 boards
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16 10:49:50 +10:00
Ben Skeggs 3acf67f66e drm/nv40/gr: oops, fix random bits getting set in engine obj
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16 10:49:47 +10:00
Emil Velikov 619d4f7e21 drm/nv50: improve nv50_pm_get_clock()
Many of the nv50 cards have their shader and/or memory pll
disabled at some stage.
This patch addresses those cases, so that the function
returns the correct frequency.

When the shader pll is disabled, the blob reports 2*core clock
Whereas for memory, the data stored in the vbios. This action
is incorrect as some vbioses store a clock value that is less
than the refference clock of the pll.

Thus we are reporting the reff_clk as it is the frequency the
pll actually operates

v2 - Convert NV_INFO() messages to NV_DEBUG()
Provide more information in the actuall message

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16 10:49:41 +10:00
Martin Peres 1f962797fb drm/nouveau/pm: fix compilation failure when CONFIG_POWER_SUPPLY is not set
Signed-off-by: Martin Peres <martin.peres@ensi-bourges.fr>
Reported-by: Stratos Psomadakis <psomas@ece.ntua.gr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16 10:49:34 +10:00
Ben Skeggs 1233bd8d31 drm/nvc0/fifo: stick user area into a gpuobj rather than a bo
Contents will now be preserved across a suspend, unlike a pinned bo

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16 10:49:30 +10:00
Ben Skeggs 1d97f4acd3 drm/nvc0/gr: no need to store context in graph_fini()
PFIFO kickoff should have handled this for us.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16 10:49:26 +10:00
Ben Skeggs 0638df425f drm/nvc0/fifo: restore context table on resume
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16 10:49:22 +10:00
Ben Skeggs 7a5c23de36 drm/nvc0/fifo: kick channels off during suspend
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16 10:49:17 +10:00
Ben Skeggs fe799114e2 drm/nvc0/gr: better handling of fuc firmware
Allows per-chipset firmware to be installed, and keeps a copy in memory
for suspend/resume purposes.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16 10:49:13 +10:00
Ben Skeggs 9548258fbc drm/nv50: support PMPEG on original nv50
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16 10:49:08 +10:00
Ben Skeggs 93187450fa drm/nv50: rename nv84_mpeg to nv50_mpeg
In preparation for adding 0x50 support.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16 10:49:04 +10:00
Ben Skeggs c0924326c8 drm/nv84: add support for PMPEG
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16 10:48:59 +10:00
Ben Skeggs a02ccc7f97 drm/nv40/vpe: add support for PMPEG
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16 10:48:56 +10:00
Ben Skeggs d5a27370b5 drm/nvc0: implement support for copy engines
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16 10:48:53 +10:00
Ben Skeggs 7ff5441e55 drm/nva3: implement support for copy engine
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16 10:48:48 +10:00
Ben Skeggs a82dd49f14 drm/nouveau: remove remnants of nouveau_pgraph_engine
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16 10:48:45 +10:00
Ben Skeggs 92abe74992 drm/nouveau: fix suspend failure path to reinitialise all engines
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16 10:48:42 +10:00
Ben Skeggs 39a654d5b9 drm/nouveau: remove remnants of nouveau_pgraph_engine from nouveau_channel
The nouveau_wait_for_idle() call should hopefully not have been actually
necessary, we *do* wait for the channel to go idle already.  If it's
an issue somehow, the chipset-specific hooks can wait for idle themselves
before taking the lock.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16 10:48:37 +10:00
Ben Skeggs 96c5008290 drm/nouveau: move set_tile_region to nouveau_exec_engine
In the very least VPE (PMPEG and friends) also has this style of tile
region regs, lets make them just work if/when they get added.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16 10:48:33 +10:00