Commit Graph

105 Commits

Author SHA1 Message Date
Felipe Balbi b673cf3002 usb: dwc3: ep0: fix Get Status handling
data was prepared on setup_buf but transfer
was started on ctrl_req, fix it.

Signed-off-by: Felipe Balbi <balbi@ti.com>
2011-09-09 13:02:15 +03:00
Felipe Balbi c7fcdeb262 usb: dwc3: ep0: simplify EP0 state machine
The DesignWare USB3 core tells us which phase
of a control transfer should be started, it
also tells us which physical endpoint needs
that transfer.

With these two informations, we have all we
need to simply EP0 handling quite a lot and
get rid rid of the SW state machine tracking
ep0 states.

For achieving this perfectly, we needed to
add support for situations where we get
XferNotReady while endpoint is still busy
and XferNotReady while gadget driver still
hasn't queued a request.

Signed-off-by: Felipe Balbi <balbi@ti.com>
2011-09-09 13:02:07 +03:00
Felipe Balbi a6829706ce usb: dwc3: ep0: add handling for unaligned OUT transfers
In case we have transfers which aren't aligned
to wMaxPacketSize, we need to be careful with
how we start the transfer with the HW. OUT
transfers _must_ be aligned with wMaxPacketSize
and in order to guarantee that, we use a bounce
buffer.

Signed-off-by: Felipe Balbi <balbi@ti.com>
2011-09-09 13:02:05 +03:00
Felipe Balbi c611ccb48a usb: dwc3: ep0: fix 'transfered' typo
trivial patch. No functional changes.

Signed-off-by: Felipe Balbi <balbi@ti.com>
2011-09-09 13:02:00 +03:00
Felipe Balbi 72246da40f usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.

Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.

The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.

More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.

While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.

[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2

Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-22 16:03:11 -07:00