This clock provider uses the consumer API, so include clk.h
explicitly.
Cc: Andrew Bresticker <abrestic@chromium.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
When setting the PLL rates, check that:
- VCO is within range
- PFD is within range
- PLL is disabled when postdiv is changed
- postdiv2 <= postdiv1
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Kevin Cernekee <cernekee@chromium.org>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@imgtec.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Currently, when the rate is changed, the driver makes sure the
PLL is enabled before doing so. This is done because the PLL
cannot be locked while disabled. Once locked, the drivers
returns the PLL to its previous enable/disable state.
This is a bit cumbersome, and can be simplified.
This commit reworks the .set_rate() functions for the integer
and fractional PLLs. Upon rate change, the PLL is now locked
only if it's already enabled.
Also, the driver locks the PLL on .enable(). This makes sure
the PLL is locked when enabled, and not locked when disabled.
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@imgtec.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This commit adds a pll_lock() helper making the code more readable.
Cosmetic change only, no functionality changes.
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@imgtec.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Register the clock gates for the external audio and ethernet
reference clocks provided by the top-level general control block.
Signed-off-by: Damien Horsley <Damien.Horsley@imgtec.com>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: devicetree@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: Ezequiel Garcia <ezequiel.garcia@imgtec.com>
Cc: James Hartley <james.hartley@imgtec.com>
Cc: James Hogan <james.hogan@imgtec.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Patchwork: https://patchwork.linux-mips.org/patch/9321/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Register the system interface gate clocks provided by the peripheral
general control block. These clocks gate register access for various
peripherals.
Signed-off-by: Damien Horsley <Damien.Horsley@imgtec.com>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: devicetree@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: Ezequiel Garcia <ezequiel.garcia@imgtec.com>
Cc: James Hartley <james.hartley@imgtec.com>
Cc: James Hogan <james.hogan@imgtec.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Patchwork: https://patchwork.linux-mips.org/patch/9322/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Register the clocks generated by the peripheral clock controller.
This includes the clocks for several peripherals, including I2C,
PWM, watchdog, and timer.
Signed-off-by: Damien Horsley <Damien.Horsley@imgtec.com>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: devicetree@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: Ezequiel Garcia <ezequiel.garcia@imgtec.com>
Cc: James Hartley <james.hartley@imgtec.com>
Cc: James Hogan <james.hogan@imgtec.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Patchwork: https://patchwork.linux-mips.org/patch/9320/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Register the clocks generated by the core clock controller.
This includes the 7 PLLs and clocks for the CPU, RPU co-processor,
audio, WiFi, bluetooth, and several other peripherals.
The MIPS and PERIPH_SYS clocks must remain enabled at all times.
Signed-off-by: Damien Horsley <Damien.Horsley@imgtec.com>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: devicetree@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: Ezequiel Garcia <ezequiel.garcia@imgtec.com>
Cc: James Hartley <james.hartley@imgtec.com>
Cc: James Hogan <james.hogan@imgtec.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Patchwork: https://patchwork.linux-mips.org/patch/9317/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Add a driver for the integer (GF40LP_LAINT) and fractional (GF40LP_FRAC)
PLLs present on Pistachio.
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: devicetree@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: Ezequiel Garcia <ezequiel.garcia@imgtec.com>
Cc: James Hartley <james.hartley@imgtec.com>
Cc: James Hogan <james.hogan@imgtec.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Patchwork: https://patchwork.linux-mips.org/patch/9316/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Stephen Boyd