Device aliases are board-specific, if needed one should define them
in board dts rather than in the SoC dtsi. If an alias from the SoC
dtsi is addressed by a driver that does not use any of the of_alias*()
methods, we can drop it. This is the case for the i2s aliases, drop
them. tcb aliases point to nodes that are not enabled in any of the
sama5d2 based platforms. atmel_tclib.c is scheduled to go away, any
board using that alias is already broken, so get rid of the tcb aliases
too.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20200514050301.147442-14-tudor.ambarus@microchip.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Spare boards of duplicating the DMA bindings. Describe the flx0
DMA bindings in the SoC dtsi. Users that don't want to use DMA
for their flexcom functions have to overwrite the flexcom DMA
bindings in their board device tree.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20200514050301.147442-12-tudor.ambarus@microchip.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Spare boards of duplicating the DMA bindings. Describe the flx1
DMA bindings in the SoC dtsi. Users that don't want to use DMA
for their flexcom functions have to overwrite the flexcom DMA
bindings in their board device tree.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20200514050301.147442-11-tudor.ambarus@microchip.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Spare boards of duplicating the DMA bindings. Describe the flx3
DMA bindings in the SoC dtsi. Users that don't want to use DMA
for their flexcom functions have to overwrite the flexcom DMA
bindings in their board device tree.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20200514050301.147442-10-tudor.ambarus@microchip.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Spare boards of duplicating the DMA bindings. Describe the flx4
DMA bindings in the SoC dtsi. Users that don't want to use DMA
for their flexcom functions have to overwrite the flexcom DMA
bindings in their board device tree.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20200514050301.147442-9-tudor.ambarus@microchip.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
The UART submodule in Flexcom has 32-byte Transmit and Receive FIFOs.
Tested uart7 on sama5d2-icp, which has both DMA and FIFO enabled.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20200514050301.147442-8-tudor.ambarus@microchip.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
The Flexcom IP is part of the sama5d2 SoC. Move the flx0 node together
with its function definitions in sama5d2.dtsi. Boards will just fill
the pins and enable the desired functions.
There is a single functional change in this patch. With the move of the
flx0 uart5 definition in the SoC dtsi, the uart5 from
at91-sama5d27_wlsom1_ek.dts inherits the following optional property:
atmel,fifo-size = <32>;
This particular change was tested by Codrin.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Tested-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
Link: https://lore.kernel.org/r/20200514050301.147442-7-tudor.ambarus@microchip.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
The Flexcom IP is part of the sama5d2 SoC. Move the flx0 node together
with its function definitions in sama5d2.dtsi. Boards will just fill
the pins and enable the desired functions.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20200514050301.147442-6-tudor.ambarus@microchip.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
The Flexcom IP is part of the sama5d2 SoC. Move the flx2 node together
with its function definitions in sama5d2.dtsi. Boards will just fill
the pins and enable the desired functions.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20200514050301.147442-5-tudor.ambarus@microchip.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
The Flexcom IP is part of the sama5d2 SoC. Move the flx3 node together
with its function definitions in sama5d2.dtsi. Boards will just fill
the pins and enable the desired functions.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20200514050301.147442-4-tudor.ambarus@microchip.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
The Flexcom IP is part of the sama5d2 SoC. Move the flx0 node together
with its function definitions in sama5d2.dtsi. Boards will just fill
the pins and enable the desired functions.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20200514050301.147442-3-tudor.ambarus@microchip.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Document the iW-RainboW-G21D-Qseven-RZG1H device tree bindings,
listing it as a supported board.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/1588542414-14826-9-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Document the iW-RainboW-G21M-Qseven-RZG1H device tree bindings,
listing it as a supported system on module.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/1588542414-14826-8-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Presumably the GPU node needs to control both the GPU and GPU GX power
domains, but given that GPU GX now depends on the GPU GDSC both can
effectively be controlled by controlling GPU GX. So use this instead.
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20200417070044.1376212-5-bjorn.andersson@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Add the SPMI regulator node in the PMI8994, use it to give us VDD_GX
at a fixed max nominal voltage for the db820c and specify this as supply
for the MMSS GPU_GX GDSC.
With the introduction of CPR support the range for VDD_GX should be
expanded.
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Link: https://lore.kernel.org/r/20200417070044.1376212-4-bjorn.andersson@linaro.org
[bjorn: Split between pmi8994 and db820c, changed voltage, rewrote commit message]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
apq8016-sbc.dtsi is the only remaining device which takes up
4 files since it has its pinctrl split into separate files.
Actually this does not really make the device tree easier to read
(just harder to find nodes). For db820c the files were merged in
commit 88264f1f6b ("arm64: dts: qcom: db820c: Remove pin specific files").
Do the same for apq8016-sbc (db410c) and move the pinctrl definitions
into apq8016-sbc.dtsi.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20200514112754.148919-3-stephan@gerhold.net
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
In msm8916.dtsi the GPU OPP table is defined under the root node,
whereas in msm8996.dtsi/sdm845.dtsi it is a subnode of the gpu device
(which makes it easier to find).
Move it to the gpu device node to make this consistent.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20200514112754.148919-2-stephan@gerhold.net
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Many nodes in the MSM8916 device trees use '_' in node names
(especially pinctrl), even though (seemingly) '-' is preferred now.
Make this more consistent by replacing '_' with '-' where possible.
Similar naming is used for pinctrl in newer device trees (e.g. sdm845.dtsi).
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20200514112754.148919-1-stephan@gerhold.net
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
On some device the reset line for the UFS memory needs to be tickled in
order for UFS to initialize properly, add this to the ufs_mem_hc node.
Reviewed-by: Robert Foss <robert.foss@linaro.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20200406060049.227029-1-bjorn.andersson@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Specify regulators and enable the &wifi node. The firmware uses the 8
bit version of the host capability message, so specify this quirk.
Reviewed-by: Robert Foss <robert.foss@linaro.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20191018055841.3729591-1-bjorn.andersson@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
The Avenger96 is in fact an assembly of DH Electronics DHCOR SoM on top
of an Avenger96 reference board. The DHCOR SoM can be populated with any
STM32MP15xx. Split the DTs to reflect this such that the common SoM and
Avenger96 parts are now in stm32mp15xx-dhcor-*dtsi and a specific example
implementation of STM32MP157A SoM and Avenger96 board is separated into
stm32mp157a-dhcor-*dts* . The stm32mp157a-avenger96.dts is retained for
the sake of backward naming compatibility.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
The DH Electronics PDK2 can be populated with SoM with any STM32MP15xx
variant. Split the SoC-independent parts of the SoM and PDK2 into the
stm32mp15xx-dhcom-*.dtsi and reduce stm32mp157c-dhcom-*dts* to example
of adding STM32MP157C variant of the SoM into a PDK2 carrier board.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Add bindings for the four GPIO LEDs on DH PDK2 board. Note that LED5
GPIO-E may conflict with touchscreen interrupt, hence LED5 must be
disabled when using the DH 560-200 display unit with touchscreen.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Add bindings for the four GPIO keys on DH PDK2 board. Note that TA1
key is polled because it's IRQ line conflicts with ethernet IRQ, the
rest of the GPIO keys, TA2, TA3, TA4, are interrupt-driven and wake
up sources.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
It's uncertain where the "vreg_s8a_l3a_input" comes from, but the supply
for VDD_L3_L11 on PM8994 should be VREG_S3A_1P3, so correct this - and
drop the vreg_s8a_l3a_input.
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Fixes: 83d9ed4342 ("arm64: dts: qcom: db820c: Use regulator names from schematics")
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20200417070712.1376355-1-bjorn.andersson@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
The PMI8994 provides 3 SPMS regulators and one boost/bypass regulator.
Define s1 and the boot/bypass and update pm8994 to appropriately
describe the supply from PMI8994.
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20200417070303.1376290-1-bjorn.andersson@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
IoT Box is an IoT gateway device based on Stinger96 board powered by
STM32MP1 SoC, designed and manufactured by Shiratech Solutions. This
device makes use of Stinger96 board by having it as a base board with
one additional mezzanine on top.
Following are the features exposed by this device in addition to the
Stinger96 board:
* WiFi/BT
* CCS811 VOC sensor
* 2x Digital microphones IM69D130
* 12x WS2812B LEDs
Following peripherals are tested and known to work:
* WiFi/BT
* CCS811
More information about this device can be found in Shiratech website:
https://www.shiratech-solutions.com/products/iot-box/
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Stinger96 is a 96Boards IoT Extended edition board designed and
manufactured by Shiratech solutions based on STM32MP1 SoC. Following
are the features of this board:
* 256MB DDR
* 125MB NAND Flash
* Onboard BG96 modem
* 1x uSD
* 2x USB (1 available as external connector and another connected to BG96)
* 1x SPI
* 1x PCM
* 2x UART (apart from serial console)
* 2x I2C (apart from one connected to PMIC)
Following peripherals are tested and known to work:
* BG96 modem
* 1x I2C (LS-I2C0)
* 1x SPI
* 1x UART (LS-UART0)
* USB (Only Gadget mode)
* uSD
More information about this board can be found in Shiratech website:
https://www.shiratech-solutions.com/products/stinger96/
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
These pinctrl definitions will be used by Stinger96/IoTBox boards
from Shiratech.
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
On some msm8916 devices, attempts at initializing coresight cause the boot to
fail. This was fixed by disabling the coresight-related nodes in the board dts
files. However, a cleaner approach was chosen for fixing the same issue on
msm8998: disabling coresight by default, and enabling it in board dts files
where desired.
This patch implements the same solution for msm8916, removes now redundant
overwrites in board specific dts files and and enables coresight in db410c's
board dts in order to keep the current behavior.
Fixes: b1fcc5702a ("arm64: dts: qcom: msm8916: Add CTI options")
Signed-off-by: Michael Srba <michael.srba@seznam.cz>
Reviewed-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com>
Link: https://lore.kernel.org/r/20200513184735.30104-1-michael.srba@seznam.cz
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Enable CPU opp tables for Tanix TX6.
Also add the fixed regulator that provided vdd-cpu-gpu required for
CPU opp tables.
This voltage has been found using a voltmeter and could be wrong.
Tested-by: Jernej Škrabec <jernej.skrabec@gmail.com>
Signed-off-by: Clément Péron <peron.clem@gmail.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Some boards have a fixed regulator and can't reach the voltage set
by the OPP table.
Add a range where the minimal voltage is the target and the maximal
voltage is 1.2V.
Suggested-by: Ondřej Jirman <megous@megous.com>
Signed-off-by: Clément Péron <peron.clem@gmail.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
The Tegra210 features an instance of the Tegra I2C controller that is
part of the host1x domain and typically used for camera use-cases. It
uses pretty much the same programming model but the registers are laid
out differently.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Tegra contains VI controller which can support up to 6 MIPI CSI
camera sensors.
Each Tegra CSI port from CSI unit can be one-to-one mapper to
VI channel and can capture from an external camera sensor or
from built-in test pattern generator.
This patch adds dt-bindings for Tegra VI and CSI.
Acked-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add device-tree binding that describes CPU frequency-scaling hardware
found on NVIDIA Tegra20/30 SoCs.
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add the binding document for the external memory controller (EMC) which
communicates with external LPDDR4 devices. It includes the bindings of
the EMC node and a sub-node of EMC table which under the reserved memory
node. The EMC table contains the data of the rates that EMC supported.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
clk_out_1, clk_out_2, clk_out_3, blink are part of Tegra PMC block so
these clocks should be provided by the Tegra PMC. IDs for these clocks
have been defined in dt-bindings/soc/tegra-pmc.h.
This patch removes the IDs for these clocks from the Tegra clock device
tree bindings.
Tested-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Tegra210 uses PLLD out internally for CSI TPG. This patch adds a clock
ID for this CSI TPG clock from PLLD.
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The example in the bindings and all the current users (except sc7180)
have "no-map". I'm pretty sure we need it on sc7180 too. Add it.
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Fixes: e0abc5eb52 ("arm64: dts: qcom: sc7180: Add cmd_db reserved area")
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20200424085121.1.I9d1e84d30f488cdb5a957f582abaecd2c0b24d70@changeid
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
A5U uses a Melfas MMS345L touchscreen that is connected to
blsp_i2c5. Add it to the device tree.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20200426140642.204395-5-stephan@gerhold.net
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
A3U and A5U both use an extra touchscreen LDO regulator
that provides 3.3V for the touch screen controller.
Add it as fixed regulator to the common include.
Cc: Michael Srba <Michael.Srba@seznam.cz>
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20200426140642.204395-4-stephan@gerhold.net
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
MSM8916 has another I2C QUP controller that can be enabled on
GPIO 18 and 19.
Add blsp_i2c5 to msm8916.dtsi and disable it by default.
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20200426140642.204395-3-stephan@gerhold.net
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
MSM8916 has another I2C QUP controller that can be enabled on
GPIO 2 and 3.
Add blsp_i2c1 to msm8916.dtsi and disable it by default.
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20200426140642.204395-2-stephan@gerhold.net
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Now that deep idle states are properly supported on SC7180,
we need to add "coresight-loses-context-with-cpu" property
to avoid failure of trace session because of losing context
on entering deep idle states.
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Link: https://lore.kernel.org/r/20200424111644.27970-1-saiprakash.ranjan@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Tudor Ambarus