CPU frequency cannot be scaled.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.14 (GNU/Linux)
iQIcBAABAgAGBQJTGoj7AAoJEDqPOy9afJhJm6oQAMEw19Xyz/Of4n4/7sTogL+G
SXSQK9Ava2rbYNaPrU267dpgFausCQZNIN2uCsrvQtIsWq6ScInKgVxjXUHhE2rm
F2UkapBBctPhJYKS1W+6WzZzUNNE1Lo4Ab33GlpWV+DBZlJ/XFVDmgbtEs/H59lC
woedh6q9JZSDa8QSk8t4gG7Fkk15ImgXI2pm9/WiCkh7ZHLgBPTGOpe9rVOiieNf
uzALWBhpgySEJXDjqK2O6cbng11EvUJGmLYxrOwfOBwcnLe4fk6t26KEovT0e/2s
HidGVoiGSMWZfY1xrnHaehJvqO7qu7iBsWfn5KRFoMW7NbjDKFUg5YfEIjuh3R/J
KSEHovNO/PmS2xyQowLplgP2pAuHfZ80oRgsOWZ1fG3CCfXghfr5WVMAL1pqtSQV
HzTqm+Aiaf4rbKOTcGISYBjG+X7/wU0w/tvDgjpoMo08mR+RmmTC0wkauWXmDOZQ
P91lWuUtSbpY2B9JdjVNHKTLWpKD8nDBV+aTXj4OwxVIk6s9FhNw6+++9l46OrT8
02BVhU0Z3rg20o69Nx1vShQFN7vhxsKXC9UePdpt3NnlgUUe1JYiVe44ut/AMr5O
PIAXQQXj+zgFQX8PdKtLAvRO2DnF4OpCH758AXywmarYZYDahmc6XSJTEqsk3Tbt
rQCfsnVwgbyQTHfvgqk7
=UEPE
-----END PGP SIGNATURE-----
Merge tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mike.turquette/linux
Pull clk driver fix from Mike Turquette:
"Single fix for a clock driver merged in 3.14-rc1. Without this fix
the CPU frequency cannot be scaled"
* tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mike.turquette/linux:
clk: shmobile: rcar-gen2: Use kick bit to allow Z clock frequency change
The Z clock frequency change is effective only after setting the kick
bit located in the FRQCRB register.
Without that, the CA15 CPUs clock rate will never change.
Fix that by checking if the kick bit is cleared and enable it to make
the clock rate change effective. The bit is cleared automatically upon
completion.
Signed-off-by: Benoit Cousson <bcousson+renesas@baylibre.com>
Acked-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
The qspi clock divisor is incorrectly set to twice the value it should
have, possibly because it has been computed based on PLL1 as the clock
parent instead of PLL1 / 2 (the datasheets specifies the qspi nominal
frequencies, not the divisor values). Fix it.
Reported-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Geert Uytterhoeven <geert@linux-m68k.org>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
The lb, qspi, sdh, sd0 and sd1 clocks have the PLL1 (divided by 2) as
their parent, not the main clock. Fix it.
Reported-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Geert Uytterhoeven <geert@linux-m68k.org>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
The R-Car Gen2 SoCs (R8A7790 and R8A7791) have several clocks that are
too custom to be supported in a generic driver. Those clocks can be
divided in two categories:
- Fixed rate clocks with multiplier and divisor set according to boot
mode configuration
- Custom divider clocks with SoC-specific divider values
This driver supports both.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>