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3 Commits

Author SHA1 Message Date
Shawn Guo 3320f39bee clk: hi3798cv200: correct parent mux clock for 'clk_sdio0_ciu' 
Other than 'mmc_mux', 'clk_sdio0_ciu' uses a different parent mux clock.
Let's add this mux clock as 'sdio0_mux', and correct the parent of
'clk_sdio0_ciu' to be it.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
 2017-11-14 09:49:00 -08:00
Jiancheng Xue 0d84659619 clk: hisilicon: add usb2 clocks for hi3798cv200 SoC 
Add usb2 clocks for hi3798cv200 SoC.

Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com>
Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
 2017-06-21 10:46:45 -07:00
Jiancheng Xue 707d33cb0b clk: hisilicon: add CRG driver for Hi3798CV200 SoC 
Add CRG driver for Hi3798CV200 SoC. CRG(Clock and Reset
Generator) module generates clock and reset signals used
by other module blocks on SoC.

Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
 2016-11-11 15:43:49 -08:00