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4 Commits

Author SHA1 Message Date
Anson Huang 0c40e631cd mailbox: imx: use devm_platform_ioremap_resource() to simplify code 
Use the new helper devm_platform_ioremap_resource() which wraps the
platform_get_resource() and devm_ioremap_resource() together, to
simplify the code.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Mukesh Ojha <mojha@codeaurora.org>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
 2019-05-09 00:40:49 -05:00
Anson Huang 17b860bbfc mailbox: imx: keep MU irq working during suspend/resume 
During noirq suspend phase, mailbox MU irq will be masked
but many drivers still need to communicate with system
controller firmware via mailbox, if MU irq is masked, it
will cause RPC timeout as below:

[   23.372103] imx-scu scu: RPC send msg timeout

Setting MU irq to be wakeup source is NOT working as GIC
driver does NOT have .irq_set_wake implemented, so to
support suspend/resume, just make imx mailbox driver NOT
suspend, since MU is always a wakeup source on i.MX platforms
with system controller inside, and its power/clock is
maintained by system controller, mailbox driver no need
to manage them.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
 2019-03-11 02:51:43 -05:00
Thierry Reding 4013286c72 mailbox: imx: Use device-managed registration API 
Get rid of some boilerplate driver removal code by using the newly added
device-managed registration API.

Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
 2018-12-21 16:49:25 -06:00
Oleksij Rempel 2bb7005696 mailbox: Add support for i.MX messaging unit 
The i.MX Messaging Unit is a two side block which allows applications
implement communication over this sides.

The MU includes the following features:
- Messaging control by interrupts or by polling
- Four general-purpose interrupt requests reflected to the other side
- Three general-purpose flags reflected to the other side
- Four receive registers with maskable interrupt
- Four transmit registers with maskable interrupt

Reviewed-by: Vladimir Zapolskiy <vz@mleia.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
 2018-08-15 09:53:07 +05:30