Device manufacturers frequently provide register sequences, usually not
fully documented, to be run at startup in order to provide better defaults
for devices (for example, improving performance in the light of silicon
evaluation). Support such updates by allowing drivers to register update
sets with the core. These updates will be written to the device immediately
and will also be rewritten when the cache is synced.
The assumption is that the reason for resyncing the cache will always be
that the device has been powered off. If this turns out to not be the case
then a separate operation can be provided.
Currently the implementation only allows a single set of updates to be
specified for a device, this could be extended in future.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Allows devices to discover their own interrupt without having to remember
it themselves.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Sometimes the register map information may change in ways that drivers can
discover at runtime. For example, new revisions of a device may add new
registers. Support runtime discovery by drivers by allowing the register
cache to be reinitialised with a new function regmap_reinit_cache() which
discards the existing cache and creates a new one.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Currently we only trace physical reads, there's no instrumentation if
the read is satisfied from cache.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Some users of regmap_update_bits() would like to be able to tell their
users if they actually did an update so provide a variant which also
returns a flag indicating if an update took place. We could return a
tristate in the return value of regmap_update_bits() but this makes the
API more cumbersome to use and doesn't fit with the general zero for
success idiom we have.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
While the IRQ core doesn't currently support shared threaded interrupts
that's no reason for drivers not to do their bit and report IRQ_NONE when
they don't get an interrupt. This allows the core spurious/wedget interrupt
detection support to do its thing.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
The debugfs functions don't stub themselves out quite so well as might
be desirable so provide functions which do do this stubbing.
Reported-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Show the register ranges we have in each rbtree node in debugfs, plus
some statistics on how big each node is and the total number of nodes.
It may also be worth collecting data on the ranges of dirty registers
to see if there's much mileage in trying to coalesce writes on sync.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
If the new register value is identical to the original one then suppress
the write to the hardware in regmap_update_bits(), saving some I/O cost.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
There should be no situation where it offers any advantage over rbtree
and there are no current users so remove the code for simplicity.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
One of the reasons for using a cache is to have a software shadow of a register
which is writable but not readable. This allows us to do a read-modify-write
operation on such a register.
Currently regcache checks whether a register is readable when performing a
cached read and returns an error if it is not. Drop this check, since it will
prevent us from using the cache for registers where read-back is not possible.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
regcache currently only properly works with val bit sizes of 8 or 16, since
it will, when calculating the cache word size, round down. This causes the
cache storage to be too small to hold the full register value. Fix this by
rounding up instead.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
This patch adds support for 10 bits register, 14 bits value type register
formating. This is for example used by the Analog Devices AD5380.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
For some register format types we do not provide a parse_val so we can not do a
hardware read. But a cached read is still possible, so try to read from the
cache first, before checking whether a hardware read is possible. Otherwise the
cache becomes pretty useless for these register types.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
The reg_defaults field usually points to a static per driver array, which should
not be modified. Make requirement this explicit by making reg_defaults const.
To allow this the regcache_init code needs some minor changes. Previoulsy the
reg_config was not available in regcache_init and regmap->reg_defaults was used
to pass the default register set to regcache_init. Now that the reg_config is
available we can work on it directly.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Move the initialization regcache related fields of the regmap struct to
regcache_init. This allows us to keep regmap and regcache code better
separated.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Calling regcache_exit from regcache_lzo_init is first of all a layering
violation and secondly will cause double frees. regcache_exit will free buffers
allocated by the core, but the core will also free the same buffers when the
cacheops init callback returns an error. Thus we end up with a double free.
Fix this by not calling regcache_exit but only free those buffers which, have
been allocated in this function.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Acked-by: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Calling regcache_exit from regcache_rbtree_init is first of all a layering
violation and secondly will cause double frees. regcache_exit will free buffers
allocated by the core, but the core will also free the same buffers when the
cacheops init callback returns an error. Thus we end up with a double free.
Fix this by not calling regcache_exit but only free those buffers which, have
been allocated in this function.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Acked-by: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Make sure all allocated memory gets freed again in case initializing the cache
failed.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Acked-by: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Make sure reg_defaults_raw gets freed in case of an error.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Acked-by: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
The regmap_init documentation states that it will either return a pointer to a
valid regmap structure or a ERR_PTR in case of an error. Currently it returns a
NULL pointer in case no bus or no config was given. Since NULL is not a
ERR_PTR a caller might assume that it is a pointer to a valid regmap structure,
so return a ERR_PTR(-EINVAL) instead.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
If regcache initialization fails regmap_init will currently exit without
freeing work_buf.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Commit 10a08d9f ("regmap: Support some block operations on cached devices")
allowed raw read operations without throwing a warning when using caches if
all registers are volatile. This patch does the same for raw write operations.
This is for example useful when loading a firmware in a predefined volatile
region on a chip where we otherwise want registers to be cached.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
We already have the same code for checking whether a register range is volatile
in two different places. Instead of duplicating it once more add a small helper
function for checking whether a register range is voltaile.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Users probably don't care about the specific compression algorithm and
we might want to use a different algorithm (snappy being the one I'm
thinking of right now) so update the public interface to have a more
generic name.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Allow drivers to optimise out the register cache sync if they didn't need
to do one. If the hardware is desynced from the register cache (by power
loss for example) then the driver should call regcache_mark_dirty() to
let the core know about this.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Give regcache_lzo_block_count() a copy of the map so that when we decide
we want to make the LZO cache more controllable we can more easily do so.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
There seem to be lots of regmap-using devices with very similar interrupt
controllers with a small bank of interrupt registers and mask registers
with an interrupt per bit. This won't cover everything but it's a good
start.
Each chip supplies a base for the status registers, a base for the mask
registers, an optional base for writing acknowledgements (which may be the
same as the status registers) and an array of bits within each of these
register banks which indicate the interrupt.
There is an assumption that the bit for each interrupt will be the same
in each of the register bank.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Most of these files were implicitly getting EXPORT_SYMBOL via
device.h which was including module.h, but that path will be broken
soon.
[ with input from Stephen Rothwell <sfr@canb.auug.org.au> ]
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
* 'for-linus' of git://opensource.wolfsonmicro.com/regmap: (62 commits)
mfd: Enable rbtree cache for wm831x devices
regmap: Support some block operations on cached devices
regmap: Allow caches for devices with no defaults
regmap: Ensure rbtree syncs registers set to zero properly
regmap: Allow rbtree to cache zero default values
regmap: Warn on raw I/O as well as bulk reads that bypass cache
regmap: Return a sensible error code if we fail to read the cache
regmap: Use bsearch() to search the register defaults
regmap: Fix doc comment
regmap: Optimize the lookup path to use binary search
regmap: Ensure we scream if we enable cache bypass/only at the same time
regmap: Implement regcache_cache_bypass helper function
regmap: Save/restore the bypass state upon syncing
regmap: Lock the sync path, ensure we use the lockless _regmap_write()
regmap: Fix apostrophe usage
regmap: Make _regmap_write() global
regmap: Fix lock used for regcache_cache_only()
regmap: Grab the lock in regcache_cache_only()
regmap: Modify map->cache_bypass directly
regmap: Fix regcache_sync generic implementation
...
Support raw reads if all the registers being read are volatile, the cache
will have no impact for tem.
Support bulk reads either directly (if all the registers are volatile) or
by falling back to iterating over single register reads otherwise.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
We only really need the defaults in order to cut down the number of
registers we sync and to satisfy reads while the device is powered off
but not all devices are going to need to do that (always on devices like
PMICs being the prime example) so don't require those devices to supply
a default. Instead only try to fall back to hardware defaults if the
driver told us to.
Devices using LZO won't be able to instantiate with this, that will require
some updates in the LZO code to handle this case.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
Simplify the check for registers set at their default value by avoiding
picking a default value in the case where we don't have one. Instead we
only compare the current value to the current value when we looked one
up. This fixes the case where we don't have a default stored but the value
was set to zero when that isn't the chip default.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
Ensure that when we start up in cache only mode we can store defaults of
zero, otherwise if the hardware is unavailable we won't be able to read.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
As with the bulk reads we really should be able to make these play
nicely with the cache but warn for now.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
If a register isn't cached then let callers know that so they can fall
back or error handle appropriately.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
Rather than open coding a binary search use the standard bsearch() using
the comparison function we're already using for sort() on insert. This
fixes a lockup I was observing due to iterating on min <= max rather
than min < max when we fail to look up.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
Since there are more lookups than insertions in a typical
scenario, optimize the linear search into a binary search. For
this to work, we need to keep reg_defaults sorted upon
insertions, for now be lazy and use sort().
Signed-off-by: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Ensure we've got a function so users can enable/disable the
cache bypass option.
Signed-off-by: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Mark Brown