Commit Graph

17 Commits

Author SHA1 Message Date
Rob Herring 250a27237e ARM: shmobile: remove NR_IRQS
Remove NR_IRQS and explicitly include mach/irqs.h as needed. shmobile
properly allocates irq_descs for each irqchip, so setting .nr_irqs for
each machine is not needed.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
2012-01-25 20:37:51 -06:00
Rafael J. Wysocki 0f966d74cf PM / shmobile: Don't include SH7372's INTCS in syscore suspend/resume
Since the SH7372's INTCS in included into syscore suspend/resume,
which causes the chip to be accessed when PM domains have been
turned off during system suspend, the A4R domain containing the
INTCS has to stay on during system sleep, which is suboptimal
from the power consumption point of view.

For this reason, add a new INTC flag, skip_syscore_suspend, to mark
the INTCS for intc_suspend() and intc_resume(), so that they don't
touch it.  This allows the A4R domain to be turned off during
system suspend and the INTCS state is resrored during system
resume by the A4R's "power on" code.

Suggested-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Acked-by: Magnus Damm <damm@opensource.se>
2011-12-25 23:39:11 +01:00
Magnus Damm f7dadb3793 PM / shmobile: Add support for the sh7372 A4S power domain / sleep mode
The sh7372 contains a power domain named A4S which in turn
contains power domains for both I/O Devices and CPU cores.

At this point only System wide Suspend-to-RAM is supported,
but the the hardware can also support CPUIdle. With more
efforts in the future CPUIdle can work with bot A4S and A3SM.

Tested on the sh7372 Mackerel board.

[rjw: Rebased on top of the current linux-pm tree.]

Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
2011-12-25 23:39:03 +01:00
Magnus Damm da5713ef03 ARM: mach-shmobile: Use common INTC IRQ code on sh7372
Make use of INTC_IRQ_PINS_32() for INTCA on sh7372.

Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2011-11-05 01:02:51 +09:00
Magnus Damm 382414b93a ARM: mach-shmobile: sh7372 A4R support (v4)
This change adds support for the sh7372 A4R power domain.

The sh7372 A4R hardware power domain contains the
SH CPU Core and a set of I/O devices including
multimedia accelerators and I2C controllers.

One special case about A4R is the INTCS interrupt
controller that needs to be saved and restored to
keep working as expected. Also the LCDC hardware
blocks are in a different hardware power domain
but have their IRQs routed only through INTCS. So
as long as LCDCs are active we cannot power down
INTCS because that would risk losing interrupts.

Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
2011-10-22 00:20:12 +02:00
Magnus Damm 4861da4fee ARM: mach-shmobile: Remove 3DG/SGX from sh7372 INTCS
This patch removes support for the SGX interrupt source in
the sh7372 INTCS controller.

The SGX hardware block included in sh7372 is already hooked
up to the ARM Cortex-A8 core using the INTCA controller,
so SGX users are encouraged to make use of that interrupt
source instead.

Removing support for the SGX interrupt source in INTCS
simplifies the sh7372 power management code by allowing
us to assume that only INTCA needs to be powered on to
operate the SGX hardware.

If the INTCS interrupt source would be kept then the kernel
would be forced to deal with additional dependencies that does
not follow the regular power domain hiearachy. With this
patch in place we can safely power down INTCS while the
SGX is operating.

Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2011-08-29 16:13:10 +09:00
Simon Horman 2007aea18c ARM: arch-shmobile: Use multiple irq vectors for SDHI
This patch reverts "ARM: mach-shmobile: sh7372 SDHI vector merge" and
supplies 3 IRQ resources for each SDHI block.

Some blocks have a 4th IRQ, but this is used for DRM feathres
that I do not have access tot he documentation for and are almost
certainly tainted by licensing issues. So the 4th IRQ is not
hooked-up even if it exists.

Cc: Chris Ball <cjb@laptop.org>
Cc: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: Magnus Damm <magnus.damm@gmail.com>
Signed-off-by: Simon Horman <horms@verge.net.au>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2011-05-24 12:42:46 +09:00
Thomas Gleixner 6845664a6a arm: Cleanup the irq namespace
Convert to the new function names. Automated with coccinelle.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2011-03-29 14:47:57 +02:00
Magnus Damm a2bc19e586 ARM: mach-shmobile: sh7372 INTCS MFIS2 interrupt update
Enable the MFIS2 interrupt source in the INTCS interrupt
controller included in the sh7372 processor. The priority
field is constantly enabled to let the interrupt through to
both the ARM side and the SH side.

Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2011-01-18 13:51:51 +09:00
Arnd Hannemann 330e4e7169 ARM: mach-shmobile: sh7372 Enable SDIO IRQs
This patch enables the interrupt generation for SDIO IRQs
of the sdhi controllers of the SoC. To make sure interrupts
are handled announce the MMC_CAP_SDIO_IRQ capability
on AP4EVB. Tested with a b43-based SDIO wireless card.

Signed-off-by: Arnd Hannemann <arnd@arndnet.de>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2011-01-12 14:44:19 +09:00
Tony SIM 3f25cb042c ARM: mach-shmobile: intc-sh7372: fix interrupt number
Signed-off-by: Tony SIM <chinyeow.sim.xt@renesas.com>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2010-11-08 13:48:50 +09:00
Kuninori Morimoto 7923ac133b ARM: mach-shmobile: sh7372: modify INTCS table
Add ignored device name by comment-out in INTCS.
And MSIOF which has been forgotten is added

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2010-09-14 17:20:20 +09:00
Magnus Damm f4dd61853e ARM: mach-shmobile: sh7372 INTCS support
Add support for the sh7372 INTCS interrupt controller.

INTCS is the interrupt controller for the sh7372 SuperH
processor core. It is tied into the INTCA interrupt
controller which interfaces to the ARM processor.

INTCS support is implemented using a new INTC table
together with a chained interrupt handler that ties
into the already supported INTCA controller.

Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2010-05-20 12:00:44 +09:00
Kuninori Morimoto 0fff9ec116 ARM: mach-shmobile: intc-sh7372: modify wrong address
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2010-04-15 13:04:19 +09:00
Magnus Damm c57a31abf0 ARM: mach-shmobile: sh7372 SDHI vector merge
Merge the SDHI vectors for sh7372 using the recently
merged INTC force_enable/disable feature.

With this in place SDHI hotplug is supported using
the drivers sh_mobile_sdhi and tmio_mmc.

Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2010-03-15 12:06:46 +09:00
Kuninori Morimoto deded43508 ARM: mach-shmobile: intc-sh7372 tidyup
This patch is based on Rev 0.5 manual

Signed-off-by: Kuninori Morimoto <morimoto.kuninori@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2010-02-15 13:43:43 +09:00
Magnus Damm e4e430c611 ARM: mach-shmobile: sh7372 INTCA support
Add support for the sh7372 INTCA hardware block.

Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2010-02-09 18:01:46 +09:00