linux

Author SHA1 Message Date

Author	SHA1	Message	Date
Florian Fainelli	dbe4a39331	ARM: dts: HR2: Fix interrupt types for i2c and PCIe The i2c and PCIe controllers had an incorrect type which should have been set to IRQ_TYPE_LEVEL_HIGH, fix that. Fixes: `b9099ec754` ("ARM: dts: Add Broadcom Hurricane 2 DTS include file") Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>	2018-06-18 09:37:09 -07:00
Florian Fainelli	b9099ec754	ARM: dts: Add Broadcom Hurricane 2 DTS include file Describe the Broadcom Hurricane 2 SoC comprised of a Cortex-A9 CPU complex along with standard iProc peripherals: * timers * SPI controller * NAND controller * a single AMAC (Ethernet MAC controller) * dual PCIe controllers The design is largely similar to existing iProc-based SoCs such as Northstar Plus. Acked-by: Jon Mason <jon.mason@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>	2017-10-12 11:30:52 -07:00

Florian Fainelli

dbe4a39331

ARM: dts: HR2: Fix interrupt types for i2c and PCIe

The i2c and PCIe controllers had an incorrect type which should have
been set to IRQ_TYPE_LEVEL_HIGH, fix that.

Fixes: b9099ec754 ("ARM: dts: Add Broadcom Hurricane 2 DTS include file")
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>

2018-06-18 09:37:09 -07:00

Florian Fainelli

b9099ec754

ARM: dts: Add Broadcom Hurricane 2 DTS include file

Describe the Broadcom Hurricane 2 SoC comprised of a Cortex-A9 CPU
complex along with standard iProc peripherals:

* timers
* SPI controller
* NAND controller
* a single AMAC (Ethernet MAC controller)
* dual PCIe controllers

The design is largely similar to existing iProc-based SoCs such as
Northstar Plus.

Acked-by: Jon Mason <jon.mason@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>

2017-10-12 11:30:52 -07:00

2 Commits