2 Commits

Author	SHA1	Message	Date
John Crispin	db9c4a1e65	clk: mediatek: add mt2701 ethernet reset ... The ethernet clock core has a reset register that is currently not exposed to the user. Fix this by adding the missing registration code. Signed-off-by: John Crispin <john@phrozen.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>	2017-04-21 19:20:33 -07:00
Shunli Wang	e986211827	clk: mediatek: Add MT2701 clock support ... Add MT2701 clock support, include topckgen, apmixedsys, infracfg, pericfg and subsystem clocks. Signed-off-by: Shunli Wang <shunli.wang@mediatek.com> Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Erin Lo <erin.lo@mediatek.com> Tested-by: John Crispin <blogic@openwrt.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>	2016-11-08 15:59:49 -08:00