mirror of https://gitee.com/openkylin/linux.git
64 Commits
| Author | SHA1 | Message | Date |
|---|---|---|---|
Linus Torvalds
|
b4b50fd78b |
ARM: SoC platform changes for 3.12
This branch contains mostly additions and changes to platform enablement
and SoC-level drivers. Since there's sometimes a dependency on device-tree
changes, there's also a fair amount of those in this branch.
Pieces worth mentioning are:
- Mbus driver for Marvell platforms, allowing kernel configuration
and resource allocation of on-chip peripherals.
- Enablement of the mbus infrastructure from Marvell PCI-e drivers.
- Preparation of MSI support for Marvell platforms.
- Addition of new PCI-e host controller driver for Tegra platforms
- Some churn caused by sharing of macro names between i.MX 6Q and 6DL
platforms in the device tree sources and header files.
- Various suspend/PM updates for Tegra, including LP1 support.
- Versatile Express support for MCPM, part of big little support.
- Allwinner platform support for A20 and A31 SoCs (dual and quad Cortex-A7)
- OMAP2+ support for DRA7, a new Cortex-A15-based SoC.
The code that touches other architectures are patches moving
MSI arch-specific functions over to weak symbols and removal of
ARCH_SUPPORTS_MSI, acked by PCI maintainers.
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Merge tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC platform changes from Olof Johansson:
"This branch contains mostly additions and changes to platform
enablement and SoC-level drivers. Since there's sometimes a
dependency on device-tree changes, there's also a fair amount of
those in this branch.
Pieces worth mentioning are:
- Mbus driver for Marvell platforms, allowing kernel configuration
and resource allocation of on-chip peripherals.
- Enablement of the mbus infrastructure from Marvell PCI-e drivers.
- Preparation of MSI support for Marvell platforms.
- Addition of new PCI-e host controller driver for Tegra platforms
- Some churn caused by sharing of macro names between i.MX 6Q and 6DL
platforms in the device tree sources and header files.
- Various suspend/PM updates for Tegra, including LP1 support.
- Versatile Express support for MCPM, part of big little support.
- Allwinner platform support for A20 and A31 SoCs (dual and quad
Cortex-A7)
- OMAP2+ support for DRA7, a new Cortex-A15-based SoC.
The code that touches other architectures are patches moving MSI
arch-specific functions over to weak symbols and removal of
ARCH_SUPPORTS_MSI, acked by PCI maintainers"
* tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (266 commits)
tegra-cpuidle: provide stub when !CONFIG_CPU_IDLE
PCI: tegra: replace devm_request_and_ioremap by devm_ioremap_resource
ARM: tegra: Drop ARCH_SUPPORTS_MSI and sort list
ARM: dts: vf610-twr: enable i2c0 device
ARM: dts: i.MX51: Add one more I2C2 pinmux entry
ARM: dts: i.MX51: Move pins configuration under "iomuxc" label
ARM: dtsi: imx6qdl-sabresd: Add USB OTG vbus pin to pinctrl_hog
ARM: dtsi: imx6qdl-sabresd: Add USB host 1 VBUS regulator
ARM: dts: imx27-phytec-phycore-som: Enable AUDMUX
ARM: dts: i.MX27: Disable AUDMUX in the template
ARM: dts: wandboard: Add support for SDIO bcm4329
ARM: i.MX5 clocks: Remove optional clock setup (CKIH1) from i.MX51 template
ARM: dts: imx53-qsb: Make USBH1 functional
ARM i.MX6Q: dts: Enable I2C1 with EEPROM and PMIC on Phytec phyFLEX-i.MX6 Ouad module
ARM i.MX6Q: dts: Enable SPI NOR flash on Phytec phyFLEX-i.MX6 Ouad module
ARM: dts: imx6qdl-sabresd: Add touchscreen support
ARM: imx: add ocram clock for imx53
ARM: dts: imx: ocram size is different between imx6q and imx6dl
ARM: dts: imx27-phytec-phycore-som: Fix regulator settings
ARM: dts: i.MX27: Remove clock name from CPU node
...
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Linus Torvalds
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a923874198 |
PCI changes for the v3.12 merge window:
PCI device hotplug
- Use PCIe native hotplug, not ACPI hotplug, when possible (Neil Horman)
- Assign resources on per-host bridge basis (Yinghai Lu)
MPS (Max Payload Size)
- Allow larger MPS settings below hotplug-capable Root Port (Yijing Wang)
- Add warnings about unsafe MPS settings (Yijing Wang)
- Simplify interface and messages (Bjorn Helgaas)
SR-IOV
- Return -ENOSYS on non-SR-IOV devices (Stefan Assmann)
- Update NumVFs register when disabling SR-IOV (Yijing Wang)
Virtualization
- Add bus and slot reset support (Alex Williamson)
- Fix ACS (Access Control Services) issues (Alex Williamson)
Miscellaneous
- Simplify PCIe Capability accessors (Bjorn Helgaas)
- Add pcibios_pm_ops for arch-specific hibernate stuff (Sebastian Ott)
- Disable decoding during BAR sizing only when necessary (Zoltan Kiss)
- Delay enabling bridges until they're needed (Yinghai Lu)
- Split Designware support into Synopsys and Exynos parts (Jingoo Han)
- Convert class code to use dev_groups (Greg Kroah-Hartman)
- Cleanup Designware and Exynos I/O access wrappers (Seungwon Jeon)
- Fix bridge I/O window alignment (Bjorn Helgaas)
- Add pci_wait_for_pending_transaction() (Casey Leedom)
- Use devm_ioremap_resource() in Marvell driver (Tushar Behera)
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Merge tag 'pci-v3.12-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci
Pull PCI changes from Bjorn Helgaas:
PCI device hotplug:
- Use PCIe native hotplug, not ACPI hotplug, when possible (Neil Horman)
- Assign resources on per-host bridge basis (Yinghai Lu)
MPS (Max Payload Size):
- Allow larger MPS settings below hotplug-capable Root Port (Yijing Wang)
- Add warnings about unsafe MPS settings (Yijing Wang)
- Simplify interface and messages (Bjorn Helgaas)
SR-IOV:
- Return -ENOSYS on non-SR-IOV devices (Stefan Assmann)
- Update NumVFs register when disabling SR-IOV (Yijing Wang)
Virtualization:
- Add bus and slot reset support (Alex Williamson)
- Fix ACS (Access Control Services) issues (Alex Williamson)
Miscellaneous:
- Simplify PCIe Capability accessors (Bjorn Helgaas)
- Add pcibios_pm_ops for arch-specific hibernate stuff (Sebastian Ott)
- Disable decoding during BAR sizing only when necessary (Zoltan Kiss)
- Delay enabling bridges until they're needed (Yinghai Lu)
- Split Designware support into Synopsys and Exynos parts (Jingoo Han)
- Convert class code to use dev_groups (Greg Kroah-Hartman)
- Cleanup Designware and Exynos I/O access wrappers (Seungwon Jeon)
- Fix bridge I/O window alignment (Bjorn Helgaas)
- Add pci_wait_for_pending_transaction() (Casey Leedom)
- Use devm_ioremap_resource() in Marvell driver (Tushar Behera)
* tag 'pci-v3.12-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (63 commits)
PCI/ACPI: Fix _OSC ordering to allow PCIe hotplug use when available
PCI: exynos: Add I/O access wrappers
PCI: designware: Drop "addr" arg from dw_pcie_readl_rc()/dw_pcie_writel_rc()
PCI: Remove pcie_cap_has_devctl()
PCI: Support PCIe Capability Slot registers only for ports with slots
PCI: Remove PCIe Capability version checks
PCI: Allow PCIe Capability link-related register access for switches
PCI: Add offsets of PCIe capability registers
PCI: Tidy bitmasks and spacing of PCIe capability definitions
PCI: Remove obsolete comment reference to pci_pcie_cap2()
PCI: Clarify PCI_EXP_TYPE_PCI_BRIDGE comment
PCI: Rename PCIe capability definitions to follow convention
PCI: Warn if unsafe MPS settings detected
PCI: Fix MPS peer-to-peer DMA comment syntax
PCI: Disable decoding for BAR sizing only when it was actually enabled
PCI: Add comment about needing pci_msi_off() even when CONFIG_PCI_MSI=n
PCI: Add pcibios_pm_ops for optional arch-specific hibernate functionality
PCI: Don't restrict MPS for slots below Root Ports
PCI: Simplify MPS test for Downstream Port
PCI: Remove unnecessary check for pcie_get_mps() failure
...
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Kevin Hilman
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5515d9981f |
Minimal DRA7xx based SoC core support via Rajendra Nayak <rnayak@ti.com>
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Tushar Behera
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f48fbf9c7e |
PCI: mvebu: Convert to use devm_ioremap_resource
Commit
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Ezequiel Garcia
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b22503a9c3 |
PCI: mvebu: Check valid base address before port setup
This driver does not fail to probe when it cannot obtain a port base address. Therefore, add a check for NULL base address before setting up the port, which prevents a kernel panic in such cases. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Tested-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net> |
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Thomas Petazzoni
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11be65472a |
PCI: mvebu: Adapt to the new device tree layout
The new device tree layout encodes the window's target ID and attribute in the PCIe controller node's ranges property. This allows to parse such entries to obtain such information and use the recently introduced MBus API to create the windows, instead of using the current name based scheme. Acked-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net> |
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Thomas Petazzoni
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36dd1f3e02 |
PCI: mvebu: Disable prefetchable memory support in PCI-to-PCI bridge
The Marvell PCIe driver uses an emulated PCI-to-PCI bridge to be able to dynamically set up MBus address decoding windows for PCI I/O and memory regions depending on the PCI devices enumerated by Linux. However, this emulated PCI-to-PCI bridge logic makes the Linux PCI core believe that prefetchable memory regions are supported (because the registers are read/write), while in fact no adress decoding window is ever created for such regions. Since the Marvell MBus address decoding windows do not distinguish memory regions and prefetchable memory regions, this patch takes a simple approach: change the PCI-to-PCI bridge emulation to let the Linux PCI core know that we don't support prefetchable memory regions. To achieve this, we simply make the prefetchable memory base a read-only register that always returns 0. Reading/writing all the other prefetchable memory related registers has no effect. This problem was originally reported by Finn Hoffmann <finn@uni-bremen.de>, who couldn't get a RTL8111/8168B PCI NIC working on the NSA310 Kirkwood platform after updating to 3.11-rc. The problem was that the PCI-to-PCI bridge emulation was making the Linux PCI core believe that we support prefetchable memory, so the Linux PCI core was only filling the prefetchable memory base and limit registers, which does not lead to a MBus window being created. The below patch has been confirmed by Finn Hoffmann to fix his problem on Kirkwood, and has otherwise been successfully tested on the Armada XP GP platform with a e1000e PCIe NIC and a Marvell SATA PCIe card. Reported-by: Finn Hoffmann <finn@uni-bremen.de> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> |
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Olof Johansson
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2dbefbf6a8 |
mvebu pcie driver (bridge) for v3.11
- mvebu
- allow enumeration of devices beyond physical bridges
- remove faking the slot location
- fix status register emulation
depends
- mvebu/pcie
-mvebu/of_pci
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Merge tag 'pcie_bridge-3.11' of git://git.infradead.org/users/jcooper/linux into next/soc
From Jason Cooper:
mvebu pcie driver (bridge) for v3.11
- mvebu
- allow enumeration of devices beyond physical bridges
- remove faking the slot location
- fix status register emulation
Signed-off-by: Olof Johansson <olof@lixom.net>
* tag 'pcie_bridge-3.11' of git://git.infradead.org/users/jcooper/linux:
pci: mvebu: fix the emulation of the status register
pci: mvebu: allow the enumeration of devices beyond physical bridges
pci: mvebu: no longer fake the slot location of downstream devices
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Thomas Petazzoni
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005625fc5d |
pci: mvebu: enable driver usage on Kirkwood
We allow the pci-mvebu driver to be compiled on the Kirkwood platform, and add the 'marvell,kirkwood-pcie' as a compatible string supported by the driver. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Jason Cooper <jason@lakedaemon.net> |
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Thomas Petazzoni
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6eb237c41a |
pci: mvebu: fix the emulation of the status register
The status register of the PCI configuration space of PCI-to-PCI bridges contain some read-only bits, and so write-1-to-clear bits. So, the Linux PCI core sometimes writes 0xffff to this status register, and in the current PCI-to-PCI bridge emulation code of the Marvell driver, we do take all those 1s being written. Even the read-only bits are being overwritten. For now, all the read-only bits should be emulated to have the zero value. The other bits, that are write-1-to-clear bits are used to report various kind of errors, and are never set by the emulated bridge, so there is no need to support this write-1-to-clear bits mechanism. As a conclusion, the easiest solution is to simply emulate this status register by returning zero when read, and ignore the writes to it. This has two visible effects: * The devsel is no longer 'unknown' in, i.e Flags: bus master, 66MHz, user-definable features, ?? devsel, latency 0 becomes: Flags: bus master, 66MHz, user-definable features, fast devsel, latency 0 in lspci -v. This was caused by a value of 11b being read for devsel, which is an invalid value. This 11b value being read was due to a previous write of 0xffff into the status register. * The capability list is no longer broken, because we indicate to the Linux PCI core that we don't have a Capabilities Pointer in the PCI configuration space of this bridge. The following message is therefore no longer visible in lspci -v: Capabilities: [fc] <chain broken> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net> |
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Thomas Petazzoni
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197fc226d9 |
pci: mvebu: allow the enumeration of devices beyond physical bridges
Until now, the Marvell PCIe driver was only allowing the enumeration
of the devices in the secondary bus of the emulated PCI-to-PCI
bridge. This works fine when a PCIe device is directly connected into
a PCIe slot of the Marvell board.
However, when the device connected in the PCIe slot is a physical PCIe
bridge, beyond which a real PCIe device is connected, it no longer
worked, as the driver was preventing the Linux PCI core from seeing
such devices.
This commit fixes that by ensuring that configuration transactions on
subordinate busses are properly forwarded on the right PCIe interface.
Thanks to this patch, a PCIe card beyond a PCIe bridge, itself beyond
the emulated PCI-to-PCI bridge is properly detected, with the
following layout:
-[0000:00]-+-01.0-[01]----00.0
+-09.0-[02-07]----00.0-[03-07]--+-01.0-[04]--
| +-05.0-[05]--
| +-07.0-[06]--
| \-09.0-[07]----00.0
\-0a.0-[08]----00.0
Where the PCIe interface that sits beyond the emulated PCI-to-PCI
bridge at 09.0 allows to access the secondary bus 02, on which there
is a PCIe bridge that allows to access the 3 to 7 busses, that are
subordinates to this bridge. And on one of this bus (bus 7), there is
one real PCIe device connected.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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Thomas Petazzoni
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f4ac99011e |
pci: mvebu: no longer fake the slot location of downstream devices
By default, the Marvell hardware, for each PCIe interface, exhibits the following devices: * On slot 0, a "Marvell Memory controller", identical on all PCIe interfaces, and which isn't useful when the Marvell SoC is the PCIe root complex (i.e, the normal case when we run Linux on the Marvell SoC). * On slot 1, the real PCIe card connected into the PCIe slot of the board. So, what the Marvell PCIe driver was doing in its PCI-to-PCI bridge emulation is that when the Linux PCI core was trying to access the device in slot 0, we were in fact forwarding the configuration transaction to the device in slot 1. For all other slots, we were telling the Linux PCI core that there was no device connected. However, new versions of bootloaders from Marvell change the default PCIe configuration, and make the real device appear in slot 0, and the "Marvell Memory controller" in slot 1. Therefore, this commit modifies the Marvell PCIe driver to adjust the PCIe hardware configuration to make sure that this behavior (real device in slot 0, "Marvell Memory controller" in slot 1) is the one we'll see regardless of what the bootloader has done. It allows to remove the little hack that was forwarding configuration transactions on slot 0 to slot 1, which is nice. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net> |
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Wei Yongjun
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3d9939c92e |
pci: mvebu: fix return value check in mvebu_pcie_probe()
In case of error, function of_clk_get_by_name() returns ERR_PTR() never returns NULL. The NULL test in the return value check should be replaced with IS_ERR(). Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn> Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net> |
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Thomas Petazzoni
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45361a4fe4 |
pci: PCIe driver for Marvell Armada 370/XP systems
This driver implements the support for the PCIe interfaces on the Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to cover earlier families of Marvell SoCs, such as Dove, Orion and Kirkwood. The driver implements the hw_pci operations needed by the core ARM PCI code to setup PCI devices and get their corresponding IRQs, and the pci_ops operations that are used by the PCI core to read/write the configuration space of PCI devices. Since the PCIe interfaces of Marvell SoCs are completely separate and not linked together in a bus, this driver sets up an emulated PCI host bridge, with one PCI-to-PCI bridge as child for each hardware PCIe interface. In addition, this driver enumerates the different PCIe slots, and for those having a device plugged in, it sets up the necessary address decoding windows, using the mvebu-mbus driver. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net> |