Commit Graph

368 Commits

Author SHA1 Message Date
Arnd Bergmann ab64920c37 mvebu SoC suspend changes for v3.19
- Armada 370/XP suspend/resume support
 
  - mvebu SoC driver suspend/resume support
     - irqchip
     - clocksource
     - mbus
     - clk
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Merge tag 'mvebu-soc-suspend-3.19' of git://git.infradead.org/linux-mvebu into next/soc

Pull "mvebu SoC suspend changes for v3.19" from Jason Cooper:

 - Armada 370/XP suspend/resume support

 - mvebu SoC driver suspend/resume support
    - irqchip
    - clocksource
    - mbus
    - clk

* tag 'mvebu-soc-suspend-3.19' of git://git.infradead.org/linux-mvebu:
  ARM: mvebu: add SDRAM controller description for Armada XP
  ARM: mvebu: adjust mbus controller description on Armada 370/XP
  ARM: mvebu: add suspend/resume DT information for Armada XP GP
  ARM: mvebu: synchronize secondary CPU clocks on resume
  ARM: mvebu: make sure MMU is disabled in armada_370_xp_cpu_resume
  ARM: mvebu: Armada XP GP specific suspend/resume code
  ARM: mvebu: reserve the first 10 KB of each memory bank for suspend/resume
  ARM: mvebu: implement suspend/resume support for Armada XP
  clk: mvebu: add suspend/resume for gatable clocks
  bus: mvebu-mbus: provide a mechanism to save SDRAM window configuration
  bus: mvebu-mbus: suspend/resume support
  clocksource: time-armada-370-xp: add suspend/resume support
  irqchip: armada-370-xp: Add suspend/resume support
  Documentation: dt-bindings: minimal documentation for MVEBU SDRAM controller

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-12-04 16:46:43 +01:00
Thomas Petazzoni b9b1de0f4d ARM: mvebu: synchronize secondary CPU clocks on resume
The Armada XP has multiple cores clocked by independent clocks. The
SMP startup code contains a function called set_secondary_cpus_clock()
called in armada_xp_smp_prepare_cpus() to ensure the clocks of the
secondary CPUs match the clock of the boot CPU.

With the introduction of suspend/resume, this operation is no longer
needed when booting the system, but also when existing the suspend to
RAM state. Therefore this commit reworks a bit the logic: instead of
configuring the clock of all secondary CPUs in
armada_xp_smp_prepare_cpus(), we do it on a per-secondary CPU basis in
armada_xp_boot_secondary(), as this function gets called when existing
suspend to RAM for each secondary CPU.

Since the function now only takes care of one CPU, we rename it from
set_secondary_cpus_clock() to set_secondary_cpu_clock(), and it looses
its __init marker, as it is now used beyond the system initialization.

Note that we can't use smp_processor_id() directly, because when
exiting from suspend to RAM, the code is apparently executed with
preemption enabled, so smp_processor_id() is not happy (prints a
warning). We therefore switch to using get_cpu()/put_cpu(), even
though we pretty much have the guarantee that the code starting the
secondary CPUs is going to run on the boot CPU and will not be
migrated.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1416585613-2113-14-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-30 16:40:16 +00:00
Thomas Petazzoni 77ea46d133 ARM: mvebu: make sure MMU is disabled in armada_370_xp_cpu_resume
The armada_370_xp_cpu_resume() until now was used only as the function
called by the SoC when returning from a deep idle state (as used in
cpuidle, or when the CPU is brought offline using CPU hotplug).

However, it is now also used when exiting the suspend to RAM state. In
this case, it is the bootloader that calls back into this function,
with the MMU left enabled by the BootROM. Having the MMU enabled when
entering this function confuses the kerrnel because we are not using
the kernel page tables at this point, but in other mvebu functions we
use the information on whether the MMU is enabled or not to find out
whether we should talk to the coherency fabric using a physical
address or a virtual address. To fix that, we simply disable the MMU
when entering this function, so that the kernel is in an expected
situation.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1416585613-2113-13-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-30 16:40:15 +00:00
Thomas Petazzoni 27432825ae ARM: mvebu: Armada XP GP specific suspend/resume code
On the Armada XP GP platform, entering suspend to RAM state is
triggering by talking to an external PIC micro-controller connected to
the SoC using 3 GPIOs. There is then a small magic sequence of GPIO
toggling that needs to be used to tell the PIC to turn off the SoC.

The code uses the Device Tree to find out which GPIOs are used to
connect to the PIC micro-controller, and then registers its
mvebu_armada_xp_gp_pm_enter() callback to the SoC-level PM code. The
SoC PM code will call back into this registered function at the very
end of the suspend procedure.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1416585613-2113-12-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-30 16:40:14 +00:00
Thomas Petazzoni 8da2b2f7ce ARM: mvebu: reserve the first 10 KB of each memory bank for suspend/resume
When going out of suspend to RAM, the Marvell EBU platforms go through
the bootloader, which re-configures the DRAM controller. To achieve
this, the bootloader executes a piece of code called the "DDR3
training code". It does some reads/writes to the memory to find out
the optimal timings for the memory chip being used.

This has the nasty side effect that the first 10 KB of each DRAM
chip-select are overwritten by the bootloader when exiting the suspend
to RAM state.

Therefore, this commit implements the ->reserve() hook for the 'struct
machine_desc' used on Armada XP, to reserve the 10 KB of each DRAM
chip-select using the memblock API.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1416585613-2113-11-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-30 16:40:13 +00:00
Thomas Petazzoni 8446be5d03 ARM: mvebu: implement suspend/resume support for Armada XP
This commit implements the core of the platform code to enable
suspend/resume on Armada XP. It registers the platform_suspend_ops
structure, and implements the ->enter() hook of this structure.

It is worth mentioning that this commit only provides the SoC-level
part of suspend/resume, which calls into some board-specific code
provided in a follow-up commit.

The most important thing that this SoC-level code has to do is to
build an in-memory structure that contains a magic number, the return
address in the kernel after resume, and a set of address/value
pairs. This structure is used by the bootloader to restore a certain
number of registers (according to the set of address/value pairs) and
then jump back into the kernel at the provided location.

The code also puts the SDRAM into self-refresh mode, before calling
into board-specific code to actually enter the suspend to RAM state.

[ jac - add email exchange between Andrew Lunn and Thomas Petazzoni to better
describe who consumes the address/value pairs ]

> > Is this a well defined mechanism supported by mainline uboot, barebox
> > etc. Or is it some Marvell extension to their uboot?
>
> As far as I know, it is a Marvell extension to their "binary header",
> so it's done even before U-Boot starts. Since the hardware needs
> assistance from the bootloader to do suspend/resume, there is
> necessarily a certain amount of cooperation/agreement needed by what
> the kernel does and what the bootloader expects. I'm not sure there's
> any "standard" mechanism here. Do you know of any?
>
> I know the suspend/resume on the Blackfin architecture works the same
> way (at least it used to work that way years ago when I did a bit of
> Blackfin stuff). And here as well, there was some cooperation between
> the kernel and the bootloader. See
> arch/blackfin/mach-common/dpmc_modes.S, function do_hibernate() at the
> end.
>

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1416585613-2113-10-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-30 16:40:12 +00:00
Gregory CLEMENT 626d686487 ARM: mvebu: Implement the CPU hotplug support for the Armada 38x SoCs
This commit implements the CPU hotplug support for the Marvell Armada
38x platform. Similarly to what was done for the Armada XP, this
commit:

 * Implements the ->cpu_die() function of SMP operations by calling
   armada_38x_do_cpu_suspend() to enter the deep idle state for
   CPUs going offline.

 * Implements a dummy ->cpu_kill() function, simply needed for the
   kernel to know we have CPU hotplug support.

 * The mvebu_cortex_a9_boot_secondary() function makes sure to wake up
   the CPU if waiting in deep idle state by sending an IPI before
   deasserting the CPUs from reset. This is because
   mvebu_cortex_a9_boot_secondary() is now used in two different
   situations: for the initial boot of secondary CPUs (where CPU reset
   deassert is used to wake up CPUs) and for CPU hotplug (where an IPI
   is used to take CPU out of deep idle).

 * At boot time, we exit from the idle state in the
    ->smp_secondary_init() hook.

This commit has been tested using CPU hotplug through sysfs
(/sys/devices/system/cpu/cpuX/online) and using kexec.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1414669184-16785-5-git-send-email-gregory.clement@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-22 02:14:38 +00:00
Gregory CLEMENT f5789cbb22 ARM: mvebu: Fix the secondary startup for Cortex A9 SoC
During the secondary startup the SCU was assumed to be in normal
mode. It is not always the case, and especially after a kexec. This
commit adds the needed sequence to put the SCU in normal mode.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1414669184-16785-4-git-send-email-gregory.clement@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-22 02:14:20 +00:00
Gregory CLEMENT f746ac327b ARM: mvebu: Move SCU power up in a function
This will allow reusing the same function in the secondary_startup
for the Cortex A9 SoC.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1414669184-16785-3-git-send-email-gregory.clement@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-22 02:14:08 +00:00
Gregory CLEMENT 316fbbc400 ARM: mvebu: Clean-up the Armada XP support
This patch removes the unneeded include of the armada-370-xp.h header.

It also moves some declarations from this file into more accurate
places.

Finally, it also adds a comment explaining that we can't remove yet the
smp field in the dt machine struct due to backward compatibly of the
device tree.

In a few releases, when the old device tree will be obsolete, we will be
able to remove the smp field and then the armada-370-xp.h header.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1414669184-16785-2-git-send-email-gregory.clement@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-22 02:13:24 +00:00
Thomas Petazzoni e12f12ac1a ARM: mvebu: update comments in coherency.c
The coherency.c top-level comment mentions that it supports the
coherency fabric for Armada 370 and XP, but it also supports the
coherency fabric on Armada 375 and 38x, so this commit updates the
comment accordingly.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1415871540-20302-6-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-22 01:49:42 +00:00
Thomas Petazzoni ef01c6c36b ARM: mvebu: remove Armada 375 Z1 workaround for I/O coherency
This reverts commit 5ab5afd8ba ("ARM: mvebu: implement Armada 375
coherency workaround"), since we are removing the support for the very
early Z1 revision of the Armada 375 SoC.

This commit is an exact revert, with two exceptions:

 - minor adaptations needed due to other changes that have taken place
   in coherency.c since the original commit

 - keep the definition of pr_fmt. This shouldn't originally have been
   part of the Armada 375 Z1 workaround commit since it had nothing to
   do with it.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1415871540-20302-5-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-22 01:49:37 +00:00
Thomas Petazzoni 3b8509b5f2 ARM: mvebu: remove unused register offset definition
Since commit b21dcafea3 ("arm: mvebu: remove dependency of SMP init
on static I/O mapping"), the COHERENCY_FABRIC_CFG_OFFSET register
offset definition is no longer used, so this commit removes it.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1415871540-20302-4-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-22 01:49:35 +00:00
Thomas Petazzoni e553554536 ARM: mvebu: disable I/O coherency on non-SMP situations on Armada 370/375/38x/XP
Enabling the hardware I/O coherency on Armada 370, Armada 375, Armada
38x and Armada XP requires a certain number of conditions:

 - On Armada 370, the cache policy must be set to write-allocate.

 - On Armada 375, 38x and XP, the cache policy must be set to
   write-allocate, the pages must be mapped with the shareable
   attribute, and the SMP bit must be set

Currently, on Armada XP, when CONFIG_SMP is enabled, those conditions
are met. However, when Armada XP is used in a !CONFIG_SMP kernel, none
of these conditions are met. With Armada 370, the situation is worse:
since the processor is single core, regardless of whether CONFIG_SMP
or !CONFIG_SMP is used, the cache policy will be set to write-back by
the kernel and not write-allocate.

Since solving this problem turns out to be quite complicated, and we
don't want to let users with a mainline kernel known to have
infrequent but existing data corruptions, this commit proposes to
simply disable hardware I/O coherency in situations where it is known
not to work.

And basically, the is_smp() function of the kernel tells us whether it
is OK to enable hardware I/O coherency or not, so this commit slightly
refactors the coherency_type() function to return
COHERENCY_FABRIC_TYPE_NONE when is_smp() is false, or the appropriate
type of the coherency fabric in the other case.

Thanks to this, the I/O coherency fabric will no longer be used at all
in !CONFIG_SMP configurations. It will continue to be used in
CONFIG_SMP configurations on Armada XP, Armada 375 and Armada 38x
(which are multiple cores processors), but will no longer be used on
Armada 370 (which is a single core processor).

In the process, it simplifies the implementation of the
coherency_type() function, and adds a missing call to of_node_put().

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Fixes: e60304f8cb ("arm: mvebu: Add hardware I/O Coherency support")
Cc: <stable@vger.kernel.org> # v3.8+
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1415871540-20302-3-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-22 01:49:33 +00:00
Thomas Petazzoni 30cdef9710 ARM: mvebu: make the coherency_ll.S functions work with no coherency fabric
The ll_add_cpu_to_smp_group(), ll_enable_coherency() and
ll_disable_coherency() are used on Armada XP to control the coherency
fabric. However, they make the assumption that the coherency fabric is
always available, which is currently a correct assumption but will no
longer be true with a followup commit that disables the usage of the
coherency fabric when the conditions are not met to use it.

Therefore, this commit modifies those functions so that they check the
return value of ll_get_coherency_base(), and if the return value is 0,
they simply return without configuring anything in the coherency
fabric.

The ll_get_coherency_base() function is also modified to properly
return 0 when the function is called with the MMU disabled. In this
case, it normally returns the physical address of the coherency
fabric, but we now check if the virtual address is 0, and if that's
case, return a physical address of 0 to indicate that the coherency
fabric is not enabled.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: <stable@vger.kernel.org> # v3.8+
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1415871540-20302-2-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-22 01:49:27 +00:00
Jason Cooper 93a93d19c7 Merge branch 'mvebu/fixes' into mvebu/soc 2014-11-22 01:48:20 +00:00
Ezequiel Garcia 172ed82cef ARM: mvebu: Remove thermal quirk for A375 Z1 revision
The Armada 375 Z1 SoC revision is no longer supported. This commit
removes the quirk required to "fix" the reg property and the compatible
string of the thermal devicetree node.

Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Link: https://lkml.kernel.org/r/1415116839-4323-3-git-send-email-ezequiel.garcia@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-09 03:19:39 +00:00
Thomas Petazzoni 2eb04ae010 ARM: mvebu: add missing of_node_put() call in coherency.c
There is a missing of_node_put() to decrement the device_node
reference counter after a of_find_matching_node() in coherency_init().

Fixes: 501f928e00 ("ARM: mvebu: add a coherency_available() call")
Cc: <stable@vger.kernel.org> # v3.16+
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1414423955-5933-4-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-07 02:56:36 +00:00
Andrew Lunn 5129ee22ce ARM: mvebu: armada xp: Generalize use of i2c quirk
A second product has come to light which makes use of the A0 stepping
of the Armada XP SoC. A0 stepping has a hardware bug in the i2c core
meaning that hardware offload does not work, resulting in the kernel
failing to boot. The quirk detects that the kernel is running on an A0
stepping SoC and disables the use of hardware offload.

Currently the quirk is only enabled for PlatHome Openblocks AX3. The
AX3 has been produced with both A0 and B0 stepping SoCs. The second
product is the Lenovo Iomega IX4-300d. It seems likely that this
device will also swap from A0 to B0 SoC sometime during its life.

If there are two products using A0, it seems likely there are more
products with A0. Also, since the number of A0 SoCs is limited, these
products are also likely to transition to B0. Hence detecting at run
time is the safest option. So enable the quirk for all Armada XP
boards.

Tested on an AX3 with A0 stepping.

Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: stable@vger.kernel.org # v3.12+
Fixes: 930ab3d403ae: ("i2c: mv64xxx: Add I2C Transaction Generator support")
Link: https://lkml.kernel.org/r/1406395238-29758-2-git-send-email-andrew@lunn.ch
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-01 22:07:44 +00:00
Viresh Kumar bbcf071969 cpufreq: cpu0: rename driver and internals to 'cpufreq_dt'
The naming convention of this driver was always under the scanner, people
complained that it should have a more generic name than cpu0, as it manages all
CPUs that are sharing clock lines.

Also, in future it will be modified to support any number of clusters with
separate clock/voltage lines.

Lets rename it to 'cpufreq_dt' from 'cpufreq_cpu0'.

Tested-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2014-10-03 15:37:54 +02:00
Linus Torvalds b3345d7c57 ARM: SoC platform changes for 3.17
This is the bulk of new SoC enablement and other platform changes for 3.17:
 
 * Samsung S5PV210 has been converted to DT and multiplatform
 * Clock drivers and bindings for some of the lower-end i.MX 1/2 platforms
 * Kirkwood, one of the popular Marvell platforms, is folded into the
   mvebu platform code, removing mach-kirkwood.
 * Hwmod data for TI AM43xx and DRA7 platforms.
 * More additions of Renesas shmobile platform support
 * Removal of plat-samsung contents that can be removed with S5PV210 being
   multiplatform/DT-enabled and the other two old platforms being removed.
 
 New platforms (most with only basic support right now):
 
 * Hisilicon X5HD2 settop box chipset is introduced
 * Mediatek MT6589 (mobile chipset) is introduced
 * Broadcom BCM7xxx settop box chipset is introduced
 
 + as usual a lot other pieces all over the platform code.
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Merge tag 'soc-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC platform changes from Olof Johansson:
 "This is the bulk of new SoC enablement and other platform changes for
  3.17:

   - Samsung S5PV210 has been converted to DT and multiplatform
   - Clock drivers and bindings for some of the lower-end i.MX 1/2
     platforms
   - Kirkwood, one of the popular Marvell platforms, is folded into the
     mvebu platform code, removing mach-kirkwood
   - Hwmod data for TI AM43xx and DRA7 platforms
   - More additions of Renesas shmobile platform support
   - Removal of plat-samsung contents that can be removed with S5PV210
     being multiplatform/DT-enabled and the other two old platforms
     being removed

  New platforms (most with only basic support right now):

   - Hisilicon X5HD2 settop box chipset is introduced
   - Mediatek MT6589 (mobile chipset) is introduced
   - Broadcom BCM7xxx settop box chipset is introduced

  + as usual a lot other pieces all over the platform code"

* tag 'soc-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (240 commits)
  ARM: hisi: remove smp from machine descriptor
  power: reset: move hisilicon reboot code
  ARM: dts: Add hix5hd2-dkb dts file.
  ARM: debug: Rename Hi3716 to HIX5HD2
  ARM: hisi: enable hix5hd2 SoC
  ARM: hisi: add ARCH_HISI
  MAINTAINERS: add entry for Broadcom ARM STB architecture
  ARM: brcmstb: select GISB arbiter and interrupt drivers
  ARM: brcmstb: add infrastructure for ARM-based Broadcom STB SoCs
  ARM: configs: enable SMP in bcm_defconfig
  ARM: add SMP support for Broadcom mobile SoCs
  Documentation: arm: misc updates to Marvell EBU SoC status
  Documentation: arm: add URLs to public datasheets for the Marvell Armada XP SoC
  ARM: mvebu: fix build without platforms selected
  ARM: mvebu: add cpuidle support for Armada 38x
  ARM: mvebu: add cpuidle support for Armada 370
  cpuidle: mvebu: add Armada 38x support
  cpuidle: mvebu: add Armada 370 support
  cpuidle: mvebu: rename the driver from armada-370-xp to mvebu-v7
  ARM: mvebu: export the SCU address
  ...
2014-08-08 11:14:29 -07:00
Linus Torvalds c489d98c8c Merge branch 'for-linus' of git://ftp.arm.linux.org.uk/~rmk/linux-arm
Pull ARM updates from Russell King:
 "Included in this update:

   - perf updates from Will Deacon:

     The main changes are callchain stability fixes from Jean Pihet and
     event mapping and PMU name rework from Mark Rutland

     The latter is preparatory work for enabling some code re-use with
     arm64 in the future.

   - updates for nommu from Uwe Kleine-König:

     Two different fixes for the same problem making some ARM nommu
     configurations not boot since 3.6-rc1.  The problem is that
     user_addr_max returned the biggest available RAM address which
     makes some copy_from_user variants fail to read from XIP memory.

   - deprecate legacy OMAP DMA API, in preparation for it's removal.

     The popular drivers have been converted over, leaving a very small
     number of rarely used drivers, which hopefully can be converted
     during the next cycle with a bit more visibility (and hopefully
     people popping out of the woodwork to help test)

   - more tweaks for BE systems, particularly with the kernel image
     format.  In connection with this, I've cleaned up the way we
     generate the linker script for the decompressor.

   - removal of hard-coded assumptions of the kernel stack size, making
     everywhere depend on the value of THREAD_SIZE_ORDER.

   - MCPM updates from Nicolas Pitre.

   - Make it easier for proper CPU part number checks (which should
     always include the vendor field).

   - Assembly code optimisation - use the "bx" instruction when
     returning from a function on ARMv6+ rather than "mov pc, reg".

   - Save the last kernel misaligned fault location and report it via
     the procfs alignment file.

   - Clean up the way we create the initial stack frame, which is a
     repeated pattern in several different locations.

   - Support for 8-byte get_user(), needed for some DRM implementations.

   - mcs locking from Will Deacon.

   - Save and restore a few more Cortex-A9 registers (for errata
     workarounds)

   - Fix various aspects of the SWP emulation, and the ELF hwcap for the
     SWP instruction.

   - Update LPAE logic for pte_write and pmd_write to make it more
     correct.

   - Support for Broadcom Brahma15 CPU cores.

   - ARM assembly crypto updates from Ard Biesheuvel"

* 'for-linus' of git://ftp.arm.linux.org.uk/~rmk/linux-arm: (53 commits)
  ARM: add comments to the early page table remap code
  ARM: 8122/1: smp_scu: enable SCU standby support
  ARM: 8121/1: smp_scu: use macro for SCU enable bit
  ARM: 8120/1: crypto: sha512: add ARM NEON implementation
  ARM: 8119/1: crypto: sha1: add ARM NEON implementation
  ARM: 8118/1: crypto: sha1/make use of common SHA-1 structures
  ARM: 8113/1: remove remaining definitions of PLAT_PHYS_OFFSET from <mach/memory.h>
  ARM: 8111/1: Enable erratum 798181 for Broadcom Brahma-B15
  ARM: 8110/1: do CPU-specific init for Broadcom Brahma15 cores
  ARM: 8109/1: mm: Modify pte_write and pmd_write logic for LPAE
  ARM: 8108/1: mm: Introduce {pte,pmd}_isset and {pte,pmd}_isclear
  ARM: hwcap: disable HWCAP_SWP if the CPU advertises it has exclusives
  ARM: SWP emulation: only initialise on ARMv7 CPUs
  ARM: SWP emulation: always enable when SMP is enabled
  ARM: 8103/1: save/restore Cortex-A9 CP15 registers on suspend/resume
  ARM: 8098/1: mcs lock: implement wfe-based polling for MCS locking
  ARM: 8091/2: add get_user() support for 8 byte types
  ARM: 8097/1: unistd.h: relocate comments back to place
  ARM: 8096/1: Describe required sort order for textofs-y (TEXT_OFFSET)
  ARM: 8090/1: add revision info for PL310 errata 588369 and 727915
  ...
2014-08-05 10:05:29 -07:00
Arnd Bergmann 39fbf98408 mvebu SoC changes for v3.17 (round 4)
- Armada XP
     - Fix return value check in pmsu code
     - Document URLs for new public datasheets (Thanks, Marvell & free-electrons!)
 
  - Armada 370/38x
     - Add cpuidle support
 
  - mvebu
     - Fix build when no platforms are selected
     - Update EBU SoC status in docs
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Merge tag 'mvebu-soc-3.17-4' of git://git.infradead.org/linux-mvebu into next/soc

Merge "mvebu SoC changes for v3.17 (round 4)" from Jason Cooper:

 - Armada XP
    - Fix return value check in pmsu code
    - Document URLs for new public datasheets (Thanks, Marvell & free-electrons!)

 - Armada 370/38x
    - Add cpuidle support

 - mvebu
    - Fix build when no platforms are selected
    - Update EBU SoC status in docs

* tag 'mvebu-soc-3.17-4' of git://git.infradead.org/linux-mvebu: (21 commits)
  Documentation: arm: misc updates to Marvell EBU SoC status
  Documentation: arm: add URLs to public datasheets for the Marvell Armada XP SoC
  ARM: mvebu: fix build without platforms selected
  ARM: mvebu: add cpuidle support for Armada 38x
  ARM: mvebu: add cpuidle support for Armada 370
  cpuidle: mvebu: add Armada 38x support
  cpuidle: mvebu: add Armada 370 support
  cpuidle: mvebu: rename the driver from armada-370-xp to mvebu-v7
  ARM: mvebu: export the SCU address
  ARM: mvebu: make the snoop disabling optional in mvebu_v7_pmsu_idle_prepare()
  ARM: mvebu: use a local variable to store the resume address
  ARM: mvebu: make the cpuidle initialization more generic
  ARM: mvebu: rename the armada_370_xp symbols to mvebu_v7 in pmsu.c
  ARM: mvebu: use the common function for Armada 375 SMP workaround
  ARM: mvebu: add a common function for the boot address work around
  ARM: mvebu: sort the #include of pmsu.c in alphabetic order
  ARM: mvebu: split again armada_370_xp_pmsu_idle_enter() in PMSU code
  ARM: mvebu: fix return value check in armada_xp_pmsu_cpufreq_init()
  clk: mvebu: extend clk-cpu for dynamic frequency scaling
  ARM: mvebu: extend PMSU code to support dynamic frequency scaling
  ...

Conflicts:
	arch/arm/mach-mvebu/Kconfig
	drivers/cpuidle/cpuidle-armada-370-xp.c

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-07-26 18:17:08 +02:00
Arnd Bergmann f169f4007e Linux 3.16-rc6
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Merge branches 'samsung/cleanup' and 'samsung/s5p-cleanup-v2', tag 'v3.16-rc6' into next/soc

The following samsung branches are based on these cleanups,
which are already in mainline before this branch gets pulled.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-07-26 11:59:20 +02:00
Arnd Bergmann ce800342c8 ARM: mvebu: fix build without platforms selected
When building a multiplatform kernel that enables 'ARCH_MVEBU' but
none of the individual options under it, we get this link error:

arch/arm/mach-mvebu/built-in.o: In function `mvebu_armada375_smp_wa_init':
:(.text+0x190): undefined reference to `mvebu_setup_boot_addr_wa'

The best solution seems to be to ensure that in this configuration,
we don't actually build any of the mvebu code.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lkml.kernel.org/r/7339332.ZE2mWIdyDh@wuerfel
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-07-24 23:14:36 +00:00
Jason Cooper 54ef3fe697 Merge branch 'mvebu/soc-cpuidle' into mvebu/soc
Conflicts:
	arch/arm/mach-mvebu/pmsu.c
2014-07-24 23:10:02 +00:00
Gregory CLEMENT e53b1fd432 ARM: mvebu: add cpuidle support for Armada 38x
Unlike the Armada XP and the Armada 370, this SoC uses a Cortex A9
core. Consequently, the procedure to enter the idle state is
different: interaction with the SCU, not disabling snooping, etc.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1406120453-29291-16-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-07-24 11:47:40 +00:00
Gregory CLEMENT 3b9e4b1441 ARM: mvebu: add cpuidle support for Armada 370
This commit introduces the cpuidle support for Armada 370. The main
difference compared to the already supported Armada XP is that the
Armada 370 has an issue caused by "a slow exit process from the deep
idle state due to heavy L1/L2 cache cleanup operations performed by
the BootROM software" (cf errata GL-BootROM-10).

To work around this issue, we replace the restart code of the BootROM
by some custom code located in an internal SRAM. For this purpose, we
use the common function mvebu_boot_addr_wa() introduced in the commit
"ARM: mvebu: Add a common function for the boot address work around".

The message in case of failure to suspend the system was switched from
the warn level to the debug level. Indeed due to the "slow exit
process from the deep idle state" in Armada 370, this situation
happens quite often. Using the debug level avoids spamming the kernel
logs, but still allows to enable it if needed.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1406120453-29291-15-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-07-24 11:47:37 +00:00
Gregory CLEMENT f50ee82471 cpuidle: mvebu: rename the driver from armada-370-xp to mvebu-v7
This driver will be able to manage the cpuidle for more SoCs than just
Armada 370 and XP. It will also support Armada 38x and potentially
other SoC of the Marvell Armada EBU family. To take this into account,
this patch renames the driver and its symbols.

It also changes the driver name from cpuidle-armada-370-xp to
cpuidle-armada-xp, because separate platform drivers will be
registered for the other SoC types. This change must be done
simultaneously in the cpuidle driver and in the PMSU code in order to
remain bisectable.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lkml.kernel.org/r/1406120453-29291-12-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-07-24 11:47:11 +00:00
Gregory CLEMENT 6a2b5343e2 ARM: mvebu: export the SCU address
The SCU address will be needed in other files than board-v7.c,
especially in pmsu.c for cpuidle related activities. So this patch
adds a function that allows to retrieve the virtual address at which
the SCU has been mapped.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1406120453-29291-10-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-07-24 11:46:40 +00:00
Gregory CLEMENT 5da964e0fa ARM: mvebu: make the snoop disabling optional in mvebu_v7_pmsu_idle_prepare()
On some mvebu v7 SoCs (the ones using a Cortex-A9 core and not a PJ4B
core), the snoop disabling feature does not exist as the hardware
coherency is handled in a different way. Therefore, in preparation to
the introduction of the cpuidle support for those SoCs, this commit
modifies the mvebu_v7_psmu_idle_prepare() function to take several
flags, which allow to decide whether snooping should be disabled, and
whether we should use the deep idle mode or not.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1406120453-29291-9-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-07-24 11:46:35 +00:00
Gregory CLEMENT 752a993776 ARM: mvebu: use a local variable to store the resume address
The resume address used by the cpuidle code will not always be the
same depending on the SoC. Using a local variable to store the resume
address allows to keep the same function for the PM notifier but with
a different address. This address will be set during the
initialization of the cpuidle logic in pmsu.c.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1406120453-29291-8-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-07-24 11:46:19 +00:00
Gregory CLEMENT 54a4d1b8d4 ARM: mvebu: make the cpuidle initialization more generic
In preparation to the addition of the cpuidle support for more SoCs,
this patch moves the Armada XP specific initialization to a separate
function.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1406120453-29291-7-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-07-24 11:46:16 +00:00
Gregory CLEMENT 898ef3e9bf ARM: mvebu: rename the armada_370_xp symbols to mvebu_v7 in pmsu.c
Most of the function related to the PMSU are not specific to the
Armada 370 or Armada XP SoCs. They can also be used for most of the
other mvebu ARMv7 SoCs, and will actually be used to support cpuidle
on Armada 38x.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1406120453-29291-6-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-07-24 11:46:13 +00:00
Gregory CLEMENT 305969fb62 ARM: mvebu: use the common function for Armada 375 SMP workaround
Use the common function mvebu_setup_boot_addr_wa() introduced in the
commit "ARM: mvebu: Add a common function for the boot address work
around" instead of the dedicated version for Armada 375.

This commit also moves the workaround in the system-controller
module. Indeed the workaround on 375 is really related to setting the
boot address which is done by the system controller.

As a bonus we no longer use an harcoded value to access the register
storing the boot address.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1406120453-29291-5-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-07-24 11:46:10 +00:00
Gregory CLEMENT 3076cc58c9 ARM: mvebu: add a common function for the boot address work around
On some of the mvebu SoCs and due to internal BootROM issue, the CPU
initial jump code must be placed in the SRAM memory of the SoC. In
order to achieve this, we have to unmap the BootROM and at some
specific location where the BootROM was placed, create a dedicated
MBus window for the SRAM. This SRAM is initialized with a few
instructions of code that allows to jump to the real secondary CPU
boot address. The SRAM used is the Crypto engine one.

This work around is currently needed for booting SMP on Armada 375 Z1
and will be needed for cpuidle support on Armada 370. Instead of
duplicating the same code, this commit introduces a common function to
handle it: mvebu_setup_boot_addr_wa().

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1406120453-29291-4-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-07-24 11:46:06 +00:00
Gregory CLEMENT 3e328428d4 ARM: mvebu: sort the #include of pmsu.c in alphabetic order
Sorting the headers in alphabetic order will help to reduce conflicts
when adding new headers later.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1406120453-29291-3-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-07-24 11:46:03 +00:00
Gregory CLEMENT 9ce35884bd ARM: mvebu: split again armada_370_xp_pmsu_idle_enter() in PMSU code
do_armada_370_xp_cpu_suspend() and armada_370_xp_pmsu_idle_prepare(),
have been merged into a single function called
armada_370_xp_pmsu_idle_enter() by the commit "bbb92284b6c8 ARM:
mvebu: slightly refactor/rename PMSU idle related functions", in
prepare for the introduction of the CPU hotplug support for Armada XP.

But for cpuidle the prepare function will be common to all the mvebu
SoCs that use the PMSU, while the suspend function will be specific to
each SoC. Keeping the prepare function separate will help reducing
code duplication while new SoC support is added.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1406120453-29291-2-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-07-24 11:45:59 +00:00
Jason Cooper 5abe65e3d6 Merge branch 'mvebu/fixes' into mvebu/soc-cpuidle 2014-07-24 11:41:36 +00:00
Wei Yongjun b03e119fff ARM: mvebu: fix return value check in armada_xp_pmsu_cpufreq_init()
In case of error, the function clk_get() returns ERR_PTR()
and never returns NULL. The NULL test in the return value
check should be replaced with IS_ERR().

Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn>
Link: https://lkml.kernel.org/r/1406038688-26417-1-git-send-email-weiyj_lk@163.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-07-23 12:31:13 +00:00
Jason Cooper ba3ec5780b Merge branch 'mvebu/soc-cpufreq' into mvebu/soc 2014-07-22 20:46:48 +00:00
Olof Johansson f37ac9e5a4 exynos cpuidle update for v3.17
- add callbacks exynos_suspend() and exynos_powered_up()
   for support cpuidle through mcpm
 - skip exynos_cpuidle for exynos5420 because is uses
   cpuidle-big-liggle generic cpuidle driver
 - add generic functions to calculate cpu number is used
   for pmu and this is required for exynos5420 multi-cluster
 - add of_device_id structure for big.LITTLE cpuidle and
   add "samsung,exynos5420" compatible string for exynos5420
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Merge tag 'exynos-cpuidle' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/soc

Merge "Samsung exynos cpuidle update for v3.17" from Kukjin Kim:

- add callbacks exynos_suspend() and exynos_powered_up()
  for support cpuidle through mcpm
- skip exynos_cpuidle for exynos5420 because is uses
  cpuidle-big-liggle generic cpuidle driver
- add generic functions to calculate cpu number is used
  for pmu and this is required for exynos5420 multi-cluster
- add of_device_id structure for big.LITTLE cpuidle and
  add "samsung,exynos5420" compatible string for exynos5420

* tag 'exynos-cpuidle' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
  ARM: EXYNOS: populate suspend and powered_up callbacks for mcpm
  ARM: EXYNOS: do not allow cpuidle registration for exynos5420
  cpuidle: big.LITTLE: init driver for exynos5420
  cpuidle: big.LITTLE: Add ARCH_EXYNOS entry in config
  ARM: EXYNOS: add generic function to calculate cpu number
  cpuidle: big.LITTLE: add of_device_id structure
  + Linux 3.16-rc5

Signed-off-by: Olof Johansson <olof@lixom.net>
2014-07-19 15:03:08 -07:00
Olof Johansson 81cca645b6 mvebu fixes for v3.16 (round 3)
- Fix SMP boot on 38x/375 in big endian
  - Fix operand list for pmsu on 370/XP
  - Fix coherency bus notifiers
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Merge tag 'mvebu-fixes-3.16-3' of git://git.infradead.org/linux-mvebu into fixes

Merge "mvebu fixes for v3.16 (round 3)" from Jason Cooper:

 - Fix SMP boot on 38x/375 in big endian
 - Fix operand list for pmsu on 370/XP
 - Fix coherency bus notifiers

* tag 'mvebu-fixes-3.16-3' of git://git.infradead.org/linux-mvebu:
  ARM: mvebu: Fix coherency bus notifiers by using separate notifiers
  ARM: mvebu: Fix the operand list in the inline asm of armada_370_xp_pmsu_idle_enter
  ARM: mvebu: fix SMP boot for Armada 38x and Armada 375 Z1 in big endian

Signed-off-by: Olof Johansson <olof@lixom.net>
2014-07-18 14:38:28 -07:00
Russell King 6ebbf2ce43 ARM: convert all "mov.* pc, reg" to "bx reg" for ARMv6+
ARMv6 and greater introduced a new instruction ("bx") which can be used
to return from function calls.  Recent CPUs perform better when the
"bx lr" instruction is used rather than the "mov pc, lr" instruction,
and this sequence is strongly recommended to be used by the ARM
architecture manual (section A.4.1.1).

We provide a new macro "ret" with all its variants for the condition
code which will resolve to the appropriate instruction.

Rather than doing this piecemeal, and miss some instances, change all
the "mov pc" instances to use the new macro, with the exception of
the "movs" instruction and the kprobes code.  This allows us to detect
the "mov pc, lr" case and fix it up - and also gives us the possibility
of deploying this for other registers depending on the CPU selection.

Reported-by: Will Deacon <will.deacon@arm.com>
Tested-by: Stephen Warren <swarren@nvidia.com> # Tegra Jetson TK1
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> # mioa701_bootresume.S
Tested-by: Andrew Lunn <andrew@lunn.ch> # Kirkwood
Tested-by: Shawn Guo <shawn.guo@freescale.com>
Tested-by: Tony Lindgren <tony@atomide.com> # OMAPs
Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com> # Armada XP, 375, 385
Acked-by: Sekhar Nori <nsekhar@ti.com> # DaVinci
Acked-by: Christoffer Dall <christoffer.dall@linaro.org> # kvm/hyp
Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> # PXA3xx
Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> # Xen
Tested-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> # ARMv7M
Tested-by: Simon Horman <horms+renesas@verge.net.au> # Shmobile
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-07-18 12:29:04 +01:00
Thomas Petazzoni a509ea840b ARM: mvebu: extend PMSU code to support dynamic frequency scaling
This commit adds the necessary code in the Marvell EBU PMSU driver to
support dynamic frequency scaling. In essence, what this new code does
is that it:

 * registers the frequency operating points supported by the CPU;

 * registers a clock notifier of the CPU clocks. The notifier function
   listens to the newly introduced APPLY_RATE_CHANGE event, and uses
   that to finalize the frequency transition by doing the part of the
   procedure that involves the PMSU;

 * registers a platform device for the cpufreq-generic driver, which
   will take care of the CPU frequency transitions.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1404920715-19834-3-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-07-16 12:58:36 +00:00
Thomas Petazzoni 831e251889 ARM: mvebu: ensure CPU clocks are enabled
In the Armada XP SMP support code, we are reading the clock frequency
of the booting CPU, and use that to assign the same frequency to the
other CPUs, and we do this while the clocks are disabled.

However, the CPU clocks are in fact never prepared/enabled, and to
support cpufreq, we now have two code paths to change the frequency of
the CPU clocks in the CPU clock driver: one when the clock is enabled
(dynamic frequency scaling), one when the clock is disabled (adjusting
the CPU frequency before starting the CPU). In order for this to work,
the CPU clocks now have to be prepared and enabled after the initial
synchronization of the clock frequencies is done, so that all future
rate changes of the CPU clocks will trigger a dynamic frequency
scaling transition.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1404920715-19834-2-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-07-16 12:58:30 +00:00
Ezequiel Garcia a728b97742 ARM: mvebu: Fix coherency bus notifiers by using separate notifiers
Currently, the coherency fabric support registers two bus notifiers;
one for platform, one for pci bus types, with the same notifier block.
However, this is illegal and can cause serious issues: the notifier
block is also a link in the notifier list and cannot be inserted twice.

This commit fixes this by using different notifier blocks (with the same
notifier callback) to set the platform and pci bus types notifiers.

Fixes: b0063aad5d ("ARM: mvebu: use hardware I/O coherency also for PCI devices")
Reported-by: Paolo Pisati <p.pisati@gmail.com>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Link: https://lkml.kernel.org/r/1404826657-6977-1-git-send-email-ezequiel.garcia@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-07-08 13:53:53 +00:00
Gregory CLEMENT 0d461e1b08 ARM: mvebu: Fix the operand list in the inline asm of armada_370_xp_pmsu_idle_enter
In the inline asm part of the function armada_370_xp_pmsu_idle_enter()
the input operand was used. The intent here was to let the compiler
choose this register so it could do the optimization it
needed.

However an input operand is not supposed to be modified by the inline
asm code. This can lead to improper generated instructions.

In some case generated instruction the compiler made the choice to
reuse the same register to store the return value. But in the assembly
part this register was modified, so it can lead to return an wrong
value.

The fix is to use a clobber. Thanks to this the compiler will know
that the value of this register will be modified.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1404483736-16938-1-git-send-email-gregory.clement@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-07-08 12:25:39 +00:00
Olof Johansson b3c20e9832 mvebu SoC changes for v3.17
- kirkwood
     - add setup file for netxbig LEDs (non-trivial DT binding doesn't exist yet)
 
  - mvebu
     - staticize where needed
     - add CPU hotplug for Armada XP
     - add public datasheet for Armada 370
     - don't apply thermal quirk by default
     - get SoC ID from the system controller when possible
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Merge tag 'mvebu-soc-3.17' of git://git.infradead.org/linux-mvebu into next/soc

Merge "mvebu SoC changes for v3.17" from Jason Cooper:

- kirkwood
  * add setup file for netxbig LEDs (non-trivial DT binding doesn't exist yet)

- mvebu
  * staticize where needed
  * add CPU hotplug for Armada XP
  * add public datasheet for Armada 370
  * don't apply thermal quirk by default
  * get SoC ID from the system controller when possible

* tag 'mvebu-soc-3.17' of git://git.infradead.org/linux-mvebu:
  ARM: mvebu: Staticize mvebu_cpu_reset_init
  ARM: mvebu: Staticize armada_370_xp_cpu_pm_init
  ARM: mvebu: Staticize armada_375_smp_cpu1_enable_wa
  ARM: mvebu: Use system controller to get the soc id when possible
  ARM: mvebu: Use the a standard errno in mvebu_get_soc_id
  ARM: mvebu: Don't apply the thermal quirk if the SoC revision is unknown
  Documentation: arm: add URLs to public datasheets for the Marvell Armada 370 SoC
  ARM: mvebu: implement CPU hotplug support for Armada XP
  ARM: mvebu: export PMSU idle enter/exit functions
  ARM: mvebu: slightly refactor/rename PMSU idle related functions
  ARM: mvebu: remove stub implementation of CPU hotplug on Armada 375/38x
  ARM: Kirkwood: Add setup file for netxbig LEDs
  ARM: mvebu: mark armada_370_xp_pmsu_idle_prepare() as static

Signed-off-by: Olof Johansson <olof@lixom.net>
2014-07-07 22:27:00 -07:00
Olof Johansson 25d11631f9 mvebu fixes for v3.16 (round #2)
- mvebu
     - Fix PCIe deadlock now that SMP is enabled
     - Fix cpuidle for big-endian systems
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Merge tag 'mvebu-fixes-3.16-2' of git://git.infradead.org/linux-mvebu into fixes

mvebu fixes for v3.16 (round #2)

 - mvebu
    - Fix PCIe deadlock now that SMP is enabled
    - Fix cpuidle for big-endian systems

* tag 'mvebu-fixes-3.16-2' of git://git.infradead.org/linux-mvebu:
  ARM: mvebu: fix cpuidle implementation to work on big-endian systems
  ARM: mvebu: update L2/PCIe deadlock workaround after L2CC cleanup
  ARM: mvebu: move Armada 375 external abort logic as a quirk

Signed-off-by: Olof Johansson <olof@lixom.net>
2014-07-04 21:51:19 -07:00
Thomas Petazzoni 0e2be4c112 ARM: mvebu: fix SMP boot for Armada 38x and Armada 375 Z1 in big endian
The SMP boot on Armada 38x and Armada 375 Z1 is currently broken in
big-endian configurations, and this commit fixes it for both
platforms.

For Armada 375 Z1, the problem was in the
armada_375_smp_cpu1_enable_code part of the code that gets copied to
the Crypto SRAM as a work-around for an issue of the Z1 stepping. This
piece of code was not switching the CPU core to big-endian, and not
endian-swapping the value read from the Resume Address register (the
value is stored little-endian). Due to the introduction of the
conditional 'rev r1, r1' instruction, the offset between the 'ldr r0,
[pc, #4]' instruction and the value it was looking is different
between LE and BE configurations. To solve this, we instead use one
'adr' instruction followed by one 'ldr'.

For Armada 38x, the problem was simply that the CPU core was not
switched to big endian in the secondary CPU startup function.

This change was tested in LE and BE configurations on Armada 385,
Armada 375 Z1 and Armada 375 A0.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1404228186-21203-1-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-07-01 17:02:26 +00:00
Thomas Petazzoni 6509dc74c9 ARM: mvebu: fix cpuidle implementation to work on big-endian systems
On Marvell Armada XP, when a CPU comes back from deep idle state of
cpuidle, it restarts its execution at armada_370_xp_cpu_resume(),
which puts back the CPU into the coherency, and then calls the generic
cpu_resume() function.

While this works on little-endian configurations, it doesn't work on
big-endian configurations because the CPU restarts in little-endian,
and therefore must be switched back to big-endian to operate
properly. To achieve this, a 'setend be' instruction must be executed
in big-endian configurations. However, the ARM_BE8() macro that is
used to implement nice compile-time conditional for ARM LE vs. ARM BE8
is not easily usable in inline assembly.

Therefore, this patch moves the armada_370_xp_cpu_resume() C function,
which was anyway just a block of inline assembly, into a proper
pmsu_ll.S file, and adds the appropriate ARM_BE8(setend be)
instruction.

Without this patch, an Armada XP big endian configuration with cpuidle
enabled fails to boot, as it hangs as soon as one of the CPU hits the
deep idle state.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1404130165-3593-1-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-06-30 18:15:11 +00:00
Sachin Kamat e65714740d ARM: mvebu: Staticize mvebu_cpu_reset_init
'mvebu_cpu_reset_init' is local to this file.

Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Link: https://lkml.kernel.org/r/1403610235-22654-4-git-send-email-sachin.kamat@samsung.com
Signed-off-by: Sachin Kamat <sachin.kamat@samsung.com>
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-06-30 17:41:04 +00:00
Sachin Kamat 6fc770f28d ARM: mvebu: Staticize armada_370_xp_cpu_pm_init
'armada_370_xp_cpu_pm_init' is local to this file.

Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Link: https://lkml.kernel.org/r/1403610235-22654-3-git-send-email-sachin.kamat@samsung.com
Signed-off-by: Sachin Kamat <sachin.kamat@samsung.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-06-30 17:41:02 +00:00
Sachin Kamat 1440fbd271 ARM: mvebu: Staticize armada_375_smp_cpu1_enable_wa
'armada_375_smp_cpu1_enable_wa' is local to this file.

Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Link: https://lkml.kernel.org/r/1403610235-22654-2-git-send-email-sachin.kamat@samsung.com
Signed-off-by: Sachin Kamat <sachin.kamat@samsung.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-06-30 17:41:01 +00:00
Gregory CLEMENT 9674d4a3cf ARM: mvebu: Use system controller to get the soc id when possible
On Armada 38x it is possible to get the SoC Id and the revision
without using the PCI register. Accessing the PCI registers implies
enabling its clock and, because of the initialization issue, not
keeping them enable. So if possible it is better to avoid it.

Armada 370 and Armada XP provides the SoC ID values from the system
controller but not the revision.

Armada 375 provides both but the SoC ID value looks buggy (0x6660
instead of 0x6720).

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1403538128-27859-1-git-send-email-gregory.clement@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-06-30 17:40:59 +00:00
Gregory CLEMENT 5e80d81acc ARM: mvebu: Use the a standard errno in mvebu_get_soc_id
Instead of using -1 as error value, use a standard errno.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1403274953-21790-2-git-send-email-gregory.clement@free-electrons.com
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-06-30 17:40:58 +00:00
Thomas Petazzoni 011788907b ARM: mvebu: update L2/PCIe deadlock workaround after L2CC cleanup
Commit 497a92308a ("ARM: mvebu:
implement L2/PCIe deadlock workaround") introduced some logic in
coherency.c to adjust the PL310 cache controller Device Tree node of
Armada 375 and Armada 38x platform to include the 'arm,io-coherent'
property if the system is running with hardware I/O coherency enabled.

However, with the L2CC driver cleanup done by Russell King, the
initialization of the L2CC driver has been moved earlier, and is now
part of the init_IRQ() ARM function in
arch/arm/kernel/irq.c. Therefore, calling coherency_init() in
->init_time() is now too late, as the Device Tree property gets added
too late (after the L2CC driver has been initialized).

In order to fix this, this commit removes the ->init_time() callback
use in board-v7.c and replaces it with an ->init_irq() callback. We
therefore no longer use the default ->init_irq() callback, but we now
use the default ->init_time() callback.

In this newly introduced ->init_irq() callback, we call irqchip_init()
which is the default behavior when ->init_irq() isn't defined, and
then do the initialization related to the coherency: SCU, coherency
fabric, and mvebu-mbus (which is needed to start secondary CPUs).

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1402585772-10405-4-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-06-30 17:38:43 +00:00
Thomas Petazzoni 752ef800a6 ARM: mvebu: move Armada 375 external abort logic as a quirk
In preparation to a small re-organization of the initialization
sequence in board-v7.c, this commit moves the registration of the
custom external abort handler on Armada 375 later in the boot
sequence, and makes it more similar to the other quirks that we
already have. There is indeed no need to register this abort handler
particularly early, it simply needs to be registered before switching
to userspace.

In addition to this, this commit makes the registration of the custom
abort handler conditional on Armada 375 Z1, because Armada 375 A0 and
later iterations are not affected by the issue.

This commit was tested on both Armada 375 Z1 and Armada 375 A0
platforms.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1402585772-10405-3-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-06-30 17:38:21 +00:00
Arnd Bergmann 6d12e79698 mvebu fixes for v3.16
- mvebu
     - Fix broken SoC ID detection
     - Select ARM_CPU_SUSPEND for v7
     - Remove armada38x compatible string (no users yet)
 
  - kirkwood
     - Fix phy-connection-type on GuruPlug board
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Merge tag 'mvebu-fixes-3.16' of git://git.infradead.org/linux-mvebu into fixes

Merge "mvebu fixes for v3.16" from Jason Cooper:

 - mvebu
    - Fix broken SoC ID detection
    - Select ARM_CPU_SUSPEND for v7
    - Remove armada38x compatible string (no users yet)

 - kirkwood
    - Fix phy-connection-type on GuruPlug board

* tag 'mvebu-fixes-3.16' of git://git.infradead.org/linux-mvebu:
  ARM: mvebu: Fix the improper use of the compatible string armada38x using a wildcard
  ARM: dts: kirkwood: fix phy-connection-type for Guruplug
  ARM: mvebu: select ARM_CPU_SUSPEND for Marvell EBU v7 platforms
  ARM: mvebu: Fix broken SoC ID detection
2014-06-25 20:26:30 +02:00
Ezequiel Garcia 9d6373485c ARM: mvebu: Don't apply the thermal quirk if the SoC revision is unknown
Currently, the thermal quirk is skipped only if the SoC revision is known to be
one that does not need them, but if the SoC revision cannot be obtained, the
quirk is applied assuming it's needed.

However, this quirk must be applied only we are sure the SoC needs it, for it
breaks the thermal support if applied on a SoC that doesn't need it. The reason
for this is that the quirk consists in changing the thermal devicetree
compatible string and register offsets, to workaround a hardware bug in the
early SoC revision.

Such changes are wrong if the SoC is a new revision and doesn't need
the workaround. Therefore, this commit changes the behavior, by
requiring the SoC revision to be known in order to peform a quirk.

Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Link: https://lkml.kernel.org/r/1402425283-24989-1-git-send-email-ezequiel.garcia@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-06-21 00:45:48 +00:00
Thomas Petazzoni 2633777946 ARM: mvebu: implement CPU hotplug support for Armada XP
This commit implements CPU hotplug support for the Marvell Armada XP
platform. The CPU hotplug stub functions from hotplug.c are moved into
platsmp.c, as it doesn't make much sense to have a separate file just
for these two functions.

In addition, this commit:

 * Implements the ->cpu_die() function of SMP operations by calling
   armada_370_xp_pmsu_idle_enter() to enter the deep idle state for
   CPUs going offline.

 * Implements a dummy ->cpu_kill() function, simply needed for the
   kernel to know we have CPU hotplug support.

 * The armada_xp_boot_secondary() function makes sure to wake up the
   CPU if waiting in deep idle state by sending an IPI. This is
   because armada_xp_boot_secondary() is now used in two different
   situations: for the initial boot of secondary CPUs (where CPU reset
   deassert is used to wake up CPUs) and for CPU hotplug (where an IPI
   is used to take CPU out of deep idle).

 * At boot time, we exit from the idle state in the
   ->smp_secondary_init() hook.

This commit has been tested using CPU hotplug through sysfs
(/sys/devices/system/cpu/cpuX/online) and using kexec.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1401481098-23326-5-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-06-21 00:31:47 +00:00
Thomas Petazzoni 8ea875e72d ARM: mvebu: export PMSU idle enter/exit functions
The PMSU idle enter/exit functions will be needed for the CPU hotplug
implementation on Armada XP, so this commit removes their static
qualifier, and adds the appropriate prototypes in armada-370-xp.h.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1401481098-23326-4-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-06-21 00:31:38 +00:00
Thomas Petazzoni bbb92284b6 ARM: mvebu: slightly refactor/rename PMSU idle related functions
The CPU hotplug code will need to call into PMSU functions to enter
and exit from deep idle states. However, the deep idle state is
currently entered by a function called do_armada_370_xp_cpu_suspend()
whose name really suggests it's an internal function, but we need to
export it to other files in mach-mvebu.

Therefore, this commit:

 * Merges the code of do_armada_370_xp_cpu_suspend() into
   armada_370_xp_pmsu_idle_prepare(), into a single function called
   armada_370_xp_pmsu_idle_enter(), which prepares the PMSU for deep
   idle, and then enters the deep idle state. This code will be common
   to both cpuidle and CPU hotplug.

 * For symetry, it renames the armada_370_xp_pmsu_idle_restore()
   function to armada_370_xp_pmsu_idle_exit().

We also remove the 'noinline' qualifier for these functions, which
apparently had no reason to be here.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1401481098-23326-3-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-06-21 00:31:00 +00:00
Thomas Petazzoni 3169455448 ARM: mvebu: remove stub implementation of CPU hotplug on Armada 375/38x
In preparation to the addition of CPU hotplug support for Armada XP,
and therefore moving the existing stub functions for hotplug support,
this commit removes the reference from the SMP implementation of
Armada 375/38x to the armada_xp_cpu_die() function. Proper CPU hotplug
support for Armada 375 and 38x will be implemented at a later point.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1401481098-23326-2-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-06-21 00:28:53 +00:00
Andrew Lunn 55fc830232 ARM: Kirkwood: Add setup file for netxbig LEDs
There is currently no DT binding for the CPLD which controls the LEDs
on the Net 2Big and Net 5Big. So use a platform device.

Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Link: https://lkml.kernel.org/r/1401132591-26305-2-git-send-email-andrew@lunn.ch
Tested-by: Simon Guinot <simon.guinot@sequanux.org>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-06-20 23:47:27 +00:00
Thomas Petazzoni adb1d99384 ARM: mvebu: mark armada_370_xp_pmsu_idle_prepare() as static
The armada_370_xp_pmsu_idle_prepare() function is only used internally
to pmsu.c, so there's no reason to not use the static qualifier.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1401116474-31221-1-git-send-email-thomas.petazzoni@free-electrons.com
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-06-20 20:42:28 +00:00
Thomas Petazzoni 52fcc56753 ARM: mvebu: select ARM_CPU_SUSPEND for Marvell EBU v7 platforms
On Marvell Armada platforms, the PMSU (Power Management Service Unit)
controls a number of power management related activities, needed for
things like suspend/resume, CPU hotplug, cpuidle or even simply SMP.

Since cpuidle support was added for Armada XP, the pmsu.c file in
arch/arm/mach-mvebu/ calls the cpu_suspend() and cpu_resume() ARM
functions, which are only available when
CONFIG_ARM_CPU_SUSPEND=y. Therefore, configurations that have
CONFIG_ARM_CPU_SUSPEND disabled due to PM_SLEEP being disabled no
longer build properly, due to undefined references to cpu_suspend()
and cpu_resume().

To fix this, this patch simply ensures CONFIG_ARM_CPU_SUSPEND is
always enabled for Marvell EBU v7 platforms. Doing things in a more
fine-grained way would require a lot of #ifdef-ery in pmsu.c to
isolate the parts that use cpu_suspend()/cpu_resume(), and those parts
would anyway have been needed as soon as either one of suspend/resume,
CPU hotplug or cpuidle was enabled.

Reported-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1402488397-31381-1-git-send-email-thomas.petazzoni@free-electrons.com
Acked-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-06-20 20:38:14 +00:00
Ezequiel Garcia ed2d859119 ARM: mvebu: Fix broken SoC ID detection
Currently the mvebu boards need to detect the SoC revision in order to apply
some quirks needed to workaround issues found on I2C and thermal controllers
present only in very early SoC.

This detection requires PCI address translation to work, so we need to
explicitly select OF_ADDRESS_PCI.

This can be considered a partial revert of the following commit, that
wrongly removed the option selection:

commit 55400f3a1f
Author: Rob Herring <robh@kernel.org>
Date:   Tue Apr 22 14:15:52 2014 -0500

    ARM: mvebu: clean-up unneeded kconfig selects

Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Link: https://lkml.kernel.org/r/1402347165-19988-1-git-send-email-ezequiel.garcia@free-electrons.com
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-06-20 20:32:14 +00:00
Rob Herring 21278aeafb ARM: use menuconfig for sub-arch menus
The System Type menu is getting quite long with platforms and is
inconsistent in handling of sub-arch specific options. Tidy up the menu
by making platform options a menuconfig entry containing any platform
specific config items.

[arnd: change OMAP part according to suggestion from
 Tony Lindgren <tony@atomide.com>]

Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-06-17 17:09:48 +02:00
Stephen Boyd 19682f72f5 ARM: Remove ARCH_HAS_CPUFREQ config option
This config exists entirely to hide the cpufreq menu from the
kernel configuration unless a platform has selected it. Nothing
is actually built if this config is 'Y' and it just leads to more
patches that add a select under a platform Kconfig so that some
other CPUfreq option can be chosen. Let's remove the option so
that we can always enable CPUfreq drivers on ARM platforms.

Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-06-17 17:09:39 +02:00
Linus Torvalds 9e47aaef0b Fix ARM merge mistake in mvebu board file
Russell King points out that my ARM merge (commit eb3d3ec567) was
broken wrt the arch/arm/mach-mvebu/board-v7.c file, leaving in a stale
l2x0_of_init() call (it's now handled by the DT description).

Which is kind of embarrassing, since I knew about it as it wasn't the
only file that had similar merge issues.  At least I got the other ones
right.

Reported-by: Russell King <rmk@arm.linux.org.uk>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2014-06-06 10:24:07 -07:00
Linus Torvalds eb3d3ec567 Merge branch 'for-linus' of git://ftp.arm.linux.org.uk/~rmk/linux-arm into next
Pull ARM updates from Russell King:

 - Major clean-up of the L2 cache support code.  The existing mess was
   becoming rather unmaintainable through all the additions that others
   have done over time.  This turns it into a much nicer structure, and
   implements a few performance improvements as well.

 - Clean up some of the CP15 control register tweaks for alignment
   support, moving some code and data into alignment.c

 - DMA properties for ARM, from Santosh and reviewed by DT people.  This
   adds DT properties to specify bus translations we can't discover
   automatically, and to indicate whether devices are coherent.

 - Hibernation support for ARM

 - Make ftrace work with read-only text in modules

 - add suspend support for PJ4B CPUs

 - rework interrupt masking for undefined instruction handling, which
   allows us to enable interrupts earlier in the handling of these
   exceptions.

 - support for big endian page tables

 - fix stacktrace support to exclude stacktrace functions from the
   trace, and add save_stack_trace_regs() implementation so that kprobes
   can record stack traces.

 - Add support for the Cortex-A17 CPU.

 - Remove last vestiges of ARM710 support.

 - Removal of ARM "meminfo" structure, finally converting us solely to
   memblock to handle the early memory initialisation.

* 'for-linus' of git://ftp.arm.linux.org.uk/~rmk/linux-arm: (142 commits)
  ARM: ensure C page table setup code follows assembly code (part II)
  ARM: ensure C page table setup code follows assembly code
  ARM: consolidate last remaining open-coded alignment trap enable
  ARM: remove global cr_no_alignment
  ARM: remove CPU_CP15 conditional from alignment.c
  ARM: remove unused adjust_cr() function
  ARM: move "noalign" command line option to alignment.c
  ARM: provide common method to clear bits in CPU control register
  ARM: 8025/1: Get rid of meminfo
  ARM: 8060/1: mm: allow sub-architectures to override PCI I/O memory type
  ARM: 8066/1: correction for ARM patch 8031/2
  ARM: 8049/1: ftrace/add save_stack_trace_regs() implementation
  ARM: 8065/1: remove last use of CONFIG_CPU_ARM710
  ARM: 8062/1: Modify ldrt fixup handler to re-execute the userspace instruction
  ARM: 8047/1: rwsem: use asm-generic rwsem implementation
  ARM: l2c: trial at enabling some Cortex-A9 optimisations
  ARM: l2c: add warnings for stuff modifying aux_ctrl register values
  ARM: l2c: print a warning with L2C-310 caches if the cache size is modified
  ARM: l2c: remove old .set_debug method
  ARM: l2c: kill L2X0_AUX_CTRL_MASK before anyone else makes use of this
  ...
2014-06-05 15:57:04 -07:00
Linus Torvalds 825f4e0271 ARM: SoC updates for 3.16 (part 1)
A quite large set of SoC updates this cycle. In no particular order:
 
 - Multi-cluster power management for Samsung Exynos, adding support for
   big.LITTLE CPU switching on EXYNOS5
 - SMP support for Marvell Armada 375 and 38x
 - SMP rework on Allwinner A31
 - Xilinx Zynq support for SOC_BUS, big endian
 - Marvell orion5x platform cleanup, modernizing the implementation and
   moving to DT.
 - _Finally_ moving Samsung Exynos over to support MULTIPLATFORM, so
   that their platform can be enabled in the same kernel binary as most
   of the other v7 platforms in the tree. \o/ The work isn't quite complete,
   there's some driver fixes still needed, but the basics now work.
 
 New SoC support added:
 - Freescale i.MX6SX
 - LSI Axxia AXM55xx SoCs
 - Samsung EXYNOS 3250, 5260, 5410, 5420 and 5800
 - STi STIH407
 
 Plus a large set of various smaller updates for different platforms. I'm
 probably missing some important one here.
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Merge tag 'soc-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc into next

Pull part one of ARM SoC updates from Olof Johansson:
 "A quite large set of SoC updates this cycle.  In no particular order:

   - Multi-cluster power management for Samsung Exynos, adding support
     for big.LITTLE CPU switching on EXYNOS5

   - SMP support for Marvell Armada 375 and 38x

   - SMP rework on Allwinner A31

   - Xilinx Zynq support for SOC_BUS, big endian

   - Marvell orion5x platform cleanup, modernizing the implementation
     and moving to DT.

   - _Finally_ moving Samsung Exynos over to support MULTIPLATFORM, so
     that their platform can be enabled in the same kernel binary as
     most of the other v7 platforms in the tree.  \o/

     The work isn't quite complete, there's some driver fixes still
     needed, but the basics now work.

  New SoC support added:

   - Freescale i.MX6SX

   - LSI Axxia AXM55xx SoCs

   - Samsung EXYNOS 3250, 5260, 5410, 5420 and 5800

   - STi STIH407

  plus a large set of various smaller updates for different platforms.
  I'm probably missing some important one here"

* tag 'soc-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (281 commits)
  ARM: exynos: don't run exynos4 l2x0 setup on other platforms
  ARM: exynos: Fix "allmodconfig" build errors in mcpm and hotplug
  ARM: EXYNOS: mcpm rename the power_down_finish
  ARM: EXYNOS: Enable mcpm for dual-cluster exynos5800 SoC
  ARM: EXYNOS: Enable multi-platform build support
  ARM: EXYNOS: Consolidate Kconfig entries
  ARM: EXYNOS: Add support for EXYNOS5410 SoC
  ARM: EXYNOS: Support secondary CPU boot of Exynos3250
  ARM: EXYNOS: Add Exynos3250 SoC ID
  ARM: EXYNOS: Add 5800 SoC support
  ARM: EXYNOS: initial board support for exynos5260 SoC
  clk: exynos5410: register clocks using common clock framework
  ARM: debug: qcom: add UART addresses to Kconfig help for APQ8084
  ARM: sunxi: allow building without reset controller
  Documentation: devicetree: arm: sort enable-method entries
  ARM: rockchip: convert smp bringup to CPU_METHOD_OF_DECLARE
  clk: exynos5250: Add missing sysmmu clocks for DISP and ISP blocks
  ARM: dts: axxia: Add reset controller
  power: reset: Add Axxia system reset driver
  ARM: axxia: Adding defconfig for AXM55xx
  ...
2014-06-02 16:15:12 -07:00
Linus Torvalds 0a58471541 ARM: SoC cleanups for 3.16
Cleanups for 3.16. Among these are:
 
 - A bunch of misc cleanups for Broadcom platforms, mostly housekeeping
 - Enabling Common Clock Framework on the older s3c24xx Samsung chipsets
 - Cleanup of the Versatile Express system controller code, moving it to syscon
 - Power management cleanups for OMAP platforms
 
 + a handful of other cleanups across the place
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Merge tag 'cleanup-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc into next

Pull ARM SoC cleanups from Olof Johansson:
 "Cleanups for 3.16.  Among these are:

   - a bunch of misc cleanups for Broadcom platforms, mostly
     housekeeping
   - enabling Common Clock Framework on the older s3c24xx Samsung
     chipsets
   - cleanup of the Versatile Express system controller code, moving it
     to syscon
   - power management cleanups for OMAP platforms

  plus a handful of other cleanups across the place"

* tag 'cleanup-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (87 commits)
  ARM: kconfig: allow PCI support to be selected with ARCH_MULTIPLATFORM
  clk: samsung: fix build error
  ARM: vexpress: refine dependencies for new code
  clk: samsung: clk-s3c2410-dlck: do not use PNAME macro as it declares __initdata
  cpufreq: exynos: Fix the compile error
  ARM: S3C24XX: move debug-macro.S into the common space
  ARM: S3C24XX: use generic DEBUG_UART_PHY/_VIRT in debug macro
  ARM: S3C24XX: trim down debug uart handling
  ARM: compressed/head.S: remove s3c24xx special case
  ARM: EXYNOS: Remove unnecessary inclusion of cpu.h
  ARM: EXYNOS: Migrate Exynos specific macros from plat to mach
  ARM: EXYNOS: Remove exynos_subsys registration
  ARM: EXYNOS: Remove duplicate lines in Makefile
  ARM: EXYNOS: use v7_exit_coherency_flush macro for cache disabling
  ARM: OMAP4: PRCM: remove references to cm-regbits-44xx.h from PRCM core files
  ARM: OMAP3/4: PRM: add support of late_init call to prm_ll_ops
  ARM: OMAP3/OMAP4: PRM: add prm_features flags and add IO wakeup under it
  ARM: OMAP3/4: PRM: provide io chain reconfig function through irq setup
  ARM: OMAP2+: PRM: remove unnecessary cpu_is_XXX calls from prm_init / exit
  ARM: OMAP2+: PRCM: cleanup some header includes
  ...
2014-06-02 16:14:07 -07:00
Russell King 9847cf0403 ARM: l2c: mvebu: convert to generic l2c OF initialisation
Remove the explicit call to l2x0_of_init(), converting to the generic
infrastructure instead.

Acked-by: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:49:30 +01:00
Will Deacon 08d38bebb4 ARM: kconfig: allow PCI support to be selected with ARCH_MULTIPLATFORM
When targetting ARCH_MULTIPLATFORM, we may include support for SoCs with
PCI-capable devices (e.g. mach-virt with virtio-pci).

This patch allows PCI support to be selected for these SoCs by selecting
CONFIG_MIGHT_HAVE_PCI when CONFIG_ARCH_MULTIPLATFORM=y and removes the
individual selections from multi-platform enabled SoCs.

Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
2014-05-29 12:42:38 -07:00
Arnd Bergmann 37f5f4e173 Merge tag 'mvebu-soc-3.16-2' of git://git.infradead.org/linux-mvebu into next/soc
Merge "mvebu SoC changes for v3.16 (incremental #2)" from Jason Cooper <jason@lakedaemon.net>:

 - mvebu
    - fix coherency on big-endian in -next
    - hardware IO coherency
    - L2/PCIe deadlock workaround
    - small coherency cleanups

* tag 'mvebu-soc-3.16-2' of git://git.infradead.org/linux-mvebu:
  ARM: mvebu: returns ll_get_cpuid() to ll_get_coherency_cpumask()
  ARM: mvebu: improve comments in coherency_ll.S
  ARM: mvebu: fix indentation of assembly instructions in coherency_ll.S
  ARM: mvebu: fix big endian booting after coherency code rework
  ARM: mvebu: coherency: fix registration of PCI bus notifier when !PCI
  ARM: mvebu: implement L2/PCIe deadlock workaround
  ARM: mvebu: use hardware I/O coherency also for PCI devices

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-05-23 21:56:29 +02:00
Russell King d453ef752c ARM: l2c: remove unnecessary UL-suffix to mask values
They're u32, they're not unsigned long.  The UL suffix is not required
here.

Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-22 16:38:43 +01:00
Thomas Petazzoni 07ae144be1 ARM: mvebu: returns ll_get_cpuid() to ll_get_coherency_cpumask()
In the refactoring of the coherency fabric assembly code, a function
called ll_get_cpuid() was created to factorize common logic between
functions adding CPU to the SMP coherency group, enabling and
disabling the coherency.

However, the name of the function is highly misleading: ll_get_cpuid()
makes one think tat it returns the ID of the CPU, i.e 0 for CPU0, 1
for CPU1, etc. In fact, this is not at all what this function returns:
it returns a CPU mask for the current CPU, usable for the coherency
fabric configuration and control registers.

Therefore this commit renames this function to
ll_get_coherency_cpumask(), and adds additional comments on top of the
function to explain in more details what it does, and also how the
endianess issue is handled.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1400762882-10116-5-git-send-email-thomas.petazzoni@free-electrons.com
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-05-22 14:26:30 +00:00
Thomas Petazzoni 4dd1b7fa43 ARM: mvebu: improve comments in coherency_ll.S
This commit makes no functional change, it only improves a bit the
various code comments in mach-mvebu/coherency_ll.S, by fixing a few
typos and adding a few more details.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1400762882-10116-4-git-send-email-thomas.petazzoni@free-electrons.com
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-05-22 14:26:17 +00:00
Thomas Petazzoni 90ba76f610 ARM: mvebu: fix indentation of assembly instructions in coherency_ll.S
This commit does not make any functional change, it only fixes the
indentation of a few assembly instructions in
arch/arm/mach-mvebu/coherency_ll.S.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1400762882-10116-3-git-send-email-thomas.petazzoni@free-electrons.com
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-05-22 14:26:08 +00:00
Thomas Petazzoni 4fbe63937e ARM: mvebu: fix big endian booting after coherency code rework
As part of the introduction of the cpuidle support for Armada XP, the
coherency code was significantly reworked, especially in the
coherency_ll.S file. However, when the ll_get_cpuid function was
created, the big-endian specific code that switches the endianess of
the register was not updated properly.

This patch fixes this code, and therefore makes big endian systems
bootable again.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1400762882-10116-2-git-send-email-thomas.petazzoni@free-electrons.com
Fixes: 2e8a5942f8 ("ARM: mvebu: Split low level functions to manipulate HW coherency")
Reported-by: Kevin Hilman <khilman@linaro.org>
Cc: Kevin Hilman <khilman@linaro.org>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-05-22 14:25:57 +00:00
Thomas Petazzoni 8828ccc3f2 ARM: mvebu: coherency: fix registration of PCI bus notifier when !PCI
Commit b0063aad5d ("ARM: mvebu: use hardware I/O coherency also for
PCI devices") added a reference to the pci_bus_type variable, but this
variable is only available when CONFIG_PCI is enabled. Therefore,
there is now a build failure in !CONFIG_PCI situations.

This commit fixes that by enclosing the entire initcall into a
IS_ENABLED(CONFIG_PCI) condition.

Reported-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1400598783-706-1-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-05-22 14:17:46 +00:00
Thomas Petazzoni 497a92308a ARM: mvebu: implement L2/PCIe deadlock workaround
The Marvell Armada 375 and Armada 38x SOCs, which use the Cortex-A9
CPU core, the PL310 cache and the Marvell PCIe hardware block are
affected a L2/PCIe deadlock caused by a system erratum when hardware
I/O coherency is used.

This deadlock can be avoided by mapping the PCIe memory areas as
strongly-ordered (note: MT_UNCACHED is strongly-ordered), and by
removing the outer cache sync done in software. This is implemented in
this patch by:

 * Registering a custom arch_ioremap_caller function that allows to
   make sure PCI memory regions are mapped MT_UNCACHED.

 * Adding at runtime the 'arm,io-coherent' property to the PL310 cache
   controller. This cannot be done permanently in the DT, because the
   hardware I/O coherency can only be enabled when CONFIG_SMP is
   enabled, in the current kernel situation.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1400165974-9059-4-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-05-22 14:07:18 +00:00
Olof Johansson 5fe0163aea Merge branch 'cleanup/kconfig' into next/soc
Bring in the cleanup branch due to conflicts in new additions. Should really
have been the base before the other branch, but this way works too.

* cleanup/kconfig:
  ARM: qcom: clean-up unneeded kconfig selects
  ARM: bcm: clean-up unneeded kconfig selects
  ARM: mvebu: clean-up unneeded kconfig selects

Signed-off-by: Olof Johansson <olof@lixom.net>
2014-05-19 23:29:01 -07:00
Thomas Petazzoni b0063aad5d ARM: mvebu: use hardware I/O coherency also for PCI devices
Since the beginning of the introduction of hardware I/O coherency
support for Armada 370 and Armada XP, the special DMA operations
should have applied to all DMA capable devices. Unfortunately, while
the original code properly took into account platform devices, it
didn't take into account PCI devices, which can also be DMA masters.

This commit fixes that by registering a bus notifier on pci_bus_type,
to register our custom DMA operations, like is already done for
platform devices. While doing this, we also rename
mvebu_hwcc_platform_notifier() to mvebu_hwcc_notifier() and
mvebu_hwcc_platform_nb to mvebu_hwcc_nb because they are no longer
specific to platform devices.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1399997070-11434-1-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-05-16 05:34:24 +00:00
Thomas Petazzoni b25bcf1bca ARM: mvebu: mvebu-soc-id: keep clock enabled if PCIe unit is enabled
Since the mvebu-soc-id code in mach-mvebu/ was introduced, several
users have noticed a regression: the PCIe card connected in the first
PCIe interface is not detected properly.

This is due to the fact that the mvebu-soc-id code enables the PCIe
clock of the first PCIe interface, reads the SoC device ID and
revision number (yes this information is made available as part of
PCIe registers), and then disables the clock. However, by doing this,
we gate the clock and therefore loose the complex PCIe configuration
that was done by the bootloader.

Unfortunately, as of today, the kernel is not capable of doing this
complex configuration by itself, so we really need to keep the PCIe
clock enabled. However, we don't want to keep it enabled
unconditionally: if the PCIe interface is not enabled or PCI support
is not compiled into the kernel, there is no reason to keep the PCIe
clock running.

This issue was discussed with Kevin Hilman, and the suggested solution
was to make the mvebu-soc-id code keep the clock enabled in case it
will be needed for PCIe. This is therefore the solution implemented in
this patch.

Long term, we hope to make the kernel more capable in terms of PCIe
configuration for this platform, which will anyway be needed to
support the compilation of the PCIe host controller driver as a
module. In the mean time however, we don't have much other choice than
to implement the currently proposed solution.

Reported-by: Neil Greatorex <neil@fatboyfat.co.uk>
Cc: Neil Greatorex <neil@fatboyfat.co.uk>
Cc: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Cc: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1399903900-29977-3-git-send-email-thomas.petazzoni@free-electrons.com
Fixes: af8d1c63af ("ARM: mvebu: Add support to get the ID and the revision of a SoC")
Cc: <stable@vger.kernel.org> # 3.14+: 42a18d1cf484: ARM: mvebu: mvebu-soc-id: add missing clk_put() call
Cc: <stable@vger.kernel.org> # 3.14+
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Willy Tarreau <w@1wt.eu>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-05-13 14:57:27 +00:00
Thomas Petazzoni 42a18d1cf4 ARM: mvebu: mvebu-soc-id: add missing clk_put() call
The mvebu-soc-id code in mach-mvebu/ needs to enable a clock to read
the SoC device ID and revision number. To do so, it does a clk_get(),
then a clk_prepare_enable(), reads the value, and disables the clock
with clk_disable_unprepare(). However, it forgets to clk_put() the
clock. This commit fixes this issue.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1399903900-29977-2-git-send-email-thomas.petazzoni@free-electrons.com
Cc: <stable@vger.kernel.org> # 3.14+
Fixes: af8d1c63af ("ARM: mvebu: Add support to get the ID and the revision of a SoC")
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Willy Tarreau <w@1wt.eu>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-05-13 14:54:46 +00:00
Vincent Stehlé 9f0affcf3e ARM: mvebu: Fix pmsu compilation when ARMv6 is selected
When compiling for multiplatform for both ARMv6 and ARMv7, the default compiler
flags are for ARMv6, and we will get:

  /tmp/ccwDEzd0.s: Assembler messages:
  /tmp/ccwDEzd0.s:639: Error: selected processor does not support ARM mode `isb '
  /tmp/ccwDEzd0.s:645: Error: selected processor does not support ARM mode `isb '
  /tmp/ccwDEzd0.s:646: Error: selected processor does not support ARM mode `dsb '
  /tmp/ccwDEzd0.s:695: Error: selected processor does not support ARM mode `isb '
  make[1]: *** [arch/arm/mach-mvebu/pmsu.o] Error 1

Fix this in a similar manner than done previously in commit
72533b77d3, by specifying ARMv7 flags for pmsu.o.

Signed-off-by: Vincent Stehlé <vincent.stehle@laposte.net>
Link: https://lkml.kernel.org/r/1399407782-29091-1-git-send-email-vincent.stehle@laposte.net
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Russell King <linux@arm.linux.org.uk>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-05-08 16:55:55 +00:00
Thomas Petazzoni 3943856717 ARM: mvebu: conditionalize Armada 375 coherency workaround
The Armada 375 coherency workaround only needs to be applied to the Z1
revision of the SoC. The A0 and later revisions have been fixed, and
no longer need this workaround.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1399302326-6917-6-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-05-08 16:40:17 +00:00
Thomas Petazzoni a58d5af7d9 ARM: mvebu: conditionalize Armada 375 SMP workaround
The Armada 375 SMP workaround only needs to be applied to the Z1
revision of the SoC. The A0 and later revisions have been fixed, and
no longer need this workaround.

Note that the initialization of the SMP workaround is delayed from
->smp_prepare_cpus() to ->smp_boot_secondary() because when
->smp_prepare_cpus() is called, the early initcalls have not be
called, so the mvebu-soc-id mechanism is not operational. Since the
workaround is anyway not needed before the secondary CPU is started,
we can delay its implementation until the ->smp_boot_secondary() call.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1399302326-6917-5-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-05-08 16:40:15 +00:00
Thomas Petazzoni 5093dcfb42 ARM: mvebu: add Armada 375 A0 revision definition
Now that we have access to Armada 375 A0 platforms, we can add the
corresponding revision definition in mvebu-soc-id.h.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1399302326-6917-4-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-05-08 16:40:14 +00:00
Thomas Petazzoni 73c3c79137 ARM: mvebu: initialize mvebu-soc-id earlier
Currently, the mvebu-soc-id logic is initialized through a
core_initcall(). However, we will soon need to know the SoC revision
before booting secondary CPUs, because a workaround affects Armada 375
Z1 steppings, but should not be applied on Armada 375 A0 steppings.

Unfortunately, core_initcall() are called way too late compared to the
SMP initialization. Therefore, the mvebu-soc-id initialization is move
to an early_initcall(), which is called before the SMP initialization.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1399302326-6917-3-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-05-08 16:40:13 +00:00
Thomas Petazzoni c1a01a0360 ARM: mvebu: fix thermal quirk SoC revision check
In commit 54fe26a900bc528f3df1e4235cb6b9ca5c6d4dc2 ('ARM: mvebu: Add
thermal quirk for the Armada 375 DB board'), a check on the Armada SoC
revision was added to decide whether a quirk for the thermal device
should be applied or not.

However, the quirk implementation has a bug: it assumes
mvebu_get_soc_id() returns true on success, but it returns
0. Therefore, the condition:

  if (mvebu_get_soc_id(&dev, &rev) && rev > ARMADA_375_Z1_REV)

is always false (as long as mvebu-soc-id is properly initialized). As
a consequence, the quirk is always applied, even on A0 steppings, for
which the quirk should not be applied.

This was spotted by testing the thermal driver on Armada 375 A0, which
Ezequiel could not do since he does not have access to the A0 revision
of the SoC for the moment.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1399302326-6917-2-git-send-email-thomas.petazzoni@free-electrons.com
Fixes: 54fe26a900bc528f3df1e4235cb6b9ca5c6d4dc2 ('ARM: mvebu: Add thermal quirk for the Armada 375 DB board')
Acked-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-05-08 16:40:13 +00:00
Andrew Lunn efdf811d82 ARM: Kirkwood: t5325: Remove platform device to instantiate audio
Remove platform device instantiating of the audio, which results in
board-t5325.c being removed. A DT node will be added to take its
place.

Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Link: https://lkml.kernel.org/r/1399141819-23924-7-git-send-email-andrew@lunn.ch
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-05-08 16:23:28 +00:00
Andrew Lunn 7745b25128 ARM: Kirkwood: Remove platform driver for codec
Remove the platform driver and platform data for the audio codec.
A DT node will replace it.

Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Link: https://lkml.kernel.org/r/1399141819-23924-3-git-send-email-andrew@lunn.ch
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-05-08 16:23:18 +00:00
Ezequiel Garcia 5fd62066d2 ARM: mvebu: Add thermal quirk for the Armada 375 DB board
The initial release of the Armada 375 DB board has an Armada 375
Z1 stepping silicon. This commit introduces a quirk that allows
to workaround a series of issues with the thermal sensor in this
stepping, but updating the devicetree:

  * Updates the compatible string for the thermal, so the driver
    can perform a specific initialization of the sensor.

  * Moves the offset of the thermal control register. This quirk
    allows to specifiy the correct (A0 stepping) offset in the
    devicetree.

Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Link: https://lkml.kernel.org/r/1398371004-15807-9-git-send-email-ezequiel.garcia@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-05-08 16:23:10 +00:00
Ezequiel Garcia e9d3c849a8 ARM: mvebu: Select HAVE_ARM_TWD only if SMP is enabled
HAVE_ARM_TWD depends on SMP, so we should only select it if
SMP is enabled, as the others platforms do.

Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Link: https://lkml.kernel.org/r/1398339276-5754-1-git-send-email-ezequiel.garcia@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-05-08 16:23:03 +00:00
Gregory CLEMENT 8eee0f81cd ARM: mvebu: fix the name of the parameter used in mvebu_get_soc_id
The name of the two parameters of mvebu_get_soc_id were inverted. This
patch fix it in order to have a more readable code.

Reported-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1397925170-8202-3-git-send-email-gregory.clement@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-05-08 16:22:52 +00:00
Gregory CLEMENT c42e1ffa26 ARM: mvebu: remove unnecessary ifdef around l2x0_of_init
l2x0_of_init function is always defined
arch/arm/include/asm/hardware/cache-l2x0.h: in case of
CONFIG_CACHE_L2X0 is not selected then a placeholder is defined.
Then there is no need to have ifdef around  l2x0_of_init.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1397925170-8202-2-git-send-email-gregory.clement@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-05-08 16:22:43 +00:00
Gregory CLEMENT 8c16babc64 ARM: mvebu: register the cpuidle driver for the Armada XP SoCs
The cpuidle is a platform driver so we register the device just after
the initialization of the board in an arch_initcall.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1397488214-20685-12-git-send-email-gregory.clement@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-05-08 16:19:03 +00:00
Gregory CLEMENT d163ee165b ARM: mvebu: Register notifier callback for the cpuidle transition
In order to have well encapsulated code, we use notifier callbacks for
CPU_PM_ENTER and CPU_PM_EXIT inside the mvebu power management code.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1397488214-20685-10-git-send-email-gregory.clement@free-electrons.com
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-05-08 16:19:00 +00:00
Thomas Petazzoni 0041464cee ARM: mvebu: refine which files are build in mach-mvebu
Following the integration into mach-mvebu of the Kirkwood ARMv5
support, we need to be more careful about which files get built. For
example, the pmsu.c file now calls wfi(), which only exists on ARMv7
platforms.

Therefore, this commit changes mach-mvebu/Makefile to build the Armada
370/XP/375/38x specific files only when CONFIG_MACH_MVEBU_V7 is
enabled.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1398709239-6126-1-git-send-email-thomas.petazzoni@free-electrons.com
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-05-08 16:18:59 +00:00
Gregory CLEMENT c3e04cabb1 ARM: mvebu: Add the PMSU related part of the cpu idle functions
The cpu idle support will need to access to Power Management Service
Unit. This commit adds the architecture related functions that will be
used in the idle path of the cpuidle driver.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1397488214-20685-9-git-send-email-gregory.clement@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-05-08 16:18:58 +00:00
Gregory CLEMENT f713c7e742 ARM: mvebu: Allow to power down L2 cache controller in idle mode
This commit adds a function which adjusts the PMSU configuration to
automatically power down the L2 and coherency fabric when we enter a
certain idle state.

This feature is part of the Power Management Service Unit of the
Armada 370 and Armada XP SoCs.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1397488214-20685-8-git-send-email-gregory.clement@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-05-08 16:18:56 +00:00
Gregory CLEMENT 1a6bfbc339 ARM: mvebu: Low level function to disable HW coherency support
When going to deep idle we need to disable the SoC snooping (aka
hardware coherency support). Playing with the coherency fabric
requires to use assembly code to be sure that the compiler doesn't
reorder the instructions nor do wrong optimization.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1397488214-20685-7-git-send-email-gregory.clement@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-05-08 16:18:55 +00:00
Gregory CLEMENT 2e8a5942f8 ARM: mvebu: Split low level functions to manipulate HW coherency
Actually enabling coherency and adding a CPU on a SMP group are two
different operations which can be done separately. This patch splits
this in two functions.

Moreover as they use common pattern, this patch also creates local low
level functions (ll_get_coherency_base and ll_get_cpuid) to be used by
the exposed functions (ll_add_cpu_to_smp_group and
ll_enable_coherency)

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1397488214-20685-6-git-send-email-gregory.clement@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-05-08 16:18:54 +00:00
Gregory CLEMENT 952f4ca79b ARM: mvebu: Remove the unused argument of set_cpu_coherent()
set_cpu_coherent() took the SMP group ID as parameter. But this
parameter was never used, and the CPU always uses the SMP group 0. So
we can remove this parameter.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1397488214-20685-5-git-send-email-gregory.clement@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-05-08 16:18:52 +00:00
Gregory CLEMENT b41375f71a ARM: mvebu: ll_set_cpu_coherent always uses the current CPU
ll_set_cpu_coherent is always used on the current CPU, so instead of
passing the CPU id as argument, ll_set_cpu_coherent() can find it by
itself.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1397488214-20685-4-git-send-email-gregory.clement@free-electrons.com
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-05-08 16:18:51 +00:00
Gregory CLEMENT ccd6a13180 ARM: mvebu: remove the address parameter for ll_set_cpu_coherent
In order to be able to deal with the MMU enabled and the MMU disabled
cases, the base address of the coherency registers was passed to the
function. The address by itself was not interesting as it can't change
for a given SoC, the only thing we need is to have a distinction
between the physical or the virtual address.

This patch add a check of the MMU bit to choose the accurate address,
then the calling function doesn't have to pass this information.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1397488214-20685-3-git-send-email-gregory.clement@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-05-08 16:10:24 +00:00
Thomas Petazzoni b4bca24957 ARM: mvebu: add Armada 38x compatible string to pmsu
Since the Armada 38x PMSU registers are slightly different than the
Armada 370/XP PMSU ones, we introduce a new compatible string
"armada-380-pmsu" in the PMSU driver. These differences are not
visible for the current usage of the PMSU, but they might become
visible in the future.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483648-26611-8-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-05-08 16:08:38 +00:00
Gregory CLEMENT 87384cc0b4 ARM: mvebu: add workaround for SMP support for Armada 375 stepping Z1
Due to internal bootrom issue, CPU[1] initial jump code (four
instructions) should be placed in SRAM memory of the SoC. In order to
achieve this, we have to unmap the BootROM and at some specific
location where the BootROM was place, create a specific MBus window
for the SRAM. This SRAM is initialized with a few instructions of code
that allows to jump into the real secondary CPU boot address.

This workaround will most likely be disabled when newer steppings of
the Armada 375 will be made available, in which case a dynamic test
based on mvebu-soc-id will be added.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483648-26611-10-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483648-26611-10-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-05-08 16:08:30 +00:00
Gregory CLEMENT 1ee89e2231 ARM: mvebu: add SMP support for Armada 375 and Armada 38x
This commit adds the SMP support for Armada 375 and Armada 38x. It
turns out that the SMP logic for both of these SOCs are fairly
similar, the only differences being:

 * A different method to set the secondary CPU boot address

 * An Armada 375 specific workaround needed for the early Z1 stepping,
   added by the following patch.

Other than that, the patch is fairly straightforward and adds the
usual platsmp and headsmp code, defining the smp_operations structure
that is referenced from the DT_MACHINE structures.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483648-26611-9-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483648-26611-9-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-05-08 16:08:22 +00:00
Gregory CLEMENT 00504be42a ARM: mvebu: add function to set the resume boot address for Armada 375
In order to boot the secondary CPUs on Armada 375, we need to set the
boot address of these CPUs, through a register part of the System
Controller (this deviates from the Armada XP design, where the boot
address was defined using a register part of the PMSU unit).

Therefore, this commit adds a new helper function in the System
Controller driver to set the secondary CPU boot address.

Moreover, it moves the System Controller initialization as an
early_initcall(), since arch_initcall() is too late for an SMP-related
initialization.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483648-26611-7-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483648-26611-7-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-05-08 16:08:14 +00:00
Jason Cooper 5194efc5c6 Merge branch 'mvebu/irqchip' into mvebu/soc 2014-05-08 16:07:56 +00:00
Thomas Petazzoni 2c9b2240be ARM: mvebu: use CPU_METHOD_OF_DECLARE for SMP on Armada XP
This commit adds the CPU_METHOD_OF_DECLARE declaration for the Armada
XP SMP operations. Note that the .smp_ops field of Armada XP
DT_MACHINE structure is kept, in order to ensure we remain compatible
with older Device Trees that do not include the "enable-method"
property for the CPUs.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483648-26611-3-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-05-08 16:07:45 +00:00
Thomas Petazzoni 05ad690608 ARM: mvebu: move Armada XP specific SMP initialization to platsmp.c
The pmsu.c driver contained an armada_xp_boot_cpu() function that sets
the boot address of a secondary CPUs and deasserts the reset. However,
the Armada 375 needs a slightly different logic, so it makes more
sense to move this code into the Armada XP specific platsmp.c.

In order to achieve this, the mvebu_pmsu_set_cpu_boot_addr() function
is exported. It will be needed for both the Armada XP and Armada 38x
SMP implementations.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483648-26611-2-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-05-08 16:07:37 +00:00
Jason Cooper d269a36ae7 Merge branch 'mvebu/soc-pmsu' into mvebu/soc 2014-05-08 16:06:57 +00:00
Thomas Petazzoni d7df84b3ce irqchip: irq-armada-370-xp: Use cpu notifier to initialize secondary CPUs
Some irqchip initialization must be done on secondary CPUs. On mvebu
platforms, this is currently achieved by having the
arch/arm/mach-mvebu/platsmp.c code directly call into a function
exported by the irqchip driver, which isn't really nice.

This commit changes this by using the same solution as the one used in
the GIC driver: the irqchip driver registers a CPU notifier, which is
used to do the secondary CPU IRQ initialization. This way, the irqchip
driver is completely autonomous, and the function no longer needs to
be exposed from the irqchip driver to the SoC code.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483648-26611-6-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-05-08 14:42:00 +00:00
Thomas Petazzoni ef37d337e1 irqchip: irq-armada-370-xp: Do the set_smp_cross_call() in the driver
Instead of having the SoC code in arch/arm/mach-mvebu/platsmp.c do the
set_smp_cross_call() to register the IPI-triggering function, it makes
more sense to do exactly what the GIC driver is doing: let the irqchip
driver do it. This way, it avoids having to expose the
armada_mpic_send_doorbell() function between the irqchip driver and
the SoC code.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483648-26611-5-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-05-08 14:41:49 +00:00
Gregory CLEMENT 02e7b06795 ARM: mvebu: use a separate function to set the boot address of CPUs
Setting the start (or boot) address of a CPU is no more used only
during SMP bring up on Armada 370/XP, but it will also be used by the
CPU idle function of Armada XP, and by the Armada 38x SMP support.

Therefore this commit creates a separate PMSU function to set the boot
address of a CPU with the PMSU.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483433-25836-7-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483433-25836-7-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-04-24 05:24:30 +00:00
Gregory CLEMENT 0c3acc746d ARM: mvebu: extend the PMSU registers
The initial binding for PMSU was wrong, as it didn't take into account
all the registers from the PMSU and moreover it referred to the CPU
reset registers which are not part of PMSU.

The Power Management Unit Service block also controls the Coherency
Fabric subsystem. These registers are needed for the CPU idle
implementation for the Armada 370/XP, it allows to enter a deep CPU
idle state where the Coherency Fabric and the L2 cache are powered
down.

This commit adds support for a new compatible for the PMSU node which
includes the registers related to the coherency fabric. It also keeps
compatibility with the old compatible string.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483433-25836-5-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483433-25836-5-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-04-24 05:24:26 +00:00
Thomas Petazzoni bd045a1ebb ARM: mvebu: improve PMSU driver to request its resource
Until now, the PMSU driver was using of_iomap() to map its registers,
but of_iomap() doesn't call request_mem_region(). This commit fixes
the memory mapping code of the PMSU to do so, which will also be
useful for a later commit since we will need to adjust the resource
base address and size for Device Tree backward compatibility.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483433-25836-4-git-send-email-thomas.petazzoni@free-electrons.com
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-04-24 05:24:03 +00:00
Thomas Petazzoni 49754ffef5 ARM: mvebu: start using the CPU reset driver
This commit changes the PMSU driver to no longer map itself the CPU
reset registers, and instead call into the CPU reset driver to
deassert the secondary CPUs for SMP booting.

In order to provide Device Tree backward compatibility, the CPU reset
driver is extended to not only support its official compatible string
"marvell,armada-370-cpu-reset", but to also look at the PMSU
compatible string "marvell,armada-370-xp-pmsu" to find the CPU reset
registers address. This allows old Device Tree to work correctly with
newer kernel versions. Therefore, the CPU reset driver implements the
following logic:

 * If one of the normal compatible strings
   "marvell,armada-370-cpu-reset" is found, then we map its first
   memory resource as the CPU reset registers.

 * Otherwise, if none of the normal compatible strings have been
   found, we look for the "marvell,armada-370-xp-pmsu" compatible
   string, and we map the second memory as the CPU reset registers.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483433-25836-3-git-send-email-thomas.petazzoni@free-electrons.com
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-04-24 05:24:03 +00:00
Thomas Petazzoni 3f20fb1153 ARM: mvebu: introduce CPU reset code
The Armada 370 and Armada XP have registers that allow to reset the
CPUs, which is particularly useful to take the secondary CPUs out of
reset in the context of the SMP support.

Unfortunately, an implementation mistake was originally made and the
support for these registers was integrated into the PMSU driver, which
is in fact completely unrelated. And it turns out that the Armada 375
has the same CPU reset registers, but does not have the PMSU
registers.

Therefore, this commit creates a small CPU reset driver. All it does
is provide a simple mvebu_cpu_reset_deassert() function that the SMP
support code can call to take secondary CPUs out of reset. As of this
commit, the driver isn't being used, it will be used through changes
in the following commits.

Note that we initially planned to use the 'reset controller'
framework, but it requires the addition of "resets" properties in the
Device Tree, which are causing too many problems if we want to keep
the Device Tree backward compatibility. Moreover, the 'reset
controller' framework is mainly useful when a device driver needs to
request a reset of its device from a separate reset controller. In our
case, the CPU reset handling and the SMP core code are both located in
arch/arm/mach-mvebu/ and are tightly linked together, so there's no
real benefit in going through a separate framework.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483433-25836-2-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-04-24 05:24:02 +00:00
Thomas Petazzoni d0de932382 ARM: mvebu: add Armada 38x support to the coherency code
The Armada 38x has a coherency unit that is similar to the one of the
Armada 375 SoC, except that it does not have the bug of the Armada 375
coherency unit that requires the XOR based workaround.

This commit therefore extends the Marvell EBU coherency code with a
new compatible string to support the Armada 38x coherency unit.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483228-25625-9-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-04-24 05:00:38 +00:00
Thomas Petazzoni 5ab5afd8ba ARM: mvebu: implement Armada 375 coherency workaround
The early revisions of Armada 375 SOCs (Z1 stepping) have a bug in the
I/O coherency unit that prevents using the normal method for the I/O
coherency barrier. The recommended workaround is to use a XOR memset
transfer to act as the I/O coherency barrier.

This involves "borrowing" a XOR engine, which gets disabled in the
Device Tree so the normal XOR driver doesn't use it.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483228-25625-8-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-04-24 05:00:37 +00:00
Thomas Petazzoni 77fa4b9ab0 ARM: mvebu: add Armada 375 support to the coherency code
The Armada 375, like the Armada 370 and Armada XP, has a coherency
unit. However, unlike the coherency unit of 370/XP which does both CPU
and I/O coherency, the one on Armada 735 only does I/O
coherency. Therefore, instead of having two sets of registers (the
first one being used mainly to register each CPU in the coherency
fabric, the second one being used for the I/O coherency barrier), it
has only one set of register (for the I/O coherency barrier).

This commit adds a new "marvell,armada-375-coherency-fabric"
compatible string for this variant of the coherency fabric. The custom
DMA operations, and the way of triggering an I/O barrier is the same
as Armada 370/XP, so the code changes are minimal. However, the
set_cpu_coherent() function is not needed on Armada 375 and will not
work.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483228-25625-7-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-04-24 05:00:37 +00:00
Thomas Petazzoni 8e6ac20338 ARM: mvebu: enable the ARM SCU on Armada 375 and Armada 38x
Contrary to the Armada 370 and XP that used the PJ4B Marvell cores,
the Armada 375 and Armada 38x use the ARM Cortex-A9. A consequence of
this is that the unit responsible for the coherency between CPUs is
now the ARM SCU, and not the Marvell coherency unit (which is still
present to do coherency with I/O devices).

Therefore this commit:

 * Ensures that the selection of the Armada 375 or Armada 38x SoC
   support enables the ARM SCU support in the kernel.

 * Make sure to initialize the SCU at boot time.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483228-25625-6-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-04-24 05:00:37 +00:00
Thomas Petazzoni 5fbba08051 ARM: mvebu: ARM: mvebu: use of_find_matching_node_and_match() in coherency.c
In the mach-mvebu coherency code, instead of using
of_find_matching_node() and then of_match_node(), directly use the
of_find_matching_node_and_match() which does both at once.

We take this opportunity to also simplify the initialization of the
"type" variable.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483228-25625-5-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-04-24 05:00:36 +00:00
Thomas Petazzoni 5686a1e5aa bus: mvebu: pass the coherency availability information at init time
Until now, the mvebu-mbus was guessing by itself whether hardware I/O
coherency was available or not by poking into the Device Tree to see
if the coherency fabric Device Tree node was present or not.

However, on some upcoming SoCs, the presence or absence of the
coherency fabric DT node isn't sufficient: in CONFIG_SMP, the
coherency can be enabled, but not in !CONFIG_SMP.

In order to clean this up, the mvebu_mbus_dt_init() function is
extended to get a boolean argument telling whether coherency is
enabled or not. Therefore, the logic to decide whether coherency is
available or not now belongs to the core SoC code instead of the
mvebu-mbus driver itself, which is much better.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483228-25625-4-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-04-24 05:00:36 +00:00
Thomas Petazzoni 501f928e00 ARM: mvebu: add a coherency_available() call
This commit extends the coherency fabric code to provide a
coherency_available()function that the SoC code can call to be told
whether coherency support is available or not. On Armada 370/XP,
coherency support is available as soon as the relevant DT node is
present. On some upcoming SoCs, the DT node needs to be present *and*
the system running with CONFIG_SMP enabled.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483228-25625-3-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-04-24 05:00:36 +00:00
Thomas Petazzoni 924d38f404 ARM: mvebu: prepare coherency code to support more SOCs
The code that handles the coherency fabric of Armada 370 and Armada XP
in arch/arm/mach-mvebu/coherency.c made the assumption that there was
only one type of coherency fabric. Unfortunately, it turns out that
upcoming SoCs have a slightly different coherency unit.

In preparation to the introduction of the coherency support for more
SoCs, this commit:

 * Introduces a data associated to the compatible string in the
   compatible string match table, so that the code can differantiate
   the variant of coherency unit being used.

 * Separates the coherency unit initialization code into its own
   function.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483228-25625-2-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-04-24 05:00:35 +00:00
Andrew Lunn 56a705a48e ARM: mvebu: Add a SOC bus device entry
Add the SoC Family, device ID and revision to /sys/bus/soc.

Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Link: https://lkml.kernel.org/r/1393955507-26436-1-git-send-email-andrew@lunn.ch
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-04-24 04:31:03 +00:00
Rob Herring 55400f3a1f ARM: mvebu: clean-up unneeded kconfig selects
Multi-platform support implies all these options are already selected and
individual platforms don't need to select them.

Signed-off-by: Rob Herring <robh@kernel.org>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-04-22 14:33:27 -05:00
Linus Torvalds ff050ad12c ARM: SoC specific changes
Lots of changes specific to one of the SoC families. Some that
 stick out are:
 
 * mach-qcom gains new features, most importantly SMP support for
   the newer chips (Stephen Boyd, Rohit Vaswani)
 * mvebu gains support for three new SoCs: Armada 375, 380 and 385
   (Thomas Petazzoni and Free-electrons team)
 * SMP support for Rockchips (Heiko Stübner)
 * Lots of i.MX changes (Shawn Guo)
 * Added support for BCM5301x SoC (Hauke Mehrtens)
 * Multiplatform support for Marvell Kirkwood and Dove
   (Andrew Lunn and Sebastian Hesselbarth doing the final part
   of a long journey)
 * Unify davinci platforms and remove obsolete ones (Sekhar Nori,
   Arnd Bergmann)
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Merge tag 'soc-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC specific changes from Arnd Bergmann:
 "Lots of changes specific to one of the SoC families.  Some that stick
  out are:

   - mach-qcom gains new features, most importantly SMP support for the
     newer chips (Stephen Boyd, Rohit Vaswani)
   - mvebu gains support for three new SoCs: Armada 375, 380 and 385
     (Thomas Petazzoni and Free-electrons team)
   - SMP support for Rockchips (Heiko Stübner)
   - Lots of i.MX changes (Shawn Guo)
   - Added support for BCM5301x SoC (Hauke Mehrtens)
   - Multiplatform support for Marvell Kirkwood and Dove (Andrew Lunn
     and Sebastian Hesselbarth doing the final part of a long journey)
   - Unify davinci platforms and remove obsolete ones (Sekhar Nori, Arnd
     Bergmann)"

* tag 'soc-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (126 commits)
  ARM: sunxi: Select HAVE_ARM_ARCH_TIMER
  ARM: cache-tauros2: remove ARMv6 code
  ARM: mvebu: don't select CONFIG_NEON
  ARM: davinci: fix DT booting with default defconfig
  ARM: configs: bcm_defconfig: enable bcm590xx regulator support
  ARM: davinci: remove tnetv107x support
  MAINTAINERS: Update ARM STi maintainers
  ARM: restrict BCM_KONA_UART to ARCH_BCM_MOBILE
  ARM: bcm21664: Add board support.
  ARM: sunxi: Add the new watchog compatibles to the reboot code
  ARM: enable ARM_HAS_SG_CHAIN for multiplatform
  ARM: davinci: remove da8xx_omapl_defconfig
  ARM: davinci: da8xx: fix multiple watchdog device registration
  ARM: davinci: add da8xx specific configs to davinci_all_defconfig
  ARM: davinci: enable da8xx build concurrently with older devices
  ARM: BCM5301X: workaround suppress fault
  ARM: BCM5301X: add early debugging support
  ARM: BCM5301X: initial support for the BCM5301X/BCM470X SoCs with ARM CPU
  ARM: mach-bcm: Remove GENERIC_TIME
  ARM: shmobile: APMU: Fix warnings due to improper printk formats
  ...
2014-04-05 14:19:54 -07:00
Linus Torvalds dfc25e4503 ARM: SoC: cleanups for 3.15
These cleanup patches are mainly move stuff around and should all
 be harmless. They are mainly split out so that other branches can
 be based on top to avoid conflicts.
 
 Notable changes are:
 
 * We finally remove all mach/timex.h, after CLOCK_TICK_RATE is no
   longer used. (Uwe Kleine-König)
 * The Qualcomm MSM platform is split out into legacy mach-msm and
   new-style mach-qcom, to allow easier maintainance of the new
   hardware support without regressions. (Kumar Gala)
 * A rework of some of the Kconfig logic to simplify multiplatform
   support (Rob Herring)
 * Samsung Exynos gets closer to supporting multiplatform (Sachin
   Kamat and others)
 * mach-bcm3528 gets merged into mach-bcm (Stephen Warren)
 * at91 gains some common clock framework support (Alexandre Belloni,
   Jean-Jacques Hiblot and other French people).
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Merge tag 'cleanup-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC cleanups from Arnd Bergmann:
 "These cleanup patches are mainly move stuff around and should all be
  harmless.  They are mainly split out so that other branches can be
  based on top to avoid conflicts.

  Notable changes are:

   - We finally remove all mach/timex.h, after CLOCK_TICK_RATE is no
     longer used (Uwe Kleine-König)
   - The Qualcomm MSM platform is split out into legacy mach-msm and
     new-style mach-qcom, to allow easier maintainance of the new
     hardware support without regressions (Kumar Gala)
   - A rework of some of the Kconfig logic to simplify multiplatform
     support (Rob Herring)
   - Samsung Exynos gets closer to supporting multiplatform (Sachin
     Kamat and others)
   - mach-bcm3528 gets merged into mach-bcm (Stephen Warren)
   - at91 gains some common clock framework support (Alexandre Belloni,
     Jean-Jacques Hiblot and other French people)"

* tag 'cleanup-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (89 commits)
  ARM: hisi: select HAVE_ARM_SCU only for SMP
  ARM: efm32: allow uncompress debug output
  ARM: prima2: build reset code standalone
  ARM: at91: add PWM clock
  ARM: at91: move sam9261 SoC to common clk
  ARM: at91: prepare common clk transition for sam9261 SoC
  ARM: at91: updated the at91_dt_defconfig with support for the ADS7846
  ARM: at91: dt: sam9261: Device Tree support for the at91sam9261ek
  ARM: at91: dt: defconfig: Added the sam9261 to the list of DT-enabled SOCs
  ARM: at91: dt: Add at91sam9261 dt SoC support
  ARM: at91: switch sam9rl to common clock framework
  ARM: at91/dt: define main clk frequency of at91sam9rlek
  ARM: at91/dt: define at91sam9rl clocks
  ARM: at91: prepare common clk transition for sam9rl SoCs
  ARM: at91: prepare sam9 dt boards transition to common clk
  ARM: at91: dt: sam9rl: Device Tree for the at91sam9rlek
  ARM: at91/defconfig: Add the sam9rl to the list of DT-enabled SOCs
  ARM: at91: Add at91sam9rl DT SoC support
  ARM: at91: prepare at91sam9rl DT transition
  ARM: at91/defconfig: refresh at91sam9260_9g20_defconfig
  ...
2014-04-05 13:51:19 -07:00
Linus Torvalds 9f800363bb ARM: SoC non-critical bug fixes for 3.15
Lots of isolated bug fixes that were not found to be important
 enough to be submitted before the merge window or backported
 into stable kernels.
 The vast majority of these came out of Arnd's randconfig testing
 and just prevents running into build-time bugs in configurations
 that we do not care about in practice.
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Merge tag 'fixes-non-critical-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC non-critical bug fixes from Arnd Bergmann:
 "Lots of isolated bug fixes that were not found to be important enough
  to be submitted before the merge window or backported into stable
  kernels.

  The vast majority of these came out of Arnd's randconfig testing and
  just prevents running into build-time bugs in configurations that we
  do not care about in practice"

* tag 'fixes-non-critical-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (75 commits)
  ARM: at91: fix a typo
  ARM: moxart: fix CPU selection
  ARM: tegra: fix board DT pinmux setup
  ARM: nspire: Fix compiler warning
  IXP4xx: Fix DMA masks.
  Revert "ARM: ixp4xx: Make dma_set_coherent_mask common, correct implementation"
  IXP4xx: Fix Goramo Multilink GPIO conversion.
  Revert "ARM: ixp4xx: fix gpio rework"
  ARM: tegra: make debug_ll code build for ARMv6
  ARM: sunxi: fix build for THUMB2_KERNEL
  ARM: exynos: add missing include of linux/module.h
  ARM: exynos: fix l2x0 saved regs handling
  ARM: samsung: select CRC32 for SAMSUNG_PM_CHECK
  ARM: samsung: select ATAGS where necessary
  ARM: samsung: fix SAMSUNG_PM_DEBUG Kconfig logic
  ARM: samsung: allow serial driver to be disabled
  ARM: s5pv210: enable IDE support in MACH_TORBRECK
  ARM: s5p64x0: fix building with only one soc type
  ARM: s3c64xx: select power domains only when used
  ARM: s3c64xx: MACH_SMDK6400 needs HSMMC1
  ...
2014-04-05 13:44:27 -07:00
Arnd Bergmann c7f094d5e8 ARM: mvebu: don't select CONFIG_NEON
CONFIG_NEON is meant to be user-selectable. Turning it on
unconditionally means we can't build a smaller kernel when
we don't need it, and causes build errors if CONFIG_VFP
is not also enabled.

To still have neon enabled however, we need to turn it on
now in multi_v7_defconfig and mvebu_v7_defconfig.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Jason Cooper <jason@lakedaemon.net>
Acked-by: Gregory Clement <gregory.clement@free-electrons.com>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-03-21 18:31:42 +01:00
Arnd Bergmann 9e1280419e ARM: mvebu: add missing header
The definition for SIGBUS may not be visible without including
linux/signal.h, as I found during randconfig testing.

Adding an explicit include is certainly the right thing to do.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Jason Cooper <jason@lakedaemon.net>
Acked-by: Gregory Clement <gregory.clement@free-electrons.com>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2014-03-21 18:23:35 +01:00
Arnd Bergmann e7f274dccf mvebu soc changes for v3.15 (incremental #3)
- dove
     - move devicetree code from mach-dove/ to mach-mvebu/ :-)
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Merge tag 'mvebu-soc-3.15-3' of git://git.infradead.org/linux-mvebu into next/soc

Merge "mvebu soc changes for v3.15 (incremental #3)" from Jason Cooper:

 - dove
    - move devicetree code from mach-dove/ to mach-mvebu/ :-)

* tag 'mvebu-soc-3.15-3' of git://git.infradead.org/linux-mvebu:
  ARM: mvebu: move DT Dove to MVEBU

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-03-17 10:53:49 +01:00
Arnd Bergmann d4324ce357 mvebu soc changes for v3.15 (incremental pull #2)
- mvebu
     - Add Armada 375, 380 and 385 SoCs
 
  - kirkwood
     - move kirkwood DT support to mach-mvebu
     - add mostly DT support for HP T5325 thin client
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Merge tag 'mvebu-soc-3.15-2' of git://git.infradead.org/linux-mvebu into next/soc

Merge "mvebu soc changes for v3.15 (incremental pull #2)" from Jason Cooper:

 - mvebu
    - Add Armada 375, 380 and 385 SoCs

 - kirkwood
    - move kirkwood DT support to mach-mvebu
    - add mostly DT support for HP T5325 thin client

* tag 'mvebu-soc-3.15-2' of git://git.infradead.org/linux-mvebu:
  ARM: kirkwood: Add HP T5325 thin client
  ARM: kirkwood: select dtbs based on SoC
  ARM: kirkwood: Remove redundant kexec code
  ARM: mvebu: Armada 375/38x depend on MULTI_V7
  ARM: mvebu: Simplify headers and make local
  ARM: mvebu: Enable mvebu-soc-id on Kirkwood
  ARM: mvebu: Let kirkwood use the system controller for restart
  ARM: mvebu: Move kirkwood DT boards into mach-mvebu
  ARM: MM Enable building Feroceon L2 cache controller with ARCH_MVEBU
  ARM: Fix default CPU selection for ARCH_MULTI_V5
  ARM: MM: Add DT binding for Feroceon L2 cache
  ARM: orion: Move cache-feroceon-l2.h out of plat-orion
  ARM: mvebu: Add ARCH_MULTI_V7 to SoCs
  ARM: kirkwood: ioremap memory control register
  ARM: kirkwood: ioremap the cpu_config register before using it.
  ARM: kirkwood: Separate board-dt from common and pcie code.
  ARM: kirkwood: Drop printing the SoC type and revision
  ARM: kirkwood: Convert mv88f6281gtw_ge switch setup to DT
  ARM: kirkwood: Give pm.c its own header file.
  ARM: mvebu: Rename the ARCH_MVEBU menu option

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-03-17 10:49:14 +01:00
Olof Johansson 1760e4f855 i.MX SoC changes for 3.15:
- Support suspend from ocram (DDR IO floating) for imx6 platforms
  - Add cpuidle support for imx6sl
  - Sparse warning fixes for imx6sl and vf610 clock code
  - Remove PWM platform code
  - Support ptp and rmii clock from pad
  - Support WEIM CS GPR configuration
  - Random cleanups and defconfig updates
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Merge tag 'imx-soc-3.15' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/soc

i.MX SoC changes for 3.15 from Shawn Guo:
 - Support suspend from ocram (DDR IO floating) for imx6 platforms
 - Add cpuidle support for imx6sl
 - Sparse warning fixes for imx6sl and vf610 clock code
 - Remove PWM platform code
 - Support ptp and rmii clock from pad
 - Support WEIM CS GPR configuration
 - Random cleanups and defconfig updates

* tag 'imx-soc-3.15' of git://git.linaro.org/people/shawnguo/linux-2.6: (373 commits)
  ARM: imx6: drop .text.head section annotation from headsmp.S
  ARM: imx6: build suspend-imx6.o with CONFIG_SOC_IMX6
  ARM: imx6: rename pm-imx6q.c to pm-imx6.c
  ARM: imx6: introduce CONFIG_SOC_IMX6 for i.MX6 common stuff
  ARM: imx6: do not call imx6q_suspend_init() with !CONFIG_SUSPEND
  ARM: imx6: call suspend_set_ops() from suspend routine
  ARM: imx6: build headsmp.o only on CONFIG_SMP
  ARM: imx6: move v7_cpu_resume() into suspend-imx6.S
  ARM i.MX6q: Mark VPU and IPU AXI transfers as cacheable, increase IPU priority
  ARM: imx6q: Add GPR6 and GPR7 register definitions for iomuxc gpr
  bus: imx-weim: support CS GPR configuration
  ARM: mach-imx: Kconfig: Remove IMX_HAVE_PLATFORM_IMX2_WDT from SOC_IMX53
  ARM: imx_v6_v7_defconfig: Select CONFIG_DEBUG_FS
  ARM: mach-imx: Select CONFIG_SRAM at ARCH_MXC level
  ARM: imx: add speed grading check for i.mx6 soc
  ARM: imx: avoid calling clk APIs in idle thread which may cause schedule
  ARM: imx6q: support ptp and rmii clock from pad
  ARM: imx6q: remove unneeded clk lookups
  ARM: imx_v6_v7_defconfig: Select CONFIG_MMC_UNSAFE_RESUME
  ARM: imx_v4_v5_defconfig: Select CONFIG_MMC_UNSAFE_RESUME
  ...
2014-03-09 12:03:18 -07:00
Sebastian Hesselbarth 00e8ec2f0b ARM: mvebu: move DT Dove to MVEBU
With all the DT support preparation done, we are able to move Dove
to MVEBU easily. Legacy non-DT mach-dove is left untouched to rot
for a while before removal.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-03-04 04:13:48 +00:00
Jason Cooper 0d75ab68fd Merge branch 'mvebu/soc-kw' into mvebu/soc 2014-03-01 03:21:04 +00:00
Jason Cooper aa89b0ad4f Merge branch 'mvebu/soc-3xx' into mvebu/soc 2014-03-01 03:20:55 +00:00
Arnd Bergmann ead47a75cf - Remove common kconfig options required by multi-platform builds out
of individual platforms as they are redundant.
 - Make SMP, CACHE_L2X0 and GPIO config options user visible on
 multi-platform builds as most platforms enable these options and all
 platforms can run with them enabled.
 - Make multi-platform v6 default to more optimal v6k rather than v6
 - Remove the last bit of mach-virt and convert it to just a kconfig
 option.
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Merge tag 'kconfig-cleanup-for-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux into next/cleanup

Merge "kconfig clean-up and mach-virt removal for 3.15" from Rob Herring

- Remove common kconfig options required by multi-platform builds out
of individual platforms as they are redundant.
- Make SMP, CACHE_L2X0 and GPIO config options user visible on
multi-platform builds as most platforms enable these options and all
platforms can run with them enabled.
- Make multi-platform v6 default to more optimal v6k rather than v6
- Remove the last bit of mach-virt and convert it to just a kconfig
option.

* tag 'kconfig-cleanup-for-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux:
  ARM: virt: select ARM_AMBA
  ARM: virt: make mach-virt just a kconfig option
  ARM: vt8500: enable V6K instead of plain V6
  ARM: cns3xxx: enable V6K instead of plain V6
  ARM: bcm2835: enable V6K instead of plain V6
  ARM: Select V6K instead of V6 by default for multi-platform
  ARM: select MIGHT_HAVE_CACHE_L2X0 for V6 and V7 multi-platform
  ARM: select HAVE_SMP for V7 multi-platform
  ARM: centralize common multi-platform kconfig options

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-02-28 17:08:21 +01:00
Andrew Lunn b02b643846 ARM: kirkwood: Add HP T5325 thin client
Convert the kirkwood t5325-setup.c to mostly device tree for
mach-mvebu. Part of the audio setup needs to remain in C for the
moment until suitable bindings are designed and implemented. So add
board code, triggered by the compatibility string.

Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-02-25 20:32:16 +00:00
Jason Cooper 665ca874e1 ARM: mvebu: Armada 375/38x depend on MULTI_V7
During this release cycle, we're adding the new Armada 375, 380, and 385
SoCs.  We're also migrating DT kirkwood boards into mach-mvebu.  The
kirkwood changes make the different SoCs in mach-mvebu/ depend on
MULTI_V7 or MULTI_V5 as appropriate.

We add this dependency to the new SoCs so that when the branches are
merged, everything is as it should be.

Acked-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-02-24 17:33:44 +00:00