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4 Commits

Author SHA1 Message Date
Matthew McClintock a9b0b1fe9e pinctrl: qcom: ipq4019: fix register offsets 
For this SoC the register offsets changed from previous versions to be
separated by a larger amount.

Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
Acked-by: Björn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2016-03-31 11:56:13 +02:00
Matthew McClintock cdbac7349f pinctrl: qcom: ipq4019: fix the function enum for gpio mode 
Without this, we would fail to set the mode to gpio if trying to
configure for that mode

Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
Acked-by: Björn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2016-03-31 11:55:57 +02:00
Matthew McClintock 5303f7827f pinctrl: qcom: ipq4019: set ngpios to correct value 
This should have been bumped to 100 when the extra pins
were added in the original pinctrl patch

Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
Acked-by: Björn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2016-03-31 11:53:02 +02:00
Varadarajan Narayanan e260d2bbc9 pinctrl: qcom: ipq4019: Add IPQ4019 pinctrl support 
Add pinctrl driver support for IPQ4019 platform

Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Andy Gross <andy.gross@linaro.org>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
[Dropped .owner assignment]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2016-02-16 15:52:21 +01:00