Commit Graph

13 Commits

Author SHA1 Message Date
Thierry Reding 078c445733 drm/tegra: dp: Add DisplayPort link training helper
Add a helper that will perform link training as described in the
DisplayPort specification.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-28 11:18:53 +01:00
Thierry Reding 6a127160c4 drm/tegra: dp: Add support for eDP link rates
Parses additional link rates from DPCD if the sink supports eDP 1.4.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-28 11:18:53 +01:00
Thierry Reding 01f09f242e drm/tegra: dp: Add drm_dp_link_choose() helper
This helper chooses an appropriate configuration, according to the
bitrate requirements of the video mode and the capabilities of the
DisplayPort sink.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-28 11:18:52 +01:00
Thierry Reding ad7f2dda38 drm/tegra: dp: Read AUX read interval from DPCD
Store the AUX read interval from DPCD, so that it can be used to wait
for the durations given in the specification during link training.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-28 11:18:52 +01:00
Thierry Reding 7aa3cc540d drm/tegra: dp: Read eDP version from DPCD
If the sink supports eDP, read the eDP revision from it's DPCD.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-28 11:18:45 +01:00
Thierry Reding 4ff9ba5674 drm/tegra: dp: Read alternate scrambler reset capability from sink
Parse from the sink capabilities whether or not the eDP alternate
scrambler reset value of 0xfffe is supported.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-28 11:18:45 +01:00
Thierry Reding 6c651b13e4 drm/tegra: dp: Read channel coding capability from sink
Parse from the sink capabilities whether or not it supports ANSI 8B/10B
channel coding as specified in ANSI X3.230-1994, clause 11.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-28 11:18:45 +01:00
Thierry Reding db199502fa drm/tegra: dp: Read TPS3 capability from sink
The TPS3 capability can be exposed by DP 1.2 and later sinks if they
support the alternative training pattern for channel equalization.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-28 11:18:45 +01:00
Thierry Reding cb072eebfa drm/tegra: dp: Read fast training capability from link
While probing the DisplayPort link, query the fast training capability.
If supported, drivers can use the fast link training sequence instead of
the more involved full link training sequence.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-28 11:18:44 +01:00
Thierry Reding 27ba465ce3 drm/tegra: dp: Turn link capabilities into booleans
Rather than storing capabilities as flags in an integer, use a separate
boolean per capability. This simplifies the code that checks for these
capabilities.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-28 11:18:44 +01:00
Thierry Reding c728e2d4a6 drm/tegra: dp: Track link capabilities alongside settings
Store capabilities in max_* fields and add separate fields for the
currently selected settings.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-28 11:18:44 +01:00
Thierry Reding 0fa5c1bdd2 drm/tegra: Add missing kerneldoc for struct drm_dp_link
The drm_dp_link structure tracks capabilities on the DP link. Add some
kerneldoc to explain what each of its fields means.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-10-28 11:18:44 +01:00
Thierry Reding 9a42c7c647 drm/tegra: Move drm_dp_link helpers to Tegra DRM
During the discussion of patches that enhance the drm_dp_link helpers it
was concluded that these helpers aren't very useful to begin with. After
all other drivers have been converted not to use these helpers anymore,
move these helpers into the last remaining user: Tegra DRM.

If at some point these helpers are deemed more widely useful, they can
be moved out into the DRM DP helpers again.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: https://patchwork.freedesktop.org/patch/msgid/20191021143437.1477719-14-thierry.reding@gmail.com
2019-10-23 18:22:10 +02:00