Commit Graph

49 Commits

Author SHA1 Message Date
Linus Walleij 0bfe5167b2 ARM: dts: ux500: use the GIC include header
Use the <dt-bindings/interrupt-controller/arm-gic.h> header for
generating the flags for the first cell of the interrupt
definitions.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-03-29 09:34:08 +02:00
Linus Walleij 1b1e8e024b ARM: dts: ux500: use the GPIO DT header
Use the <dt-bindings/gpio/gpio.h> header instead of using
hardcoded values for the GPIO flags. Eradicate the totally
bogus "0x4" flag used and set that to GPIO_ACTIVE_HIGH as is
proper, switch the inverted card detect on the Snowball to
flag using GPIO_ACTIVE_LOW instead of using the MMC-specific
inversion flag.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-03-29 09:34:08 +02:00
Javier Martinez Canillas 25e8930ce8 ARM: ux500: remove regulator-compatible usage
The regulator-compatible property from the regulator DT binding was
deprecated and the correct approach is to use the node's name.

This patch has no functional changes since the values of the node's
name and the regulator-compatible match for all the regulators.

Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-11-17 14:51:23 +01:00
Linus Torvalds 88a99886c2 This is the bulk of pin control changes for the v4.3 development
cycle
 
 Core changes:
 
 - It is possible configure groups in debugfs.
 
 - Consolidation of chained IRQ handler install/remove replacing
   all call sites where irq_set_handler_data() and
   irq_set_chained_handler() were done in succession with a
   combined call to irq_set_chained_handler_and_data(). This
   series was created by Thomas Gleixner after the problem was
   observed by Russell King.
 
 - Tglx also made another series of patches switching
   __irq_set_handler_locked() for irq_set_handler_locked() which
   is way cleaner.
 
 - Tglx also wrote a good bunch of patches to make use of
   irq_desc_get_xxx() accessors and avoid looking up irq_descs
   from IRQ numbers. The goal is to get rid of the irq number
   from the handlers in the IRQ flow which is nice.
 
 Driver feature enhancements:
 
 - Power management support for the SiRF SoC Atlas 7.
 
 - Power down support for the Qualcomm driver.
 
 - Intel Cherryview and Baytrail: switch drivers to use raw
   spinlocks in IRQ handlers to play nice with the realtime
   patch set.
 
 - Rework and new modes handling for Qualcomm SPMI-MPP.
 
 - Pinconf power source config for SH PFC.
 
 New drivers and subdrivers:
 
 - A new driver for Conexant Digicolor CX92755.
 
 - A new driver for UniPhier PH1-LD4, PH1-Pro4, PH1-sLD8,
   PH1-Pro5, ProXtream2 and PH1-LD6b SoC pin control support.
 
 - Reverse-egineered the S/PDIF settings for the Allwinner
   sun4i driver.
 
 - Support for Qualcomm Technologies QDF2xxx ARM64 SoCs
 
 - A new Freescale i.mx6ul subdriver.
 
 Cleanup:
 
 - Remove platform data support in a number of SH PFC
   subdrivers.
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Merge tag 'pinctrl-v4.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control updates from Linus Walleij:
 "This is the bulk of pin control changes for the v4.3 development
  cycle.

  Like with GPIO it's a lot of stuff.  If my subsystems are any sign of
  the overall tempo of the kernel v4.3 will be a gigantic diff.

[ It looks like 4.3 is calmer than 4.2 in most other subsystems, but
  we'll see - Linus ]

  Core changes:

   - It is possible configure groups in debugfs.

   - Consolidation of chained IRQ handler install/remove replacing all
     call sites where irq_set_handler_data() and
     irq_set_chained_handler() were done in succession with a combined
     call to irq_set_chained_handler_and_data().  This series was
     created by Thomas Gleixner after the problem was observed by
     Russell King.

   - Tglx also made another series of patches switching
     __irq_set_handler_locked() for irq_set_handler_locked() which is
     way cleaner.

   - Tglx also wrote a good bunch of patches to make use of
     irq_desc_get_xxx() accessors and avoid looking up irq_descs from
     IRQ numbers.  The goal is to get rid of the irq number from the
     handlers in the IRQ flow which is nice.

  Driver feature enhancements:

   - Power management support for the SiRF SoC Atlas 7.

   - Power down support for the Qualcomm driver.

   - Intel Cherryview and Baytrail: switch drivers to use raw spinlocks
     in IRQ handlers to play nice with the realtime patch set.

   - Rework and new modes handling for Qualcomm SPMI-MPP.

   - Pinconf power source config for SH PFC.

  New drivers and subdrivers:

   - A new driver for Conexant Digicolor CX92755.

   - A new driver for UniPhier PH1-LD4, PH1-Pro4, PH1-sLD8, PH1-Pro5,
     ProXtream2 and PH1-LD6b SoC pin control support.

   - Reverse-egineered the S/PDIF settings for the Allwinner sun4i
     driver.

   - Support for Qualcomm Technologies QDF2xxx ARM64 SoCs

   - A new Freescale i.mx6ul subdriver.

  Cleanup:

   - Remove platform data support in a number of SH PFC subdrivers"

* tag 'pinctrl-v4.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (95 commits)
  pinctrl: at91: fix null pointer dereference
  pinctrl: mediatek: Implement wake handler and suspend resume
  pinctrl: mediatek: Fix multiple registration issue.
  pinctrl: sh-pfc: r8a7794: add USB pin groups
  pinctrl: at91: Use generic irq_{request,release}_resources()
  pinctrl: cherryview: Use raw_spinlock for locking
  pinctrl: baytrail: Use raw_spinlock for locking
  pinctrl: imx6ul: Remove .owner field
  pinctrl: zynq: Fix typos in smc0_nand_grp and smc0_nor_grp
  pinctrl: sh-pfc: Implement pinconf power-source param for voltage switching
  clk: rockchip: add pclk_pd_pmu to the list of rk3288 critical clocks
  pinctrl: sun4i: add spdif to pin description.
  pinctrl: atlas7: clear ugly branch statements for pull and drivestrength
  pinctrl: baytrail: Serialize all register access
  pinctrl: baytrail: Drop FSF mailing address
  pinctrl: rockchip: only enable gpio clock when it setting
  pinctrl/mediatek: fix spelling mistake in dev_err error message
  pinctrl: cherryview: Serialize all register access
  pinctrl: UniPhier: PH1-Pro5: add I2C ch6 pin-mux setting
  pinctrl: nomadik: reflect current input value
  ...
2015-09-04 10:22:09 -07:00
Linus Torvalds f36fc04e4c The clk framework changes for 4.3 are mostly updates to existing drivers
and the addition of new clock drivers. Stephen Boyd has also done a lot
 of subsystem-wide driver clean-ups (thanks!). There are also fixes to
 the framework core and changes to better split clock provider drivers
 from clock consumer drivers.
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Merge tag 'clk-for-linus-4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Michael Turquette:
 "The clk framework changes for 4.3 are mostly updates to existing
  drivers and the addition of new clock drivers.  Stephen Boyd has also
  done a lot of subsystem-wide driver clean-ups (thanks!).  There are
  also fixes to the framework core and changes to better split clock
  provider drivers from clock consumer drivers"

* tag 'clk-for-linus-4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (227 commits)
  clk: s5pv210: add missing call to samsung_clk_of_add_provider()
  clk: pistachio: correct critical clock list
  clk: pistachio: Fix PLL rate calculation in integer mode
  clk: pistachio: Fix override of clk-pll settings from boot loader
  clk: pistachio: Fix 32bit integer overflows
  clk: tegra: Fix some static checker problems
  clk: qcom: Fix MSM8916 prng clock enable bit
  clk: Add missing header for 'bool' definition to clk-conf.h
  drivers/clk: appropriate __init annotation for const data
  clk: rockchip: register pll mux before pll itself
  clk: add bindings for the Ux500 clocks
  clk/ARM: move Ux500 PRCC bases to the device tree
  clk: remove duplicated code with __clk_set_parent_after
  clk: Convert __clk_get_name(hw->clk) to clk_hw_get_name(hw)
  clk: Constify clk_hw argument to provider APIs
  clk: Hi6220: add stub clock driver
  dt-bindings: clk: Hi6220: Document stub clock driver
  dt-bindings: arm: Hi6220: add doc for SRAM controller
  clk: atlas7: fix pll missed divide NR in fraction mode
  clk: atlas7: fix bit field and its root clk for coresight_tpiu
  ...
2015-08-31 17:26:48 -07:00
Linus Walleij 5dc0fe199b clk/ARM: move Ux500 PRCC bases to the device tree
The base addresses for the Ux500 PRCC controllers are hardcoded,
let's move them to the clock node in the device tree and delete
the constants.

Cc: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Olof Johansson <olof@lixom.net>
Acked-by: Michael Turquette <mturquette@baylibre.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-08-24 16:49:14 -07:00
Linus Walleij bf64dd262e ARM: ux500: add an SMP enablement type and move cpu nodes
The "cpus" node cannot be inside the "soc" node, while this
works for the CoreSight blocks, the early boot code will look
for "cpus" directly under the root node, so this is a hard
convention. So move the CPU nodes.

Augment the "reg" property to match what is actually in the
hardware: 0x300 and 0x301 respectively.

Then add an SMP enablement type to be used by the SMP init
code, "ste,dbx500-smp".

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
2015-08-06 10:10:34 +02:00
Linus Walleij ee04139d91 pinctrl/ARM: move GPIO and pinctrl deps to device tree
This gets the GPIO ranges out of the driver and into the device
tree where they belong. Standard DT bindings already exist for
this. Since no systems with this are deployed we can just augment
all device trees and the drivers at the same time and simplify
the world.

This also defines the array of GPIO chips related to the pin
controller.

Cc: arm@kernel.org
Acked-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-07-27 15:04:40 +02:00
Linus Walleij 109978dea4 ARM: ux500: define serial port aliases
This enumerates the PL011 serial ports on the Ux500. This is
necessary to do if we want to remove one of the serial ports,
since userspace depends on console to be present on ttyAMA2
and we must not break userspace.

Cc: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
2015-07-14 11:15:42 +02:00
Linus Walleij 724814b4fa ARM: ux500: define the backupram in the device tree
The Ux500 SOCs have a special backup RAM that needs to be
defined in the device tree.

Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-05-18 16:00:11 +02:00
Linus Walleij 487934109d ARM: ux500: add SCU and WD to device tree
The Ux500 like other Cortex-A9 SoC's has a Snoop Control
Unit (SCU) and a Watchdog in the same address range as
the local timers. Add these to the SoC device tree.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2015-05-15 17:22:39 +02:00
Arnd Bergmann 9d8a71ff5c Ux500 Device Tree changes for the v4.2 series:
Define CPU topology, connect that with CoreSight blocks,
 add sensor information to DT boards.
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Merge tag 'ux500-v4.2-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson into next/dt

Merge "Ux500 Device Tree changes for the v4.2 series" form Linus Walleij:

Define CPU topology, connect that with CoreSight blocks,
add sensor information to DT boards.

* tag 'ux500-v4.2-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson:
  ARM: ux500: add the sensors to the STUIB board
  ARM: ux500: assign the sensor trigger IRQs
  ARM: ux500: fix lsm303dlh magnetometer compat string
  ARM: ux500: add CoreSight blocks to DTS file
  ARM: ux500: define CPU topology
2015-05-13 13:37:26 +02:00
Linus Walleij b557457f63 ARM: ux500: add CoreSight blocks to DTS file
This registers all the CoreSight blocks on the DB8500 SoC:
each core has a PTM (v1.0, r1p0-00rel0) connected, both connected
to a funnel (DK-TM908-r0p1-00rel0) which in turn connects to a
replicator (DM-TM909-r0p1-00rel0). The replicator has two outputs,
port 0 to a TPIU interface and port 1 to an ETB
(DK-TM907-r0p3-00rel0). The CoreSight blocks are all clocked by
the APEATCLK from the PRCMU and their AHB interconnect is clocked
from a separate clock called APETRACECLK.

The SoC also has a CTI/CTM block which can be added later as we
have upstream support in the CoreSight subsystem.

Acked-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-05-13 12:22:17 +02:00
Linus Walleij 771969ec96 ARM: ux500: define CPU topology
The CPU topology is unspecified for Ux500 but will be needed
for things like CoreSight. Let's just add it.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-04-27 09:01:30 +02:00
Ulf Hansson 53d2669844 ARM: ux500: Move GPIO regulator for SD-card into board DTSs
The GPIO regulator for the SD-card isn't a ux500 SOC configuration, but
instead it's specific to the board. Move the definition of it, into the
board DTSs.

Fixes: c94a4ab7af ("ARM: ux500: Disable the MMCI gpio-regulator by default")
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-04-27 09:01:01 +02:00
Ulf Hansson 29417fe80a ARM: ux500: Add i2c devices to the VAPE PM domain
The i2c-nomadik driver handle these devices properly from a runtime PM
perspective. Therefore, let's add them into VAPE PM domain for ux500.

Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-10-28 10:50:46 +01:00
Ulf Hansson 770e2f6bc3 ARM: ux500: Add spi and ssp devices to the VAPE PM domain
The spi-pl022 driver handle these devices properly from a runtime PM
perspective. Therefore, let's add them into VAPE PM domain for ux500.

Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-10-28 10:50:21 +01:00
Ulf Hansson 067addec0e ARM: ux500: Add sdi devices to the VAPE PM domain
The mmci driver handle these devices properly from a runtime PM
perspective, including register context save/restore. Therefore let's
add them into VAPE PM domain for ux500.

Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-10-28 10:49:52 +01:00
Ulf Hansson 6c6693599b ARM: ux500: Add DT node for ux500 PM domains
Add a DT node for the ux500 PM domains. Follow the DT semantics of the
generic PM domain.

Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-10-28 10:49:27 +01:00
Linus Walleij 14cdf8cbc7 ARM: ux500: add some DB8500 DMA channel info
This adds some missing DMA channel information to the disabled
MMC/SD/SDIO blocks number 3 and 5, and notes that the assignment
of MSP channels vary with ASIC variant.

Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-07-07 11:54:06 +02:00
Linus Walleij 80fbe30f63 ARM: ux500: switch SSP/SPI clock name to "SSPCLK"
As noted in recent discussions the name of the core clock for
the PL022 derived SPI blocks is erroneously named in the
Ux500 device trees. The kernel doesn't currently use the name,
but may do so soon so let use rename all these clocks in
accordance with the name given in the PL022 TRM (ARM DDI 0194G).

Reviewed-by: Mark Brown <broonie@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-02-26 13:35:49 +01:00
Linus Walleij 6e9a88a0e5 ARM: ux500: create MCDE node to collect resources
As we need to connect resources such as pin mappings and clocks
when deleting board files, we create a MCDE node even though there
is no driver for it. As it is only using standard bindings right
now, this does not matter much. When a proper driver is written
for the MCDE, it can augment this node with custom properties.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-11-26 21:01:55 +01:00
Lee Jones 618111ca9a ARM: ux500: Add DMA config bindings for MSP devices
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-11-26 21:01:54 +01:00
Linus Walleij 6e1484c276 ARM: ux500: register all SSP and SPI blocks
This adds the SSP and SPI blocks to the device tree and makes
them active. Only this way can their clocks be properly gated
off at boot.

Acked-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-10-18 14:55:44 +02:00
Linus Walleij 72b3e249ce ARM: ux500: fix I2C4 clock bit
The PCLK for I2C4 is controlled by bit 10 in the PCKEN registers
while the KCLK is controlled by bit 9 on the KCKEN, it's
one of these odd assymetric things. Correct the PCLK bit to 10.

Acked-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-10-18 14:55:43 +02:00
Linus Walleij d591640adc ARM: ux500: fix clock for GPIO blocks 6 and 7
The clock assignment in the device tree for GPIO blocks 6
and 7 was incorrect, indicating this was managed by bit 1 on
PRCC 2 while it was in fact bit 11 on PRCC 2.

Acked-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-10-18 13:25:46 +02:00
Linus Walleij 84873cb773 ARM: ux500: fix clock for GPIO block 8
The clock assignment in the device tree for GPIO block 8 was
incorrect, indicating this was managed by bit 1 on PRCC 6
while it was in fact bit 1 on PRCC 5.

Acked-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-10-18 13:25:21 +02:00
Lee Jones 985856167d ARM: ux500: Provide a Device Tree node for CPUFreq in the DBx500
This is required to fetch the ARMSS clock when booting with DT.

Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-09-26 11:09:23 +02:00
Lee Jones 024cfe880b ARM: ux500: Provide a clock lookup for the Hash driver
The common clock framework will use the 'clock' property provided to do
a clock lookup when Device Tree is enabled.

Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-09-26 11:09:20 +02:00
Lee Jones d2f898cec8 ARM: ux500: Provide a clock lookup for the Crypto driver
The common clock framework will use the 'clock' property provided to do
a clock lookup when Device Tree is enabled.

Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-09-26 11:09:16 +02:00
Lee Jones d460d28bfb ARM: ux500: Fix trivial white-space error in the DBX500 DTSI file
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-09-26 11:09:13 +02:00
Lee Jones 8132ed1bb8 ARM: ux500: Add a DT node for the Nomadik System Timer (MTU0)
The MTU0 is required for full booting of the system. The driver has
been previously DT:ed and is in use on the Nomadik platform, but we
also need to enable it on ux500 based systems.

Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-09-26 11:05:13 +02:00
Lee Jones a8acb1ecc5 ARM: ux500: Supply the TWD Timer clock lookup to the DBX500 DT
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-09-26 11:05:10 +02:00
Lee Jones 309012d7e0 ARM: ux500: Add TWD (fixed-factor) clock node to DBx500 Device Tree
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-09-26 11:05:07 +02:00
Lee Jones d299b5a5ee ARM: ux500: Supply the RTC clock lookup to the DBX500 DT
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-09-26 11:05:03 +02:00
Lee Jones 589d9839df ARM: ux500: Add RTC (fixed-frequency) clock node to DBx500 Device Tree
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-09-26 11:05:00 +02:00
Lee Jones 133e6027e7 ARM: ux500: Supply the MSP (Audio) clocks lookup to the DBX500 DT
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-09-26 11:04:57 +02:00
Lee Jones 604be89846 ARM: ux500: Supply the SDI (MMC) clocks lookup to the DBX500 DT
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-09-26 11:04:54 +02:00
Lee Jones 5a323fb4f7 ARM: ux500: Supply the UART clocks lookup to the DBX500 DT
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-09-26 11:04:50 +02:00
Lee Jones afd653e97d ARM: ux500: Supply the I2C clocks lookup to the DBX500 DT
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-09-26 11:04:47 +02:00
Lee Jones 2588fea6a5 ARM: ux500: Add PRCC Kernel clock node to DBx500 Device Tree
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-09-26 11:04:44 +02:00
Lee Jones e47339fff2 ARM: ux500: Supply the USB clock lookup to the DBX500 DT
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-09-26 11:04:37 +02:00
Lee Jones 9d89107374 ARM: ux500: Supply the GPIO clocks lookup to the DBX500 DT
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-09-26 11:04:33 +02:00
Lee Jones fcbe5e90f8 ARM: ux500: Add PRCC Peripheral clock node to DBx500 Device Tree
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-09-26 11:04:30 +02:00
Lee Jones e064cb24f2 ARM: ux500: Supply the DMA clock lookup to the DBX500 DT
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-09-26 11:04:26 +02:00
Lee Jones 841cd0c0d8 ARM: ux500: Add PRCMU clock node to DBx500 Device Tree
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-09-26 11:04:21 +02:00
Sebastian Andrzej Siewior 4a6cd43fb7 dt: dbx5x0: remove mentor,musb binding
The "mentor,musb" binding isn't documented so I was about
to document it.

The node is missing a few properties for configuration like
"multipoint", "dyn_fifo", "num_eps" or "ram_bits". However
I am not sure "missing" is the right word here because some
of those informations might be obtained from the chip itself
but it is not done (yet).

Further the ePARP 2.3.1 says the matching goes from left to
right taking the fist match. Right now there is jus a driver
for "stericsson,db8500-musb" and none for "mentor,musb".
I'm not 100% that it is simply possible to have a generic
since even for DMA we have ifdefs in the driver between
"generic mentor dma" and "ux500 dma" and I mean within musb
and not the dma code.

For that reason (that I am not sure a generic musb binding
is possible and how its binding / required properties will
look like) and the reason that we have here a minor binding
without a driver to look at I suggest to remove that binding.

If the majority of people prefer to keep this binding I'm
curious how the documentation of the binding should look like.

Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-09-26 11:04:02 +02:00
Lee Jones ffefbd7511 ARM: ux500: Remove PrimeCell IDs from Nomadik I2C DT nodes
Turns out that they're actually not required and the driver probes just
fine without them. The ID is incorrect at the moment anyway. They actually
currently specify the stn8815.

Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-09-26 11:03:37 +02:00
Lee Jones c105424a51 ARM: ux500: Apply a ste-* prefix onto dbx5x0.dtsi
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
2013-08-07 15:35:50 +02:00